From mboxrd@z Thu Jan  1 00:00:00 1970
From: Frantisek Dufka <dufkaf@seznam.cz>
Subject: clock divisor in  mmc_omap_set_ios in drivers/mmc/omap.c wrong
Date: Fri, 10 Nov 2006 10:54:25 +0100
Message-ID: <45544C51.1050106@seznam.cz>
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Hello,

anyone knows real reason why the divisor is intentionally lowered in
mmc_omap_set_ios so the result frequency is _not_ near the one requested?

First there is a code which tries hard to select the divisor that
produces highest possible frequency which is lower or equal to the
requested one

        fclk_rate = clk_get_rate(host->fclk);
        dsor = fclk_rate / freq;
        if (dsor < 1)
                dsor = 1;
        if (fclk_rate / dsor > freq)
                dsor++;

        if (dsor > 250)
                dsor = 250;

and then there is additional

        dsor++;

which intentionally makes resulting frequency lower by unknown factor.

If this is some workaround for specific cards maybe it should be solved
in different place like blacklisting offending cards and actually
requesting lower frequency for them. Or is  there some real reason?

For requested 20Mhz MMC bus speed and 48Mhz omap clock current code
results in 12Mhz instead of 16Mhz.

Frantisek