Fwd: OMAP 2430 nand/nor booting

Fwd: OMAP 2430 nand/nor booting

[Amit Gupta]

Hi

I have been working on OMAP 2430 SDP BSP support.

For sometime I have been trying to port the boot loader image in NAND and
try to get it execute but I haven't been successful in the same.



Just have some basic doubts on flashing of images through NAND/NOR :-

   1. I tried creating a small image in which I do some hardware
initialization and make something print on LCD and throw some characters on
HyperTerminal. I tried executing the same in NOR and it executed
successfully because NOR is of XIP type but when I had reset my board the
image did not executed successfully. This means that NOR code is not being
relocated automatically to the different location by boot ROM code and its
not executing at the NOR location also.



While as per my documents study, it's clear that after reset the code is
relocated from NOR to different location for execution . But why is this not
happening automatically in my case.



   2. When I tried the downloading the same above image (converted into
.ift) in NAND flash , the code id not executed itself. I have given SRAM
addresses as execution address.  I also heard that NAND flash also has some
XIP region.



The logic is clear that NAND and (NOR image after reset) is not executing
until and unless you have copy code to relocate it to SRAM or SDRAM( if
SDRAM has already been initialized prior to relocation).


Kindly tell me that is my above understanding true or Boot ROM code does
copy some part of code because even if we have copy section within the code,
it needs to be executed before the copy actually takes place.

Thanks & Regards

Aman

Re: Fwd: OMAP 2430 nand/nor booting

[Nishanth Menon]

Hi Amit,
Amit Gupta stated on 6/3/2007 9:02 AM:
> While as per my documents study, it's clear that after reset the code is
> relocated from NOR to different location for execution . But why is
> this not
> happening automatically in my case.
>
Code relocation does not happen automatically. If ur boot code/sample
code desires to relocate itself to SDRAM or any other location. it needs
to be done by itself.
> I also heard that NAND flash also has some
> XIP region.
The 2430 SDP has two nands: one is a 16 bit Samsung SLC NAND and other
is a OneNAND device. The Onenand has limited XIP support, but the 16 bit
nand is not XIP.
> The logic is clear that NAND and (NOR image after reset) is not executing
> until and unless you have copy code to relocate it to SRAM or SDRAM( if
> SDRAM has already been initialized prior to relocation).
>
The code to relocate is part of your image. so it is upto your image to
decide how it should work.
> Kindly tell me that is my above understanding true or Boot ROM code does
> copy some part of code because even if we have copy section within the
> code,
> it needs to be executed before the copy actually takes place.
rom code behavior depends on the type of device:
in the case of NOR: instruction execution is given straight to the NOR
flash offset 0x0.
in the case of NAND: a limited number of pages is copied to SRAM and
execution commences in SRAM. note the fact of limited pages. the image
in those initial pages should be self sustaining and should be capable
of loading the rest of the image from nand and proceeding with
execution.. this is the role of X-Loader - a stripped down version of uboot.

Regards,
Nishanth Menon

Re: Fwd: OMAP 2430 nand/nor booting

[Amit Gupta]

Hello

Thanks for your reply.

But i am sure that after reset of processor with NOR settings the
reset address is not that of NOR. Its different because NOR shares its
switch settings with mDOC and some other device.

So after reset it does not executes from NOR location,so it does relocate
the
NOR code and there is an offset I suppose.

Now this is logical since my processor is sharing its switch settings with
other memory regions so my processsor wont be knowing that my image does
exists
in NOR or mDOC.

And  I dont think I need to relocate my NOR source code to this offset
location
since this should be carried out by boot ROM code.

Small Example which I carried out :-

I had writtten small LCD program which I downloaded through CSST in
NOR at addresss at location 0x04000000 and I ticked execute after download
at location 0x04000000 and the LCD got correct vaoue and hence image
executed sucessfully but
when I reset the processor, the image did not executed and the LCD did not
changed

This makes sure that even with NOR settings the PC does not jumps to NOR
strating location of 0X04000000 but rather it moves at an offset which is at
location
0x08000000 i suppose( which I saw in case of sample image)
Now in the Linux uboot and xload  code there have been some aprtial SRAM and
full SRAM configurations
happening which tells that some code executed in SRAM and part in SDRAM and
in the other case completely
in SDRAM. Do i need to do it explicitly for making the image execute after
reset but
still what is important to know is the reset address and how the boot loader
copies from NOR to that address.

With the NAND image is not at all executing, I dont understand why but I
suppose I will get the clue once I get answer to this.

Thanks & Regards

Aman


On 6/4/07, Nishanth Menon <menon.nishanth@gmail.com> wrote:
>
> Hi Amit,
> Amit Gupta stated on 6/3/2007 9:02 AM:
> > While as per my documents study, it's clear that after reset the code is
> > relocated from NOR to different location for execution . But why is
> > this not
> > happening automatically in my case.
> >
> Code relocation does not happen automatically. If ur boot code/sample
> code desires to relocate itself to SDRAM or any other location. it needs
> to be done by itself.
> > I also heard that NAND flash also has some
> > XIP region.
> The 2430 SDP has two nands: one is a 16 bit Samsung SLC NAND and other
> is a OneNAND device. The Onenand has limited XIP support, but the 16 bit
> nand is not XIP.
> > The logic is clear that NAND and (NOR image after reset) is not
> executing
> > until and unless you have copy code to relocate it to SRAM or SDRAM( if
> > SDRAM has already been initialized prior to relocation).
> >
> The code to relocate is part of your image. so it is upto your image to
> decide how it should work.
> > Kindly tell me that is my above understanding true or Boot ROM code does
> > copy some part of code because even if we have copy section within the
> > code,
> > it needs to be executed before the copy actually takes place.
> rom code behavior depends on the type of device:
> in the case of NOR: instruction execution is given straight to the NOR
> flash offset 0x0.
> in the case of NAND: a limited number of pages is copied to SRAM and
> execution commences in SRAM. note the fact of limited pages. the image
> in those initial pages should be self sustaining and should be capable
> of loading the rest of the image from nand and proceeding with
> execution.. this is the role of X-Loader - a stripped down version of
> uboot.
>
> Regards,
> Nishanth Menon
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> Linux-omap-open-source mailing list
> Linux-omap-open-source@linux.omap.com
> http://linux.omap.com/mailman/listinfo/linux-omap-open-source
>

Re: Fwd: OMAP 2430 nand/nor booting

[Nishanth Menon]

Amit / Aman,

Amit Gupta stated on 6/4/2007 1:06 PM:
> But i am sure that after reset of processor with NOR settings the
> reset address is not that of NOR. Its different because NOR shares its
> switch settings with mDOC and some other device.
>
What is your sysboot settings? if you do read the sysboot reg, u'd know
from where it did boot. there is something called internal and external
boot described in the TRM.
>
> Small Example which I carried out :-
>
> I had writtten small LCD program which I downloaded through CSST in
> NOR at addresss at location 0x04000000 and I ticked execute after
> download
> at location 0x04000000 and the LCD got correct vaoue and hence image
> executed sucessfully but
> when I reset the processor, the image did not executed and the LCD did
> not
> changed
>
Obviously, the CSST does something called peripheral boot. it has an
initialization code which setup all required regs.. when ur image boots,
dont expect that to be done automatically, unless you have put that code
in ur image.
> This makes sure that even with NOR settings the PC does not jumps to NOR
> strating location of 0X04000000 but rather it moves at an offset which
> is at
> location
> 0x08000000 i suppose( which I saw in case of sample image)
yes, the 0x0800... is the address ROM code programs for CS0 on NOR
flash. did u read GPMC regs to figure out the settings? GPMC can map
that Chip select to anywhere from 0x0 to 0x3000... so it does not make a
difference what CSST thinks the CS address is.. it configured it to be
0x0400.. this is the same address u-boot also does.. Essentially, from
what u stated, u did boot off NOR flash.. only ur code messed up somewhere..
>
> still what is important to know is the reset address and how the boot
> loader
> copies from NOR to that address.
It is simple: your reset address is baseaddress programmed in
GPMC_CS0_CONFIG7 reg+0x0

>
> With the NAND image is not at all executing, I dont understand why but I
> suppose I will get the clue once I get answer to this.
I suggest more reading of documentation.. it gives you a better picture
of boot sequence - which fortunately is simple once u trace it out.
>
>
> On 6/4/07, Nishanth Menon <menon.nishanth@gmail.com> wrote:
>>
>> Hi Amit,
>> Amit Gupta stated on 6/3/2007 9:02 AM:
Please do not TOP post while replying in email list.. most folks hate
having to get a 2 k mail when 100 bytes would have done. AND only in
text format.

Thanks and Regards,
Nishanth Menon