Boot failure on OMAP 3430 SDP

Boot failure on OMAP 3430 SDP

[Gadiyar, Anand]

Hi all,

Commit 5b36d70fa08f09de161487fe7f6e04200ffb8d71 breaks boot on OMAP3430 SDP. Reversing the patch allows the boot to work.

Bootlog and the patch are shown below.

Regards,
Anand

================================================

commit 5b36d70fa08f09de161487fe7f6e04200ffb8d71
Author: Jouni Hogander <jouni.hogander@nokia.com>
Date:   Mon Jun 9 12:32:40 2008 +0300

    PRCM: OMAP3: Fix to wrongly modified omap2_clk_wait_ready

    omap2_clk_wait_ready was wrongly modified to check
    registers contents. This fix changes it back to check
    addresses.

    Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com>
    Acked-by: Paul Walmsley <paul@pwsan.com>
    Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index d3ab537..ed15868 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -246,8 +246,8 @@ static void omap2_clk_wait_ready(struct clk *clk)
        /* REVISIT: What are the appropriate exclusions for 34XX? */
        /* OMAP3: ignore DSS-mod clocks */
        if (cpu_is_omap34xx() &&
-           ((reg & ~0xff) == cm_read_mod_reg(OMAP3430_DSS_MOD, 0) ||
-            (((reg & ~0xff) == cm_read_mod_reg(CORE_MOD, 0)) &&
+           ((reg & ~0xff) == (__force u32)OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, 0) ||
+            (((reg & ~0xff) == (__force u32)OMAP34XX_CM_REGADDR(CORE_MOD, 0)) &&
              clk->enable_bit == OMAP3430_EN_SSI_SHIFT)))
                return;

==============================================================================
<6>omapfb: configured for panel sdp2430
<6>omapfb: DISPC version 3.0 initialized
<1>Unhandled fault: external abort on non-linefetch (0x1028) at 0xd80504a0
Internal error: : 1028 [#1]
Modules linked in:
CPU: 0    Not tainted  (2.6.26-rc6-omap1 #4)
PC is at omap_dispc_enable_plane+0x40/0x68
LR is at omap2_clk_enable+0x5c/0x9c
pc : [<c017f948>]    lr : [<c0035ce4>]    psr: 60000013
sp : c7c1ddd8  ip : c034c534  fp : c7c1ddf4
r10: 00000000  r9 : c7d16000  r8 : 00000001
r7 : c7d16004  r6 : c037848c  r5 : 00000001  r4 : 00000000
r3 : c029dab0  r2 : 000000a0  r1 : d8050400  r0 : 00000000
Flags: nZCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment kernel
Control: 00c5387f  Table: 80004018  DAC: 00000017
Process swapper (pid: 1, stack limit = 0xc7c1c2e0)
Stack: (0xc7c1ddd8 to 0xc7c1e000)
ddc0:                                                       c7d7fc00 c0378424
dde0: c7d7fe30 c7d16004 c7c1de4c c7c1ddf8 c017e888 c017f914 c7c1de30 c7c1de30
de00: c7c1de2c c7d16000 c00d9c04 69c1de30 7265746e 006c616e 00000000 00000000
de20: c7c1de5c c034e418 c034e4c0 c035ceb0 c035ceb0 c0360bd0 00000000 c0023bdc
de40: c7c1de5c c7c1de50 c017ebec c017e380 c7c1de6c c7c1de60 c0181354 c017ebc0
de60: c7c1de7c c7c1de70 c01a134c c018134c c7c1de9c c7c1de80 c01a0708 c01a1338
de80: c034e418 c034e4c0 c035ceb0 c035ceb0 c7c1debc c7c1dea0 c01a0800 c01a0644
dea0: 00000000 c7c1dec4 c01a07b4 c035ceb0 c7c1deec c7c1dec0 c019fd80 c01a07c0
dec0: 00000000 c7c037d8 c7c037d8 c034e460 00000000 c035ceb0 00000000 c7c6c9e0
dee0: c7c1defc c7c1def0 c01a0550 c019fd40 c7c1df2c c7c1df00 c01a020c c01a053c
df00: c02fd3ea c035ceb0 00000000 c0024000 c035ceb0 00000000 c0019364 c7c1c000
df20: c7c1df54 c7c1df30 c01a09f4 c01a0170 c0024000 00000000 00000000 c0019364
df40: c7c1c000 c0023bdc c7c1df64 c7c1df58 c01a15d4 c01a0968 c7c1df74 c7c1df68
df60: c0019378 c01a1574 c7c1dff4 c7c1df78 c0008928 c0019370 00050000 01004000
df80: c7c1c000 00000000 c7c1df00 c7c1df98 c004bf3c c004bc04 00000000 00000000
dfa0: 00000000 c7c1dfb0 c002bac4 c004bf24 00000000 00000000 c0008888 c0051ecc
dfc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
dfe0: 00000000 00000000 00000000 c7c1dff8 c0051ecc c0008894 ffffffff ffffffff
Backtrace:
[<c017f908>] (omap_dispc_enable_plane+0x0/0x68) from [<c017e888>] (omapfb_do_probe+0x514/0x840)
 r7:c7d16004 r6:c7d7fe30 r5:c0378424 r4:c7d7fc00
[<c017e374>] (omapfb_do_probe+0x0/0x840) from [<c017ebec>] (omapfb_register_panel+0x38/0x40)
[<c017ebb4>] (omapfb_register_panel+0x0/0x40) from [<c0181354>] (sdp2430_panel_probe+0x14/0x20)
[<c0181340>] (sdp2430_panel_probe+0x0/0x20) from [<c01a134c>] (platform_drv_probe+0x20/0x24)
[<c01a132c>] (platform_drv_probe+0x0/0x24) from [<c01a0708>] (driver_probe_device+0xd0/0x17c)
[<c01a0638>] (driver_probe_device+0x0/0x17c) from [<c01a0800>] (__driver_attach+0x4c/0x70)
 r7:c035ceb0 r6:c035ceb0 r5:c034e4c0 r4:c034e418
[<c01a07b4>] (__driver_attach+0x0/0x70) from [<c019fd80>] (bus_for_each_dev+0x4c/0x84)
 r7:c035ceb0 r6:c01a07b4 r5:c7c1dec4 r4:00000000
[<c019fd34>] (bus_for_each_dev+0x0/0x84) from [<c01a0550>] (driver_attach+0x20/0x28)
 r7:c7c6c9e0 r6:00000000 r5:c035ceb0 r4:00000000
[<c01a0530>] (driver_attach+0x0/0x28) from [<c01a020c>] (bus_add_driver+0xa8/0x214)
[<c01a0164>] (bus_add_driver+0x0/0x214) from [<c01a09f4>] (driver_register+0x98/0x120)
 r8:c7c1c000 r7:c0019364 r6:00000000 r5:c035ceb0 r4:c0024000
[<c01a095c>] (driver_register+0x0/0x120) from [<c01a15d4>] (platform_driver_register+0x6c/0x88)
[<c01a1568>] (platform_driver_register+0x0/0x88) from [<c0019378>] (sdp2430_panel_drv_init+0x14/0x1c)
[<c0019364>] (sdp2430_panel_drv_init+0x0/0x1c) from [<c0008928>] (kernel_init+0xa0/0x230)
[<c0008888>] (kernel_init+0x0/0x230) from [<c0051ecc>] (do_exit+0x0/0x5fc)
Code: e59f302c e5961000 e3a00000 e7932104 (e7923001)
<4>---[ end trace da227214a82491b7 ]---
<0>Kernel panic - not syncing: Attempted to kill init!

Re: Boot failure on OMAP 3430 SDP

[Dirk Behme]

Gadiyar, Anand wrote:
> Hi all,
> 
> Commit 5b36d70fa08f09de161487fe7f6e04200ffb8d71 breaks boot on OMAP3430 SDP. Reversing the patch allows the boot to work.
> 
> Bootlog and the patch are shown below.
> 
> Regards,
> Anand
> 
> ================================================
> 
> commit 5b36d70fa08f09de161487fe7f6e04200ffb8d71
> Author: Jouni Hogander <jouni.hogander@nokia.com>
> Date:   Mon Jun 9 12:32:40 2008 +0300
> 
>     PRCM: OMAP3: Fix to wrongly modified omap2_clk_wait_ready
> 
>     omap2_clk_wait_ready was wrongly modified to check
>     registers contents. This fix changes it back to check
>     addresses.
> 
>     Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com>
>     Acked-by: Paul Walmsley <paul@pwsan.com>
>     Signed-off-by: Tony Lindgren <tony@atomide.com>
> 
> diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
> index d3ab537..ed15868 100644
> --- a/arch/arm/mach-omap2/clock.c
> +++ b/arch/arm/mach-omap2/clock.c
> @@ -246,8 +246,8 @@ static void omap2_clk_wait_ready(struct clk *clk)
>         /* REVISIT: What are the appropriate exclusions for 34XX? */
>         /* OMAP3: ignore DSS-mod clocks */
>         if (cpu_is_omap34xx() &&
> -           ((reg & ~0xff) == cm_read_mod_reg(OMAP3430_DSS_MOD, 0) ||
> -            (((reg & ~0xff) == cm_read_mod_reg(CORE_MOD, 0)) &&
> +           ((reg & ~0xff) == (__force u32)OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, 0) ||
> +            (((reg & ~0xff) == (__force u32)OMAP34XX_CM_REGADDR(CORE_MOD, 0)) &&
>               clk->enable_bit == OMAP3430_EN_SSI_SHIFT)))
>                 return;

Hmm, looking at recent git, we already have OMAP34XX_CM_REGADDR 
instead of cm_read_mod_reg there

http://source.mvista.com/git/?p=linux-omap-2.6.git;a=blob;f=arch/arm/mach-omap2/clock.c;h=ed1586847db4dd95cff8016e4259b533f1582737;hb=HEAD

and it seems that this patch is already applied

http://source.mvista.com/git/?p=linux-omap-2.6.git;a=commitdiff;h=5b36d70fa08f09de161487fe7f6e04200ffb8d71

?

*BUT*: I still see below Unhandled fault at OMAP3 based Beagle board! 
Any idea?

Thanks

Dirk

Btw: Next time sending a patch, adding [PATCH] to subject would be 
helpful. And e.g. "PRCM: OMAP3: Fix to wrongly modified 
omap2_clk_wait_ready" would have been a better subject ;)

> ==============================================================================
> <6>omapfb: configured for panel sdp2430
> <6>omapfb: DISPC version 3.0 initialized
> <1>Unhandled fault: external abort on non-linefetch (0x1028) at 0xd80504a0
> Internal error: : 1028 [#1]
> Modules linked in:
> CPU: 0    Not tainted  (2.6.26-rc6-omap1 #4)
> PC is at omap_dispc_enable_plane+0x40/0x68
> LR is at omap2_clk_enable+0x5c/0x9c
> pc : [<c017f948>]    lr : [<c0035ce4>]    psr: 60000013
> sp : c7c1ddd8  ip : c034c534  fp : c7c1ddf4
> r10: 00000000  r9 : c7d16000  r8 : 00000001
> r7 : c7d16004  r6 : c037848c  r5 : 00000001  r4 : 00000000
> r3 : c029dab0  r2 : 000000a0  r1 : d8050400  r0 : 00000000
> Flags: nZCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment kernel
> Control: 00c5387f  Table: 80004018  DAC: 00000017
> Process swapper (pid: 1, stack limit = 0xc7c1c2e0)
> Stack: (0xc7c1ddd8 to 0xc7c1e000)
> ddc0:                                                       c7d7fc00 c0378424
> dde0: c7d7fe30 c7d16004 c7c1de4c c7c1ddf8 c017e888 c017f914 c7c1de30 c7c1de30
> de00: c7c1de2c c7d16000 c00d9c04 69c1de30 7265746e 006c616e 00000000 00000000
> de20: c7c1de5c c034e418 c034e4c0 c035ceb0 c035ceb0 c0360bd0 00000000 c0023bdc
> de40: c7c1de5c c7c1de50 c017ebec c017e380 c7c1de6c c7c1de60 c0181354 c017ebc0
> de60: c7c1de7c c7c1de70 c01a134c c018134c c7c1de9c c7c1de80 c01a0708 c01a1338
> de80: c034e418 c034e4c0 c035ceb0 c035ceb0 c7c1debc c7c1dea0 c01a0800 c01a0644
> dea0: 00000000 c7c1dec4 c01a07b4 c035ceb0 c7c1deec c7c1dec0 c019fd80 c01a07c0
> dec0: 00000000 c7c037d8 c7c037d8 c034e460 00000000 c035ceb0 00000000 c7c6c9e0
> dee0: c7c1defc c7c1def0 c01a0550 c019fd40 c7c1df2c c7c1df00 c01a020c c01a053c
> df00: c02fd3ea c035ceb0 00000000 c0024000 c035ceb0 00000000 c0019364 c7c1c000
> df20: c7c1df54 c7c1df30 c01a09f4 c01a0170 c0024000 00000000 00000000 c0019364
> df40: c7c1c000 c0023bdc c7c1df64 c7c1df58 c01a15d4 c01a0968 c7c1df74 c7c1df68
> df60: c0019378 c01a1574 c7c1dff4 c7c1df78 c0008928 c0019370 00050000 01004000
> df80: c7c1c000 00000000 c7c1df00 c7c1df98 c004bf3c c004bc04 00000000 00000000
> dfa0: 00000000 c7c1dfb0 c002bac4 c004bf24 00000000 00000000 c0008888 c0051ecc
> dfc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
> dfe0: 00000000 00000000 00000000 c7c1dff8 c0051ecc c0008894 ffffffff ffffffff
> Backtrace:
> [<c017f908>] (omap_dispc_enable_plane+0x0/0x68) from [<c017e888>] (omapfb_do_probe+0x514/0x840)
>  r7:c7d16004 r6:c7d7fe30 r5:c0378424 r4:c7d7fc00
> [<c017e374>] (omapfb_do_probe+0x0/0x840) from [<c017ebec>] (omapfb_register_panel+0x38/0x40)
> [<c017ebb4>] (omapfb_register_panel+0x0/0x40) from [<c0181354>] (sdp2430_panel_probe+0x14/0x20)
> [<c0181340>] (sdp2430_panel_probe+0x0/0x20) from [<c01a134c>] (platform_drv_probe+0x20/0x24)
> [<c01a132c>] (platform_drv_probe+0x0/0x24) from [<c01a0708>] (driver_probe_device+0xd0/0x17c)
> [<c01a0638>] (driver_probe_device+0x0/0x17c) from [<c01a0800>] (__driver_attach+0x4c/0x70)
>  r7:c035ceb0 r6:c035ceb0 r5:c034e4c0 r4:c034e418
> [<c01a07b4>] (__driver_attach+0x0/0x70) from [<c019fd80>] (bus_for_each_dev+0x4c/0x84)
>  r7:c035ceb0 r6:c01a07b4 r5:c7c1dec4 r4:00000000
> [<c019fd34>] (bus_for_each_dev+0x0/0x84) from [<c01a0550>] (driver_attach+0x20/0x28)
>  r7:c7c6c9e0 r6:00000000 r5:c035ceb0 r4:00000000
> [<c01a0530>] (driver_attach+0x0/0x28) from [<c01a020c>] (bus_add_driver+0xa8/0x214)
> [<c01a0164>] (bus_add_driver+0x0/0x214) from [<c01a09f4>] (driver_register+0x98/0x120)
>  r8:c7c1c000 r7:c0019364 r6:00000000 r5:c035ceb0 r4:c0024000
> [<c01a095c>] (driver_register+0x0/0x120) from [<c01a15d4>] (platform_driver_register+0x6c/0x88)
> [<c01a1568>] (platform_driver_register+0x0/0x88) from [<c0019378>] (sdp2430_panel_drv_init+0x14/0x1c)
> [<c0019364>] (sdp2430_panel_drv_init+0x0/0x1c) from [<c0008928>] (kernel_init+0xa0/0x230)
> [<c0008888>] (kernel_init+0x0/0x230) from [<c0051ecc>] (do_exit+0x0/0x5fc)
> Code: e59f302c e5961000 e3a00000 e7932104 (e7923001)
> <4>---[ end trace da227214a82491b7 ]---
> <0>Kernel panic - not syncing: Attempted to kill init!
> 
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
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> 

RE: Boot failure on OMAP 3430 SDP

[Gadiyar, Anand]

> > Hi all,
> >
> > Commit 5b36d70fa08f09de161487fe7f6e04200ffb8d71 breaks boot on OMAP3430 SDP. Reversing the patch allows the boot to work.
> >
> > Bootlog and the patch are shown below.
> >
> > Regards,
> > Anand
> >
> > ================================================
> >
> > commit 5b36d70fa08f09de161487fe7f6e04200ffb8d71
> > Author: Jouni Hogander <jouni.hogander@nokia.com> >
> > Date:   Mon Jun 9 12:32:40 2008 +0300
> >
> >     PRCM: OMAP3: Fix to wrongly modified omap2_clk_wait_ready
> >
> >     omap2_clk_wait_ready was wrongly modified to check
> >     registers contents. This fix changes it back to check
> >     addresses.
> >
> >     Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com> >
> >     Acked-by: Paul Walmsley <paul@pwsan.com> >
> >     Signed-off-by: Tony Lindgren <tony@atomide.com> >
> >
> > diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
> > index d3ab537..ed15868 100644
> > --- a/arch/arm/mach-omap2/clock.c
> > +++ b/arch/arm/mach-omap2/clock.c
> > @@ -246,8 +246,8 @@ static void omap2_clk_wait_ready(struct clk *clk)
> >         /* REVISIT: What are the appropriate exclusions for 34XX? */
> >         /* OMAP3: ignore DSS-mod clocks */
> >         if (cpu_is_omap34xx() &&
> > -           ((reg & ~0xff) == cm_read_mod_reg(OMAP3430_DSS_MOD, 0) ||
> > -            (((reg & ~0xff) == cm_read_mod_reg(CORE_MOD, 0)) &&
> > +           ((reg & ~0xff) == (__force u32)OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, 0) ||
> > +            (((reg & ~0xff) == (__force u32)OMAP34XX_CM_REGADDR(CORE_MOD, 0)) &&
> >               clk-> >enable_bit == OMAP3430_EN_SSI_SHIFT)))
> >                 return;
> Hmm, looking at recent git, we already have OMAP34XX_CM_REGADDR
> instead of cm_read_mod_reg there
>
> http://source.mvista.com/git/?p=linux-omap-2.6.git;a=blob;f=arch/arm/mach-omap2/clock.c;h=ed1586847db4dd95cff8016e4259b533f1582737;hb=HEAD
>
> and it seems that this patch is already applied
>
> http://source.mvista.com/git/?p=linux-omap-2.6.git;a=commitdiff;h=5b36d70fa08f09de161487fe7f6e04200ffb8d71
>
> ?
>
> *BUT*: I still see below Unhandled fault at OMAP3 based Beagle board!
> Any idea?

Oops. Sorry for this confusion. The patch inlined in the mail was the commit that
causes the boot failure - not the fix. I would rather have Jouni and Paul look at the
commit. I haven't looked too deeply at the patch to see why it causes the crash.

Until this is fixed, you might just want to apply the patch in reverse.

>
> Btw: Next time sending a patch, adding [PATCH] to subject would be
> helpful. And e.g. "PRCM: OMAP3: Fix to wrongly modified
> omap2_clk_wait_ready" would have been a better subject ;)

Yes, I know. As I've said, this mail was not a patch. Should have worded it better.
I was just trying to save people some time by inlining the contents of the commit.

- Anand

Re: Boot failure on OMAP 3430 SDP

[Dirk Behme]

Gadiyar, Anand wrote:
>>>Hi all,
>>>
>>>Commit 5b36d70fa08f09de161487fe7f6e04200ffb8d71 breaks boot on OMAP3430 SDP. Reversing the patch allows the boot to work.
>>>
>>>Bootlog and the patch are shown below.
>>>
>>>Regards,
>>>Anand
>>>
>>>================================================
>>>
>>>commit 5b36d70fa08f09de161487fe7f6e04200ffb8d71
>>>Author: Jouni Hogander <jouni.hogander@nokia.com> >
>>>Date:   Mon Jun 9 12:32:40 2008 +0300
>>>
>>>    PRCM: OMAP3: Fix to wrongly modified omap2_clk_wait_ready
>>>
>>>    omap2_clk_wait_ready was wrongly modified to check
>>>    registers contents. This fix changes it back to check
>>>    addresses.
>>>
>>>    Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com> >
>>>    Acked-by: Paul Walmsley <paul@pwsan.com> >
>>>    Signed-off-by: Tony Lindgren <tony@atomide.com> >
>>>
>>>diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
>>>index d3ab537..ed15868 100644
>>>--- a/arch/arm/mach-omap2/clock.c
>>>+++ b/arch/arm/mach-omap2/clock.c
>>>@@ -246,8 +246,8 @@ static void omap2_clk_wait_ready(struct clk *clk)
>>>        /* REVISIT: What are the appropriate exclusions for 34XX? */
>>>        /* OMAP3: ignore DSS-mod clocks */
>>>        if (cpu_is_omap34xx() &&
>>>-           ((reg & ~0xff) == cm_read_mod_reg(OMAP3430_DSS_MOD, 0) ||
>>>-            (((reg & ~0xff) == cm_read_mod_reg(CORE_MOD, 0)) &&
>>>+           ((reg & ~0xff) == (__force u32)OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, 0) ||
>>>+            (((reg & ~0xff) == (__force u32)OMAP34XX_CM_REGADDR(CORE_MOD, 0)) &&
>>>              clk-> >enable_bit == OMAP3430_EN_SSI_SHIFT)))
>>>                return;
>>
>>Hmm, looking at recent git, we already have OMAP34XX_CM_REGADDR
>>instead of cm_read_mod_reg there
>>
>>http://source.mvista.com/git/?p=linux-omap-2.6.git;a=blob;f=arch/arm/mach-omap2/clock.c;h=ed1586847db4dd95cff8016e4259b533f1582737;hb=HEAD
>>
>>and it seems that this patch is already applied
>>
>>http://source.mvista.com/git/?p=linux-omap-2.6.git;a=commitdiff;h=5b36d70fa08f09de161487fe7f6e04200ffb8d71
>>
>>?
>>
>>*BUT*: I still see below Unhandled fault at OMAP3 based Beagle board!
>>Any idea?
> 
> Oops. Sorry for this confusion. The patch inlined in the mail was the commit that
> causes the boot failure - not the fix. I would rather have Jouni and Paul look at the
> commit. I haven't looked too deeply at the patch to see why it causes the crash.
> 
> Until this is fixed, you might just want to apply the patch in reverse.

Ah, yes, sorry for my misunderstanding! And many thanks for finding 
the cause of this issue. Hopefully we will have a fix for this soon now.

Sorry and thanks

Dirk

[PATCH] OMAP3 clock: fix omap2_clk_wait_ready for OMAP3430ES2 DSS

[Paul Walmsley]

On OMAP3430ES2, DSS has both an initiator standby CM_IDLEST bit, and a
target idle CM_IDLEST bit.  This is a departure from previous silicon,
which only had an initiator standby bit.

This means we need to test the target idle bit after enabling
dss1_alwon_fclk.  Previous clock code has done the wrong thing since ES2
came out: it's either tested the wrong bit, causing intermittent

    Clock dss1_alwon_fck didn't enable in 100000 tries

messages; or not tested anything at all, causing intermittent crashes 
during DISPC initialization with:

    Unhandled fault: external abort on non-linefetch (0x1028)

This patch modifies omap2_clk_wait_ready() to wait for the DSS to become
accessible after dss1_alwon_fclk is enabled.

Thanks to Anand Gadiyar <gadiyar@ti.com> for identifying one of the
problem patches.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
---

 arch/arm/mach-omap2/clock.c           |   30 ++++++++++++++++++++++++------
 arch/arm/mach-omap2/cm-regbits-34xx.h |    4 +++-
 2 files changed, 27 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index ed15868..1820f75 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -244,18 +244,36 @@ static void omap2_clk_wait_ready(struct clk *clk)
 	}
 
 	/* REVISIT: What are the appropriate exclusions for 34XX? */
-	/* OMAP3: ignore DSS-mod clocks */
-	if (cpu_is_omap34xx() &&
-	    ((reg & ~0xff) == (__force u32)OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, 0) ||
-	     (((reg & ~0xff) == (__force u32)OMAP34XX_CM_REGADDR(CORE_MOD, 0)) &&
-	      clk->enable_bit == OMAP3430_EN_SSI_SHIFT)))
-		return;
+	if (cpu_is_omap34xx()) {
+
+		/* 3430ES1 DSS and SSI have no target idlest bits */
+		if (is_sil_rev_equal_to(OMAP3430_REV_ES1_0) &&
+		    ((reg & ~0xff) == (__force u32)OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, 0) ||
+		     ((reg & ~0xff) == (__force u32)OMAP34XX_CM_REGADDR(CORE_MOD, 0) &&
+		      clk->enable_bit == OMAP3430_EN_SSI_SHIFT)))
+			return;
+
+		/* Even for 3430ES2 DSS, only wait for dss1_alwon_fclk */
+		if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0) &&
+		    (reg & ~0xff) == (__force u32)OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, 0) &&
+		    clk->enable_bit != OMAP3430_EN_DSS1_SHIFT)
+			return;
+
+	}
 
 	/* Check if both functional and interface clocks
 	 * are running. */
 	bit = 1 << clk->enable_bit;
 	if (!(__raw_readl((__force void __iomem *)other_reg) & bit))
 		return;
+
+	/* OMAP3430ES2 DSS is an unusual case */
+	if (cpu_is_omap34xx() &&
+	    (reg & ~0xff) == (__force u32)OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, 0) &&
+	    clk->enable_bit == OMAP3430_EN_DSS1_SHIFT) {
+		bit = OMAP3430ES2_ST_DSS_IDLE;
+	}
+
 	st_reg = ((other_reg & ~0xf0) | 0x20); /* CM_IDLEST* */
 
 	omap2_wait_clock_ready((__force void __iomem *)st_reg, bit, clk->name);
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h
index 6ec66f4..946c552 100644
--- a/arch/arm/mach-omap2/cm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
@@ -500,7 +500,9 @@
 #define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT		0
 
 /* CM_IDLEST_DSS */
-#define OMAP3430_ST_DSS					(1 << 0)
+#define OMAP3430ES2_ST_DSS_IDLE				(1 << 1)
+#define OMAP3430ES2_ST_DSS_STDBY			(1 << 0)
+#define OMAP3430ES1_ST_DSS				(1 << 0)
 
 /* CM_AUTOIDLE_DSS */
 #define OMAP3430_AUTO_DSS				(1 << 0)

Re: [PATCH] OMAP3 clock: fix omap2_clk_wait_ready for OMAP3430ES2 DSS

[Koen Kooi]

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1


Op 21 jun 2008, om 19:05 heeft Paul Walmsley het volgende geschreven:

>
> On OMAP3430ES2, DSS has both an initiator standby CM_IDLEST bit, and a
> target idle CM_IDLEST bit.  This is a departure from previous silicon,
> which only had an initiator standby bit.
>
> This means we need to test the target idle bit after enabling
> dss1_alwon_fclk.  Previous clock code has done the wrong thing since  
> ES2
> came out: it's either tested the wrong bit, causing intermittent
>
>    Clock dss1_alwon_fck didn't enable in 100000 tries
>
> messages; or not tested anything at all, causing intermittent crashes
> during DISPC initialization with:
>
>    Unhandled fault: external abort on non-linefetch (0x1028)
>
> This patch modifies omap2_clk_wait_ready() to wait for the DSS to  
> become
> accessible after dss1_alwon_fclk is enabled.
>
> Thanks to Anand Gadiyar <gadiyar@ti.com> for identifying one of the
> problem patches.

What this patch and the timer suppression patch I now get:

PowerTOP version 1.10      (C) 2007 Intel Corporation

Cn                Avg residency       P-states (frequencies)
C0 (cpu running)        ( 0.0%)
C0                0.0ms ( 0.0%)
C1              188.9ms (0.7%)*
C2              2036.1ms (8.0%)*
C3              23285.1ms (91.3%)*

Wakeups-from-idle per second : 61.7     interval: 3.0s

Top causes for wakeups:
   44.9% ( 57.7)       <interrupt> : musb_hdrc.0
   17.9% ( 23.0)       <interrupt> : gp timer
   14.3% ( 18.3)   USB device 2-1.2 : LCD2USB Interface (Till Harbaum)
    9.9% ( 12.7)         lcd4linux : do_nanosleep (hrtimer_wakeup)
    7.5% (  9.7)   USB device 2-1.4 : Linksys USB2.0 Network Adapter  
(USB)
    3.9% (  5.0)            Xfbdev : fbcon_add_cursor_timer  
(cursor_timer_handler)
    0.5% (  0.7)              hald : schedule_timeout (process_timeout)
    0.3% (  0.3)          dropbear : sk_reset_timer (tcp_write_timer)
    0.3% (  0.3)     <kernel core> : neigh_table_init_no_netlink  
(neigh_periodic_timer)
    0.3% (  0.3)        pulseaudio : schedule_timeout (process_timeout)
    0.3% (  0.3)              init : schedule_timeout (process_timeout)

The dispc crashes are gone and I get fewer wakeups per second :)

regards,

Koen


* There's a bug in powertop 1.10 that reports percentages wrong, so  
the percentages  where approximated by hand.

C0 (cpu running)        ( 0.0%)
C0                0.0ms ( 0.0%)
C1              176.5ms ( 4.7%)
C2              3601.7ms (4090.7%)
C3              17956.3ms (92938.0%)





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Re: [PATCH] OMAP3 clock: fix omap2_clk_wait_ready for OMAP3430ES2 DSS

[Dirk Behme]

Paul Walmsley wrote:
> On OMAP3430ES2, DSS has both an initiator standby CM_IDLEST bit, and a
> target idle CM_IDLEST bit.  This is a departure from previous silicon,
> which only had an initiator standby bit.
> 
> This means we need to test the target idle bit after enabling
> dss1_alwon_fclk.  Previous clock code has done the wrong thing since ES2
> came out: it's either tested the wrong bit, causing intermittent
> 
>     Clock dss1_alwon_fck didn't enable in 100000 tries
> 
> messages; or not tested anything at all, causing intermittent crashes 
> during DISPC initialization with:
> 
>     Unhandled fault: external abort on non-linefetch (0x1028)
> 
> This patch modifies omap2_clk_wait_ready() to wait for the DSS to become
> accessible after dss1_alwon_fclk is enabled.
> 
> Thanks to Anand Gadiyar <gadiyar@ti.com> for identifying one of the
> problem patches.
> 
> Signed-off-by: Paul Walmsley <paul@pwsan.com>

Acked-by: Dirk Behme <dirk.behme@gmail.com>

>  arch/arm/mach-omap2/clock.c           |   30 ++++++++++++++++++++++++------
>  arch/arm/mach-omap2/cm-regbits-34xx.h |    4 +++-
>  2 files changed, 27 insertions(+), 7 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
> index ed15868..1820f75 100644
> --- a/arch/arm/mach-omap2/clock.c
> +++ b/arch/arm/mach-omap2/clock.c
> @@ -244,18 +244,36 @@ static void omap2_clk_wait_ready(struct clk *clk)
>  	}
>  
>  	/* REVISIT: What are the appropriate exclusions for 34XX? */
> -	/* OMAP3: ignore DSS-mod clocks */
> -	if (cpu_is_omap34xx() &&
> -	    ((reg & ~0xff) == (__force u32)OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, 0) ||
> -	     (((reg & ~0xff) == (__force u32)OMAP34XX_CM_REGADDR(CORE_MOD, 0)) &&
> -	      clk->enable_bit == OMAP3430_EN_SSI_SHIFT)))
> -		return;
> +	if (cpu_is_omap34xx()) {
> +
> +		/* 3430ES1 DSS and SSI have no target idlest bits */
> +		if (is_sil_rev_equal_to(OMAP3430_REV_ES1_0) &&
> +		    ((reg & ~0xff) == (__force u32)OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, 0) ||
> +		     ((reg & ~0xff) == (__force u32)OMAP34XX_CM_REGADDR(CORE_MOD, 0) &&
> +		      clk->enable_bit == OMAP3430_EN_SSI_SHIFT)))
> +			return;
> +
> +		/* Even for 3430ES2 DSS, only wait for dss1_alwon_fclk */
> +		if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0) &&
> +		    (reg & ~0xff) == (__force u32)OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, 0) &&
> +		    clk->enable_bit != OMAP3430_EN_DSS1_SHIFT)
> +			return;
> +
> +	}
>  
>  	/* Check if both functional and interface clocks
>  	 * are running. */
>  	bit = 1 << clk->enable_bit;
>  	if (!(__raw_readl((__force void __iomem *)other_reg) & bit))
>  		return;
> +
> +	/* OMAP3430ES2 DSS is an unusual case */
> +	if (cpu_is_omap34xx() &&
> +	    (reg & ~0xff) == (__force u32)OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, 0) &&
> +	    clk->enable_bit == OMAP3430_EN_DSS1_SHIFT) {
> +		bit = OMAP3430ES2_ST_DSS_IDLE;
> +	}
> +
>  	st_reg = ((other_reg & ~0xf0) | 0x20); /* CM_IDLEST* */
>  
>  	omap2_wait_clock_ready((__force void __iomem *)st_reg, bit, clk->name);
> diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h
> index 6ec66f4..946c552 100644
> --- a/arch/arm/mach-omap2/cm-regbits-34xx.h
> +++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
> @@ -500,7 +500,9 @@
>  #define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT		0
>  
>  /* CM_IDLEST_DSS */
> -#define OMAP3430_ST_DSS					(1 << 0)
> +#define OMAP3430ES2_ST_DSS_IDLE				(1 << 1)
> +#define OMAP3430ES2_ST_DSS_STDBY			(1 << 0)
> +#define OMAP3430ES1_ST_DSS				(1 << 0)
>  
>  /* CM_AUTOIDLE_DSS */
>  #define OMAP3430_AUTO_DSS				(1 << 0)
> 

RE: [PATCH] OMAP3 clock: fix omap2_clk_wait_ready for OMAP3430ES2 DSS

[Woodruff, Richard]

> PowerTOP version 1.10      (C) 2007 Intel Corporation
>
> Cn                Avg residency       P-states (frequencies)
> C0 (cpu running)        ( 0.0%)
> C0                0.0ms ( 0.0%)
> C1              188.9ms (0.7%)*
> C2              2036.1ms (8.0%)*
> C3              23285.1ms (91.3%)*
>
> Wakeups-from-idle per second : 61.7     interval: 3.0s
>
> Top causes for wakeups:
>    44.9% ( 57.7)       <interrupt> : musb_hdrc.0
>    17.9% ( 23.0)       <interrupt> : gp timer
>    14.3% ( 18.3)   USB device 2-1.2 : LCD2USB Interface (Till Harbaum)
>     9.9% ( 12.7)         lcd4linux : do_nanosleep (hrtimer_wakeup)
>     7.5% (  9.7)   USB device 2-1.4 : Linksys USB2.0 Network Adapter
> (USB)
>     3.9% (  5.0)            Xfbdev : fbcon_add_cursor_timer
> (cursor_timer_handler)
>     0.5% (  0.7)              hald : schedule_timeout (process_timeout)
>     0.3% (  0.3)          dropbear : sk_reset_timer (tcp_write_timer)
>     0.3% (  0.3)     <kernel core> : neigh_table_init_no_netlink
> (neigh_periodic_timer)
>     0.3% (  0.3)        pulseaudio : schedule_timeout (process_timeout)
>     0.3% (  0.3)              init : schedule_timeout (process_timeout)
>
> The dispc crashes are gone and I get fewer wakeups per second :)
>
> regards,
>
> Koen
>
>
> * There's a bug in powertop 1.10 that reports percentages wrong, so
> the percentages  where approximated by hand.
>
> C0 (cpu running)        ( 0.0%)
> C0                0.0ms ( 0.0%)
> C1              176.5ms ( 4.7%)
> C2              3601.7ms (4090.7%)
> C3              17956.3ms (92938.0%)

Those C-State residency times are clearly wrong also.

If you try hard with a minimal kernel the maximum sleep you can get is like 1.5 seconds.  The kernel has some hard coded timers with 1 to 2 second periods (like slab cache reaper threads).

For our non-edge kernel code these things report about right.  As long as you have a 99.9% duty cycle of OFF to ON you get pretty good savings.

The wake up information should be about right.  Your USB Networking with MUSB will probably assure you of never getting ultra low power numbers but probably good for development.

What is that USB2LCD device?



Regards,
Richard W.

Re: [PATCH] OMAP3 clock: fix omap2_clk_wait_ready for OMAP3430ES2 DSS

[Koen Kooi]

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1


Op 22 jun 2008, om 14:51 heeft Woodruff, Richard het volgende  
geschreven:

>
>> PowerTOP version 1.10      (C) 2007 Intel Corporation
>>
>> Cn                Avg residency       P-states (frequencies)
>> C0 (cpu running)        ( 0.0%)
>> C0                0.0ms ( 0.0%)
>> C1              188.9ms (0.7%)*
>> C2              2036.1ms (8.0%)*
>> C3              23285.1ms (91.3%)*
>>
>> Wakeups-from-idle per second : 61.7     interval: 3.0s
>>
>> Top causes for wakeups:
>>   44.9% ( 57.7)       <interrupt> : musb_hdrc.0
>>   17.9% ( 23.0)       <interrupt> : gp timer
>>   14.3% ( 18.3)   USB device 2-1.2 : LCD2USB Interface (Till Harbaum)
>>    9.9% ( 12.7)         lcd4linux : do_nanosleep (hrtimer_wakeup)
>>    7.5% (  9.7)   USB device 2-1.4 : Linksys USB2.0 Network Adapter
>> (USB)
>>    3.9% (  5.0)            Xfbdev : fbcon_add_cursor_timer
>> (cursor_timer_handler)
>>    0.5% (  0.7)              hald : schedule_timeout  
>> (process_timeout)
>>    0.3% (  0.3)          dropbear : sk_reset_timer (tcp_write_timer)
>>    0.3% (  0.3)     <kernel core> : neigh_table_init_no_netlink
>> (neigh_periodic_timer)
>>    0.3% (  0.3)        pulseaudio : schedule_timeout  
>> (process_timeout)
>>    0.3% (  0.3)              init : schedule_timeout  
>> (process_timeout)
>>
>> The dispc crashes are gone and I get fewer wakeups per second :)
>>
>> regards,
>>
>> Koen
>>
>>
>> * There's a bug in powertop 1.10 that reports percentages wrong, so
>> the percentages  where approximated by hand.
>>
>> C0 (cpu running)        ( 0.0%)
>> C0                0.0ms ( 0.0%)
>> C1              176.5ms ( 4.7%)
>> C2              3601.7ms (4090.7%)
>> C3              17956.3ms (92938.0%)
>
> Those C-State residency times are clearly wrong also.
>
> If you try hard with a minimal kernel the maximum sleep you can get  
> is like 1.5 seconds.  The kernel has some hard coded timers with 1  
> to 2 second periods (like slab cache reaper threads).
>
> For our non-edge kernel code these things report about right.  As  
> long as you have a 99.9% duty cycle of OFF to ON you get pretty good  
> savings.
>
> The wake up information should be about right.  Your USB Networking  
> with MUSB will probably assure you of never getting ultra low power  
> numbers but probably good for development.
>
> What is that USB2LCD device?

http://www.harbaum.org/till/lcd2usb/index.shtml driven by the  
lcd4linux app, which is quite x86 oriented, so not very powersaving  
friendly, I did save ~100 wake-ups/s by using libusb1+libusbcompat  
over libusb.

regards,

Koen

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[PATCH v2] OMAP3 clock: fix omap2_clk_wait_ready for OMAP3430ES2 DSS

[Paul Walmsley]

Hi everyone,

The previous version of this patch tried to wait for the SSI module
on OMAP3; this is now fixed; also, added some code cleanup.  

- Paul

----

On OMAP3430ES2, DSS has both an initiator standby CM_IDLEST bit, and a
target idle CM_IDLEST bit.  This is a departure from previous silicon,
which only had an initiator standby bit.

This means we need to test the target idle bit after enabling
dss1_alwon_fclk.  Previous clock code has done the wrong thing since ES2
came out: it's either tested the wrong bit, causing

    Clock dss1_alwon_fck failed to enable in 100000 tries

messages, or not tested anything at all, causing crashes during DISPC
initialization with:

    Unhandled fault: external abort on non-linefetch (0x1028)

This patch modifies omap2_clk_wait_ready() to wait for the DSS to become
accessible after dss1_alwon_fclk, dss_l3_iclk, and dss_l4_iclk are enabled.
It also does some cleanup by getting rid of some casts.

Thanks to:
. Anand Gadiyar <gadiyar@ti.com> for identifying one of the problem patches,
. Koen Kooi <k.kooi@student.utwente.nl> for testing the previous version of
  this patch,
. Dirk Behme <dirk.behme@googlemail.com> for review of the previous version,
. Igor Stoppa <igor.stoppa@nokia.com> and Richard Woodruff
  <r-woodruff2@ti.com> for help with the SSI portion of the patch.


Signed-off-by: Paul Walmsley <paul@pwsan.com>
---

 arch/arm/mach-omap2/clock.c           |   63 +++++++++++++++++++++++++--------
 arch/arm/mach-omap2/cm-regbits-34xx.h |    4 ++
 2 files changed, 50 insertions(+), 17 deletions(-)

diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index ed15868..4d76ea5 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -222,20 +222,22 @@ int omap2_wait_clock_ready(void __iomem *reg, u32 mask, const char *name)
  */
 static void omap2_clk_wait_ready(struct clk *clk)
 {
-	u32 bit, reg, other_reg, st_reg;
+	u32 bit;
+	unsigned long reg, other_reg, st_reg, prcm_mod, prcm_regid;
 
-	reg = (__force u32)clk->enable_reg;
-	if (((reg & 0xff) >= CM_FCLKEN1) &&
-	    ((reg & 0xff) <= OMAP24XX_CM_FCLKEN2))
+	reg = (unsigned long)clk->enable_reg;
+	prcm_mod = reg & ~0xff;
+	prcm_regid = reg & 0xff;
+
+	if (prcm_regid >= CM_FCLKEN1 && prcm_regid <= OMAP24XX_CM_FCLKEN2)
 		other_reg = ((reg & ~0xf0) | 0x10); /* CM_ICLKEN* */
-	else if (((reg & 0xff) >= CM_ICLKEN1) &&
-		 ((reg & 0xff) <= OMAP24XX_CM_ICLKEN4))
+	else if (prcm_regid >= CM_ICLKEN1 && prcm_regid <= OMAP24XX_CM_ICLKEN4)
 		other_reg = ((reg & ~0xf0) | 0x00); /* CM_FCLKEN* */
 	else
 		return;
 
-	/* REVISIT: What are the appropriate exclusions for 34XX? */
-	/* No check for DSS or cam clocks */
+	/* No check for DSS or CAM clocks on 24xx */
+	/* REVISIT: This should check prcm_mod against CORE_MOD */
 	if (cpu_is_omap24xx() && (reg & 0x0f) == 0) { /* CM_{F,I}CLKEN1 */
 		if (clk->enable_bit == OMAP24XX_EN_DSS2_SHIFT ||
 		    clk->enable_bit == OMAP24XX_EN_DSS1_SHIFT ||
@@ -244,21 +246,50 @@ static void omap2_clk_wait_ready(struct clk *clk)
 	}
 
 	/* REVISIT: What are the appropriate exclusions for 34XX? */
-	/* OMAP3: ignore DSS-mod clocks */
-	if (cpu_is_omap34xx() &&
-	    ((reg & ~0xff) == (__force u32)OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, 0) ||
-	     (((reg & ~0xff) == (__force u32)OMAP34XX_CM_REGADDR(CORE_MOD, 0)) &&
-	      clk->enable_bit == OMAP3430_EN_SSI_SHIFT)))
-		return;
+	if (cpu_is_omap34xx()) {
+
+		/* 3430ES1 DSS has no target idlest bits */
+		if (is_sil_rev_equal_to(OMAP3430_REV_ES1_0) &&
+		    (prcm_mod == OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, 0) ||
+		     (prcm_mod == OMAP34XX_CM_REGADDR(CORE_MOD, 0) &&
+		      clk->enable_bit == OMAP3430_EN_SSI_SHIFT)))
+			return;
+
+		/* 
+		 * For 3430ES2 DSS, wait once (dss1_alwon_fclk, 
+		 * dss_l3_iclk, dss_l4_iclk) are enabled
+		 */
+		if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0) &&
+		    prcm_mod == OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, 0) &&
+		    clk->enable_bit != OMAP3430_EN_DSS1_SHIFT)
+			return;
+
+		/* SSI has no target idlest bit on OMAP3 */
+		if (prcm_mod == OMAP34XX_CM_REGADDR(CORE_MOD, 0) &&
+		    clk->enable_bit == OMAP3430_EN_SSI_SHIFT)
+			return;
+
+	}
 
 	/* Check if both functional and interface clocks
 	 * are running. */
 	bit = 1 << clk->enable_bit;
-	if (!(__raw_readl((__force void __iomem *)other_reg) & bit))
+	if (!(__raw_readl((void __iomem *)other_reg) & bit))
 		return;
+
+	/*
+	 * OMAP3430ES2 DSS target idlest bit is at a different shift than
+	 * the corresponding {I,F}CLKEN bits
+	 */
+	if (cpu_is_omap34xx() &&
+	    prcm_mod == OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, 0) &&
+	    clk->enable_bit == OMAP3430_EN_DSS1_SHIFT) {
+		bit = OMAP3430ES2_ST_DSS_IDLE;
+	}
+
 	st_reg = ((other_reg & ~0xf0) | 0x20); /* CM_IDLEST* */
 
-	omap2_wait_clock_ready((__force void __iomem *)st_reg, bit, clk->name);
+	omap2_wait_clock_ready((void __iomem *)st_reg, bit, clk->name);
 }
 
 /* Enables clock without considering parent dependencies or use count
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h
index 6ec66f4..946c552 100644
--- a/arch/arm/mach-omap2/cm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
@@ -500,7 +500,9 @@
 #define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT		0
 
 /* CM_IDLEST_DSS */
-#define OMAP3430_ST_DSS					(1 << 0)
+#define OMAP3430ES2_ST_DSS_IDLE				(1 << 1)
+#define OMAP3430ES2_ST_DSS_STDBY			(1 << 0)
+#define OMAP3430ES1_ST_DSS				(1 << 0)
 
 /* CM_AUTOIDLE_DSS */
 #define OMAP3430_AUTO_DSS				(1 << 0)

Re: [PATCH v2] OMAP3 clock: fix omap2_clk_wait_ready for OMAP3430ES2 DSS

[Högander Jouni]

Hello Paul,

"ext Paul Walmsley" <paul@pwsan.com> writes:

> Hi everyone,
>
> The previous version of this patch tried to wait for the SSI module
> on OMAP3; this is now fixed; also, added some code cleanup.  

It should actually wait for SSI also. Read my comments below.

>
> - Paul
>
> ----
>
> On OMAP3430ES2, DSS has both an initiator standby CM_IDLEST bit, and a
> target idle CM_IDLEST bit.  This is a departure from previous silicon,
> which only had an initiator standby bit.
>
> This means we need to test the target idle bit after enabling
> dss1_alwon_fclk.  Previous clock code has done the wrong thing since ES2
> came out: it's either tested the wrong bit, causing
>
>     Clock dss1_alwon_fck failed to enable in 100000 tries
>
> messages, or not tested anything at all, causing crashes during DISPC
> initialization with:
>
>     Unhandled fault: external abort on non-linefetch (0x1028)
>
> This patch modifies omap2_clk_wait_ready() to wait for the DSS to become
> accessible after dss1_alwon_fclk, dss_l3_iclk, and dss_l4_iclk are enabled.
> It also does some cleanup by getting rid of some casts.
>
> Thanks to:
> . Anand Gadiyar <gadiyar@ti.com> for identifying one of the problem patches,
> . Koen Kooi <k.kooi@student.utwente.nl> for testing the previous version of
>   this patch,
> . Dirk Behme <dirk.behme@googlemail.com> for review of the previous version,
> . Igor Stoppa <igor.stoppa@nokia.com> and Richard Woodruff
>   <r-woodruff2@ti.com> for help with the SSI portion of the patch.
>
>
> Signed-off-by: Paul Walmsley <paul@pwsan.com>
> ---
>
>  arch/arm/mach-omap2/clock.c           |   63 +++++++++++++++++++++++++--------
>  arch/arm/mach-omap2/cm-regbits-34xx.h |    4 ++
>  2 files changed, 50 insertions(+), 17 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
> index ed15868..4d76ea5 100644
> --- a/arch/arm/mach-omap2/clock.c
> +++ b/arch/arm/mach-omap2/clock.c
> @@ -222,20 +222,22 @@ int omap2_wait_clock_ready(void __iomem *reg, u32 mask, const char *name)
>   */
>  static void omap2_clk_wait_ready(struct clk *clk)
>  {
> -	u32 bit, reg, other_reg, st_reg;
> +	u32 bit;
> +	unsigned long reg, other_reg, st_reg, prcm_mod, prcm_regid;
>  
> -	reg = (__force u32)clk->enable_reg;
> -	if (((reg & 0xff) >= CM_FCLKEN1) &&
> -	    ((reg & 0xff) <= OMAP24XX_CM_FCLKEN2))
> +	reg = (unsigned long)clk->enable_reg;
> +	prcm_mod = reg & ~0xff;
> +	prcm_regid = reg & 0xff;
> +
> +	if (prcm_regid >= CM_FCLKEN1 && prcm_regid <= OMAP24XX_CM_FCLKEN2)
>  		other_reg = ((reg & ~0xf0) | 0x10); /* CM_ICLKEN* */
> -	else if (((reg & 0xff) >= CM_ICLKEN1) &&
> -		 ((reg & 0xff) <= OMAP24XX_CM_ICLKEN4))
> +	else if (prcm_regid >= CM_ICLKEN1 && prcm_regid <= OMAP24XX_CM_ICLKEN4)
>  		other_reg = ((reg & ~0xf0) | 0x00); /* CM_FCLKEN* */
>  	else
>  		return;
>  
> -	/* REVISIT: What are the appropriate exclusions for 34XX? */
> -	/* No check for DSS or cam clocks */
> +	/* No check for DSS or CAM clocks on 24xx */
> +	/* REVISIT: This should check prcm_mod against CORE_MOD */
>  	if (cpu_is_omap24xx() && (reg & 0x0f) == 0) { /* CM_{F,I}CLKEN1 */
>  		if (clk->enable_bit == OMAP24XX_EN_DSS2_SHIFT ||
>  		    clk->enable_bit == OMAP24XX_EN_DSS1_SHIFT ||
> @@ -244,21 +246,50 @@ static void omap2_clk_wait_ready(struct clk *clk)
>  	}
>  
>  	/* REVISIT: What are the appropriate exclusions for 34XX? */
> -	/* OMAP3: ignore DSS-mod clocks */
> -	if (cpu_is_omap34xx() &&
> -	    ((reg & ~0xff) == (__force u32)OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, 0) ||
> -	     (((reg & ~0xff) == (__force u32)OMAP34XX_CM_REGADDR(CORE_MOD, 0)) &&
> -	      clk->enable_bit == OMAP3430_EN_SSI_SHIFT)))
> -		return;
> +	if (cpu_is_omap34xx()) {
> +
> +		/* 3430ES1 DSS has no target idlest bits */
> +		if (is_sil_rev_equal_to(OMAP3430_REV_ES1_0) &&
> +		    (prcm_mod == OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, 0) ||
> +		     (prcm_mod == OMAP34XX_CM_REGADDR(CORE_MOD, 0) &&
> +		      clk->enable_bit == OMAP3430_EN_SSI_SHIFT)))
> +			return;
> +
> +		/* 
> +		 * For 3430ES2 DSS, wait once (dss1_alwon_fclk, 
> +		 * dss_l3_iclk, dss_l4_iclk) are enabled
> +		 */
> +		if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0) &&
> +		    prcm_mod == OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, 0) &&
> +		    clk->enable_bit != OMAP3430_EN_DSS1_SHIFT)
> +			return;

Remove from this point

> +		/* SSI has no target idlest bit on OMAP3 */
> +		if (prcm_mod == OMAP34XX_CM_REGADDR(CORE_MOD, 0) &&
> +		    clk->enable_bit == OMAP3430_EN_SSI_SHIFT)
> +			return;
> +

to this point

> +	}
>  
>  	/* Check if both functional and interface clocks
>  	 * are running. */
>  	bit = 1 << clk->enable_bit;
> -	if (!(__raw_readl((__force void __iomem *)other_reg) & bit))
> +	if (!(__raw_readl((void __iomem *)other_reg) & bit))
>  		return;
> +
> +	/*
> +	 * OMAP3430ES2 DSS target idlest bit is at a different shift than
> +	 * the corresponding {I,F}CLKEN bits
> +	 */
> +	if (cpu_is_omap34xx() &&
> +	    prcm_mod == OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, 0) &&
> +	    clk->enable_bit == OMAP3430_EN_DSS1_SHIFT) {
> +		bit = OMAP3430ES2_ST_DSS_IDLE;

And add this part

+       if (cpu_is_omap34xx() &&
+	    prcm_mod == OMAP34XX_CM_REGADDR(CORE_MOD, 0) &&
+	    clk->enable_bit == OMAP3430_EN_SSI_SHIFT) {
+		bit = OMAP3430ES2_ST_SSI_IDLE;

> +	}
> +
>  	st_reg = ((other_reg & ~0xf0) | 0x20); /* CM_IDLEST* */
>  
> -	omap2_wait_clock_ready((__force void __iomem *)st_reg, bit, clk->name);
> +	omap2_wait_clock_ready((void __iomem *)st_reg, bit, clk->name);
>  }
>  
>  /* Enables clock without considering parent dependencies or use count
> diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h
> index 6ec66f4..946c552 100644
> --- a/arch/arm/mach-omap2/cm-regbits-34xx.h
> +++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
> @@ -500,7 +500,9 @@
>  #define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT		0
>  
>  /* CM_IDLEST_DSS */
> -#define OMAP3430_ST_DSS					(1 << 0)
> +#define OMAP3430ES2_ST_DSS_IDLE				(1 << 1)
> +#define OMAP3430ES2_ST_DSS_STDBY			(1 << 0)
> +#define OMAP3430ES1_ST_DSS				(1 << 0)
>  
>  /* CM_AUTOIDLE_DSS */
>  #define OMAP3430_AUTO_DSS				(1 << 0)
>
>

-- 
Jouni Högander

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Re: [PATCH v2] OMAP3 clock: fix omap2_clk_wait_ready for OMAP3430ES2 DSS

[Paul Walmsley]

[-- Attachment #1: Type: TEXT/PLAIN, Size: 482 bytes --]

Hi Jouni

On Mon, 23 Jun 2008, Högander Jouni wrote:

> Hello Paul,
> 
> It should actually wait for SSI also. Read my comments below.

...

> And add this part
> 
> +       if (cpu_is_omap34xx() &&
> +	    prcm_mod == OMAP34XX_CM_REGADDR(CORE_MOD, 0) &&
> +	    clk->enable_bit == OMAP3430_EN_SSI_SHIFT) {
> +		bit = OMAP3430ES2_ST_SSI_IDLE;

what should OMAP3430ES2_ST_SSI_IDLE be set to?  I don't have any 
documentation here that defines this bit.


- Paul

Re: [PATCH v2] OMAP3 clock: fix omap2_clk_wait_ready for OMAP3430ES2 DSS

[Högander Jouni]

"ext Paul Walmsley" <paul@pwsan.com> writes:

> Hi Jouni
>
> On Mon, 23 Jun 2008, Högander Jouni wrote:
>
>> Hello Paul,
>> 
>> It should actually wait for SSI also. Read my comments below.
>
> ...
>
>> And add this part
>> 
>> +       if (cpu_is_omap34xx() &&
>> +	    prcm_mod == OMAP34XX_CM_REGADDR(CORE_MOD, 0) &&
>> +	    clk->enable_bit == OMAP3430_EN_SSI_SHIFT) {
>> +		bit = OMAP3430ES2_ST_SSI_IDLE;
>
> what should OMAP3430ES2_ST_SSI_IDLE be set to?  I don't have any 
> documentation here that defines this bit.

Sorry for not to mention this in my first mail:

#define OMAP3430ES2_ST_SSI_IDLE				(1 << 8)
#define OMAP3430ES2_ST_SSI_STDBY			(1 << 0)

-- 
Jouni Högander

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