[PATCHV2 0/4] OMAP3: Clock changes for OMAP3630

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* [PATCHV2 0/4] OMAP3: Clock changes for OMAP3630
@ 2009-11-20 15:28 Vishwanath BS
  2009-11-20 15:28 ` [PATCHV2 1/4] OMAP3: introduce DPLL4 Jtype Vishwanath BS
  0 siblings, 1 reply; 12+ messages in thread
From: Vishwanath BS @ 2009-11-20 15:28 UTC (permalink / raw)
  To: linux-omap, vishwanath.bs

This patch set introduces clock changes for OMAP3630. Major changes in OMAP3630 w.r.t clock are 1. Introduction of j type dpll4 2. CLKSEL filed width is increased by 1 bit for DPLL4M3, M4, M5 and M6 3. SGX can be run at 192Mhz

Patch set has been created for linux-omap-pm tree
V1: Initital Patch Series
V2: Fixed Line wrap issue and incorporated comments for adding 192MHz Feature

Richard Woodruff (1):
  OMAP3: introduce DPLL4 Jtype

Vishwanath BS (3):
  OMAP3: Clock Type change for OMAP3 Clocks
  OMAP3: Correct width for CLKSEL Fields
  OMAP3: add support for 192Mhz sgx clock

 arch/arm/mach-omap2/clock.h             |   15 +-
 arch/arm/mach-omap2/clock34xx.c         |  445 ++++++++++++++++++-------------
 arch/arm/mach-omap2/clock34xx.h         |  244 +++++++++++------
 arch/arm/mach-omap2/cm-regbits-34xx.h   |   11 +
 arch/arm/mach-omap2/id.c                |    7 +-
 arch/arm/plat-omap/include/plat/clock.h |    9 +-
 arch/arm/plat-omap/include/plat/cpu.h   |    4 +
 7 files changed, 456 insertions(+), 279 deletions(-)


^ permalink raw reply	[flat|nested] 12+ messages in thread

* [PATCHV2 1/4] OMAP3: introduce DPLL4 Jtype
  2009-11-20 15:28 [PATCHV2 0/4] OMAP3: Clock changes for OMAP3630 Vishwanath BS
@ 2009-11-20 15:28 ` Vishwanath BS
  2009-11-20 15:28   ` [PATCHV2 2/4] OMAP3: Clock Type change for OMAP3 Clocks Vishwanath BS
  0 siblings, 1 reply; 12+ messages in thread
From: Vishwanath BS @ 2009-11-20 15:28 UTC (permalink / raw)
  To: linux-omap, vishwanath.bs

From: Richard Woodruff <r-woodruff2@ti.com>

DPLL4 for 3630 introduces a changed block requiring special divisor bits and
additional reg fields. To allow for silicons to use this, this is introduced 
as a omap3_has_jtype_dpll4() and is enabled for 3630 silicon

Tested with 3630 ZOOM3
Signed-off-by: Richard Woodruff <r-woodruff2@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Vishwanath BS <Vishwanath.bs@ti.com>
---
 arch/arm/mach-omap2/clock34xx.c         |   51 ++++++++++++++++++++++++++++++-
 arch/arm/mach-omap2/cm-regbits-34xx.h   |    6 +++-
 arch/arm/mach-omap2/id.c                |    4 ++-
 arch/arm/plat-omap/include/plat/clock.h |    3 ++
 arch/arm/plat-omap/include/plat/cpu.h   |    3 +-
 5 files changed, 63 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index da5bc1f..832ed0b 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -679,6 +679,41 @@ static void omap3_noncore_dpll_disable(struct clk *clk)
 	_omap3_noncore_dpll_stop(clk);
 }
 
+/**
+ * lookup_dco_sddiv -  Set j-type DPLL4 compensation variables
+ * @clk: pointer to a DPLL struct clk
+ * @dco: digital control oscillator selector
+ * @sd_div: target sigma-delta divider
+ * @m: DPLL multiplier to set
+ * @n: DPLL divider to set
+ */
+static void lookup_dco_sddiv(struct clk *clk, u8 *dco, u8 *sd_div, u16
+								m, u8 n)
+	{
+	unsigned long fint, clkinp, sd; /* watch out for overflow */
+	int mod1, mod2;
+
+	clkinp = clk->parent->rate;
+	fint = (clkinp / n) * m;
+
+	if (fint < 1000000000)
+		*dco = 2;
+	else
+		*dco = 4;
+	/*
+	 * target sigma-delta to near 250MHz
+	 * sd = ceil[(m/(n+1)) * (clkinp_MHz / 250)]
+	 */
+	clkinp /= 100000; /* shift from MHz to 10*Hz for 38.4 and 19.2*/
+	mod1 = (clkinp * m) % (250 * n);
+	sd = (clkinp * m) / (250 * n);
+	mod2 = sd % 10;
+	sd /= 10;
+
+	if (mod1 + mod2)
+		sd++;
+	*sd_div = sd;
+}
 
 /* Non-CORE DPLL rate set code */
 
@@ -711,6 +746,13 @@ static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
 	v &= ~(dd->mult_mask | dd->div1_mask);
 	v |= m << __ffs(dd->mult_mask);
 	v |= (n - 1) << __ffs(dd->div1_mask);
+	if (dd->jtype) {
+		u8 dco, sd_div;
+		lookup_dco_sddiv(clk, &dco, &sd_div, m, n);
+		v &= ~(dd->dco_sel_mask | dd->sd_div_mask);
+		v |=  dco << __ffs(dd->dco_sel_mask);
+		v |=  sd_div << __ffs(dd->sd_div_mask);
+	}
 	__raw_writel(v, dd->mult_div1_reg);
 
 	/* We let the clock framework set the other output dividers later */
@@ -1026,7 +1068,7 @@ static unsigned long omap3_clkoutx2_recalc(struct clk *clk)
 
 	v = __raw_readl(dd->control_reg) & dd->enable_mask;
 	v >>= __ffs(dd->enable_mask);
-	if (v != OMAP3XXX_EN_DPLL_LOCKED)
+	if (v != OMAP3XXX_EN_DPLL_LOCKED && (!dd->jtype))
 		rate = clk->parent->rate;
 	else
 		rate = clk->parent->rate * 2;
@@ -1174,6 +1216,13 @@ int __init omap2_clk_init(void)
 			cpu_mask |= RATE_IN_3430ES2;
 			cpu_clkflg |= CK_3430ES2;
 		}
+		if (omap3_has_jtype_dpll4()) {
+			dpll4_ck.dpll_data->jtype = 1;
+			dpll4_ck.dpll_data->dco_sel_mask =
+				OMAP3630_PERIPH_DPLL_DCO_SEL_MASK;
+			dpll4_ck.dpll_data->sd_div_mask =
+				OMAP3630_PERIPH_DPLL_SD_DIV_MASK;
+			}
 	}
 
 	clk_init(&omap2_clk_functions);
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h
index 6923deb..6f2802b 100644
--- a/arch/arm/mach-omap2/cm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
@@ -516,9 +516,13 @@
 
 /* CM_CLKSEL2_PLL */
 #define OMAP3430_PERIPH_DPLL_MULT_SHIFT			8
-#define OMAP3430_PERIPH_DPLL_MULT_MASK			(0x7ff << 8)
+#define OMAP3430_PERIPH_DPLL_MULT_MASK			(0xfff << 8)
 #define OMAP3430_PERIPH_DPLL_DIV_SHIFT			0
 #define OMAP3430_PERIPH_DPLL_DIV_MASK			(0x7f << 0)
+#define OMAP3630_PERIPH_DPLL_DCO_SEL_SHIFT		21
+#define OMAP3630_PERIPH_DPLL_DCO_SEL_MASK		(0x7 << 21)
+#define OMAP3630_PERIPH_DPLL_SD_DIV_SHIFT		24
+#define OMAP3630_PERIPH_DPLL_SD_DIV_MASK		(0xff << 24)
 
 /* CM_CLKSEL3_PLL */
 #define OMAP3430_DIV_96M_SHIFT				0
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index f48a4b2..3c1194c 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -176,6 +176,8 @@ void __init omap3_check_features(void)
 	OMAP3_CHECK_FEATURE(status, NEON);
 	OMAP3_CHECK_FEATURE(status, ISP);
 
+	if (cpu_is_omap3630())
+		omap3_features |= OMAP3_HAS_JTYPE_DPLL4;
 	/*
 	 * TODO: Get additional info (where applicable)
 	 *       e.g. Size of L2 cache.
@@ -316,7 +318,7 @@ void __init omap3_cpuinfo(void)
 	OMAP3_SHOW_FEATURE(sgx);
 	OMAP3_SHOW_FEATURE(neon);
 	OMAP3_SHOW_FEATURE(isp);
-
+	OMAP3_SHOW_FEATURE(jtype_dpll4);
 	printk(")\n");
 }
 
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index 4b8b0d6..66648d4 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -60,6 +60,9 @@ struct dpll_data {
 	void __iomem		*idlest_reg;
 	u32			autoidle_mask;
 	u32			freqsel_mask;
+	u32			dco_sel_mask;
+	u32			sd_div_mask;
+	u8			jtype;
 	u32			idlest_mask;
 	u8			auto_recal_bit;
 	u8			recal_en_bit;
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index 2e17890..65c08d5 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -497,6 +497,7 @@ extern u32 omap3_features;
 #define OMAP3_HAS_SGX			BIT(2)
 #define OMAP3_HAS_NEON			BIT(3)
 #define OMAP3_HAS_ISP			BIT(4)
+#define OMAP3_HAS_JTYPE_DPLL4		BIT(5)
 
 #define OMAP3_HAS_FEATURE(feat,flag)			\
 static inline unsigned int omap3_has_ ##feat(void)	\
@@ -509,5 +510,5 @@ OMAP3_HAS_FEATURE(sgx, SGX)
 OMAP3_HAS_FEATURE(iva, IVA)
 OMAP3_HAS_FEATURE(neon, NEON)
 OMAP3_HAS_FEATURE(isp, ISP)
-
+OMAP3_HAS_FEATURE(jtype_dpll4, JTYPE_DPLL4)
 #endif
-- 
1.5.6.3


^ permalink raw reply related	[flat|nested] 12+ messages in thread

* [PATCHV2 2/4] OMAP3: Clock Type change for OMAP3 Clocks
  2009-11-20 15:28 ` [PATCHV2 1/4] OMAP3: introduce DPLL4 Jtype Vishwanath BS
@ 2009-11-20 15:28   ` Vishwanath BS
  2009-11-20 15:28     ` [PATCHV2 3/4] OMAP3: Correct width for CLKSEL Fields Vishwanath BS
  2009-11-20 15:44     ` [PATCHV2 2/4] OMAP3: Clock Type change for OMAP3 Clocks Nishanth Menon
  0 siblings, 2 replies; 12+ messages in thread
From: Vishwanath BS @ 2009-11-20 15:28 UTC (permalink / raw)
  To: linux-omap, vishwanath.bs

Signed-off-by: Vishwanath BS <vishwanath.bs@ti.com>
---
 arch/arm/mach-omap2/clock.h             |   15 +-
 arch/arm/mach-omap2/clock34xx.c         |  370 +++++++++++++++---------------
 arch/arm/mach-omap2/clock34xx.h         |  158 +++++++-------
 arch/arm/plat-omap/include/plat/clock.h |    2 +-
 4 files changed, 274 insertions(+), 271 deletions(-)

diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 43b6bed..8ceefcc 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -79,20 +79,23 @@ extern u8 cpu_mask;
 
 /* clksel_rate data common to 24xx/343x */
 static const struct clksel_rate gpt_32k_rates[] = {
-	 { .div = 1, .val = 0, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
+	 { .div = 1, .val = 0, .flags = RATE_IN_24XX | RATE_IN_3XXX |
+							DEFAULT_RATE },
 	 { .div = 0 }
 };
 
 static const struct clksel_rate gpt_sys_rates[] = {
-	 { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
+	 { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_3XXX |
+							DEFAULT_RATE },
 	 { .div = 0 }
 };
 
 static const struct clksel_rate gfx_l3_rates[] = {
-	{ .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X },
-	{ .div = 2, .val = 2, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
-	{ .div = 3, .val = 3, .flags = RATE_IN_243X | RATE_IN_343X },
-	{ .div = 4, .val = 4, .flags = RATE_IN_243X | RATE_IN_343X },
+	{ .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_3XXX },
+	{ .div = 2, .val = 2, .flags = RATE_IN_24XX | RATE_IN_3XXX |
+							DEFAULT_RATE },
+	{ .div = 3, .val = 3, .flags = RATE_IN_243X | RATE_IN_3XXX },
+	{ .div = 4, .val = 4, .flags = RATE_IN_243X | RATE_IN_3XXX },
 	{ .div = 0 }
 };
 
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 832ed0b..167f075 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -94,69 +94,69 @@ struct omap_clk {
 		},			\
 	}
 
-#define CK_343X		(1 << 0)
+#define CK_3XXX		(1 << 0)
 #define CK_3430ES1	(1 << 1)
 #define CK_3430ES2	(1 << 2)
 
 static struct omap_clk omap34xx_clks[] = {
-	CLK(NULL,	"omap_32k_fck",	&omap_32k_fck,	CK_343X),
-	CLK(NULL,	"virt_12m_ck",	&virt_12m_ck,	CK_343X),
-	CLK(NULL,	"virt_13m_ck",	&virt_13m_ck,	CK_343X),
+	CLK(NULL,	"omap_32k_fck",	&omap_32k_fck,	CK_3XXX),
+	CLK(NULL,	"virt_12m_ck",	&virt_12m_ck,	CK_3XXX),
+	CLK(NULL,	"virt_13m_ck",	&virt_13m_ck,	CK_3XXX),
 	CLK(NULL,	"virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2),
-	CLK(NULL,	"virt_19_2m_ck", &virt_19_2m_ck, CK_343X),
-	CLK(NULL,	"virt_26m_ck",	&virt_26m_ck,	CK_343X),
-	CLK(NULL,	"virt_38_4m_ck", &virt_38_4m_ck, CK_343X),
-	CLK(NULL,	"osc_sys_ck",	&osc_sys_ck,	CK_343X),
-	CLK(NULL,	"sys_ck",	&sys_ck,	CK_343X),
-	CLK(NULL,	"sys_altclk",	&sys_altclk,	CK_343X),
-	CLK(NULL,	"mcbsp_clks",	&mcbsp_clks,	CK_343X),
-	CLK(NULL,	"sys_clkout1",	&sys_clkout1,	CK_343X),
-	CLK(NULL,	"dpll1_ck",	&dpll1_ck,	CK_343X),
-	CLK(NULL,	"dpll1_x2_ck",	&dpll1_x2_ck,	CK_343X),
-	CLK(NULL,	"dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_343X),
-	CLK(NULL,	"dpll2_ck",	&dpll2_ck,	CK_343X),
-	CLK(NULL,	"dpll2_m2_ck",	&dpll2_m2_ck,	CK_343X),
-	CLK(NULL,	"dpll3_ck",	&dpll3_ck,	CK_343X),
-	CLK(NULL,	"core_ck",	&core_ck,	CK_343X),
-	CLK(NULL,	"dpll3_x2_ck",	&dpll3_x2_ck,	CK_343X),
-	CLK(NULL,	"dpll3_m2_ck",	&dpll3_m2_ck,	CK_343X),
-	CLK(NULL,	"dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_343X),
-	CLK(NULL,	"dpll3_m3_ck",	&dpll3_m3_ck,	CK_343X),
-	CLK(NULL,	"dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_343X),
-	CLK(NULL,	"emu_core_alwon_ck", &emu_core_alwon_ck, CK_343X),
-	CLK(NULL,	"dpll4_ck",	&dpll4_ck,	CK_343X),
-	CLK(NULL,	"dpll4_x2_ck",	&dpll4_x2_ck,	CK_343X),
-	CLK(NULL,	"omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_343X),
-	CLK(NULL,	"omap_96m_fck",	&omap_96m_fck,	CK_343X),
-	CLK(NULL,	"cm_96m_fck",	&cm_96m_fck,	CK_343X),
-	CLK(NULL,	"omap_54m_fck",	&omap_54m_fck,	CK_343X),
-	CLK(NULL,	"omap_48m_fck",	&omap_48m_fck,	CK_343X),
-	CLK(NULL,	"omap_12m_fck",	&omap_12m_fck,	CK_343X),
-	CLK(NULL,	"dpll4_m2_ck",	&dpll4_m2_ck,	CK_343X),
-	CLK(NULL,	"dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_343X),
-	CLK(NULL,	"dpll4_m3_ck",	&dpll4_m3_ck,	CK_343X),
-	CLK(NULL,	"dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_343X),
-	CLK(NULL,	"dpll4_m4_ck",	&dpll4_m4_ck,	CK_343X),
-	CLK(NULL,	"dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_343X),
-	CLK(NULL,	"dpll4_m5_ck",	&dpll4_m5_ck,	CK_343X),
-	CLK(NULL,	"dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_343X),
-	CLK(NULL,	"dpll4_m6_ck",	&dpll4_m6_ck,	CK_343X),
-	CLK(NULL,	"dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_343X),
-	CLK(NULL,	"emu_per_alwon_ck", &emu_per_alwon_ck, CK_343X),
+	CLK(NULL,	"virt_19_2m_ck", &virt_19_2m_ck, CK_3XXX),
+	CLK(NULL,	"virt_26m_ck",	&virt_26m_ck,	CK_3XXX),
+	CLK(NULL,	"virt_38_4m_ck", &virt_38_4m_ck, CK_3XXX),
+	CLK(NULL,	"osc_sys_ck",	&osc_sys_ck,	CK_3XXX),
+	CLK(NULL,	"sys_ck",	&sys_ck,	CK_3XXX),
+	CLK(NULL,	"sys_altclk",	&sys_altclk,	CK_3XXX),
+	CLK(NULL,	"mcbsp_clks",	&mcbsp_clks,	CK_3XXX),
+	CLK(NULL,	"sys_clkout1",	&sys_clkout1,	CK_3XXX),
+	CLK(NULL,	"dpll1_ck",	&dpll1_ck,	CK_3XXX),
+	CLK(NULL,	"dpll1_x2_ck",	&dpll1_x2_ck,	CK_3XXX),
+	CLK(NULL,	"dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_3XXX),
+	CLK(NULL,	"dpll2_ck",	&dpll2_ck,	CK_3XXX),
+	CLK(NULL,	"dpll2_m2_ck",	&dpll2_m2_ck,	CK_3XXX),
+	CLK(NULL,	"dpll3_ck",	&dpll3_ck,	CK_3XXX),
+	CLK(NULL,	"core_ck",	&core_ck,	CK_3XXX),
+	CLK(NULL,	"dpll3_x2_ck",	&dpll3_x2_ck,	CK_3XXX),
+	CLK(NULL,	"dpll3_m2_ck",	&dpll3_m2_ck,	CK_3XXX),
+	CLK(NULL,	"dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_3XXX),
+	CLK(NULL,	"dpll3_m3_ck",	&dpll3_m3_ck,	CK_3XXX),
+	CLK(NULL,	"dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_3XXX),
+	CLK(NULL,	"emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX),
+	CLK(NULL,	"dpll4_ck",	&dpll4_ck,	CK_3XXX),
+	CLK(NULL,	"dpll4_x2_ck",	&dpll4_x2_ck,	CK_3XXX),
+	CLK(NULL,	"omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_3XXX),
+	CLK(NULL,	"omap_96m_fck",	&omap_96m_fck,	CK_3XXX),
+	CLK(NULL,	"cm_96m_fck",	&cm_96m_fck,	CK_3XXX),
+	CLK(NULL,	"omap_54m_fck",	&omap_54m_fck,	CK_3XXX),
+	CLK(NULL,	"omap_48m_fck",	&omap_48m_fck,	CK_3XXX),
+	CLK(NULL,	"omap_12m_fck",	&omap_12m_fck,	CK_3XXX),
+	CLK(NULL,	"dpll4_m2_ck",	&dpll4_m2_ck,	CK_3XXX),
+	CLK(NULL,	"dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_3XXX),
+	CLK(NULL,	"dpll4_m3_ck",	&dpll4_m3_ck,	CK_3XXX),
+	CLK(NULL,	"dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_3XXX),
+	CLK(NULL,	"dpll4_m4_ck",	&dpll4_m4_ck,	CK_3XXX),
+	CLK(NULL,	"dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_3XXX),
+	CLK(NULL,	"dpll4_m5_ck",	&dpll4_m5_ck,	CK_3XXX),
+	CLK(NULL,	"dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_3XXX),
+	CLK(NULL,	"dpll4_m6_ck",	&dpll4_m6_ck,	CK_3XXX),
+	CLK(NULL,	"dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX),
+	CLK(NULL,	"emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX),
 	CLK(NULL,	"dpll5_ck",	&dpll5_ck,	CK_3430ES2),
 	CLK(NULL,	"dpll5_m2_ck",	&dpll5_m2_ck,	CK_3430ES2),
-	CLK(NULL,	"clkout2_src_ck", &clkout2_src_ck, CK_343X),
-	CLK(NULL,	"sys_clkout2",	&sys_clkout2,	CK_343X),
-	CLK(NULL,	"corex2_fck",	&corex2_fck,	CK_343X),
-	CLK(NULL,	"dpll1_fck",	&dpll1_fck,	CK_343X),
-	CLK(NULL,	"mpu_ck",	&mpu_ck,	CK_343X),
-	CLK(NULL,	"arm_fck",	&arm_fck,	CK_343X),
-	CLK(NULL,	"emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_343X),
-	CLK(NULL,	"dpll2_fck",	&dpll2_fck,	CK_343X),
-	CLK(NULL,	"iva2_ck",	&iva2_ck,	CK_343X),
-	CLK(NULL,	"l3_ick",	&l3_ick,	CK_343X),
-	CLK(NULL,	"l4_ick",	&l4_ick,	CK_343X),
-	CLK(NULL,	"rm_ick",	&rm_ick,	CK_343X),
+	CLK(NULL,	"clkout2_src_ck", &clkout2_src_ck, CK_3XXX),
+	CLK(NULL,	"sys_clkout2",	&sys_clkout2,	CK_3XXX),
+	CLK(NULL,	"corex2_fck",	&corex2_fck,	CK_3XXX),
+	CLK(NULL,	"dpll1_fck",	&dpll1_fck,	CK_3XXX),
+	CLK(NULL,	"mpu_ck",	&mpu_ck,	CK_3XXX),
+	CLK(NULL,	"arm_fck",	&arm_fck,	CK_3XXX),
+	CLK(NULL,	"emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX),
+	CLK(NULL,	"dpll2_fck",	&dpll2_fck,	CK_3XXX),
+	CLK(NULL,	"iva2_ck",	&iva2_ck,	CK_3XXX),
+	CLK(NULL,	"l3_ick",	&l3_ick,	CK_3XXX),
+	CLK(NULL,	"l4_ick",	&l4_ick,	CK_3XXX),
+	CLK(NULL,	"rm_ick",	&rm_ick,	CK_3XXX),
 	CLK(NULL,	"gfx_l3_ck",	&gfx_l3_ck,	CK_3430ES1),
 	CLK(NULL,	"gfx_l3_fck",	&gfx_l3_fck,	CK_3430ES1),
 	CLK(NULL,	"gfx_l3_ick",	&gfx_l3_ick,	CK_3430ES1),
@@ -165,159 +165,159 @@ static struct omap_clk omap34xx_clks[] = {
 	CLK(NULL,	"sgx_fck",	&sgx_fck,	CK_3430ES2),
 	CLK(NULL,	"sgx_ick",	&sgx_ick,	CK_3430ES2),
 	CLK(NULL,	"d2d_26m_fck",	&d2d_26m_fck,	CK_3430ES1),
-	CLK(NULL,	"modem_fck",	&modem_fck,	CK_343X),
-	CLK(NULL,	"sad2d_ick",	&sad2d_ick,	CK_343X),
-	CLK(NULL,	"mad2d_ick",	&mad2d_ick,	CK_343X),
-	CLK(NULL,	"gpt10_fck",	&gpt10_fck,	CK_343X),
-	CLK(NULL,	"gpt11_fck",	&gpt11_fck,	CK_343X),
+	CLK(NULL,	"modem_fck",	&modem_fck,	CK_3XXX),
+	CLK(NULL,	"sad2d_ick",	&sad2d_ick,	CK_3XXX),
+	CLK(NULL,	"mad2d_ick",	&mad2d_ick,	CK_3XXX),
+	CLK(NULL,	"gpt10_fck",	&gpt10_fck,	CK_3XXX),
+	CLK(NULL,	"gpt11_fck",	&gpt11_fck,	CK_3XXX),
 	CLK(NULL,	"cpefuse_fck",	&cpefuse_fck,	CK_3430ES2),
 	CLK(NULL,	"ts_fck",	&ts_fck,	CK_3430ES2),
 	CLK(NULL,	"usbtll_fck",	&usbtll_fck,	CK_3430ES2),
-	CLK(NULL,	"core_96m_fck",	&core_96m_fck,	CK_343X),
+	CLK(NULL,	"core_96m_fck",	&core_96m_fck,	CK_3XXX),
 	CLK("mmci-omap-hs.2",	"fck",	&mmchs3_fck,	CK_3430ES2),
-	CLK("mmci-omap-hs.1",	"fck",	&mmchs2_fck,	CK_343X),
-	CLK(NULL,	"mspro_fck",	&mspro_fck,	CK_343X),
-	CLK("mmci-omap-hs.0",	"fck",	&mmchs1_fck,	CK_343X),
-	CLK("i2c_omap.3", "fck",	&i2c3_fck,	CK_343X),
-	CLK("i2c_omap.2", "fck",	&i2c2_fck,	CK_343X),
-	CLK("i2c_omap.1", "fck",	&i2c1_fck,	CK_343X),
-	CLK("omap-mcbsp.5", "fck",	&mcbsp5_fck,	CK_343X),
-	CLK("omap-mcbsp.1", "fck",	&mcbsp1_fck,	CK_343X),
-	CLK(NULL,	"core_48m_fck",	&core_48m_fck,	CK_343X),
-	CLK("omap2_mcspi.4", "fck",	&mcspi4_fck,	CK_343X),
-	CLK("omap2_mcspi.3", "fck",	&mcspi3_fck,	CK_343X),
-	CLK("omap2_mcspi.2", "fck",	&mcspi2_fck,	CK_343X),
-	CLK("omap2_mcspi.1", "fck",	&mcspi1_fck,	CK_343X),
-	CLK(NULL,	"uart2_fck",	&uart2_fck,	CK_343X),
-	CLK(NULL,	"uart1_fck",	&uart1_fck,	CK_343X),
+	CLK("mmci-omap-hs.1",	"fck",	&mmchs2_fck,	CK_3XXX),
+	CLK(NULL,	"mspro_fck",	&mspro_fck,	CK_3XXX),
+	CLK("mmci-omap-hs.0",	"fck",	&mmchs1_fck,	CK_3XXX),
+	CLK("i2c_omap.3", "fck",	&i2c3_fck,	CK_3XXX),
+	CLK("i2c_omap.2", "fck",	&i2c2_fck,	CK_3XXX),
+	CLK("i2c_omap.1", "fck",	&i2c1_fck,	CK_3XXX),
+	CLK("omap-mcbsp.5", "fck",	&mcbsp5_fck,	CK_3XXX),
+	CLK("omap-mcbsp.1", "fck",	&mcbsp1_fck,	CK_3XXX),
+	CLK(NULL,	"core_48m_fck",	&core_48m_fck,	CK_3XXX),
+	CLK("omap2_mcspi.4", "fck",	&mcspi4_fck,	CK_3XXX),
+	CLK("omap2_mcspi.3", "fck",	&mcspi3_fck,	CK_3XXX),
+	CLK("omap2_mcspi.2", "fck",	&mcspi2_fck,	CK_3XXX),
+	CLK("omap2_mcspi.1", "fck",	&mcspi1_fck,	CK_3XXX),
+	CLK(NULL,	"uart2_fck",	&uart2_fck,	CK_3XXX),
+	CLK(NULL,	"uart1_fck",	&uart1_fck,	CK_3XXX),
 	CLK(NULL,	"fshostusb_fck", &fshostusb_fck, CK_3430ES1),
-	CLK(NULL,	"core_12m_fck",	&core_12m_fck,	CK_343X),
-	CLK("omap_hdq.0", "fck",	&hdq_fck,	CK_343X),
+	CLK(NULL,	"core_12m_fck",	&core_12m_fck,	CK_3XXX),
+	CLK("omap_hdq.0", "fck",	&hdq_fck,	CK_3XXX),
 	CLK(NULL,	"ssi_ssr_fck",	&ssi_ssr_fck_3430es1,	CK_3430ES1),
 	CLK(NULL,	"ssi_ssr_fck",	&ssi_ssr_fck_3430es2,	CK_3430ES2),
 	CLK(NULL,	"ssi_sst_fck",	&ssi_sst_fck_3430es1,	CK_3430ES1),
 	CLK(NULL,	"ssi_sst_fck",	&ssi_sst_fck_3430es2,	CK_3430ES2),
-	CLK(NULL,	"core_l3_ick",	&core_l3_ick,	CK_343X),
+	CLK(NULL,	"core_l3_ick",	&core_l3_ick,	CK_3XXX),
 	CLK("musb_hdrc",	"ick",	&hsotgusb_ick_3430es1,	CK_3430ES1),
 	CLK("musb_hdrc",	"ick",	&hsotgusb_ick_3430es2,	CK_3430ES2),
-	CLK(NULL,	"sdrc_ick",	&sdrc_ick,	CK_343X),
-	CLK(NULL,	"gpmc_fck",	&gpmc_fck,	CK_343X),
-	CLK(NULL,	"security_l3_ick", &security_l3_ick, CK_343X),
-	CLK(NULL,	"pka_ick",	&pka_ick,	CK_343X),
-	CLK(NULL,	"core_l4_ick",	&core_l4_ick,	CK_343X),
+	CLK(NULL,	"sdrc_ick",	&sdrc_ick,	CK_3XXX),
+	CLK(NULL,	"gpmc_fck",	&gpmc_fck,	CK_3XXX),
+	CLK(NULL,	"security_l3_ick", &security_l3_ick, CK_3XXX),
+	CLK(NULL,	"pka_ick",	&pka_ick,	CK_3XXX),
+	CLK(NULL,	"core_l4_ick",	&core_l4_ick,	CK_3XXX),
 	CLK(NULL,	"usbtll_ick",	&usbtll_ick,	CK_3430ES2),
 	CLK("mmci-omap-hs.2",	"ick",	&mmchs3_ick,	CK_3430ES2),
-	CLK(NULL,	"icr_ick",	&icr_ick,	CK_343X),
-	CLK(NULL,	"aes2_ick",	&aes2_ick,	CK_343X),
-	CLK(NULL,	"sha12_ick",	&sha12_ick,	CK_343X),
-	CLK(NULL,	"des2_ick",	&des2_ick,	CK_343X),
-	CLK("mmci-omap-hs.1",	"ick",	&mmchs2_ick,	CK_343X),
-	CLK("mmci-omap-hs.0",	"ick",	&mmchs1_ick,	CK_343X),
-	CLK(NULL,	"mspro_ick",	&mspro_ick,	CK_343X),
-	CLK("omap_hdq.0", "ick",	&hdq_ick,	CK_343X),
-	CLK("omap2_mcspi.4", "ick",	&mcspi4_ick,	CK_343X),
-	CLK("omap2_mcspi.3", "ick",	&mcspi3_ick,	CK_343X),
-	CLK("omap2_mcspi.2", "ick",	&mcspi2_ick,	CK_343X),
-	CLK("omap2_mcspi.1", "ick",	&mcspi1_ick,	CK_343X),
-	CLK("i2c_omap.3", "ick",	&i2c3_ick,	CK_343X),
-	CLK("i2c_omap.2", "ick",	&i2c2_ick,	CK_343X),
-	CLK("i2c_omap.1", "ick",	&i2c1_ick,	CK_343X),
-	CLK(NULL,	"uart2_ick",	&uart2_ick,	CK_343X),
-	CLK(NULL,	"uart1_ick",	&uart1_ick,	CK_343X),
-	CLK(NULL,	"gpt11_ick",	&gpt11_ick,	CK_343X),
-	CLK(NULL,	"gpt10_ick",	&gpt10_ick,	CK_343X),
-	CLK("omap-mcbsp.5", "ick",	&mcbsp5_ick,	CK_343X),
-	CLK("omap-mcbsp.1", "ick",	&mcbsp1_ick,	CK_343X),
+	CLK(NULL,	"icr_ick",	&icr_ick,	CK_3XXX),
+	CLK(NULL,	"aes2_ick",	&aes2_ick,	CK_3XXX),
+	CLK(NULL,	"sha12_ick",	&sha12_ick,	CK_3XXX),
+	CLK(NULL,	"des2_ick",	&des2_ick,	CK_3XXX),
+	CLK("mmci-omap-hs.1",	"ick",	&mmchs2_ick,	CK_3XXX),
+	CLK("mmci-omap-hs.0",	"ick",	&mmchs1_ick,	CK_3XXX),
+	CLK(NULL,	"mspro_ick",	&mspro_ick,	CK_3XXX),
+	CLK("omap_hdq.0", "ick",	&hdq_ick,	CK_3XXX),
+	CLK("omap2_mcspi.4", "ick",	&mcspi4_ick,	CK_3XXX),
+	CLK("omap2_mcspi.3", "ick",	&mcspi3_ick,	CK_3XXX),
+	CLK("omap2_mcspi.2", "ick",	&mcspi2_ick,	CK_3XXX),
+	CLK("omap2_mcspi.1", "ick",	&mcspi1_ick,	CK_3XXX),
+	CLK("i2c_omap.3", "ick",	&i2c3_ick,	CK_3XXX),
+	CLK("i2c_omap.2", "ick",	&i2c2_ick,	CK_3XXX),
+	CLK("i2c_omap.1", "ick",	&i2c1_ick,	CK_3XXX),
+	CLK(NULL,	"uart2_ick",	&uart2_ick,	CK_3XXX),
+	CLK(NULL,	"uart1_ick",	&uart1_ick,	CK_3XXX),
+	CLK(NULL,	"gpt11_ick",	&gpt11_ick,	CK_3XXX),
+	CLK(NULL,	"gpt10_ick",	&gpt10_ick,	CK_3XXX),
+	CLK("omap-mcbsp.5", "ick",	&mcbsp5_ick,	CK_3XXX),
+	CLK("omap-mcbsp.1", "ick",	&mcbsp1_ick,	CK_3XXX),
 	CLK(NULL,	"fac_ick",	&fac_ick,	CK_3430ES1),
-	CLK(NULL,	"mailboxes_ick", &mailboxes_ick, CK_343X),
-	CLK(NULL,	"omapctrl_ick",	&omapctrl_ick,	CK_343X),
-	CLK(NULL,	"ssi_l4_ick",	&ssi_l4_ick,	CK_343X),
+	CLK(NULL,	"mailboxes_ick", &mailboxes_ick, CK_3XXX),
+	CLK(NULL,	"omapctrl_ick",	&omapctrl_ick,	CK_3XXX),
+	CLK(NULL,	"ssi_l4_ick",	&ssi_l4_ick,	CK_3XXX),
 	CLK(NULL,	"ssi_ick",	&ssi_ick_3430es1,	CK_3430ES1),
 	CLK(NULL,	"ssi_ick",	&ssi_ick_3430es2,	CK_3430ES2),
 	CLK(NULL,	"usb_l4_ick",	&usb_l4_ick,	CK_3430ES1),
-	CLK(NULL,	"security_l4_ick2", &security_l4_ick2, CK_343X),
-	CLK(NULL,	"aes1_ick",	&aes1_ick,	CK_343X),
-	CLK("omap_rng",	"ick",		&rng_ick,	CK_343X),
-	CLK(NULL,	"sha11_ick",	&sha11_ick,	CK_343X),
-	CLK(NULL,	"des1_ick",	&des1_ick,	CK_343X),
+	CLK(NULL,	"security_l4_ick2", &security_l4_ick2, CK_3XXX),
+	CLK(NULL,	"aes1_ick",	&aes1_ick,	CK_3XXX),
+	CLK("omap_rng",	"ick",		&rng_ick,	CK_3XXX),
+	CLK(NULL,	"sha11_ick",	&sha11_ick,	CK_3XXX),
+	CLK(NULL,	"des1_ick",	&des1_ick,	CK_3XXX),
 	CLK("omapfb",	"dss1_fck",	&dss1_alwon_fck_3430es1, CK_3430ES1),
 	CLK("omapfb",	"dss1_fck",	&dss1_alwon_fck_3430es2, CK_3430ES2),
-	CLK("omapfb",	"tv_fck",	&dss_tv_fck,	CK_343X),
-	CLK("omapfb",	"video_fck",	&dss_96m_fck,	CK_343X),
-	CLK("omapfb",	"dss2_fck",	&dss2_alwon_fck, CK_343X),
+	CLK("omapfb",	"tv_fck",	&dss_tv_fck,	CK_3XXX),
+	CLK("omapfb",	"video_fck",	&dss_96m_fck,	CK_3XXX),
+	CLK("omapfb",	"dss2_fck",	&dss2_alwon_fck, CK_3XXX),
 	CLK("omapfb",	"ick",		&dss_ick_3430es1,	CK_3430ES1),
 	CLK("omapfb",	"ick",		&dss_ick_3430es2,	CK_3430ES2),
-	CLK(NULL,	"cam_mclk",	&cam_mclk,	CK_343X),
-	CLK(NULL,	"cam_ick",	&cam_ick,	CK_343X),
-	CLK(NULL,	"csi2_96m_fck",	&csi2_96m_fck,	CK_343X),
+	CLK(NULL,	"cam_mclk",	&cam_mclk,	CK_3XXX),
+	CLK(NULL,	"cam_ick",	&cam_ick,	CK_3XXX),
+	CLK(NULL,	"csi2_96m_fck",	&csi2_96m_fck,	CK_3XXX),
 	CLK(NULL,	"usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2),
 	CLK(NULL,	"usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2),
 	CLK(NULL,	"usbhost_ick",	&usbhost_ick,	CK_3430ES2),
 	CLK(NULL,	"usim_fck",	&usim_fck,	CK_3430ES2),
-	CLK(NULL,	"gpt1_fck",	&gpt1_fck,	CK_343X),
-	CLK(NULL,	"wkup_32k_fck",	&wkup_32k_fck,	CK_343X),
-	CLK(NULL,	"gpio1_dbck",	&gpio1_dbck,	CK_343X),
-	CLK("omap_wdt",	"fck",		&wdt2_fck,	CK_343X),
-	CLK(NULL,	"wkup_l4_ick",	&wkup_l4_ick,	CK_343X),
+	CLK(NULL,	"gpt1_fck",	&gpt1_fck,	CK_3XXX),
+	CLK(NULL,	"wkup_32k_fck",	&wkup_32k_fck,	CK_3XXX),
+	CLK(NULL,	"gpio1_dbck",	&gpio1_dbck,	CK_3XXX),
+	CLK("omap_wdt",	"fck",		&wdt2_fck,	CK_3XXX),
+	CLK(NULL,	"wkup_l4_ick",	&wkup_l4_ick,	CK_3XXX),
 	CLK(NULL,	"usim_ick",	&usim_ick,	CK_3430ES2),
-	CLK("omap_wdt",	"ick",		&wdt2_ick,	CK_343X),
-	CLK(NULL,	"wdt1_ick",	&wdt1_ick,	CK_343X),
-	CLK(NULL,	"gpio1_ick",	&gpio1_ick,	CK_343X),
-	CLK(NULL,	"omap_32ksync_ick", &omap_32ksync_ick, CK_343X),
-	CLK(NULL,	"gpt12_ick",	&gpt12_ick,	CK_343X),
-	CLK(NULL,	"gpt1_ick",	&gpt1_ick,	CK_343X),
-	CLK(NULL,	"per_96m_fck",	&per_96m_fck,	CK_343X),
-	CLK(NULL,	"per_48m_fck",	&per_48m_fck,	CK_343X),
-	CLK(NULL,	"uart3_fck",	&uart3_fck,	CK_343X),
-	CLK(NULL,	"gpt2_fck",	&gpt2_fck,	CK_343X),
-	CLK(NULL,	"gpt3_fck",	&gpt3_fck,	CK_343X),
-	CLK(NULL,	"gpt4_fck",	&gpt4_fck,	CK_343X),
-	CLK(NULL,	"gpt5_fck",	&gpt5_fck,	CK_343X),
-	CLK(NULL,	"gpt6_fck",	&gpt6_fck,	CK_343X),
-	CLK(NULL,	"gpt7_fck",	&gpt7_fck,	CK_343X),
-	CLK(NULL,	"gpt8_fck",	&gpt8_fck,	CK_343X),
-	CLK(NULL,	"gpt9_fck",	&gpt9_fck,	CK_343X),
-	CLK(NULL,	"per_32k_alwon_fck", &per_32k_alwon_fck, CK_343X),
-	CLK(NULL,	"gpio6_dbck",	&gpio6_dbck,	CK_343X),
-	CLK(NULL,	"gpio5_dbck",	&gpio5_dbck,	CK_343X),
-	CLK(NULL,	"gpio4_dbck",	&gpio4_dbck,	CK_343X),
-	CLK(NULL,	"gpio3_dbck",	&gpio3_dbck,	CK_343X),
-	CLK(NULL,	"gpio2_dbck",	&gpio2_dbck,	CK_343X),
-	CLK(NULL,	"wdt3_fck",	&wdt3_fck,	CK_343X),
-	CLK(NULL,	"per_l4_ick",	&per_l4_ick,	CK_343X),
-	CLK(NULL,	"gpio6_ick",	&gpio6_ick,	CK_343X),
-	CLK(NULL,	"gpio5_ick",	&gpio5_ick,	CK_343X),
-	CLK(NULL,	"gpio4_ick",	&gpio4_ick,	CK_343X),
-	CLK(NULL,	"gpio3_ick",	&gpio3_ick,	CK_343X),
-	CLK(NULL,	"gpio2_ick",	&gpio2_ick,	CK_343X),
-	CLK(NULL,	"wdt3_ick",	&wdt3_ick,	CK_343X),
-	CLK(NULL,	"uart3_ick",	&uart3_ick,	CK_343X),
-	CLK(NULL,	"gpt9_ick",	&gpt9_ick,	CK_343X),
-	CLK(NULL,	"gpt8_ick",	&gpt8_ick,	CK_343X),
-	CLK(NULL,	"gpt7_ick",	&gpt7_ick,	CK_343X),
-	CLK(NULL,	"gpt6_ick",	&gpt6_ick,	CK_343X),
-	CLK(NULL,	"gpt5_ick",	&gpt5_ick,	CK_343X),
-	CLK(NULL,	"gpt4_ick",	&gpt4_ick,	CK_343X),
-	CLK(NULL,	"gpt3_ick",	&gpt3_ick,	CK_343X),
-	CLK(NULL,	"gpt2_ick",	&gpt2_ick,	CK_343X),
-	CLK("omap-mcbsp.2", "ick",	&mcbsp2_ick,	CK_343X),
-	CLK("omap-mcbsp.3", "ick",	&mcbsp3_ick,	CK_343X),
-	CLK("omap-mcbsp.4", "ick",	&mcbsp4_ick,	CK_343X),
-	CLK("omap-mcbsp.2", "fck",	&mcbsp2_fck,	CK_343X),
-	CLK("omap-mcbsp.3", "fck",	&mcbsp3_fck,	CK_343X),
-	CLK("omap-mcbsp.4", "fck",	&mcbsp4_fck,	CK_343X),
-	CLK(NULL,	"emu_src_ck",	&emu_src_ck,	CK_343X),
-	CLK(NULL,	"pclk_fck",	&pclk_fck,	CK_343X),
-	CLK(NULL,	"pclkx2_fck",	&pclkx2_fck,	CK_343X),
-	CLK(NULL,	"atclk_fck",	&atclk_fck,	CK_343X),
-	CLK(NULL,	"traceclk_src_fck", &traceclk_src_fck, CK_343X),
-	CLK(NULL,	"traceclk_fck",	&traceclk_fck,	CK_343X),
-	CLK(NULL,	"sr1_fck",	&sr1_fck,	CK_343X),
-	CLK(NULL,	"sr2_fck",	&sr2_fck,	CK_343X),
-	CLK(NULL,	"sr_l4_ick",	&sr_l4_ick,	CK_343X),
-	CLK(NULL,	"secure_32k_fck", &secure_32k_fck, CK_343X),
-	CLK(NULL,	"gpt12_fck",	&gpt12_fck,	CK_343X),
-	CLK(NULL,	"wdt1_fck",	&wdt1_fck,	CK_343X),
+	CLK("omap_wdt",	"ick",		&wdt2_ick,	CK_3XXX),
+	CLK(NULL,	"wdt1_ick",	&wdt1_ick,	CK_3XXX),
+	CLK(NULL,	"gpio1_ick",	&gpio1_ick,	CK_3XXX),
+	CLK(NULL,	"omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX),
+	CLK(NULL,	"gpt12_ick",	&gpt12_ick,	CK_3XXX),
+	CLK(NULL,	"gpt1_ick",	&gpt1_ick,	CK_3XXX),
+	CLK(NULL,	"per_96m_fck",	&per_96m_fck,	CK_3XXX),
+	CLK(NULL,	"per_48m_fck",	&per_48m_fck,	CK_3XXX),
+	CLK(NULL,	"uart3_fck",	&uart3_fck,	CK_3XXX),
+	CLK(NULL,	"gpt2_fck",	&gpt2_fck,	CK_3XXX),
+	CLK(NULL,	"gpt3_fck",	&gpt3_fck,	CK_3XXX),
+	CLK(NULL,	"gpt4_fck",	&gpt4_fck,	CK_3XXX),
+	CLK(NULL,	"gpt5_fck",	&gpt5_fck,	CK_3XXX),
+	CLK(NULL,	"gpt6_fck",	&gpt6_fck,	CK_3XXX),
+	CLK(NULL,	"gpt7_fck",	&gpt7_fck,	CK_3XXX),
+	CLK(NULL,	"gpt8_fck",	&gpt8_fck,	CK_3XXX),
+	CLK(NULL,	"gpt9_fck",	&gpt9_fck,	CK_3XXX),
+	CLK(NULL,	"per_32k_alwon_fck", &per_32k_alwon_fck, CK_3XXX),
+	CLK(NULL,	"gpio6_dbck",	&gpio6_dbck,	CK_3XXX),
+	CLK(NULL,	"gpio5_dbck",	&gpio5_dbck,	CK_3XXX),
+	CLK(NULL,	"gpio4_dbck",	&gpio4_dbck,	CK_3XXX),
+	CLK(NULL,	"gpio3_dbck",	&gpio3_dbck,	CK_3XXX),
+	CLK(NULL,	"gpio2_dbck",	&gpio2_dbck,	CK_3XXX),
+	CLK(NULL,	"wdt3_fck",	&wdt3_fck,	CK_3XXX),
+	CLK(NULL,	"per_l4_ick",	&per_l4_ick,	CK_3XXX),
+	CLK(NULL,	"gpio6_ick",	&gpio6_ick,	CK_3XXX),
+	CLK(NULL,	"gpio5_ick",	&gpio5_ick,	CK_3XXX),
+	CLK(NULL,	"gpio4_ick",	&gpio4_ick,	CK_3XXX),
+	CLK(NULL,	"gpio3_ick",	&gpio3_ick,	CK_3XXX),
+	CLK(NULL,	"gpio2_ick",	&gpio2_ick,	CK_3XXX),
+	CLK(NULL,	"wdt3_ick",	&wdt3_ick,	CK_3XXX),
+	CLK(NULL,	"uart3_ick",	&uart3_ick,	CK_3XXX),
+	CLK(NULL,	"gpt9_ick",	&gpt9_ick,	CK_3XXX),
+	CLK(NULL,	"gpt8_ick",	&gpt8_ick,	CK_3XXX),
+	CLK(NULL,	"gpt7_ick",	&gpt7_ick,	CK_3XXX),
+	CLK(NULL,	"gpt6_ick",	&gpt6_ick,	CK_3XXX),
+	CLK(NULL,	"gpt5_ick",	&gpt5_ick,	CK_3XXX),
+	CLK(NULL,	"gpt4_ick",	&gpt4_ick,	CK_3XXX),
+	CLK(NULL,	"gpt3_ick",	&gpt3_ick,	CK_3XXX),
+	CLK(NULL,	"gpt2_ick",	&gpt2_ick,	CK_3XXX),
+	CLK("omap-mcbsp.2", "ick",	&mcbsp2_ick,	CK_3XXX),
+	CLK("omap-mcbsp.3", "ick",	&mcbsp3_ick,	CK_3XXX),
+	CLK("omap-mcbsp.4", "ick",	&mcbsp4_ick,	CK_3XXX),
+	CLK("omap-mcbsp.2", "fck",	&mcbsp2_fck,	CK_3XXX),
+	CLK("omap-mcbsp.3", "fck",	&mcbsp3_fck,	CK_3XXX),
+	CLK("omap-mcbsp.4", "fck",	&mcbsp4_fck,	CK_3XXX),
+	CLK(NULL,	"emu_src_ck",	&emu_src_ck,	CK_3XXX),
+	CLK(NULL,	"pclk_fck",	&pclk_fck,	CK_3XXX),
+	CLK(NULL,	"pclkx2_fck",	&pclkx2_fck,	CK_3XXX),
+	CLK(NULL,	"atclk_fck",	&atclk_fck,	CK_3XXX),
+	CLK(NULL,	"traceclk_src_fck", &traceclk_src_fck, CK_3XXX),
+	CLK(NULL,	"traceclk_fck",	&traceclk_fck,	CK_3XXX),
+	CLK(NULL,	"sr1_fck",	&sr1_fck,	CK_3XXX),
+	CLK(NULL,	"sr2_fck",	&sr2_fck,	CK_3XXX),
+	CLK(NULL,	"sr_l4_ick",	&sr_l4_ick,	CK_3XXX),
+	CLK(NULL,	"secure_32k_fck", &secure_32k_fck, CK_3XXX),
+	CLK(NULL,	"gpt12_fck",	&gpt12_fck,	CK_3XXX),
+	CLK(NULL,	"wdt1_fck",	&wdt1_fck,	CK_3XXX),
 };
 
 /* CM_AUTOIDLE_PLL*.AUTO_* bit values */
@@ -1202,8 +1202,8 @@ int __init omap2_clk_init(void)
 	u32 cpu_clkflg;
 
 	if (cpu_is_omap34xx()) {
-		cpu_mask = RATE_IN_343X;
-		cpu_clkflg = CK_343X;
+		cpu_mask = RATE_IN_3XXX;
+		cpu_clkflg = CK_3XXX;
 
 		/*
 		 * Update this if there are further clock changes between ES2
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index a1b3de7..813a83e 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -120,12 +120,12 @@ static struct clk virt_38_4m_ck = {
 };
 
 static const struct clksel_rate osc_sys_12m_rates[] = {
-	{ .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+	{ .div = 1, .val = 0, .flags = RATE_IN_3XXX | DEFAULT_RATE },
 	{ .div = 0 }
 };
 
 static const struct clksel_rate osc_sys_13m_rates[] = {
-	{ .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+	{ .div = 1, .val = 1, .flags = RATE_IN_3XXX | DEFAULT_RATE },
 	{ .div = 0 }
 };
 
@@ -135,17 +135,17 @@ static const struct clksel_rate osc_sys_16_8m_rates[] = {
 };
 
 static const struct clksel_rate osc_sys_19_2m_rates[] = {
-	{ .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
+	{ .div = 1, .val = 2, .flags = RATE_IN_3XXX | DEFAULT_RATE },
 	{ .div = 0 }
 };
 
 static const struct clksel_rate osc_sys_26m_rates[] = {
-	{ .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
+	{ .div = 1, .val = 3, .flags = RATE_IN_3XXX | DEFAULT_RATE },
 	{ .div = 0 }
 };
 
 static const struct clksel_rate osc_sys_38_4m_rates[] = {
-	{ .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
+	{ .div = 1, .val = 4, .flags = RATE_IN_3XXX | DEFAULT_RATE },
 	{ .div = 0 }
 };
 
@@ -174,8 +174,8 @@ static struct clk osc_sys_ck = {
 };
 
 static const struct clksel_rate div2_rates[] = {
-	{ .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
-	{ .div = 2, .val = 2, .flags = RATE_IN_343X },
+	{ .div = 1, .val = 1, .flags = RATE_IN_3XXX | DEFAULT_RATE },
+	{ .div = 2, .val = 2, .flags = RATE_IN_3XXX },
 	{ .div = 0 }
 };
 
@@ -224,22 +224,22 @@ static struct clk sys_clkout1 = {
 /* CM CLOCKS */
 
 static const struct clksel_rate div16_dpll_rates[] = {
-	{ .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
-	{ .div = 2, .val = 2, .flags = RATE_IN_343X },
-	{ .div = 3, .val = 3, .flags = RATE_IN_343X },
-	{ .div = 4, .val = 4, .flags = RATE_IN_343X },
-	{ .div = 5, .val = 5, .flags = RATE_IN_343X },
-	{ .div = 6, .val = 6, .flags = RATE_IN_343X },
-	{ .div = 7, .val = 7, .flags = RATE_IN_343X },
-	{ .div = 8, .val = 8, .flags = RATE_IN_343X },
-	{ .div = 9, .val = 9, .flags = RATE_IN_343X },
-	{ .div = 10, .val = 10, .flags = RATE_IN_343X },
-	{ .div = 11, .val = 11, .flags = RATE_IN_343X },
-	{ .div = 12, .val = 12, .flags = RATE_IN_343X },
-	{ .div = 13, .val = 13, .flags = RATE_IN_343X },
-	{ .div = 14, .val = 14, .flags = RATE_IN_343X },
-	{ .div = 15, .val = 15, .flags = RATE_IN_343X },
-	{ .div = 16, .val = 16, .flags = RATE_IN_343X },
+	{ .div = 1, .val = 1, .flags = RATE_IN_3XXX | DEFAULT_RATE },
+	{ .div = 2, .val = 2, .flags = RATE_IN_3XXX },
+	{ .div = 3, .val = 3, .flags = RATE_IN_3XXX },
+	{ .div = 4, .val = 4, .flags = RATE_IN_3XXX },
+	{ .div = 5, .val = 5, .flags = RATE_IN_3XXX },
+	{ .div = 6, .val = 6, .flags = RATE_IN_3XXX },
+	{ .div = 7, .val = 7, .flags = RATE_IN_3XXX },
+	{ .div = 8, .val = 8, .flags = RATE_IN_3XXX },
+	{ .div = 9, .val = 9, .flags = RATE_IN_3XXX },
+	{ .div = 10, .val = 10, .flags = RATE_IN_3XXX },
+	{ .div = 11, .val = 11, .flags = RATE_IN_3XXX },
+	{ .div = 12, .val = 12, .flags = RATE_IN_3XXX },
+	{ .div = 13, .val = 13, .flags = RATE_IN_3XXX },
+	{ .div = 14, .val = 14, .flags = RATE_IN_3XXX },
+	{ .div = 15, .val = 15, .flags = RATE_IN_3XXX },
+	{ .div = 16, .val = 16, .flags = RATE_IN_3XXX },
 	{ .div = 0 }
 };
 
@@ -425,8 +425,8 @@ static struct clk dpll3_x2_ck = {
 };
 
 static const struct clksel_rate div31_dpll3_rates[] = {
-	{ .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
-	{ .div = 2, .val = 2, .flags = RATE_IN_343X },
+	{ .div = 1, .val = 1, .flags = RATE_IN_3XXX | DEFAULT_RATE },
+	{ .div = 2, .val = 2, .flags = RATE_IN_3XXX },
 	{ .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
 	{ .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
 	{ .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
@@ -634,12 +634,12 @@ static struct clk cm_96m_fck = {
 };
 
 static const struct clksel_rate omap_96m_dpll_rates[] = {
-	{ .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+	{ .div = 1, .val = 0, .flags = RATE_IN_3XXX | DEFAULT_RATE },
 	{ .div = 0 }
 };
 
 static const struct clksel_rate omap_96m_sys_rates[] = {
-	{ .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+	{ .div = 1, .val = 1, .flags = RATE_IN_3XXX | DEFAULT_RATE },
 	{ .div = 0 }
 };
 
@@ -687,12 +687,12 @@ static struct clk dpll4_m3x2_ck = {
 };
 
 static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
-	{ .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+	{ .div = 1, .val = 0, .flags = RATE_IN_3XXX | DEFAULT_RATE },
 	{ .div = 0 }
 };
 
 static const struct clksel_rate omap_54m_alt_rates[] = {
-	{ .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+	{ .div = 1, .val = 1, .flags = RATE_IN_3XXX | DEFAULT_RATE },
 	{ .div = 0 }
 };
 
@@ -713,12 +713,12 @@ static struct clk omap_54m_fck = {
 };
 
 static const struct clksel_rate omap_48m_cm96m_rates[] = {
-	{ .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+	{ .div = 2, .val = 0, .flags = RATE_IN_3XXX | DEFAULT_RATE },
 	{ .div = 0 }
 };
 
 static const struct clksel_rate omap_48m_alt_rates[] = {
-	{ .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+	{ .div = 1, .val = 1, .flags = RATE_IN_3XXX | DEFAULT_RATE },
 	{ .div = 0 }
 };
 
@@ -890,22 +890,22 @@ static struct clk dpll5_m2_ck = {
 /* CM EXTERNAL CLOCK OUTPUTS */
 
 static const struct clksel_rate clkout2_src_core_rates[] = {
-	{ .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+	{ .div = 1, .val = 0, .flags = RATE_IN_3XXX | DEFAULT_RATE },
 	{ .div = 0 }
 };
 
 static const struct clksel_rate clkout2_src_sys_rates[] = {
-	{ .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+	{ .div = 1, .val = 1, .flags = RATE_IN_3XXX | DEFAULT_RATE },
 	{ .div = 0 }
 };
 
 static const struct clksel_rate clkout2_src_96m_rates[] = {
-	{ .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
+	{ .div = 1, .val = 2, .flags = RATE_IN_3XXX | DEFAULT_RATE },
 	{ .div = 0 }
 };
 
 static const struct clksel_rate clkout2_src_54m_rates[] = {
-	{ .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
+	{ .div = 1, .val = 3, .flags = RATE_IN_3XXX | DEFAULT_RATE },
 	{ .div = 0 }
 };
 
@@ -931,11 +931,11 @@ static struct clk clkout2_src_ck = {
 };
 
 static const struct clksel_rate sys_clkout2_rates[] = {
-	{ .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
-	{ .div = 2, .val = 1, .flags = RATE_IN_343X },
-	{ .div = 4, .val = 2, .flags = RATE_IN_343X },
-	{ .div = 8, .val = 3, .flags = RATE_IN_343X },
-	{ .div = 16, .val = 4, .flags = RATE_IN_343X },
+	{ .div = 1, .val = 0, .flags = RATE_IN_3XXX | DEFAULT_RATE },
+	{ .div = 2, .val = 1, .flags = RATE_IN_3XXX },
+	{ .div = 4, .val = 2, .flags = RATE_IN_3XXX },
+	{ .div = 8, .val = 3, .flags = RATE_IN_3XXX },
+	{ .div = 16, .val = 4, .flags = RATE_IN_3XXX },
 	{ .div = 0 },
 };
 
@@ -966,9 +966,9 @@ static struct clk corex2_fck = {
 /* DPLL power domain clock controls */
 
 static const struct clksel_rate div4_rates[] = {
-	{ .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
-	{ .div = 2, .val = 2, .flags = RATE_IN_343X },
-	{ .div = 4, .val = 4, .flags = RATE_IN_343X },
+	{ .div = 1, .val = 1, .flags = RATE_IN_3XXX | DEFAULT_RATE },
+	{ .div = 2, .val = 2, .flags = RATE_IN_3XXX },
+	{ .div = 4, .val = 4, .flags = RATE_IN_3XXX },
 	{ .div = 0 }
 };
 
@@ -1002,8 +1002,8 @@ static struct clk mpu_ck = {
 
 /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
 static const struct clksel_rate arm_fck_rates[] = {
-	{ .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
-	{ .div = 2, .val = 1, .flags = RATE_IN_343X },
+	{ .div = 1, .val = 0, .flags = RATE_IN_3XXX | DEFAULT_RATE },
+	{ .div = 2, .val = 1, .flags = RATE_IN_3XXX },
 	{ .div = 0 },
 };
 
@@ -1175,14 +1175,14 @@ static struct clk gfx_cg2_ck = {
 /* SGX power domain - 3430ES2 only */
 
 static const struct clksel_rate sgx_core_rates[] = {
-	{ .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
-	{ .div = 4, .val = 1, .flags = RATE_IN_343X },
-	{ .div = 6, .val = 2, .flags = RATE_IN_343X },
+	{ .div = 3, .val = 0, .flags = RATE_IN_3XXX | DEFAULT_RATE },
+	{ .div = 4, .val = 1, .flags = RATE_IN_3XXX },
+	{ .div = 6, .val = 2, .flags = RATE_IN_3XXX },
 	{ .div = 0 },
 };
 
 static const struct clksel_rate sgx_96m_rates[] = {
-	{ .div = 1,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
+	{ .div = 1,  .val = 3, .flags = RATE_IN_3XXX | DEFAULT_RATE },
 	{ .div = 0 },
 };
 
@@ -1408,12 +1408,12 @@ static struct clk i2c1_fck = {
  * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
  */
 static const struct clksel_rate common_mcbsp_96m_rates[] = {
-	{ .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+	{ .div = 1, .val = 0, .flags = RATE_IN_3XXX | DEFAULT_RATE },
 	{ .div = 0 }
 };
 
 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
-	{ .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+	{ .div = 1, .val = 1, .flags = RATE_IN_3XXX | DEFAULT_RATE },
 	{ .div = 0 }
 };
 
@@ -1550,12 +1550,12 @@ static struct clk hdq_fck = {
 /* DPLL3-derived clock */
 
 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
-	{ .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
-	{ .div = 2, .val = 2, .flags = RATE_IN_343X },
-	{ .div = 3, .val = 3, .flags = RATE_IN_343X },
-	{ .div = 4, .val = 4, .flags = RATE_IN_343X },
-	{ .div = 6, .val = 6, .flags = RATE_IN_343X },
-	{ .div = 8, .val = 8, .flags = RATE_IN_343X },
+	{ .div = 1, .val = 1, .flags = RATE_IN_3XXX | DEFAULT_RATE },
+	{ .div = 2, .val = 2, .flags = RATE_IN_3XXX },
+	{ .div = 3, .val = 3, .flags = RATE_IN_3XXX },
+	{ .div = 4, .val = 4, .flags = RATE_IN_3XXX },
+	{ .div = 6, .val = 6, .flags = RATE_IN_3XXX },
+	{ .div = 8, .val = 8, .flags = RATE_IN_3XXX },
 	{ .div = 0 }
 };
 
@@ -2200,18 +2200,18 @@ static struct clk usbhost_ick = {
 /* WKUP */
 
 static const struct clksel_rate usim_96m_rates[] = {
-	{ .div = 2,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
-	{ .div = 4,  .val = 4, .flags = RATE_IN_343X },
-	{ .div = 8,  .val = 5, .flags = RATE_IN_343X },
-	{ .div = 10, .val = 6, .flags = RATE_IN_343X },
+	{ .div = 2,  .val = 3, .flags = RATE_IN_3XXX | DEFAULT_RATE },
+	{ .div = 4,  .val = 4, .flags = RATE_IN_3XXX },
+	{ .div = 8,  .val = 5, .flags = RATE_IN_3XXX },
+	{ .div = 10, .val = 6, .flags = RATE_IN_3XXX },
 	{ .div = 0 },
 };
 
 static const struct clksel_rate usim_120m_rates[] = {
-	{ .div = 4,  .val = 7,	.flags = RATE_IN_343X | DEFAULT_RATE },
-	{ .div = 8,  .val = 8,	.flags = RATE_IN_343X },
-	{ .div = 16, .val = 9,	.flags = RATE_IN_343X },
-	{ .div = 20, .val = 10, .flags = RATE_IN_343X },
+	{ .div = 4,  .val = 7,	.flags = RATE_IN_3XXX | DEFAULT_RATE },
+	{ .div = 8,  .val = 8,	.flags = RATE_IN_3XXX },
+	{ .div = 16, .val = 9,	.flags = RATE_IN_3XXX },
+	{ .div = 20, .val = 10, .flags = RATE_IN_3XXX },
 	{ .div = 0 },
 };
 
@@ -2804,22 +2804,22 @@ static struct clk mcbsp4_fck = {
 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
 
 static const struct clksel_rate emu_src_sys_rates[] = {
-	{ .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+	{ .div = 1, .val = 0, .flags = RATE_IN_3XXX | DEFAULT_RATE },
 	{ .div = 0 },
 };
 
 static const struct clksel_rate emu_src_core_rates[] = {
-	{ .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+	{ .div = 1, .val = 1, .flags = RATE_IN_3XXX | DEFAULT_RATE },
 	{ .div = 0 },
 };
 
 static const struct clksel_rate emu_src_per_rates[] = {
-	{ .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
+	{ .div = 1, .val = 2, .flags = RATE_IN_3XXX | DEFAULT_RATE },
 	{ .div = 0 },
 };
 
 static const struct clksel_rate emu_src_mpu_rates[] = {
-	{ .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
+	{ .div = 1, .val = 3, .flags = RATE_IN_3XXX | DEFAULT_RATE },
 	{ .div = 0 },
 };
 
@@ -2848,10 +2848,10 @@ static struct clk emu_src_ck = {
 };
 
 static const struct clksel_rate pclk_emu_rates[] = {
-	{ .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
-	{ .div = 3, .val = 3, .flags = RATE_IN_343X },
-	{ .div = 4, .val = 4, .flags = RATE_IN_343X },
-	{ .div = 6, .val = 6, .flags = RATE_IN_343X },
+	{ .div = 2, .val = 2, .flags = RATE_IN_3XXX | DEFAULT_RATE },
+	{ .div = 3, .val = 3, .flags = RATE_IN_3XXX },
+	{ .div = 4, .val = 4, .flags = RATE_IN_3XXX },
+	{ .div = 6, .val = 6, .flags = RATE_IN_3XXX },
 	{ .div = 0 },
 };
 
@@ -2872,9 +2872,9 @@ static struct clk pclk_fck = {
 };
 
 static const struct clksel_rate pclkx2_emu_rates[] = {
-	{ .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
-	{ .div = 2, .val = 2, .flags = RATE_IN_343X },
-	{ .div = 3, .val = 3, .flags = RATE_IN_343X },
+	{ .div = 1, .val = 1, .flags = RATE_IN_3XXX | DEFAULT_RATE },
+	{ .div = 2, .val = 2, .flags = RATE_IN_3XXX },
+	{ .div = 3, .val = 3, .flags = RATE_IN_3XXX },
 	{ .div = 0 },
 };
 
@@ -2922,9 +2922,9 @@ static struct clk traceclk_src_fck = {
 };
 
 static const struct clksel_rate traceclk_rates[] = {
-	{ .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
-	{ .div = 2, .val = 2, .flags = RATE_IN_343X },
-	{ .div = 4, .val = 4, .flags = RATE_IN_343X },
+	{ .div = 1, .val = 1, .flags = RATE_IN_3XXX | DEFAULT_RATE },
+	{ .div = 2, .val = 2, .flags = RATE_IN_3XXX },
+	{ .div = 4, .val = 4, .flags = RATE_IN_3XXX },
 	{ .div = 0 },
 };
 
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index 66648d4..359ccb4 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -157,7 +157,7 @@ extern const struct clkops clkops_null;
 #define DEFAULT_RATE		(1 << 0)
 #define RATE_IN_242X		(1 << 1)
 #define RATE_IN_243X		(1 << 2)
-#define RATE_IN_343X		(1 << 3)	/* rates common to all 343X */
+#define RATE_IN_3XXX		(1 << 3)	/* rates common to all 343X */
 #define RATE_IN_3430ES2		(1 << 4)	/* 3430ES2 rates only */
 
 #define RATE_IN_24XX		(RATE_IN_242X | RATE_IN_243X)
-- 
1.5.6.3


^ permalink raw reply related	[flat|nested] 12+ messages in thread

* [PATCHV2 3/4] OMAP3: Correct width for CLKSEL Fields
  2009-11-20 15:28   ` [PATCHV2 2/4] OMAP3: Clock Type change for OMAP3 Clocks Vishwanath BS
@ 2009-11-20 15:28     ` Vishwanath BS
  2009-11-20 15:28       ` [PATCHV2 4/4] OMAP3: add support for 192Mhz sgx clock Vishwanath BS
                         ` (2 more replies)
  2009-11-20 15:44     ` [PATCHV2 2/4] OMAP3: Clock Type change for OMAP3 Clocks Nishanth Menon
  1 sibling, 3 replies; 12+ messages in thread
From: Vishwanath BS @ 2009-11-20 15:28 UTC (permalink / raw)
  To: linux-omap, vishwanath.bs

DPLL4 M, M3, M4, M5 and M6 field width has been increased by 1 bit in
3630.This patch has changes to accommodate this in CM dynamically based on
chip version.

Signed-off-by: Vishwanath BS <vishwanath.bs@ti.com>
---
 arch/arm/mach-omap2/clock34xx.c         |   18 ++++++++--
 arch/arm/mach-omap2/clock34xx.h         |   53 ++++++++++++++++++++++++++++--
 arch/arm/mach-omap2/cm-regbits-34xx.h   |    7 +++-
 arch/arm/plat-omap/include/plat/clock.h |    4 +-
 4 files changed, 71 insertions(+), 11 deletions(-)
 mode change 100644 => 100755 arch/arm/mach-omap2/clock34xx.c

diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 167f075..1e35f9a
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -43,6 +43,7 @@
 #include "prm-regbits-34xx.h"
 #include "cm.h"
 #include "cm-regbits-34xx.h"
+#include <plat/cpu.h>
 
 static const struct clkops clkops_noncore_dpll_ops;
 
@@ -97,6 +98,7 @@ struct omap_clk {
 #define CK_3XXX		(1 << 0)
 #define CK_3430ES1	(1 << 1)
 #define CK_3430ES2	(1 << 2)
+#define CK_363X		(1 << 3)
 
 static struct omap_clk omap34xx_clks[] = {
 	CLK(NULL,	"omap_32k_fck",	&omap_32k_fck,	CK_3XXX),
@@ -134,13 +136,13 @@ static struct omap_clk omap34xx_clks[] = {
 	CLK(NULL,	"omap_12m_fck",	&omap_12m_fck,	CK_3XXX),
 	CLK(NULL,	"dpll4_m2_ck",	&dpll4_m2_ck,	CK_3XXX),
 	CLK(NULL,	"dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_3XXX),
-	CLK(NULL,	"dpll4_m3_ck",	&dpll4_m3_ck,	CK_3XXX),
+	CLK(NULL,	"dpll4_m3_ck",	&dpll4_m3_ck,	CK_3XXX | CK_363X),
 	CLK(NULL,	"dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_3XXX),
-	CLK(NULL,	"dpll4_m4_ck",	&dpll4_m4_ck,	CK_3XXX),
+	CLK(NULL,	"dpll4_m4_ck",	&dpll4_m4_ck,	CK_3XXX | CK_363X),
 	CLK(NULL,	"dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_3XXX),
-	CLK(NULL,	"dpll4_m5_ck",	&dpll4_m5_ck,	CK_3XXX),
+	CLK(NULL,	"dpll4_m5_ck",	&dpll4_m5_ck,	CK_3XXX | CK_363X),
 	CLK(NULL,	"dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_3XXX),
-	CLK(NULL,	"dpll4_m6_ck",	&dpll4_m6_ck,	CK_3XXX),
+	CLK(NULL,	"dpll4_m6_ck",	&dpll4_m6_ck,	CK_3XXX | CK_363X),
 	CLK(NULL,	"dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX),
 	CLK(NULL,	"emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX),
 	CLK(NULL,	"dpll5_ck",	&dpll5_ck,	CK_3430ES2),
@@ -1222,6 +1224,8 @@ int __init omap2_clk_init(void)
 				OMAP3630_PERIPH_DPLL_DCO_SEL_MASK;
 			dpll4_ck.dpll_data->sd_div_mask =
 				OMAP3630_PERIPH_DPLL_SD_DIV_MASK;
+			dpll4_dd.mult_mask = OMAP3630_PERIPH_DPLL_MULT_MASK;
+			cpu_mask |= RATE_IN_363X;
 			}
 	}
 
@@ -1232,6 +1236,12 @@ int __init omap2_clk_init(void)
 
 	for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++)
 		if (c->cpu & cpu_clkflg) {
+			/* for 3630, change the mask value for clocks which are
+				marked as CK_363X*/
+			if (cpu_is_omap3630() && (c->cpu & CK_363X)) {
+				c->lk.clk->clksel_mask =
+						c->lk.clk->clksel_mask_3630;
+			}
 			clkdev_add(&c->lk);
 			clk_register(c->lk.clk);
 			omap2_init_clk_clkdm(c->lk.clk);
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index 813a83e..93c92e5 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -243,6 +243,42 @@ static const struct clksel_rate div16_dpll_rates[] = {
 	{ .div = 0 }
 };
 
+static const struct clksel_rate div32_dpll_rates[] = {
+	{ .div = 1, .val = 1, .flags = RATE_IN_3XXX | DEFAULT_RATE },
+	{ .div = 2, .val = 2, .flags = RATE_IN_3XXX },
+	{ .div = 3, .val = 3, .flags = RATE_IN_3XXX },
+	{ .div = 4, .val = 4, .flags = RATE_IN_3XXX },
+	{ .div = 5, .val = 5, .flags = RATE_IN_3XXX },
+	{ .div = 6, .val = 6, .flags = RATE_IN_3XXX },
+	{ .div = 7, .val = 7, .flags = RATE_IN_3XXX },
+	{ .div = 8, .val = 8, .flags = RATE_IN_3XXX },
+	{ .div = 9, .val = 9, .flags = RATE_IN_3XXX },
+	{ .div = 10, .val = 10, .flags = RATE_IN_3XXX },
+	{ .div = 11, .val = 11, .flags = RATE_IN_3XXX },
+	{ .div = 12, .val = 12, .flags = RATE_IN_3XXX },
+	{ .div = 13, .val = 13, .flags = RATE_IN_3XXX },
+	{ .div = 14, .val = 14, .flags = RATE_IN_3XXX },
+	{ .div = 15, .val = 15, .flags = RATE_IN_3XXX },
+	{ .div = 16, .val = 16, .flags = RATE_IN_3XXX },
+	{ .div = 17, .val = 17, .flags = RATE_IN_363X },
+	{ .div = 18, .val = 18, .flags = RATE_IN_363X },
+	{ .div = 19, .val = 19, .flags = RATE_IN_363X },
+	{ .div = 20, .val = 20, .flags = RATE_IN_363X },
+	{ .div = 21, .val = 21, .flags = RATE_IN_363X },
+	{ .div = 22, .val = 22, .flags = RATE_IN_363X },
+	{ .div = 23, .val = 23, .flags = RATE_IN_363X },
+	{ .div = 24, .val = 24, .flags = RATE_IN_363X },
+	{ .div = 25, .val = 25, .flags = RATE_IN_363X },
+	{ .div = 26, .val = 26, .flags = RATE_IN_363X },
+	{ .div = 27, .val = 27, .flags = RATE_IN_363X },
+	{ .div = 28, .val = 28, .flags = RATE_IN_363X },
+	{ .div = 29, .val = 29, .flags = RATE_IN_363X },
+	{ .div = 30, .val = 30, .flags = RATE_IN_363X },
+	{ .div = 31, .val = 31, .flags = RATE_IN_363X },
+	{ .div = 32, .val = 32, .flags = RATE_IN_363X },
+	{ .div = 0 }
+};
+
 /* DPLL1 */
 /* MPU clock source */
 /* Type: DPLL */
@@ -588,6 +624,11 @@ static const struct clksel div16_dpll4_clksel[] = {
 	{ .parent = NULL }
 };
 
+static const struct clksel div32_dpll4_clksel[] = {
+	{ .parent = &dpll4_ck, .rates = div32_dpll_rates },
+	{ .parent = NULL }
+};
+
 /* This virtual clock is the source for dpll4_m2x2_ck */
 static struct clk dpll4_m2_ck = {
 	.name		= "dpll4_m2_ck",
@@ -668,7 +709,8 @@ static struct clk dpll4_m3_ck = {
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 	.clksel_mask	= OMAP3430_CLKSEL_TV_MASK,
-	.clksel		= div16_dpll4_clksel,
+	.clksel_mask_3630 = OMAP3630_CLKSEL_TV_MASK,
+	.clksel		= div32_dpll4_clksel,
 	.clkdm_name	= "dpll4_clkdm",
 	.recalc		= &omap2_clksel_recalc,
 };
@@ -754,7 +796,8 @@ static struct clk dpll4_m4_ck = {
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 	.clksel_mask	= OMAP3430_CLKSEL_DSS1_MASK,
-	.clksel		= div16_dpll4_clksel,
+	.clksel_mask_3630 = OMAP3630_CLKSEL_DSS1_MASK,
+	.clksel		= div32_dpll4_clksel,
 	.clkdm_name	= "dpll4_clkdm",
 	.recalc		= &omap2_clksel_recalc,
 	.set_rate	= &omap2_clksel_set_rate,
@@ -781,7 +824,8 @@ static struct clk dpll4_m5_ck = {
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
 	.clksel_mask	= OMAP3430_CLKSEL_CAM_MASK,
-	.clksel		= div16_dpll4_clksel,
+	.clksel_mask_3630 = OMAP3630_CLKSEL_CAM_MASK,
+	.clksel		= div32_dpll4_clksel,
 	.clkdm_name	= "dpll4_clkdm",
 	.recalc		= &omap2_clksel_recalc,
 };
@@ -806,7 +850,8 @@ static struct clk dpll4_m6_ck = {
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 	.clksel_mask	= OMAP3430_DIV_DPLL4_MASK,
-	.clksel		= div16_dpll4_clksel,
+	.clksel_mask_3630 = OMAP3630_DIV_DPLL4_MASK,
+	.clksel		= div32_dpll4_clksel,
 	.clkdm_name	= "dpll4_clkdm",
 	.recalc		= &omap2_clksel_recalc,
 };
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h
index 6f2802b..a6383f9 100644
--- a/arch/arm/mach-omap2/cm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
@@ -516,7 +516,8 @@
 
 /* CM_CLKSEL2_PLL */
 #define OMAP3430_PERIPH_DPLL_MULT_SHIFT			8
-#define OMAP3430_PERIPH_DPLL_MULT_MASK			(0xfff << 8)
+#define OMAP3430_PERIPH_DPLL_MULT_MASK			(0x7ff << 8)
+#define OMAP3630_PERIPH_DPLL_MULT_MASK			(0xfff << 8)
 #define OMAP3430_PERIPH_DPLL_DIV_SHIFT			0
 #define OMAP3430_PERIPH_DPLL_DIV_MASK			(0x7f << 0)
 #define OMAP3630_PERIPH_DPLL_DCO_SEL_SHIFT		21
@@ -573,8 +574,10 @@
 /* CM_CLKSEL_DSS */
 #define OMAP3430_CLKSEL_TV_SHIFT			8
 #define OMAP3430_CLKSEL_TV_MASK				(0x1f << 8)
+#define OMAP3630_CLKSEL_TV_MASK				(0x3f << 8)
 #define OMAP3430_CLKSEL_DSS1_SHIFT			0
 #define OMAP3430_CLKSEL_DSS1_MASK			(0x1f << 0)
+#define OMAP3630_CLKSEL_DSS1_MASK			(0x3f << 0)
 
 /* CM_SLEEPDEP_DSS specific bits */
 
@@ -602,6 +605,7 @@
 /* CM_CLKSEL_CAM */
 #define OMAP3430_CLKSEL_CAM_SHIFT			0
 #define OMAP3430_CLKSEL_CAM_MASK			(0x1f << 0)
+#define OMAP3630_CLKSEL_CAM_MASK			(0x3f << 0)
 
 /* CM_SLEEPDEP_CAM specific bits */
 
@@ -697,6 +701,7 @@
 /* CM_CLKSEL1_EMU */
 #define OMAP3430_DIV_DPLL4_SHIFT			24
 #define OMAP3430_DIV_DPLL4_MASK				(0x1f << 24)
+#define OMAP3630_DIV_DPLL4_MASK				(0x3f << 24)
 #define OMAP3430_DIV_DPLL3_SHIFT			16
 #define OMAP3430_DIV_DPLL3_MASK				(0x1f << 16)
 #define OMAP3430_CLKSEL_TRACECLK_SHIFT			11
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index 359ccb4..0e0a5cc 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -93,7 +93,7 @@ struct clk {
 		defined(CONFIG_ARCH_OMAP4)
 	u8			fixed_div;
 	void __iomem		*clksel_reg;
-	u32			clksel_mask;
+	u32			clksel_mask, clksel_mask_3630;
 	const struct clksel	*clksel;
 	struct dpll_data	*dpll_data;
 	const char		*clkdm_name;
@@ -159,7 +159,7 @@ extern const struct clkops clkops_null;
 #define RATE_IN_243X		(1 << 2)
 #define RATE_IN_3XXX		(1 << 3)	/* rates common to all 343X */
 #define RATE_IN_3430ES2		(1 << 4)	/* 3430ES2 rates only */
-
+#define RATE_IN_363X		(1 << 5)        /* rates common to all 343X */
 #define RATE_IN_24XX		(RATE_IN_242X | RATE_IN_243X)
 
 
-- 
1.5.6.3


^ permalink raw reply related	[flat|nested] 12+ messages in thread

* [PATCHV2 4/4] OMAP3: add support for 192Mhz sgx clock
  2009-11-20 15:28     ` [PATCHV2 3/4] OMAP3: Correct width for CLKSEL Fields Vishwanath BS
@ 2009-11-20 15:28       ` Vishwanath BS
  2009-11-20 16:19         ` Nishanth Menon
  2009-11-20 15:57       ` [PATCHV2 3/4] OMAP3: Correct width for CLKSEL Fields Aguirre, Sergio
  2009-11-20 16:00       ` Nishanth Menon
  2 siblings, 1 reply; 12+ messages in thread
From: Vishwanath BS @ 2009-11-20 15:28 UTC (permalink / raw)
  To: linux-omap, vishwanath.bs

SGX can run at 192MHz on 3630 and this patch has changes to support this
feature. Basically DPLL4 M2 will be 192Mhz which will be used as SGX
Clock. 192Mhz clock is divided by 2 (using CM_CLKSEL_CORE) to generate
96Mh clock

Signed-off-by: Vishwanath BS <Vishwanath.bs@ti.com>
---
 arch/arm/mach-omap2/clock34xx.c       |   16 +++++++++++++++-
 arch/arm/mach-omap2/clock34xx.h       |   33 +++++++++++++++++++++++++++++++++
 arch/arm/mach-omap2/cm-regbits-34xx.h |    2 ++
 arch/arm/mach-omap2/id.c              |    7 +++++--
 arch/arm/plat-omap/include/plat/cpu.h |    3 +++
 5 files changed, 58 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 1e35f9a..bce7e46 100755
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -128,6 +128,7 @@ static struct omap_clk omap34xx_clks[] = {
 	CLK(NULL,	"emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX),
 	CLK(NULL,	"dpll4_ck",	&dpll4_ck,	CK_3XXX),
 	CLK(NULL,	"dpll4_x2_ck",	&dpll4_x2_ck,	CK_3XXX),
+       CLK(NULL,       "omap_192m_alwon_ck", &omap_192m_alwon_ck, CK_363X),
 	CLK(NULL,	"omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_3XXX),
 	CLK(NULL,	"omap_96m_fck",	&omap_96m_fck,	CK_3XXX),
 	CLK(NULL,	"cm_96m_fck",	&cm_96m_fck,	CK_3XXX),
@@ -1226,7 +1227,20 @@ int __init omap2_clk_init(void)
 				OMAP3630_PERIPH_DPLL_SD_DIV_MASK;
 			dpll4_dd.mult_mask = OMAP3630_PERIPH_DPLL_MULT_MASK;
 			cpu_mask |= RATE_IN_363X;
-			}
+			cpu_clkflg |= CK_363X;
+		}
+
+		if (omap3_has_192mhz_clk()) {
+			omap_96m_alwon_fck.parent = &omap_192m_alwon_ck;
+			omap_96m_alwon_fck.init = &omap2_init_clksel_parent;
+			omap_96m_alwon_fck.clksel_reg =
+					OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+			omap_96m_alwon_fck.clksel_mask =
+						OMAP3630_CLKSEL_96M_MASK;
+			omap_96m_alwon_fck.clksel = omap_96m_alwon_fck_clksel;
+			omap_96m_alwon_fck.recalc = &omap2_clksel_recalc;
+		}
+
 	}
 
 	clk_init(&omap2_clk_functions);
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index 93c92e5..6fe89df 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -654,12 +654,31 @@ static struct clk dpll4_m2x2_ck = {
 	.recalc		= &omap3_clkoutx2_recalc,
 };
 
+/* Adding 192MHz Clock node needed by SGX */
+static struct clk omap_192m_alwon_ck = {
+	.name           = "omap_192m_alwon_ck",
+	.ops            = &clkops_null,
+	.parent         = &dpll4_m2x2_ck,
+	.recalc         = &followparent_recalc,
+};
+
 /*
  * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
  * PRM_96M_ALWON_(F)CLK.  Two clocks then emerge from the PRM:
  * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
  * CM_96K_(F)CLK.
  */
+static const struct clksel_rate omap_96m_alwon_fck_rates[] = {
+	{ .div = 1, .val = 1, .flags = RATE_IN_363X },
+	{ .div = 2, .val = 2, .flags = RATE_IN_363X | DEFAULT_RATE },
+	{ .div = 0 }
+};
+
+static const struct clksel omap_96m_alwon_fck_clksel[] = {
+	{ .parent = &omap_192m_alwon_ck, .rates = omap_96m_alwon_fck_rates },
+	{ .parent = NULL }
+};
+
 static struct clk omap_96m_alwon_fck = {
 	.name		= "omap_96m_alwon_fck",
 	.ops		= &clkops_null,
@@ -1223,6 +1242,18 @@ static const struct clksel_rate sgx_core_rates[] = {
 	{ .div = 3, .val = 0, .flags = RATE_IN_3XXX | DEFAULT_RATE },
 	{ .div = 4, .val = 1, .flags = RATE_IN_3XXX },
 	{ .div = 6, .val = 2, .flags = RATE_IN_3XXX },
+	{ .div = 2, .val = 5, .flags = RATE_IN_363X },
+	{ .div = 0 },
+};
+
+static const struct clksel_rate sgx_192m_rates[] = {
+	{ .div = 1,  .val = 4, .flags = RATE_IN_363X | DEFAULT_RATE },
+	{ .div = 0 },
+};
+
+static const struct clksel_rate sgx_corex2_rates[] = {
+	{ .div = 3, .val = 6, .flags = RATE_IN_363X | DEFAULT_RATE },
+	{ .div = 5, .val = 7, .flags = RATE_IN_363X },
 	{ .div = 0 },
 };
 
@@ -1234,6 +1265,8 @@ static const struct clksel_rate sgx_96m_rates[] = {
 static const struct clksel sgx_clksel[] = {
 	{ .parent = &core_ck,	 .rates = sgx_core_rates },
 	{ .parent = &cm_96m_fck, .rates = sgx_96m_rates },
+	{ .parent = &omap_192m_alwon_ck, .rates = sgx_192m_rates },
+	{ .parent = &corex2_fck, .rates = sgx_corex2_rates },
 	{ .parent = NULL },
 };
 
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h
index a6383f9..39b3399 100644
--- a/arch/arm/mach-omap2/cm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
@@ -336,6 +336,8 @@
 #define OMAP3430_CLKSEL_L4_MASK				(0x3 << 2)
 #define OMAP3430_CLKSEL_L3_SHIFT			0
 #define OMAP3430_CLKSEL_L3_MASK				(0x3 << 0)
+#define OMAP3630_CLKSEL_96M_SHIFT                      12
+#define OMAP3630_CLKSEL_96M_MASK                       (0x3 << 12)
 
 /* CM_CLKSTCTRL_CORE */
 #define OMAP3430ES1_CLKTRCTRL_D2D_SHIFT			4
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 3c1194c..b1bc79d 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -176,8 +176,10 @@ void __init omap3_check_features(void)
 	OMAP3_CHECK_FEATURE(status, NEON);
 	OMAP3_CHECK_FEATURE(status, ISP);
 
-	if (cpu_is_omap3630())
-		omap3_features |= OMAP3_HAS_JTYPE_DPLL4;
+	if (cpu_is_omap3630()) {
+		omap3_features |= OMAP3_HAS_JTYPE_DPLL4 |
+							OMAP3_HAS_192MHZ_CLK;
+	}
 	/*
 	 * TODO: Get additional info (where applicable)
 	 *       e.g. Size of L2 cache.
@@ -319,6 +321,7 @@ void __init omap3_cpuinfo(void)
 	OMAP3_SHOW_FEATURE(neon);
 	OMAP3_SHOW_FEATURE(isp);
 	OMAP3_SHOW_FEATURE(jtype_dpll4);
+	OMAP3_SHOW_FEATURE(192mhz_clk);
 	printk(")\n");
 }
 
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index 65c08d5..1dffe25 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -498,6 +498,7 @@ extern u32 omap3_features;
 #define OMAP3_HAS_NEON			BIT(3)
 #define OMAP3_HAS_ISP			BIT(4)
 #define OMAP3_HAS_JTYPE_DPLL4		BIT(5)
+#define OMAP3_HAS_192MHZ_CLK		BIT(6)
 
 #define OMAP3_HAS_FEATURE(feat,flag)			\
 static inline unsigned int omap3_has_ ##feat(void)	\
@@ -511,4 +512,6 @@ OMAP3_HAS_FEATURE(iva, IVA)
 OMAP3_HAS_FEATURE(neon, NEON)
 OMAP3_HAS_FEATURE(isp, ISP)
 OMAP3_HAS_FEATURE(jtype_dpll4, JTYPE_DPLL4)
+OMAP3_HAS_FEATURE(192mhz_clk, 192MHZ_CLK)
+
 #endif
-- 
1.5.6.3


^ permalink raw reply related	[flat|nested] 12+ messages in thread

* Re: [PATCHV2 2/4] OMAP3: Clock Type change for OMAP3 Clocks
  2009-11-20 15:28   ` [PATCHV2 2/4] OMAP3: Clock Type change for OMAP3 Clocks Vishwanath BS
  2009-11-20 15:28     ` [PATCHV2 3/4] OMAP3: Correct width for CLKSEL Fields Vishwanath BS
@ 2009-11-20 15:44     ` Nishanth Menon
  1 sibling, 0 replies; 12+ messages in thread
From: Nishanth Menon @ 2009-11-20 15:44 UTC (permalink / raw)
  To: Vishwanath BS; +Cc: linux-omap@vger.kernel.org

Thanks for the patch. few minor comments follow

Vishwanath BS had written, on 11/20/2009 09:28 AM, the following:

please provide a detailed commit message why we want to shift from 34XX 
to 3XXX define.

> Signed-off-by: Vishwanath BS <vishwanath.bs@ti.com>
> ---
>  arch/arm/mach-omap2/clock.h             |   15 +-
>  arch/arm/mach-omap2/clock34xx.c         |  370 +++++++++++++++---------------
>  arch/arm/mach-omap2/clock34xx.h         |  158 +++++++-------
>  arch/arm/plat-omap/include/plat/clock.h |    2 +-
>  4 files changed, 274 insertions(+), 271 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
> index 43b6bed..8ceefcc 100644
> --- a/arch/arm/mach-omap2/clock.h
> +++ b/arch/arm/mach-omap2/clock.h
> @@ -79,20 +79,23 @@ extern u8 cpu_mask;
> 
>  /* clksel_rate data common to 24xx/343x */
>  static const struct clksel_rate gpt_32k_rates[] = {
> -        { .div = 1, .val = 0, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
> +        { .div = 1, .val = 0, .flags = RATE_IN_24XX | RATE_IN_3XXX |
> +                                                       DEFAULT_RATE },
>          { .div = 0 }
>  };
> 
>  static const struct clksel_rate gpt_sys_rates[] = {
> -        { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
> +        { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_3XXX |
> +                                                       DEFAULT_RATE },
>          { .div = 0 }
>  };
> 
>  static const struct clksel_rate gfx_l3_rates[] = {
> -       { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X },
> -       { .div = 2, .val = 2, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
> -       { .div = 3, .val = 3, .flags = RATE_IN_243X | RATE_IN_343X },
> -       { .div = 4, .val = 4, .flags = RATE_IN_243X | RATE_IN_343X },
> +       { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_3XXX },
> +       { .div = 2, .val = 2, .flags = RATE_IN_24XX | RATE_IN_3XXX |
> +                                                       DEFAULT_RATE },
> +       { .div = 3, .val = 3, .flags = RATE_IN_243X | RATE_IN_3XXX },
> +       { .div = 4, .val = 4, .flags = RATE_IN_243X | RATE_IN_3XXX },
>         { .div = 0 }
>  };
> 
> diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
> index 832ed0b..167f075 100644
> --- a/arch/arm/mach-omap2/clock34xx.c
> +++ b/arch/arm/mach-omap2/clock34xx.c
> @@ -94,69 +94,69 @@ struct omap_clk {
>                 },                      \
>         }
> 
> -#define CK_343X                (1 << 0)
> +#define CK_3XXX                (1 << 0)
>  #define CK_3430ES1     (1 << 1)
>  #define CK_3430ES2     (1 << 2)

unrelated to this patch - just a reminder to all that we need to kill 
the above defines at a later point -> ES1 is not a production device. 
ES2 and 3XXX should ideally not be differentiated with ES3.x devices - 
not thought yet why they would be different, any comments to the effect 
will be good -> but we probably need to clean those out elegantly later 
on I guess.

> 
>  static struct omap_clk omap34xx_clks[] = {
> -       CLK(NULL,       "omap_32k_fck", &omap_32k_fck,  CK_343X),
> -       CLK(NULL,       "virt_12m_ck",  &virt_12m_ck,   CK_343X),
> -       CLK(NULL,       "virt_13m_ck",  &virt_13m_ck,   CK_343X),
> +       CLK(NULL,       "omap_32k_fck", &omap_32k_fck,  CK_3XXX),
> +       CLK(NULL,       "virt_12m_ck",  &virt_12m_ck,   CK_3XXX),
> +       CLK(NULL,       "virt_13m_ck",  &virt_13m_ck,   CK_3XXX),
>         CLK(NULL,       "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2),
> -       CLK(NULL,       "virt_19_2m_ck", &virt_19_2m_ck, CK_343X),
> -       CLK(NULL,       "virt_26m_ck",  &virt_26m_ck,   CK_343X),
> -       CLK(NULL,       "virt_38_4m_ck", &virt_38_4m_ck, CK_343X),
> -       CLK(NULL,       "osc_sys_ck",   &osc_sys_ck,    CK_343X),
> -       CLK(NULL,       "sys_ck",       &sys_ck,        CK_343X),
> -       CLK(NULL,       "sys_altclk",   &sys_altclk,    CK_343X),
> -       CLK(NULL,       "mcbsp_clks",   &mcbsp_clks,    CK_343X),
> -       CLK(NULL,       "sys_clkout1",  &sys_clkout1,   CK_343X),
> -       CLK(NULL,       "dpll1_ck",     &dpll1_ck,      CK_343X),
> -       CLK(NULL,       "dpll1_x2_ck",  &dpll1_x2_ck,   CK_343X),
> -       CLK(NULL,       "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_343X),
> -       CLK(NULL,       "dpll2_ck",     &dpll2_ck,      CK_343X),
> -       CLK(NULL,       "dpll2_m2_ck",  &dpll2_m2_ck,   CK_343X),
> -       CLK(NULL,       "dpll3_ck",     &dpll3_ck,      CK_343X),
> -       CLK(NULL,       "core_ck",      &core_ck,       CK_343X),
> -       CLK(NULL,       "dpll3_x2_ck",  &dpll3_x2_ck,   CK_343X),
> -       CLK(NULL,       "dpll3_m2_ck",  &dpll3_m2_ck,   CK_343X),
> -       CLK(NULL,       "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_343X),
> -       CLK(NULL,       "dpll3_m3_ck",  &dpll3_m3_ck,   CK_343X),
> -       CLK(NULL,       "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_343X),
> -       CLK(NULL,       "emu_core_alwon_ck", &emu_core_alwon_ck, CK_343X),
> -       CLK(NULL,       "dpll4_ck",     &dpll4_ck,      CK_343X),
> -       CLK(NULL,       "dpll4_x2_ck",  &dpll4_x2_ck,   CK_343X),
> -       CLK(NULL,       "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_343X),
> -       CLK(NULL,       "omap_96m_fck", &omap_96m_fck,  CK_343X),
> -       CLK(NULL,       "cm_96m_fck",   &cm_96m_fck,    CK_343X),
> -       CLK(NULL,       "omap_54m_fck", &omap_54m_fck,  CK_343X),
> -       CLK(NULL,       "omap_48m_fck", &omap_48m_fck,  CK_343X),
> -       CLK(NULL,       "omap_12m_fck", &omap_12m_fck,  CK_343X),
> -       CLK(NULL,       "dpll4_m2_ck",  &dpll4_m2_ck,   CK_343X),
> -       CLK(NULL,       "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_343X),
> -       CLK(NULL,       "dpll4_m3_ck",  &dpll4_m3_ck,   CK_343X),
> -       CLK(NULL,       "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_343X),
> -       CLK(NULL,       "dpll4_m4_ck",  &dpll4_m4_ck,   CK_343X),
> -       CLK(NULL,       "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_343X),
> -       CLK(NULL,       "dpll4_m5_ck",  &dpll4_m5_ck,   CK_343X),
> -       CLK(NULL,       "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_343X),
> -       CLK(NULL,       "dpll4_m6_ck",  &dpll4_m6_ck,   CK_343X),
> -       CLK(NULL,       "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_343X),
> -       CLK(NULL,       "emu_per_alwon_ck", &emu_per_alwon_ck, CK_343X),
> +       CLK(NULL,       "virt_19_2m_ck", &virt_19_2m_ck, CK_3XXX),
> +       CLK(NULL,       "virt_26m_ck",  &virt_26m_ck,   CK_3XXX),
> +       CLK(NULL,       "virt_38_4m_ck", &virt_38_4m_ck, CK_3XXX),
> +       CLK(NULL,       "osc_sys_ck",   &osc_sys_ck,    CK_3XXX),
> +       CLK(NULL,       "sys_ck",       &sys_ck,        CK_3XXX),
> +       CLK(NULL,       "sys_altclk",   &sys_altclk,    CK_3XXX),
> +       CLK(NULL,       "mcbsp_clks",   &mcbsp_clks,    CK_3XXX),
> +       CLK(NULL,       "sys_clkout1",  &sys_clkout1,   CK_3XXX),
> +       CLK(NULL,       "dpll1_ck",     &dpll1_ck,      CK_3XXX),
> +       CLK(NULL,       "dpll1_x2_ck",  &dpll1_x2_ck,   CK_3XXX),
> +       CLK(NULL,       "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_3XXX),
> +       CLK(NULL,       "dpll2_ck",     &dpll2_ck,      CK_3XXX),
> +       CLK(NULL,       "dpll2_m2_ck",  &dpll2_m2_ck,   CK_3XXX),
> +       CLK(NULL,       "dpll3_ck",     &dpll3_ck,      CK_3XXX),
> +       CLK(NULL,       "core_ck",      &core_ck,       CK_3XXX),
> +       CLK(NULL,       "dpll3_x2_ck",  &dpll3_x2_ck,   CK_3XXX),
> +       CLK(NULL,       "dpll3_m2_ck",  &dpll3_m2_ck,   CK_3XXX),
> +       CLK(NULL,       "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_3XXX),
> +       CLK(NULL,       "dpll3_m3_ck",  &dpll3_m3_ck,   CK_3XXX),
> +       CLK(NULL,       "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_3XXX),
> +       CLK(NULL,       "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX),
> +       CLK(NULL,       "dpll4_ck",     &dpll4_ck,      CK_3XXX),
> +       CLK(NULL,       "dpll4_x2_ck",  &dpll4_x2_ck,   CK_3XXX),
> +       CLK(NULL,       "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_3XXX),
> +       CLK(NULL,       "omap_96m_fck", &omap_96m_fck,  CK_3XXX),
> +       CLK(NULL,       "cm_96m_fck",   &cm_96m_fck,    CK_3XXX),
> +       CLK(NULL,       "omap_54m_fck", &omap_54m_fck,  CK_3XXX),
> +       CLK(NULL,       "omap_48m_fck", &omap_48m_fck,  CK_3XXX),
> +       CLK(NULL,       "omap_12m_fck", &omap_12m_fck,  CK_3XXX),
> +       CLK(NULL,       "dpll4_m2_ck",  &dpll4_m2_ck,   CK_3XXX),
> +       CLK(NULL,       "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_3XXX),
> +       CLK(NULL,       "dpll4_m3_ck",  &dpll4_m3_ck,   CK_3XXX),
> +       CLK(NULL,       "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_3XXX),
> +       CLK(NULL,       "dpll4_m4_ck",  &dpll4_m4_ck,   CK_3XXX),
> +       CLK(NULL,       "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_3XXX),
> +       CLK(NULL,       "dpll4_m5_ck",  &dpll4_m5_ck,   CK_3XXX),
> +       CLK(NULL,       "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_3XXX),
> +       CLK(NULL,       "dpll4_m6_ck",  &dpll4_m6_ck,   CK_3XXX),
> +       CLK(NULL,       "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX),
> +       CLK(NULL,       "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX),
>         CLK(NULL,       "dpll5_ck",     &dpll5_ck,      CK_3430ES2),
>         CLK(NULL,       "dpll5_m2_ck",  &dpll5_m2_ck,   CK_3430ES2),
> -       CLK(NULL,       "clkout2_src_ck", &clkout2_src_ck, CK_343X),
> -       CLK(NULL,       "sys_clkout2",  &sys_clkout2,   CK_343X),
> -       CLK(NULL,       "corex2_fck",   &corex2_fck,    CK_343X),
> -       CLK(NULL,       "dpll1_fck",    &dpll1_fck,     CK_343X),
> -       CLK(NULL,       "mpu_ck",       &mpu_ck,        CK_343X),
> -       CLK(NULL,       "arm_fck",      &arm_fck,       CK_343X),
> -       CLK(NULL,       "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_343X),
> -       CLK(NULL,       "dpll2_fck",    &dpll2_fck,     CK_343X),
> -       CLK(NULL,       "iva2_ck",      &iva2_ck,       CK_343X),
> -       CLK(NULL,       "l3_ick",       &l3_ick,        CK_343X),
> -       CLK(NULL,       "l4_ick",       &l4_ick,        CK_343X),
> -       CLK(NULL,       "rm_ick",       &rm_ick,        CK_343X),
> +       CLK(NULL,       "clkout2_src_ck", &clkout2_src_ck, CK_3XXX),
> +       CLK(NULL,       "sys_clkout2",  &sys_clkout2,   CK_3XXX),
> +       CLK(NULL,       "corex2_fck",   &corex2_fck,    CK_3XXX),
> +       CLK(NULL,       "dpll1_fck",    &dpll1_fck,     CK_3XXX),
> +       CLK(NULL,       "mpu_ck",       &mpu_ck,        CK_3XXX),
> +       CLK(NULL,       "arm_fck",      &arm_fck,       CK_3XXX),
> +       CLK(NULL,       "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX),
> +       CLK(NULL,       "dpll2_fck",    &dpll2_fck,     CK_3XXX),
> +       CLK(NULL,       "iva2_ck",      &iva2_ck,       CK_3XXX),
> +       CLK(NULL,       "l3_ick",       &l3_ick,        CK_3XXX),
> +       CLK(NULL,       "l4_ick",       &l4_ick,        CK_3XXX),
> +       CLK(NULL,       "rm_ick",       &rm_ick,        CK_3XXX),
>         CLK(NULL,       "gfx_l3_ck",    &gfx_l3_ck,     CK_3430ES1),
>         CLK(NULL,       "gfx_l3_fck",   &gfx_l3_fck,    CK_3430ES1),
>         CLK(NULL,       "gfx_l3_ick",   &gfx_l3_ick,    CK_3430ES1),
> @@ -165,159 +165,159 @@ static struct omap_clk omap34xx_clks[] = {
>         CLK(NULL,       "sgx_fck",      &sgx_fck,       CK_3430ES2),
>         CLK(NULL,       "sgx_ick",      &sgx_ick,       CK_3430ES2),
>         CLK(NULL,       "d2d_26m_fck",  &d2d_26m_fck,   CK_3430ES1),
> -       CLK(NULL,       "modem_fck",    &modem_fck,     CK_343X),
> -       CLK(NULL,       "sad2d_ick",    &sad2d_ick,     CK_343X),
> -       CLK(NULL,       "mad2d_ick",    &mad2d_ick,     CK_343X),
> -       CLK(NULL,       "gpt10_fck",    &gpt10_fck,     CK_343X),
> -       CLK(NULL,       "gpt11_fck",    &gpt11_fck,     CK_343X),
> +       CLK(NULL,       "modem_fck",    &modem_fck,     CK_3XXX),
> +       CLK(NULL,       "sad2d_ick",    &sad2d_ick,     CK_3XXX),
> +       CLK(NULL,       "mad2d_ick",    &mad2d_ick,     CK_3XXX),
> +       CLK(NULL,       "gpt10_fck",    &gpt10_fck,     CK_3XXX),
> +       CLK(NULL,       "gpt11_fck",    &gpt11_fck,     CK_3XXX),
>         CLK(NULL,       "cpefuse_fck",  &cpefuse_fck,   CK_3430ES2),
>         CLK(NULL,       "ts_fck",       &ts_fck,        CK_3430ES2),
>         CLK(NULL,       "usbtll_fck",   &usbtll_fck,    CK_3430ES2),
> -       CLK(NULL,       "core_96m_fck", &core_96m_fck,  CK_343X),
> +       CLK(NULL,       "core_96m_fck", &core_96m_fck,  CK_3XXX),
>         CLK("mmci-omap-hs.2",   "fck",  &mmchs3_fck,    CK_3430ES2),
> -       CLK("mmci-omap-hs.1",   "fck",  &mmchs2_fck,    CK_343X),
> -       CLK(NULL,       "mspro_fck",    &mspro_fck,     CK_343X),
> -       CLK("mmci-omap-hs.0",   "fck",  &mmchs1_fck,    CK_343X),
> -       CLK("i2c_omap.3", "fck",        &i2c3_fck,      CK_343X),
> -       CLK("i2c_omap.2", "fck",        &i2c2_fck,      CK_343X),
> -       CLK("i2c_omap.1", "fck",        &i2c1_fck,      CK_343X),
> -       CLK("omap-mcbsp.5", "fck",      &mcbsp5_fck,    CK_343X),
> -       CLK("omap-mcbsp.1", "fck",      &mcbsp1_fck,    CK_343X),
> -       CLK(NULL,       "core_48m_fck", &core_48m_fck,  CK_343X),
> -       CLK("omap2_mcspi.4", "fck",     &mcspi4_fck,    CK_343X),
> -       CLK("omap2_mcspi.3", "fck",     &mcspi3_fck,    CK_343X),
> -       CLK("omap2_mcspi.2", "fck",     &mcspi2_fck,    CK_343X),
> -       CLK("omap2_mcspi.1", "fck",     &mcspi1_fck,    CK_343X),
> -       CLK(NULL,       "uart2_fck",    &uart2_fck,     CK_343X),
> -       CLK(NULL,       "uart1_fck",    &uart1_fck,     CK_343X),
> +       CLK("mmci-omap-hs.1",   "fck",  &mmchs2_fck,    CK_3XXX),
> +       CLK(NULL,       "mspro_fck",    &mspro_fck,     CK_3XXX),
> +       CLK("mmci-omap-hs.0",   "fck",  &mmchs1_fck,    CK_3XXX),
> +       CLK("i2c_omap.3", "fck",        &i2c3_fck,      CK_3XXX),
> +       CLK("i2c_omap.2", "fck",        &i2c2_fck,      CK_3XXX),
> +       CLK("i2c_omap.1", "fck",        &i2c1_fck,      CK_3XXX),
> +       CLK("omap-mcbsp.5", "fck",      &mcbsp5_fck,    CK_3XXX),
> +       CLK("omap-mcbsp.1", "fck",      &mcbsp1_fck,    CK_3XXX),
> +       CLK(NULL,       "core_48m_fck", &core_48m_fck,  CK_3XXX),
> +       CLK("omap2_mcspi.4", "fck",     &mcspi4_fck,    CK_3XXX),
> +       CLK("omap2_mcspi.3", "fck",     &mcspi3_fck,    CK_3XXX),
> +       CLK("omap2_mcspi.2", "fck",     &mcspi2_fck,    CK_3XXX),
> +       CLK("omap2_mcspi.1", "fck",     &mcspi1_fck,    CK_3XXX),
> +       CLK(NULL,       "uart2_fck",    &uart2_fck,     CK_3XXX),
> +       CLK(NULL,       "uart1_fck",    &uart1_fck,     CK_3XXX),
>         CLK(NULL,       "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
> -       CLK(NULL,       "core_12m_fck", &core_12m_fck,  CK_343X),
> -       CLK("omap_hdq.0", "fck",        &hdq_fck,       CK_343X),
> +       CLK(NULL,       "core_12m_fck", &core_12m_fck,  CK_3XXX),
> +       CLK("omap_hdq.0", "fck",        &hdq_fck,       CK_3XXX),
>         CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es1,   CK_3430ES1),
>         CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es2,   CK_3430ES2),
>         CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck_3430es1,   CK_3430ES1),
>         CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck_3430es2,   CK_3430ES2),
> -       CLK(NULL,       "core_l3_ick",  &core_l3_ick,   CK_343X),
> +       CLK(NULL,       "core_l3_ick",  &core_l3_ick,   CK_3XXX),
>         CLK("musb_hdrc",        "ick",  &hsotgusb_ick_3430es1,  CK_3430ES1),
>         CLK("musb_hdrc",        "ick",  &hsotgusb_ick_3430es2,  CK_3430ES2),
> -       CLK(NULL,       "sdrc_ick",     &sdrc_ick,      CK_343X),
> -       CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_343X),
> -       CLK(NULL,       "security_l3_ick", &security_l3_ick, CK_343X),
> -       CLK(NULL,       "pka_ick",      &pka_ick,       CK_343X),
> -       CLK(NULL,       "core_l4_ick",  &core_l4_ick,   CK_343X),
> +       CLK(NULL,       "sdrc_ick",     &sdrc_ick,      CK_3XXX),
> +       CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_3XXX),
> +       CLK(NULL,       "security_l3_ick", &security_l3_ick, CK_3XXX),
> +       CLK(NULL,       "pka_ick",      &pka_ick,       CK_3XXX),
> +       CLK(NULL,       "core_l4_ick",  &core_l4_ick,   CK_3XXX),
>         CLK(NULL,       "usbtll_ick",   &usbtll_ick,    CK_3430ES2),
>         CLK("mmci-omap-hs.2",   "ick",  &mmchs3_ick,    CK_3430ES2),
> -       CLK(NULL,       "icr_ick",      &icr_ick,       CK_343X),
> -       CLK(NULL,       "aes2_ick",     &aes2_ick,      CK_343X),
> -       CLK(NULL,       "sha12_ick",    &sha12_ick,     CK_343X),
> -       CLK(NULL,       "des2_ick",     &des2_ick,      CK_343X),
> -       CLK("mmci-omap-hs.1",   "ick",  &mmchs2_ick,    CK_343X),
> -       CLK("mmci-omap-hs.0",   "ick",  &mmchs1_ick,    CK_343X),
> -       CLK(NULL,       "mspro_ick",    &mspro_ick,     CK_343X),
> -       CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_343X),
> -       CLK("omap2_mcspi.4", "ick",     &mcspi4_ick,    CK_343X),
> -       CLK("omap2_mcspi.3", "ick",     &mcspi3_ick,    CK_343X),
> -       CLK("omap2_mcspi.2", "ick",     &mcspi2_ick,    CK_343X),
> -       CLK("omap2_mcspi.1", "ick",     &mcspi1_ick,    CK_343X),
> -       CLK("i2c_omap.3", "ick",        &i2c3_ick,      CK_343X),
> -       CLK("i2c_omap.2", "ick",        &i2c2_ick,      CK_343X),
> -       CLK("i2c_omap.1", "ick",        &i2c1_ick,      CK_343X),
> -       CLK(NULL,       "uart2_ick",    &uart2_ick,     CK_343X),
> -       CLK(NULL,       "uart1_ick",    &uart1_ick,     CK_343X),
> -       CLK(NULL,       "gpt11_ick",    &gpt11_ick,     CK_343X),
> -       CLK(NULL,       "gpt10_ick",    &gpt10_ick,     CK_343X),
> -       CLK("omap-mcbsp.5", "ick",      &mcbsp5_ick,    CK_343X),
> -       CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick,    CK_343X),
> +       CLK(NULL,       "icr_ick",      &icr_ick,       CK_3XXX),
> +       CLK(NULL,       "aes2_ick",     &aes2_ick,      CK_3XXX),
> +       CLK(NULL,       "sha12_ick",    &sha12_ick,     CK_3XXX),
> +       CLK(NULL,       "des2_ick",     &des2_ick,      CK_3XXX),
> +       CLK("mmci-omap-hs.1",   "ick",  &mmchs2_ick,    CK_3XXX),
> +       CLK("mmci-omap-hs.0",   "ick",  &mmchs1_ick,    CK_3XXX),
> +       CLK(NULL,       "mspro_ick",    &mspro_ick,     CK_3XXX),
> +       CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_3XXX),
> +       CLK("omap2_mcspi.4", "ick",     &mcspi4_ick,    CK_3XXX),
> +       CLK("omap2_mcspi.3", "ick",     &mcspi3_ick,    CK_3XXX),
> +       CLK("omap2_mcspi.2", "ick",     &mcspi2_ick,    CK_3XXX),
> +       CLK("omap2_mcspi.1", "ick",     &mcspi1_ick,    CK_3XXX),
> +       CLK("i2c_omap.3", "ick",        &i2c3_ick,      CK_3XXX),
> +       CLK("i2c_omap.2", "ick",        &i2c2_ick,      CK_3XXX),
> +       CLK("i2c_omap.1", "ick",        &i2c1_ick,      CK_3XXX),
> +       CLK(NULL,       "uart2_ick",    &uart2_ick,     CK_3XXX),
> +       CLK(NULL,       "uart1_ick",    &uart1_ick,     CK_3XXX),
> +       CLK(NULL,       "gpt11_ick",    &gpt11_ick,     CK_3XXX),
> +       CLK(NULL,       "gpt10_ick",    &gpt10_ick,     CK_3XXX),
> +       CLK("omap-mcbsp.5", "ick",      &mcbsp5_ick,    CK_3XXX),
> +       CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick,    CK_3XXX),
>         CLK(NULL,       "fac_ick",      &fac_ick,       CK_3430ES1),
> -       CLK(NULL,       "mailboxes_ick", &mailboxes_ick, CK_343X),
> -       CLK(NULL,       "omapctrl_ick", &omapctrl_ick,  CK_343X),
> -       CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick,    CK_343X),
> +       CLK(NULL,       "mailboxes_ick", &mailboxes_ick, CK_3XXX),
> +       CLK(NULL,       "omapctrl_ick", &omapctrl_ick,  CK_3XXX),
> +       CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick,    CK_3XXX),
>         CLK(NULL,       "ssi_ick",      &ssi_ick_3430es1,       CK_3430ES1),
>         CLK(NULL,       "ssi_ick",      &ssi_ick_3430es2,       CK_3430ES2),
>         CLK(NULL,       "usb_l4_ick",   &usb_l4_ick,    CK_3430ES1),
> -       CLK(NULL,       "security_l4_ick2", &security_l4_ick2, CK_343X),
> -       CLK(NULL,       "aes1_ick",     &aes1_ick,      CK_343X),
> -       CLK("omap_rng", "ick",          &rng_ick,       CK_343X),
> -       CLK(NULL,       "sha11_ick",    &sha11_ick,     CK_343X),
> -       CLK(NULL,       "des1_ick",     &des1_ick,      CK_343X),
> +       CLK(NULL,       "security_l4_ick2", &security_l4_ick2, CK_3XXX),
> +       CLK(NULL,       "aes1_ick",     &aes1_ick,      CK_3XXX),
> +       CLK("omap_rng", "ick",          &rng_ick,       CK_3XXX),
> +       CLK(NULL,       "sha11_ick",    &sha11_ick,     CK_3XXX),
> +       CLK(NULL,       "des1_ick",     &des1_ick,      CK_3XXX),
>         CLK("omapfb",   "dss1_fck",     &dss1_alwon_fck_3430es1, CK_3430ES1),
>         CLK("omapfb",   "dss1_fck",     &dss1_alwon_fck_3430es2, CK_3430ES2),
> -       CLK("omapfb",   "tv_fck",       &dss_tv_fck,    CK_343X),
> -       CLK("omapfb",   "video_fck",    &dss_96m_fck,   CK_343X),
> -       CLK("omapfb",   "dss2_fck",     &dss2_alwon_fck, CK_343X),
> +       CLK("omapfb",   "tv_fck",       &dss_tv_fck,    CK_3XXX),
> +       CLK("omapfb",   "video_fck",    &dss_96m_fck,   CK_3XXX),
> +       CLK("omapfb",   "dss2_fck",     &dss2_alwon_fck, CK_3XXX),
>         CLK("omapfb",   "ick",          &dss_ick_3430es1,       CK_3430ES1),
>         CLK("omapfb",   "ick",          &dss_ick_3430es2,       CK_3430ES2),
> -       CLK(NULL,       "cam_mclk",     &cam_mclk,      CK_343X),
> -       CLK(NULL,       "cam_ick",      &cam_ick,       CK_343X),
> -       CLK(NULL,       "csi2_96m_fck", &csi2_96m_fck,  CK_343X),
> +       CLK(NULL,       "cam_mclk",     &cam_mclk,      CK_3XXX),
> +       CLK(NULL,       "cam_ick",      &cam_ick,       CK_3XXX),
> +       CLK(NULL,       "csi2_96m_fck", &csi2_96m_fck,  CK_3XXX),
>         CLK(NULL,       "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2),
>         CLK(NULL,       "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2),
>         CLK(NULL,       "usbhost_ick",  &usbhost_ick,   CK_3430ES2),
>         CLK(NULL,       "usim_fck",     &usim_fck,      CK_3430ES2),
> -       CLK(NULL,       "gpt1_fck",     &gpt1_fck,      CK_343X),
> -       CLK(NULL,       "wkup_32k_fck", &wkup_32k_fck,  CK_343X),
> -       CLK(NULL,       "gpio1_dbck",   &gpio1_dbck,    CK_343X),
> -       CLK("omap_wdt", "fck",          &wdt2_fck,      CK_343X),
> -       CLK(NULL,       "wkup_l4_ick",  &wkup_l4_ick,   CK_343X),
> +       CLK(NULL,       "gpt1_fck",     &gpt1_fck,      CK_3XXX),
> +       CLK(NULL,       "wkup_32k_fck", &wkup_32k_fck,  CK_3XXX),
> +       CLK(NULL,       "gpio1_dbck",   &gpio1_dbck,    CK_3XXX),
> +       CLK("omap_wdt", "fck",          &wdt2_fck,      CK_3XXX),
> +       CLK(NULL,       "wkup_l4_ick",  &wkup_l4_ick,   CK_3XXX),
>         CLK(NULL,       "usim_ick",     &usim_ick,      CK_3430ES2),
> -       CLK("omap_wdt", "ick",          &wdt2_ick,      CK_343X),
> -       CLK(NULL,       "wdt1_ick",     &wdt1_ick,      CK_343X),
> -       CLK(NULL,       "gpio1_ick",    &gpio1_ick,     CK_343X),
> -       CLK(NULL,       "omap_32ksync_ick", &omap_32ksync_ick, CK_343X),
> -       CLK(NULL,       "gpt12_ick",    &gpt12_ick,     CK_343X),
> -       CLK(NULL,       "gpt1_ick",     &gpt1_ick,      CK_343X),
> -       CLK(NULL,       "per_96m_fck",  &per_96m_fck,   CK_343X),
> -       CLK(NULL,       "per_48m_fck",  &per_48m_fck,   CK_343X),
> -       CLK(NULL,       "uart3_fck",    &uart3_fck,     CK_343X),
> -       CLK(NULL,       "gpt2_fck",     &gpt2_fck,      CK_343X),
> -       CLK(NULL,       "gpt3_fck",     &gpt3_fck,      CK_343X),
> -       CLK(NULL,       "gpt4_fck",     &gpt4_fck,      CK_343X),
> -       CLK(NULL,       "gpt5_fck",     &gpt5_fck,      CK_343X),
> -       CLK(NULL,       "gpt6_fck",     &gpt6_fck,      CK_343X),
> -       CLK(NULL,       "gpt7_fck",     &gpt7_fck,      CK_343X),
> -       CLK(NULL,       "gpt8_fck",     &gpt8_fck,      CK_343X),
> -       CLK(NULL,       "gpt9_fck",     &gpt9_fck,      CK_343X),
> -       CLK(NULL,       "per_32k_alwon_fck", &per_32k_alwon_fck, CK_343X),
> -       CLK(NULL,       "gpio6_dbck",   &gpio6_dbck,    CK_343X),
> -       CLK(NULL,       "gpio5_dbck",   &gpio5_dbck,    CK_343X),
> -       CLK(NULL,       "gpio4_dbck",   &gpio4_dbck,    CK_343X),
> -       CLK(NULL,       "gpio3_dbck",   &gpio3_dbck,    CK_343X),
> -       CLK(NULL,       "gpio2_dbck",   &gpio2_dbck,    CK_343X),
> -       CLK(NULL,       "wdt3_fck",     &wdt3_fck,      CK_343X),
> -       CLK(NULL,       "per_l4_ick",   &per_l4_ick,    CK_343X),
> -       CLK(NULL,       "gpio6_ick",    &gpio6_ick,     CK_343X),
> -       CLK(NULL,       "gpio5_ick",    &gpio5_ick,     CK_343X),
> -       CLK(NULL,       "gpio4_ick",    &gpio4_ick,     CK_343X),
> -       CLK(NULL,       "gpio3_ick",    &gpio3_ick,     CK_343X),
> -       CLK(NULL,       "gpio2_ick",    &gpio2_ick,     CK_343X),
> -       CLK(NULL,       "wdt3_ick",     &wdt3_ick,      CK_343X),
> -       CLK(NULL,       "uart3_ick",    &uart3_ick,     CK_343X),
> -       CLK(NULL,       "gpt9_ick",     &gpt9_ick,      CK_343X),
> -       CLK(NULL,       "gpt8_ick",     &gpt8_ick,      CK_343X),
> -       CLK(NULL,       "gpt7_ick",     &gpt7_ick,      CK_343X),
> -       CLK(NULL,       "gpt6_ick",     &gpt6_ick,      CK_343X),
> -       CLK(NULL,       "gpt5_ick",     &gpt5_ick,      CK_343X),
> -       CLK(NULL,       "gpt4_ick",     &gpt4_ick,      CK_343X),
> -       CLK(NULL,       "gpt3_ick",     &gpt3_ick,      CK_343X),
> -       CLK(NULL,       "gpt2_ick",     &gpt2_ick,      CK_343X),
> -       CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick,    CK_343X),
> -       CLK("omap-mcbsp.3", "ick",      &mcbsp3_ick,    CK_343X),
> -       CLK("omap-mcbsp.4", "ick",      &mcbsp4_ick,    CK_343X),
> -       CLK("omap-mcbsp.2", "fck",      &mcbsp2_fck,    CK_343X),
> -       CLK("omap-mcbsp.3", "fck",      &mcbsp3_fck,    CK_343X),
> -       CLK("omap-mcbsp.4", "fck",      &mcbsp4_fck,    CK_343X),
> -       CLK(NULL,       "emu_src_ck",   &emu_src_ck,    CK_343X),
> -       CLK(NULL,       "pclk_fck",     &pclk_fck,      CK_343X),
> -       CLK(NULL,       "pclkx2_fck",   &pclkx2_fck,    CK_343X),
> -       CLK(NULL,       "atclk_fck",    &atclk_fck,     CK_343X),
> -       CLK(NULL,       "traceclk_src_fck", &traceclk_src_fck, CK_343X),
> -       CLK(NULL,       "traceclk_fck", &traceclk_fck,  CK_343X),
> -       CLK(NULL,       "sr1_fck",      &sr1_fck,       CK_343X),
> -       CLK(NULL,       "sr2_fck",      &sr2_fck,       CK_343X),
> -       CLK(NULL,       "sr_l4_ick",    &sr_l4_ick,     CK_343X),
> -       CLK(NULL,       "secure_32k_fck", &secure_32k_fck, CK_343X),
> -       CLK(NULL,       "gpt12_fck",    &gpt12_fck,     CK_343X),
> -       CLK(NULL,       "wdt1_fck",     &wdt1_fck,      CK_343X),
> +       CLK("omap_wdt", "ick",          &wdt2_ick,      CK_3XXX),
> +       CLK(NULL,       "wdt1_ick",     &wdt1_ick,      CK_3XXX),
> +       CLK(NULL,       "gpio1_ick",    &gpio1_ick,     CK_3XXX),
> +       CLK(NULL,       "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX),
> +       CLK(NULL,       "gpt12_ick",    &gpt12_ick,     CK_3XXX),
> +       CLK(NULL,       "gpt1_ick",     &gpt1_ick,      CK_3XXX),
> +       CLK(NULL,       "per_96m_fck",  &per_96m_fck,   CK_3XXX),
> +       CLK(NULL,       "per_48m_fck",  &per_48m_fck,   CK_3XXX),
> +       CLK(NULL,       "uart3_fck",    &uart3_fck,     CK_3XXX),
> +       CLK(NULL,       "gpt2_fck",     &gpt2_fck,      CK_3XXX),
> +       CLK(NULL,       "gpt3_fck",     &gpt3_fck,      CK_3XXX),
> +       CLK(NULL,       "gpt4_fck",     &gpt4_fck,      CK_3XXX),
> +       CLK(NULL,       "gpt5_fck",     &gpt5_fck,      CK_3XXX),
> +       CLK(NULL,       "gpt6_fck",     &gpt6_fck,      CK_3XXX),
> +       CLK(NULL,       "gpt7_fck",     &gpt7_fck,      CK_3XXX),
> +       CLK(NULL,       "gpt8_fck",     &gpt8_fck,      CK_3XXX),
> +       CLK(NULL,       "gpt9_fck",     &gpt9_fck,      CK_3XXX),
> +       CLK(NULL,       "per_32k_alwon_fck", &per_32k_alwon_fck, CK_3XXX),
> +       CLK(NULL,       "gpio6_dbck",   &gpio6_dbck,    CK_3XXX),
> +       CLK(NULL,       "gpio5_dbck",   &gpio5_dbck,    CK_3XXX),
> +       CLK(NULL,       "gpio4_dbck",   &gpio4_dbck,    CK_3XXX),
> +       CLK(NULL,       "gpio3_dbck",   &gpio3_dbck,    CK_3XXX),
> +       CLK(NULL,       "gpio2_dbck",   &gpio2_dbck,    CK_3XXX),
> +       CLK(NULL,       "wdt3_fck",     &wdt3_fck,      CK_3XXX),
> +       CLK(NULL,       "per_l4_ick",   &per_l4_ick,    CK_3XXX),
> +       CLK(NULL,       "gpio6_ick",    &gpio6_ick,     CK_3XXX),
> +       CLK(NULL,       "gpio5_ick",    &gpio5_ick,     CK_3XXX),
> +       CLK(NULL,       "gpio4_ick",    &gpio4_ick,     CK_3XXX),
> +       CLK(NULL,       "gpio3_ick",    &gpio3_ick,     CK_3XXX),
> +       CLK(NULL,       "gpio2_ick",    &gpio2_ick,     CK_3XXX),
> +       CLK(NULL,       "wdt3_ick",     &wdt3_ick,      CK_3XXX),
> +       CLK(NULL,       "uart3_ick",    &uart3_ick,     CK_3XXX),
> +       CLK(NULL,       "gpt9_ick",     &gpt9_ick,      CK_3XXX),
> +       CLK(NULL,       "gpt8_ick",     &gpt8_ick,      CK_3XXX),
> +       CLK(NULL,       "gpt7_ick",     &gpt7_ick,      CK_3XXX),
> +       CLK(NULL,       "gpt6_ick",     &gpt6_ick,      CK_3XXX),
> +       CLK(NULL,       "gpt5_ick",     &gpt5_ick,      CK_3XXX),
> +       CLK(NULL,       "gpt4_ick",     &gpt4_ick,      CK_3XXX),
> +       CLK(NULL,       "gpt3_ick",     &gpt3_ick,      CK_3XXX),
> +       CLK(NULL,       "gpt2_ick",     &gpt2_ick,      CK_3XXX),
> +       CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick,    CK_3XXX),
> +       CLK("omap-mcbsp.3", "ick",      &mcbsp3_ick,    CK_3XXX),
> +       CLK("omap-mcbsp.4", "ick",      &mcbsp4_ick,    CK_3XXX),
> +       CLK("omap-mcbsp.2", "fck",      &mcbsp2_fck,    CK_3XXX),
> +       CLK("omap-mcbsp.3", "fck",      &mcbsp3_fck,    CK_3XXX),
> +       CLK("omap-mcbsp.4", "fck",      &mcbsp4_fck,    CK_3XXX),
> +       CLK(NULL,       "emu_src_ck",   &emu_src_ck,    CK_3XXX),
> +       CLK(NULL,       "pclk_fck",     &pclk_fck,      CK_3XXX),
> +       CLK(NULL,       "pclkx2_fck",   &pclkx2_fck,    CK_3XXX),
> +       CLK(NULL,       "atclk_fck",    &atclk_fck,     CK_3XXX),
> +       CLK(NULL,       "traceclk_src_fck", &traceclk_src_fck, CK_3XXX),
> +       CLK(NULL,       "traceclk_fck", &traceclk_fck,  CK_3XXX),
> +       CLK(NULL,       "sr1_fck",      &sr1_fck,       CK_3XXX),
> +       CLK(NULL,       "sr2_fck",      &sr2_fck,       CK_3XXX),
> +       CLK(NULL,       "sr_l4_ick",    &sr_l4_ick,     CK_3XXX),
> +       CLK(NULL,       "secure_32k_fck", &secure_32k_fck, CK_3XXX),
> +       CLK(NULL,       "gpt12_fck",    &gpt12_fck,     CK_3XXX),
> +       CLK(NULL,       "wdt1_fck",     &wdt1_fck,      CK_3XXX),
>  };
> 
>  /* CM_AUTOIDLE_PLL*.AUTO_* bit values */
> @@ -1202,8 +1202,8 @@ int __init omap2_clk_init(void)
>         u32 cpu_clkflg;
> 
>         if (cpu_is_omap34xx()) {
> -               cpu_mask = RATE_IN_343X;
> -               cpu_clkflg = CK_343X;
> +               cpu_mask = RATE_IN_3XXX;
> +               cpu_clkflg = CK_3XXX;
> 
>                 /*
>                  * Update this if there are further clock changes between ES2
> diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
> index a1b3de7..813a83e 100644
> --- a/arch/arm/mach-omap2/clock34xx.h
> +++ b/arch/arm/mach-omap2/clock34xx.h
> @@ -120,12 +120,12 @@ static struct clk virt_38_4m_ck = {
>  };
> 
>  static const struct clksel_rate osc_sys_12m_rates[] = {
> -       { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
> +       { .div = 1, .val = 0, .flags = RATE_IN_3XXX | DEFAULT_RATE },
>         { .div = 0 }
>  };
> 
>  static const struct clksel_rate osc_sys_13m_rates[] = {
> -       { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
> +       { .div = 1, .val = 1, .flags = RATE_IN_3XXX | DEFAULT_RATE },
>         { .div = 0 }
>  };
> 
> @@ -135,17 +135,17 @@ static const struct clksel_rate osc_sys_16_8m_rates[] = {
>  };
> 
>  static const struct clksel_rate osc_sys_19_2m_rates[] = {
> -       { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
> +       { .div = 1, .val = 2, .flags = RATE_IN_3XXX | DEFAULT_RATE },
>         { .div = 0 }
>  };
> 
>  static const struct clksel_rate osc_sys_26m_rates[] = {
> -       { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
> +       { .div = 1, .val = 3, .flags = RATE_IN_3XXX | DEFAULT_RATE },
>         { .div = 0 }
>  };
> 
>  static const struct clksel_rate osc_sys_38_4m_rates[] = {
> -       { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
> +       { .div = 1, .val = 4, .flags = RATE_IN_3XXX | DEFAULT_RATE },
>         { .div = 0 }
>  };
> 
> @@ -174,8 +174,8 @@ static struct clk osc_sys_ck = {
>  };
> 
>  static const struct clksel_rate div2_rates[] = {
> -       { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
> -       { .div = 2, .val = 2, .flags = RATE_IN_343X },
> +       { .div = 1, .val = 1, .flags = RATE_IN_3XXX | DEFAULT_RATE },
> +       { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
>         { .div = 0 }
>  };
> 
> @@ -224,22 +224,22 @@ static struct clk sys_clkout1 = {
>  /* CM CLOCKS */
> 
>  static const struct clksel_rate div16_dpll_rates[] = {
> -       { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
> -       { .div = 2, .val = 2, .flags = RATE_IN_343X },
> -       { .div = 3, .val = 3, .flags = RATE_IN_343X },
> -       { .div = 4, .val = 4, .flags = RATE_IN_343X },
> -       { .div = 5, .val = 5, .flags = RATE_IN_343X },
> -       { .div = 6, .val = 6, .flags = RATE_IN_343X },
> -       { .div = 7, .val = 7, .flags = RATE_IN_343X },
> -       { .div = 8, .val = 8, .flags = RATE_IN_343X },
> -       { .div = 9, .val = 9, .flags = RATE_IN_343X },
> -       { .div = 10, .val = 10, .flags = RATE_IN_343X },
> -       { .div = 11, .val = 11, .flags = RATE_IN_343X },
> -       { .div = 12, .val = 12, .flags = RATE_IN_343X },
> -       { .div = 13, .val = 13, .flags = RATE_IN_343X },
> -       { .div = 14, .val = 14, .flags = RATE_IN_343X },
> -       { .div = 15, .val = 15, .flags = RATE_IN_343X },
> -       { .div = 16, .val = 16, .flags = RATE_IN_343X },
> +       { .div = 1, .val = 1, .flags = RATE_IN_3XXX | DEFAULT_RATE },
> +       { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
> +       { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
> +       { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
> +       { .div = 5, .val = 5, .flags = RATE_IN_3XXX },
> +       { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
> +       { .div = 7, .val = 7, .flags = RATE_IN_3XXX },
> +       { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
> +       { .div = 9, .val = 9, .flags = RATE_IN_3XXX },
> +       { .div = 10, .val = 10, .flags = RATE_IN_3XXX },
> +       { .div = 11, .val = 11, .flags = RATE_IN_3XXX },
> +       { .div = 12, .val = 12, .flags = RATE_IN_3XXX },
> +       { .div = 13, .val = 13, .flags = RATE_IN_3XXX },
> +       { .div = 14, .val = 14, .flags = RATE_IN_3XXX },
> +       { .div = 15, .val = 15, .flags = RATE_IN_3XXX },
> +       { .div = 16, .val = 16, .flags = RATE_IN_3XXX },
>         { .div = 0 }
>  };
> 
> @@ -425,8 +425,8 @@ static struct clk dpll3_x2_ck = {
>  };
> 
>  static const struct clksel_rate div31_dpll3_rates[] = {
> -       { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
> -       { .div = 2, .val = 2, .flags = RATE_IN_343X },
> +       { .div = 1, .val = 1, .flags = RATE_IN_3XXX | DEFAULT_RATE },
> +       { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
>         { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
>         { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
>         { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
> @@ -634,12 +634,12 @@ static struct clk cm_96m_fck = {
>  };
> 
>  static const struct clksel_rate omap_96m_dpll_rates[] = {
> -       { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
> +       { .div = 1, .val = 0, .flags = RATE_IN_3XXX | DEFAULT_RATE },
>         { .div = 0 }
>  };
> 
>  static const struct clksel_rate omap_96m_sys_rates[] = {
> -       { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
> +       { .div = 1, .val = 1, .flags = RATE_IN_3XXX | DEFAULT_RATE },
>         { .div = 0 }
>  };
> 
> @@ -687,12 +687,12 @@ static struct clk dpll4_m3x2_ck = {
>  };
> 
>  static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
> -       { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
> +       { .div = 1, .val = 0, .flags = RATE_IN_3XXX | DEFAULT_RATE },
>         { .div = 0 }
>  };
> 
>  static const struct clksel_rate omap_54m_alt_rates[] = {
> -       { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
> +       { .div = 1, .val = 1, .flags = RATE_IN_3XXX | DEFAULT_RATE },
>         { .div = 0 }
>  };
> 
> @@ -713,12 +713,12 @@ static struct clk omap_54m_fck = {
>  };
> 
>  static const struct clksel_rate omap_48m_cm96m_rates[] = {
> -       { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
> +       { .div = 2, .val = 0, .flags = RATE_IN_3XXX | DEFAULT_RATE },
>         { .div = 0 }
>  };
> 
>  static const struct clksel_rate omap_48m_alt_rates[] = {
> -       { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
> +       { .div = 1, .val = 1, .flags = RATE_IN_3XXX | DEFAULT_RATE },
>         { .div = 0 }
>  };
> 
> @@ -890,22 +890,22 @@ static struct clk dpll5_m2_ck = {
>  /* CM EXTERNAL CLOCK OUTPUTS */
> 
>  static const struct clksel_rate clkout2_src_core_rates[] = {
> -       { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
> +       { .div = 1, .val = 0, .flags = RATE_IN_3XXX | DEFAULT_RATE },
>         { .div = 0 }
>  };
> 
>  static const struct clksel_rate clkout2_src_sys_rates[] = {
> -       { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
> +       { .div = 1, .val = 1, .flags = RATE_IN_3XXX | DEFAULT_RATE },
>         { .div = 0 }
>  };
> 
>  static const struct clksel_rate clkout2_src_96m_rates[] = {
> -       { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
> +       { .div = 1, .val = 2, .flags = RATE_IN_3XXX | DEFAULT_RATE },
>         { .div = 0 }
>  };
> 
>  static const struct clksel_rate clkout2_src_54m_rates[] = {
> -       { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
> +       { .div = 1, .val = 3, .flags = RATE_IN_3XXX | DEFAULT_RATE },
>         { .div = 0 }
>  };
> 
> @@ -931,11 +931,11 @@ static struct clk clkout2_src_ck = {
>  };
> 
>  static const struct clksel_rate sys_clkout2_rates[] = {
> -       { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
> -       { .div = 2, .val = 1, .flags = RATE_IN_343X },
> -       { .div = 4, .val = 2, .flags = RATE_IN_343X },
> -       { .div = 8, .val = 3, .flags = RATE_IN_343X },
> -       { .div = 16, .val = 4, .flags = RATE_IN_343X },
> +       { .div = 1, .val = 0, .flags = RATE_IN_3XXX | DEFAULT_RATE },
> +       { .div = 2, .val = 1, .flags = RATE_IN_3XXX },
> +       { .div = 4, .val = 2, .flags = RATE_IN_3XXX },
> +       { .div = 8, .val = 3, .flags = RATE_IN_3XXX },
> +       { .div = 16, .val = 4, .flags = RATE_IN_3XXX },
>         { .div = 0 },
>  };
> 
> @@ -966,9 +966,9 @@ static struct clk corex2_fck = {
>  /* DPLL power domain clock controls */
> 
>  static const struct clksel_rate div4_rates[] = {
> -       { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
> -       { .div = 2, .val = 2, .flags = RATE_IN_343X },
> -       { .div = 4, .val = 4, .flags = RATE_IN_343X },
> +       { .div = 1, .val = 1, .flags = RATE_IN_3XXX | DEFAULT_RATE },
> +       { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
> +       { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
>         { .div = 0 }
>  };
> 
> @@ -1002,8 +1002,8 @@ static struct clk mpu_ck = {
> 
>  /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
>  static const struct clksel_rate arm_fck_rates[] = {
> -       { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
> -       { .div = 2, .val = 1, .flags = RATE_IN_343X },
> +       { .div = 1, .val = 0, .flags = RATE_IN_3XXX | DEFAULT_RATE },
> +       { .div = 2, .val = 1, .flags = RATE_IN_3XXX },
>         { .div = 0 },
>  };
> 
> @@ -1175,14 +1175,14 @@ static struct clk gfx_cg2_ck = {
>  /* SGX power domain - 3430ES2 only */
> 
>  static const struct clksel_rate sgx_core_rates[] = {
> -       { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
> -       { .div = 4, .val = 1, .flags = RATE_IN_343X },
> -       { .div = 6, .val = 2, .flags = RATE_IN_343X },
> +       { .div = 3, .val = 0, .flags = RATE_IN_3XXX | DEFAULT_RATE },
> +       { .div = 4, .val = 1, .flags = RATE_IN_3XXX },
> +       { .div = 6, .val = 2, .flags = RATE_IN_3XXX },
>         { .div = 0 },
>  };
> 
>  static const struct clksel_rate sgx_96m_rates[] = {
> -       { .div = 1,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
> +       { .div = 1,  .val = 3, .flags = RATE_IN_3XXX | DEFAULT_RATE },
>         { .div = 0 },
>  };
> 
> @@ -1408,12 +1408,12 @@ static struct clk i2c1_fck = {
>   * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
>   */
>  static const struct clksel_rate common_mcbsp_96m_rates[] = {
> -       { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
> +       { .div = 1, .val = 0, .flags = RATE_IN_3XXX | DEFAULT_RATE },
>         { .div = 0 }
>  };
> 
>  static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
> -       { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
> +       { .div = 1, .val = 1, .flags = RATE_IN_3XXX | DEFAULT_RATE },
>         { .div = 0 }
>  };
> 
> @@ -1550,12 +1550,12 @@ static struct clk hdq_fck = {
>  /* DPLL3-derived clock */
> 
>  static const struct clksel_rate ssi_ssr_corex2_rates[] = {
> -       { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
> -       { .div = 2, .val = 2, .flags = RATE_IN_343X },
> -       { .div = 3, .val = 3, .flags = RATE_IN_343X },
> -       { .div = 4, .val = 4, .flags = RATE_IN_343X },
> -       { .div = 6, .val = 6, .flags = RATE_IN_343X },
> -       { .div = 8, .val = 8, .flags = RATE_IN_343X },
> +       { .div = 1, .val = 1, .flags = RATE_IN_3XXX | DEFAULT_RATE },
> +       { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
> +       { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
> +       { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
> +       { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
> +       { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
>         { .div = 0 }
>  };
> 
> @@ -2200,18 +2200,18 @@ static struct clk usbhost_ick = {
>  /* WKUP */
> 
>  static const struct clksel_rate usim_96m_rates[] = {
> -       { .div = 2,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
> -       { .div = 4,  .val = 4, .flags = RATE_IN_343X },
> -       { .div = 8,  .val = 5, .flags = RATE_IN_343X },
> -       { .div = 10, .val = 6, .flags = RATE_IN_343X },
> +       { .div = 2,  .val = 3, .flags = RATE_IN_3XXX | DEFAULT_RATE },
> +       { .div = 4,  .val = 4, .flags = RATE_IN_3XXX },
> +       { .div = 8,  .val = 5, .flags = RATE_IN_3XXX },
> +       { .div = 10, .val = 6, .flags = RATE_IN_3XXX },
>         { .div = 0 },
>  };
> 
>  static const struct clksel_rate usim_120m_rates[] = {
> -       { .div = 4,  .val = 7,  .flags = RATE_IN_343X | DEFAULT_RATE },
> -       { .div = 8,  .val = 8,  .flags = RATE_IN_343X },
> -       { .div = 16, .val = 9,  .flags = RATE_IN_343X },
> -       { .div = 20, .val = 10, .flags = RATE_IN_343X },
> +       { .div = 4,  .val = 7,  .flags = RATE_IN_3XXX | DEFAULT_RATE },
> +       { .div = 8,  .val = 8,  .flags = RATE_IN_3XXX },
> +       { .div = 16, .val = 9,  .flags = RATE_IN_3XXX },
> +       { .div = 20, .val = 10, .flags = RATE_IN_3XXX },
>         { .div = 0 },
>  };
> 
> @@ -2804,22 +2804,22 @@ static struct clk mcbsp4_fck = {
>  /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
> 
>  static const struct clksel_rate emu_src_sys_rates[] = {
> -       { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
> +       { .div = 1, .val = 0, .flags = RATE_IN_3XXX | DEFAULT_RATE },
>         { .div = 0 },
>  };
> 
>  static const struct clksel_rate emu_src_core_rates[] = {
> -       { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
> +       { .div = 1, .val = 1, .flags = RATE_IN_3XXX | DEFAULT_RATE },
>         { .div = 0 },
>  };
> 
>  static const struct clksel_rate emu_src_per_rates[] = {
> -       { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
> +       { .div = 1, .val = 2, .flags = RATE_IN_3XXX | DEFAULT_RATE },
>         { .div = 0 },
>  };
> 
>  static const struct clksel_rate emu_src_mpu_rates[] = {
> -       { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
> +       { .div = 1, .val = 3, .flags = RATE_IN_3XXX | DEFAULT_RATE },
>         { .div = 0 },
>  };
> 
> @@ -2848,10 +2848,10 @@ static struct clk emu_src_ck = {
>  };
> 
>  static const struct clksel_rate pclk_emu_rates[] = {
> -       { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
> -       { .div = 3, .val = 3, .flags = RATE_IN_343X },
> -       { .div = 4, .val = 4, .flags = RATE_IN_343X },
> -       { .div = 6, .val = 6, .flags = RATE_IN_343X },
> +       { .div = 2, .val = 2, .flags = RATE_IN_3XXX | DEFAULT_RATE },
> +       { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
> +       { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
> +       { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
>         { .div = 0 },
>  };
> 
> @@ -2872,9 +2872,9 @@ static struct clk pclk_fck = {
>  };
> 
>  static const struct clksel_rate pclkx2_emu_rates[] = {
> -       { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
> -       { .div = 2, .val = 2, .flags = RATE_IN_343X },
> -       { .div = 3, .val = 3, .flags = RATE_IN_343X },
> +       { .div = 1, .val = 1, .flags = RATE_IN_3XXX | DEFAULT_RATE },
> +       { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
> +       { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
>         { .div = 0 },
>  };
> 
> @@ -2922,9 +2922,9 @@ static struct clk traceclk_src_fck = {
>  };
> 
>  static const struct clksel_rate traceclk_rates[] = {
> -       { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
> -       { .div = 2, .val = 2, .flags = RATE_IN_343X },
> -       { .div = 4, .val = 4, .flags = RATE_IN_343X },
> +       { .div = 1, .val = 1, .flags = RATE_IN_3XXX | DEFAULT_RATE },
> +       { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
> +       { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
>         { .div = 0 },
>  };
> 
> diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
> index 66648d4..359ccb4 100644
> --- a/arch/arm/plat-omap/include/plat/clock.h
> +++ b/arch/arm/plat-omap/include/plat/clock.h
> @@ -157,7 +157,7 @@ extern const struct clkops clkops_null;
>  #define DEFAULT_RATE           (1 << 0)
>  #define RATE_IN_242X           (1 << 1)
>  #define RATE_IN_243X           (1 << 2)
> -#define RATE_IN_343X           (1 << 3)        /* rates common to all 343X */
> +#define RATE_IN_3XXX           (1 << 3)        /* rates common to all 343X */
>  #define RATE_IN_3430ES2                (1 << 4)        /* 3430ES2 rates only */
> 
>  #define RATE_IN_24XX           (RATE_IN_242X | RATE_IN_243X)
> --
> 1.5.6.3
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 


-- 
Regards,
Nishanth Menon

^ permalink raw reply	[flat|nested] 12+ messages in thread

* RE: [PATCHV2 3/4] OMAP3: Correct width for CLKSEL Fields
  2009-11-20 15:28     ` [PATCHV2 3/4] OMAP3: Correct width for CLKSEL Fields Vishwanath BS
  2009-11-20 15:28       ` [PATCHV2 4/4] OMAP3: add support for 192Mhz sgx clock Vishwanath BS
@ 2009-11-20 15:57       ` Aguirre, Sergio
  2009-11-23  8:15         ` Sripathy, Vishwanath
  2009-11-20 16:00       ` Nishanth Menon
  2 siblings, 1 reply; 12+ messages in thread
From: Aguirre, Sergio @ 2009-11-20 15:57 UTC (permalink / raw)
  To: Sripathy, Vishwanath, linux-omap@vger.kernel.org

Vishwa, 

> -----Original Message-----
> From: linux-omap-owner@vger.kernel.org 
> [mailto:linux-omap-owner@vger.kernel.org] On Behalf Of 
> Sripathy, Vishwanath
> Sent: Friday, November 20, 2009 9:29 AM
> To: linux-omap@vger.kernel.org; Sripathy, Vishwanath
> Subject: [PATCHV2 3/4] OMAP3: Correct width for CLKSEL Fields
> 
> DPLL4 M, M3, M4, M5 and M6 field width has been increased by 1 bit in
> 3630.This patch has changes to accommodate this in CM 
> dynamically based on
> chip version.
> 
> Signed-off-by: Vishwanath BS <vishwanath.bs@ti.com>
> ---
>  arch/arm/mach-omap2/clock34xx.c         |   18 ++++++++--
>  arch/arm/mach-omap2/clock34xx.h         |   53 
> ++++++++++++++++++++++++++++--
>  arch/arm/mach-omap2/cm-regbits-34xx.h   |    7 +++-
>  arch/arm/plat-omap/include/plat/clock.h |    4 +-
>  4 files changed, 71 insertions(+), 11 deletions(-)
>  mode change 100644 => 100755 arch/arm/mach-omap2/clock34xx.c

No file mode changes, please.

> 
> diff --git a/arch/arm/mach-omap2/clock34xx.c 
> b/arch/arm/mach-omap2/clock34xx.c
> index 167f075..1e35f9a
> --- a/arch/arm/mach-omap2/clock34xx.c
> +++ b/arch/arm/mach-omap2/clock34xx.c
> @@ -43,6 +43,7 @@
>  #include "prm-regbits-34xx.h"
>  #include "cm.h"
>  #include "cm-regbits-34xx.h"
> +#include <plat/cpu.h>
>  
>  static const struct clkops clkops_noncore_dpll_ops;
>  
> @@ -97,6 +98,7 @@ struct omap_clk {
>  #define CK_3XXX		(1 << 0)
>  #define CK_3430ES1	(1 << 1)
>  #define CK_3430ES2	(1 << 2)
> +#define CK_363X		(1 << 3)
>  
>  static struct omap_clk omap34xx_clks[] = {
>  	CLK(NULL,	"omap_32k_fck",	&omap_32k_fck,	CK_3XXX),
> @@ -134,13 +136,13 @@ static struct omap_clk omap34xx_clks[] = {
>  	CLK(NULL,	"omap_12m_fck",	&omap_12m_fck,	CK_3XXX),
>  	CLK(NULL,	"dpll4_m2_ck",	&dpll4_m2_ck,	CK_3XXX),
>  	CLK(NULL,	"dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_3XXX),
> -	CLK(NULL,	"dpll4_m3_ck",	&dpll4_m3_ck,	CK_3XXX),
> +	CLK(NULL,	"dpll4_m3_ck",	&dpll4_m3_ck,	CK_3XXX 
> | CK_363X),

Shouldn't CK_363X replace CK_3XXX?

CK_363X is always inside the CK_3XXX scope, but not the other way around.

>  	CLK(NULL,	"dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_3XXX),
> -	CLK(NULL,	"dpll4_m4_ck",	&dpll4_m4_ck,	CK_3XXX),
> +	CLK(NULL,	"dpll4_m4_ck",	&dpll4_m4_ck,	CK_3XXX 
> | CK_363X),
>  	CLK(NULL,	"dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_3XXX),
> -	CLK(NULL,	"dpll4_m5_ck",	&dpll4_m5_ck,	CK_3XXX),
> +	CLK(NULL,	"dpll4_m5_ck",	&dpll4_m5_ck,	CK_3XXX 
> | CK_363X),
>  	CLK(NULL,	"dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_3XXX),
> -	CLK(NULL,	"dpll4_m6_ck",	&dpll4_m6_ck,	CK_3XXX),
> +	CLK(NULL,	"dpll4_m6_ck",	&dpll4_m6_ck,	CK_3XXX 
> | CK_363X),
>  	CLK(NULL,	"dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX),
>  	CLK(NULL,	"emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX),
>  	CLK(NULL,	"dpll5_ck",	&dpll5_ck,	CK_3430ES2),
> @@ -1222,6 +1224,8 @@ int __init omap2_clk_init(void)
>  				OMAP3630_PERIPH_DPLL_DCO_SEL_MASK;
>  			dpll4_ck.dpll_data->sd_div_mask =
>  				OMAP3630_PERIPH_DPLL_SD_DIV_MASK;
> +			dpll4_dd.mult_mask = 
> OMAP3630_PERIPH_DPLL_MULT_MASK;
> +			cpu_mask |= RATE_IN_363X;
>  			}
>  	}
>  
> @@ -1232,6 +1236,12 @@ int __init omap2_clk_init(void)
>  
>  	for (c = omap34xx_clks; c < omap34xx_clks + 
> ARRAY_SIZE(omap34xx_clks); c++)
>  		if (c->cpu & cpu_clkflg) {
> +			/* for 3630, change the mask value for 
> clocks which are
> +				marked as CK_363X*/
> +			if (cpu_is_omap3630() && (c->cpu & CK_363X)) {
> +				c->lk.clk->clksel_mask =
> +						
> c->lk.clk->clksel_mask_3630;
> +			}
>  			clkdev_add(&c->lk);
>  			clk_register(c->lk.clk);
>  			omap2_init_clk_clkdm(c->lk.clk);
> diff --git a/arch/arm/mach-omap2/clock34xx.h 
> b/arch/arm/mach-omap2/clock34xx.h
> index 813a83e..93c92e5 100644
> --- a/arch/arm/mach-omap2/clock34xx.h
> +++ b/arch/arm/mach-omap2/clock34xx.h
> @@ -243,6 +243,42 @@ static const struct clksel_rate 
> div16_dpll_rates[] = {
>  	{ .div = 0 }
>  };
>  
> +static const struct clksel_rate div32_dpll_rates[] = {
> +	{ .div = 1, .val = 1, .flags = RATE_IN_3XXX | DEFAULT_RATE },
> +	{ .div = 2, .val = 2, .flags = RATE_IN_3XXX },
> +	{ .div = 3, .val = 3, .flags = RATE_IN_3XXX },
> +	{ .div = 4, .val = 4, .flags = RATE_IN_3XXX },
> +	{ .div = 5, .val = 5, .flags = RATE_IN_3XXX },
> +	{ .div = 6, .val = 6, .flags = RATE_IN_3XXX },
> +	{ .div = 7, .val = 7, .flags = RATE_IN_3XXX },
> +	{ .div = 8, .val = 8, .flags = RATE_IN_3XXX },
> +	{ .div = 9, .val = 9, .flags = RATE_IN_3XXX },
> +	{ .div = 10, .val = 10, .flags = RATE_IN_3XXX },
> +	{ .div = 11, .val = 11, .flags = RATE_IN_3XXX },
> +	{ .div = 12, .val = 12, .flags = RATE_IN_3XXX },
> +	{ .div = 13, .val = 13, .flags = RATE_IN_3XXX },
> +	{ .div = 14, .val = 14, .flags = RATE_IN_3XXX },
> +	{ .div = 15, .val = 15, .flags = RATE_IN_3XXX },
> +	{ .div = 16, .val = 16, .flags = RATE_IN_3XXX },
> +	{ .div = 17, .val = 17, .flags = RATE_IN_363X },
> +	{ .div = 18, .val = 18, .flags = RATE_IN_363X },
> +	{ .div = 19, .val = 19, .flags = RATE_IN_363X },
> +	{ .div = 20, .val = 20, .flags = RATE_IN_363X },
> +	{ .div = 21, .val = 21, .flags = RATE_IN_363X },
> +	{ .div = 22, .val = 22, .flags = RATE_IN_363X },
> +	{ .div = 23, .val = 23, .flags = RATE_IN_363X },
> +	{ .div = 24, .val = 24, .flags = RATE_IN_363X },
> +	{ .div = 25, .val = 25, .flags = RATE_IN_363X },
> +	{ .div = 26, .val = 26, .flags = RATE_IN_363X },
> +	{ .div = 27, .val = 27, .flags = RATE_IN_363X },
> +	{ .div = 28, .val = 28, .flags = RATE_IN_363X },
> +	{ .div = 29, .val = 29, .flags = RATE_IN_363X },
> +	{ .div = 30, .val = 30, .flags = RATE_IN_363X },
> +	{ .div = 31, .val = 31, .flags = RATE_IN_363X },
> +	{ .div = 32, .val = 32, .flags = RATE_IN_363X },
> +	{ .div = 0 }
> +};
> +
>  /* DPLL1 */
>  /* MPU clock source */
>  /* Type: DPLL */
> @@ -588,6 +624,11 @@ static const struct clksel 
> div16_dpll4_clksel[] = {
>  	{ .parent = NULL }
>  };
>  
> +static const struct clksel div32_dpll4_clksel[] = {
> +	{ .parent = &dpll4_ck, .rates = div32_dpll_rates },
> +	{ .parent = NULL }
> +};
> +
>  /* This virtual clock is the source for dpll4_m2x2_ck */
>  static struct clk dpll4_m2_ck = {
>  	.name		= "dpll4_m2_ck",
> @@ -668,7 +709,8 @@ static struct clk dpll4_m3_ck = {
>  	.init		= &omap2_init_clksel_parent,
>  	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
>  	.clksel_mask	= OMAP3430_CLKSEL_TV_MASK,
> -	.clksel		= div16_dpll4_clksel,
> +	.clksel_mask_3630 = OMAP3630_CLKSEL_TV_MASK,
> +	.clksel		= div32_dpll4_clksel,
>  	.clkdm_name	= "dpll4_clkdm",
>  	.recalc		= &omap2_clksel_recalc,
>  };
> @@ -754,7 +796,8 @@ static struct clk dpll4_m4_ck = {
>  	.init		= &omap2_init_clksel_parent,
>  	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
>  	.clksel_mask	= OMAP3430_CLKSEL_DSS1_MASK,
> -	.clksel		= div16_dpll4_clksel,
> +	.clksel_mask_3630 = OMAP3630_CLKSEL_DSS1_MASK,
> +	.clksel		= div32_dpll4_clksel,
>  	.clkdm_name	= "dpll4_clkdm",
>  	.recalc		= &omap2_clksel_recalc,
>  	.set_rate	= &omap2_clksel_set_rate,
> @@ -781,7 +824,8 @@ static struct clk dpll4_m5_ck = {
>  	.init		= &omap2_init_clksel_parent,
>  	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
>  	.clksel_mask	= OMAP3430_CLKSEL_CAM_MASK,
> -	.clksel		= div16_dpll4_clksel,
> +	.clksel_mask_3630 = OMAP3630_CLKSEL_CAM_MASK,
> +	.clksel		= div32_dpll4_clksel,
>  	.clkdm_name	= "dpll4_clkdm",
>  	.recalc		= &omap2_clksel_recalc,
>  };
> @@ -806,7 +850,8 @@ static struct clk dpll4_m6_ck = {
>  	.init		= &omap2_init_clksel_parent,
>  	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
>  	.clksel_mask	= OMAP3430_DIV_DPLL4_MASK,
> -	.clksel		= div16_dpll4_clksel,
> +	.clksel_mask_3630 = OMAP3630_DIV_DPLL4_MASK,
> +	.clksel		= div32_dpll4_clksel,
>  	.clkdm_name	= "dpll4_clkdm",
>  	.recalc		= &omap2_clksel_recalc,
>  };
> diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h 
> b/arch/arm/mach-omap2/cm-regbits-34xx.h
> index 6f2802b..a6383f9 100644
> --- a/arch/arm/mach-omap2/cm-regbits-34xx.h
> +++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
> @@ -516,7 +516,8 @@
>  
>  /* CM_CLKSEL2_PLL */
>  #define OMAP3430_PERIPH_DPLL_MULT_SHIFT			8
> -#define OMAP3430_PERIPH_DPLL_MULT_MASK			
> (0xfff << 8)
> +#define OMAP3430_PERIPH_DPLL_MULT_MASK			
> (0x7ff << 8)
> +#define OMAP3630_PERIPH_DPLL_MULT_MASK			
> (0xfff << 8)
>  #define OMAP3430_PERIPH_DPLL_DIV_SHIFT			0
>  #define OMAP3430_PERIPH_DPLL_DIV_MASK			
> (0x7f << 0)
>  #define OMAP3630_PERIPH_DPLL_DCO_SEL_SHIFT		21
> @@ -573,8 +574,10 @@
>  /* CM_CLKSEL_DSS */
>  #define OMAP3430_CLKSEL_TV_SHIFT			8
>  #define OMAP3430_CLKSEL_TV_MASK				
> (0x1f << 8)
> +#define OMAP3630_CLKSEL_TV_MASK				
> (0x3f << 8)
>  #define OMAP3430_CLKSEL_DSS1_SHIFT			0
>  #define OMAP3430_CLKSEL_DSS1_MASK			(0x1f << 0)
> +#define OMAP3630_CLKSEL_DSS1_MASK			(0x3f << 0)
>  
>  /* CM_SLEEPDEP_DSS specific bits */
>  
> @@ -602,6 +605,7 @@
>  /* CM_CLKSEL_CAM */
>  #define OMAP3430_CLKSEL_CAM_SHIFT			0
>  #define OMAP3430_CLKSEL_CAM_MASK			(0x1f << 0)
> +#define OMAP3630_CLKSEL_CAM_MASK			(0x3f << 0)
>  
>  /* CM_SLEEPDEP_CAM specific bits */
>  
> @@ -697,6 +701,7 @@
>  /* CM_CLKSEL1_EMU */
>  #define OMAP3430_DIV_DPLL4_SHIFT			24
>  #define OMAP3430_DIV_DPLL4_MASK				
> (0x1f << 24)
> +#define OMAP3630_DIV_DPLL4_MASK				
> (0x3f << 24)
>  #define OMAP3430_DIV_DPLL3_SHIFT			16
>  #define OMAP3430_DIV_DPLL3_MASK				
> (0x1f << 16)
>  #define OMAP3430_CLKSEL_TRACECLK_SHIFT			11
> diff --git a/arch/arm/plat-omap/include/plat/clock.h 
> b/arch/arm/plat-omap/include/plat/clock.h
> index 359ccb4..0e0a5cc 100644
> --- a/arch/arm/plat-omap/include/plat/clock.h
> +++ b/arch/arm/plat-omap/include/plat/clock.h
> @@ -93,7 +93,7 @@ struct clk {
>  		defined(CONFIG_ARCH_OMAP4)
>  	u8			fixed_div;
>  	void __iomem		*clksel_reg;
> -	u32			clksel_mask;
> +	u32			clksel_mask, clksel_mask_3630;
>  	const struct clksel	*clksel;
>  	struct dpll_data	*dpll_data;
>  	const char		*clkdm_name;
> @@ -159,7 +159,7 @@ extern const struct clkops clkops_null;
>  #define RATE_IN_243X		(1 << 2)
>  #define RATE_IN_3XXX		(1 << 3)	/* rates common 
> to all 343X */
>  #define RATE_IN_3430ES2		(1 << 4)	/* 
> 3430ES2 rates only */
> -
> +#define RATE_IN_363X		(1 << 5)        /* rates common 
> to all 343X */

Bad comment? Please revisit.

Regards,
Sergio

>  #define RATE_IN_24XX		(RATE_IN_242X | RATE_IN_243X)
>  
>  
> -- 
> 1.5.6.3
> 
> --
> To unsubscribe from this list: send the line "unsubscribe 
> linux-omap" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 
> 

^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [PATCHV2 3/4] OMAP3: Correct width for CLKSEL Fields
  2009-11-20 15:28     ` [PATCHV2 3/4] OMAP3: Correct width for CLKSEL Fields Vishwanath BS
  2009-11-20 15:28       ` [PATCHV2 4/4] OMAP3: add support for 192Mhz sgx clock Vishwanath BS
  2009-11-20 15:57       ` [PATCHV2 3/4] OMAP3: Correct width for CLKSEL Fields Aguirre, Sergio
@ 2009-11-20 16:00       ` Nishanth Menon
  2009-11-23  9:12         ` Sripathy, Vishwanath
  2 siblings, 1 reply; 12+ messages in thread
From: Nishanth Menon @ 2009-11-20 16:00 UTC (permalink / raw)
  To: Sripathy, Vishwanath; +Cc: linux-omap@vger.kernel.org

Hi Vishwa,
Thanks for the patch, few comments follow:
Sripathy, Vishwanath had written, on 11/20/2009 09:28 AM, the following:
> DPLL4 M, M3, M4, M5 and M6 field width has been increased by 1 bit in
> 3630.This patch has changes to accommodate this in CM dynamically based on
> chip version.
> 
> Signed-off-by: Vishwanath BS <vishwanath.bs@ti.com>
> ---
>  arch/arm/mach-omap2/clock34xx.c         |   18 ++++++++--
>  arch/arm/mach-omap2/clock34xx.h         |   53 ++++++++++++++++++++++++++++--
>  arch/arm/mach-omap2/cm-regbits-34xx.h   |    7 +++-
>  arch/arm/plat-omap/include/plat/clock.h |    4 +-
>  4 files changed, 71 insertions(+), 11 deletions(-)
>  mode change 100644 => 100755 arch/arm/mach-omap2/clock34xx.c
> 
> diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
> index 167f075..1e35f9a
> --- a/arch/arm/mach-omap2/clock34xx.c
> +++ b/arch/arm/mach-omap2/clock34xx.c
> @@ -43,6 +43,7 @@
>  #include "prm-regbits-34xx.h"
>  #include "cm.h"
>  #include "cm-regbits-34xx.h"
> +#include <plat/cpu.h>
>  
>  static const struct clkops clkops_noncore_dpll_ops;
>  
> @@ -97,6 +98,7 @@ struct omap_clk {
>  #define CK_3XXX		(1 << 0)
>  #define CK_3430ES1	(1 << 1)
>  #define CK_3430ES2	(1 << 2)
> +#define CK_363X		(1 << 3)

The patch subject/commit msg and actual action here seem to differ 
unfortunately ->  you are in reality introducing the CK_36XX deltas 
here, you may want to fix the commit message OR split this patch into two:
a) introduce 36XX clocks - You may want to consider these in multiple 
patches each introducing one specific change -> clock wise perhaps.
b) introduce the DPLL4 Mx changes
this will allow:
1. Later traceability when we do a git bisect to know a specific change 
if we are tracking a bug at a later date.
2. easier review for us as each would be one smaller chunk topic to review

>  
>  static struct omap_clk omap34xx_clks[] = {
>  	CLK(NULL,	"omap_32k_fck",	&omap_32k_fck,	CK_3XXX),
> @@ -134,13 +136,13 @@ static struct omap_clk omap34xx_clks[] = {
>  	CLK(NULL,	"omap_12m_fck",	&omap_12m_fck,	CK_3XXX),
>  	CLK(NULL,	"dpll4_m2_ck",	&dpll4_m2_ck,	CK_3XXX),
>  	CLK(NULL,	"dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_3XXX),
> -	CLK(NULL,	"dpll4_m3_ck",	&dpll4_m3_ck,	CK_3XXX),
> +	CLK(NULL,	"dpll4_m3_ck",	&dpll4_m3_ck,	CK_3XXX | CK_363X),

>  	CLK(NULL,	"dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_3XXX),
> -	CLK(NULL,	"dpll4_m4_ck",	&dpll4_m4_ck,	CK_3XXX),
> +	CLK(NULL,	"dpll4_m4_ck",	&dpll4_m4_ck,	CK_3XXX | CK_363X),
>  	CLK(NULL,	"dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_3XXX),
> -	CLK(NULL,	"dpll4_m5_ck",	&dpll4_m5_ck,	CK_3XXX),
> +	CLK(NULL,	"dpll4_m5_ck",	&dpll4_m5_ck,	CK_3XXX | CK_363X),
>  	CLK(NULL,	"dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_3XXX),
> -	CLK(NULL,	"dpll4_m6_ck",	&dpll4_m6_ck,	CK_3XXX),
> +	CLK(NULL,	"dpll4_m6_ck",	&dpll4_m6_ck,	CK_3XXX | CK_363X),
>  	CLK(NULL,	"dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX),
>  	CLK(NULL,	"emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX),
>  	CLK(NULL,	"dpll5_ck",	&dpll5_ck,	CK_3430ES2),
> @@ -1222,6 +1224,8 @@ int __init omap2_clk_init(void)
>  				OMAP3630_PERIPH_DPLL_DCO_SEL_MASK;
>  			dpll4_ck.dpll_data->sd_div_mask =
>  				OMAP3630_PERIPH_DPLL_SD_DIV_MASK;
> +			dpll4_dd.mult_mask = OMAP3630_PERIPH_DPLL_MULT_MASK;
> +			cpu_mask |= RATE_IN_363X;
these two things probably are different actions..

>  			}
>  	}
>  
> @@ -1232,6 +1236,12 @@ int __init omap2_clk_init(void)
>  
>  	for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++)
>  		if (c->cpu & cpu_clkflg) {
> +			/* for 3630, change the mask value for clocks which are
> +				marked as CK_363X*/
> +			if (cpu_is_omap3630() && (c->cpu & CK_363X)) {
> +				c->lk.clk->clksel_mask =
> +						c->lk.clk->clksel_mask_3630;
> +			}
>  			clkdev_add(&c->lk);
>  			clk_register(c->lk.clk);
>  			omap2_init_clk_clkdm(c->lk.clk);
> diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
> index 813a83e..93c92e5 100644
> --- a/arch/arm/mach-omap2/clock34xx.h
> +++ b/arch/arm/mach-omap2/clock34xx.h
> @@ -243,6 +243,42 @@ static const struct clksel_rate div16_dpll_rates[] = {
>  	{ .div = 0 }
>  };
>  
> +static const struct clksel_rate div32_dpll_rates[] = {
> +	{ .div = 1, .val = 1, .flags = RATE_IN_3XXX | DEFAULT_RATE },
> +	{ .div = 2, .val = 2, .flags = RATE_IN_3XXX },
> +	{ .div = 3, .val = 3, .flags = RATE_IN_3XXX },
> +	{ .div = 4, .val = 4, .flags = RATE_IN_3XXX },
> +	{ .div = 5, .val = 5, .flags = RATE_IN_3XXX },
> +	{ .div = 6, .val = 6, .flags = RATE_IN_3XXX },
> +	{ .div = 7, .val = 7, .flags = RATE_IN_3XXX },
> +	{ .div = 8, .val = 8, .flags = RATE_IN_3XXX },
> +	{ .div = 9, .val = 9, .flags = RATE_IN_3XXX },
> +	{ .div = 10, .val = 10, .flags = RATE_IN_3XXX },
> +	{ .div = 11, .val = 11, .flags = RATE_IN_3XXX },
> +	{ .div = 12, .val = 12, .flags = RATE_IN_3XXX },
> +	{ .div = 13, .val = 13, .flags = RATE_IN_3XXX },
> +	{ .div = 14, .val = 14, .flags = RATE_IN_3XXX },
> +	{ .div = 15, .val = 15, .flags = RATE_IN_3XXX },
> +	{ .div = 16, .val = 16, .flags = RATE_IN_3XXX },
> +	{ .div = 17, .val = 17, .flags = RATE_IN_363X },
> +	{ .div = 18, .val = 18, .flags = RATE_IN_363X },
> +	{ .div = 19, .val = 19, .flags = RATE_IN_363X },
> +	{ .div = 20, .val = 20, .flags = RATE_IN_363X },
> +	{ .div = 21, .val = 21, .flags = RATE_IN_363X },
> +	{ .div = 22, .val = 22, .flags = RATE_IN_363X },
> +	{ .div = 23, .val = 23, .flags = RATE_IN_363X },
> +	{ .div = 24, .val = 24, .flags = RATE_IN_363X },
> +	{ .div = 25, .val = 25, .flags = RATE_IN_363X },
> +	{ .div = 26, .val = 26, .flags = RATE_IN_363X },
> +	{ .div = 27, .val = 27, .flags = RATE_IN_363X },
> +	{ .div = 28, .val = 28, .flags = RATE_IN_363X },
> +	{ .div = 29, .val = 29, .flags = RATE_IN_363X },
> +	{ .div = 30, .val = 30, .flags = RATE_IN_363X },
> +	{ .div = 31, .val = 31, .flags = RATE_IN_363X },
> +	{ .div = 32, .val = 32, .flags = RATE_IN_363X },
> +	{ .div = 0 }
> +};
> +

I this this change deserves it's own patch.. as it introduces something 
for 34xx and 36xx in one shot - which I think was the intention of your 
original patch.

>  /* DPLL1 */
>  /* MPU clock source */
>  /* Type: DPLL */
> @@ -588,6 +624,11 @@ static const struct clksel div16_dpll4_clksel[] = {
>  	{ .parent = NULL }
>  };
>  
> +static const struct clksel div32_dpll4_clksel[] = {
> +	{ .parent = &dpll4_ck, .rates = div32_dpll_rates },
> +	{ .parent = NULL }
> +};
> +
>  /* This virtual clock is the source for dpll4_m2x2_ck */
>  static struct clk dpll4_m2_ck = {
>  	.name		= "dpll4_m2_ck",
> @@ -668,7 +709,8 @@ static struct clk dpll4_m3_ck = {
>  	.init		= &omap2_init_clksel_parent,
>  	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
>  	.clksel_mask	= OMAP3430_CLKSEL_TV_MASK,
> -	.clksel		= div16_dpll4_clksel,
> +	.clksel_mask_3630 = OMAP3630_CLKSEL_TV_MASK,
> +	.clksel		= div32_dpll4_clksel,
>  	.clkdm_name	= "dpll4_clkdm",
>  	.recalc		= &omap2_clksel_recalc,
>  };
> @@ -754,7 +796,8 @@ static struct clk dpll4_m4_ck = {
>  	.init		= &omap2_init_clksel_parent,
>  	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
>  	.clksel_mask	= OMAP3430_CLKSEL_DSS1_MASK,
> -	.clksel		= div16_dpll4_clksel,
> +	.clksel_mask_3630 = OMAP3630_CLKSEL_DSS1_MASK,
> +	.clksel		= div32_dpll4_clksel,
>  	.clkdm_name	= "dpll4_clkdm",
>  	.recalc		= &omap2_clksel_recalc,
>  	.set_rate	= &omap2_clksel_set_rate,
> @@ -781,7 +824,8 @@ static struct clk dpll4_m5_ck = {
>  	.init		= &omap2_init_clksel_parent,
>  	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
>  	.clksel_mask	= OMAP3430_CLKSEL_CAM_MASK,
> -	.clksel		= div16_dpll4_clksel,
> +	.clksel_mask_3630 = OMAP3630_CLKSEL_CAM_MASK,
> +	.clksel		= div32_dpll4_clksel,
>  	.clkdm_name	= "dpll4_clkdm",
>  	.recalc		= &omap2_clksel_recalc,
>  };
> @@ -806,7 +850,8 @@ static struct clk dpll4_m6_ck = {
>  	.init		= &omap2_init_clksel_parent,
>  	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
>  	.clksel_mask	= OMAP3430_DIV_DPLL4_MASK,
> -	.clksel		= div16_dpll4_clksel,
> +	.clksel_mask_3630 = OMAP3630_DIV_DPLL4_MASK,
> +	.clksel		= div32_dpll4_clksel,
>  	.clkdm_name	= "dpll4_clkdm",
>  	.recalc		= &omap2_clksel_recalc,
>  };
> diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h
> index 6f2802b..a6383f9 100644
> --- a/arch/arm/mach-omap2/cm-regbits-34xx.h
> +++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
> @@ -516,7 +516,8 @@
>  
>  /* CM_CLKSEL2_PLL */
>  #define OMAP3430_PERIPH_DPLL_MULT_SHIFT			8
> -#define OMAP3430_PERIPH_DPLL_MULT_MASK			(0xfff << 8)
> +#define OMAP3430_PERIPH_DPLL_MULT_MASK			(0x7ff << 8)
> +#define OMAP3630_PERIPH_DPLL_MULT_MASK			(0xfff << 8)
>  #define OMAP3430_PERIPH_DPLL_DIV_SHIFT			0
>  #define OMAP3430_PERIPH_DPLL_DIV_MASK			(0x7f << 0)
>  #define OMAP3630_PERIPH_DPLL_DCO_SEL_SHIFT		21
> @@ -573,8 +574,10 @@
>  /* CM_CLKSEL_DSS */
>  #define OMAP3430_CLKSEL_TV_SHIFT			8
>  #define OMAP3430_CLKSEL_TV_MASK				(0x1f << 8)
> +#define OMAP3630_CLKSEL_TV_MASK				(0x3f << 8)
>  #define OMAP3430_CLKSEL_DSS1_SHIFT			0
>  #define OMAP3430_CLKSEL_DSS1_MASK			(0x1f << 0)
> +#define OMAP3630_CLKSEL_DSS1_MASK			(0x3f << 0)
>  
>  /* CM_SLEEPDEP_DSS specific bits */
>  
> @@ -602,6 +605,7 @@
>  /* CM_CLKSEL_CAM */
>  #define OMAP3430_CLKSEL_CAM_SHIFT			0
>  #define OMAP3430_CLKSEL_CAM_MASK			(0x1f << 0)
> +#define OMAP3630_CLKSEL_CAM_MASK			(0x3f << 0)
>  
>  /* CM_SLEEPDEP_CAM specific bits */
>  
> @@ -697,6 +701,7 @@
>  /* CM_CLKSEL1_EMU */
>  #define OMAP3430_DIV_DPLL4_SHIFT			24
>  #define OMAP3430_DIV_DPLL4_MASK				(0x1f << 24)
> +#define OMAP3630_DIV_DPLL4_MASK				(0x3f << 24)
>  #define OMAP3430_DIV_DPLL3_SHIFT			16
>  #define OMAP3430_DIV_DPLL3_MASK				(0x1f << 16)
>  #define OMAP3430_CLKSEL_TRACECLK_SHIFT			11
> diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
> index 359ccb4..0e0a5cc 100644
> --- a/arch/arm/plat-omap/include/plat/clock.h
> +++ b/arch/arm/plat-omap/include/plat/clock.h
> @@ -93,7 +93,7 @@ struct clk {
>  		defined(CONFIG_ARCH_OMAP4)
>  	u8			fixed_div;
>  	void __iomem		*clksel_reg;
> -	u32			clksel_mask;
> +	u32			clksel_mask, clksel_mask_3630;

why cant we use clksel_mask instead of introducing mask_3630? from my 
reading, you have specific dividers marked with 3XX and 36XX masks anyways..

>  	const struct clksel	*clksel;
>  	struct dpll_data	*dpll_data;
>  	const char		*clkdm_name;
> @@ -159,7 +159,7 @@ extern const struct clkops clkops_null;
>  #define RATE_IN_243X		(1 << 2)
>  #define RATE_IN_3XXX		(1 << 3)	/* rates common to all 343X */
>  #define RATE_IN_3430ES2		(1 << 4)	/* 3430ES2 rates only */
> -
> +#define RATE_IN_363X		(1 << 5)        /* rates common to all 343X */
>  #define RATE_IN_24XX		(RATE_IN_242X | RATE_IN_243X)
>  
>  


-- 
Regards,
Nishanth Menon

^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [PATCHV2 4/4] OMAP3: add support for 192Mhz sgx clock
  2009-11-20 15:28       ` [PATCHV2 4/4] OMAP3: add support for 192Mhz sgx clock Vishwanath BS
@ 2009-11-20 16:19         ` Nishanth Menon
  2009-11-23  9:30           ` Sripathy, Vishwanath
  0 siblings, 1 reply; 12+ messages in thread
From: Nishanth Menon @ 2009-11-20 16:19 UTC (permalink / raw)
  To: Sripathy, Vishwanath; +Cc: linux-omap@vger.kernel.org

unrelated to this patch comment: we might want to consider thinking in 
terms of optimizing the memory as OMAP4 also kicks in.. some sort of 
dynamic clock tree traversal and __initdata method perhaps??

Hi Vishwa,
Thanks for the patch, few minor comments follow:

Sripathy, Vishwanath had written, on 11/20/2009 09:28 AM, the following:
> SGX can run at 192MHz on 3630 and this patch has changes to support this
> feature. Basically DPLL4 M2 will be 192Mhz which will be used as SGX
> Clock. 192Mhz clock is divided by 2 (using CM_CLKSEL_CORE) to generate
> 96Mh clock
   ^^^^ <- you probably intended 96Mhz
> 
> Signed-off-by: Vishwanath BS <Vishwanath.bs@ti.com>
> ---
>  arch/arm/mach-omap2/clock34xx.c       |   16 +++++++++++++++-
>  arch/arm/mach-omap2/clock34xx.h       |   33 +++++++++++++++++++++++++++++++++
>  arch/arm/mach-omap2/cm-regbits-34xx.h |    2 ++
>  arch/arm/mach-omap2/id.c              |    7 +++++--
>  arch/arm/plat-omap/include/plat/cpu.h |    3 +++
>  5 files changed, 58 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
> index 1e35f9a..bce7e46 100755
> --- a/arch/arm/mach-omap2/clock34xx.c
> +++ b/arch/arm/mach-omap2/clock34xx.c
> @@ -128,6 +128,7 @@ static struct omap_clk omap34xx_clks[] = {
>  	CLK(NULL,	"emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX),
>  	CLK(NULL,	"dpll4_ck",	&dpll4_ck,	CK_3XXX),
>  	CLK(NULL,	"dpll4_x2_ck",	&dpll4_x2_ck,	CK_3XXX),
> +       CLK(NULL,       "omap_192m_alwon_ck", &omap_192m_alwon_ck, CK_363X),
>  	CLK(NULL,	"omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_3XXX),
>  	CLK(NULL,	"omap_96m_fck",	&omap_96m_fck,	CK_3XXX),
>  	CLK(NULL,	"cm_96m_fck",	&cm_96m_fck,	CK_3XXX),
> @@ -1226,7 +1227,20 @@ int __init omap2_clk_init(void)
>  				OMAP3630_PERIPH_DPLL_SD_DIV_MASK;
>  			dpll4_dd.mult_mask = OMAP3630_PERIPH_DPLL_MULT_MASK;
>  			cpu_mask |= RATE_IN_363X;
> -			}
> +			cpu_clkflg |= CK_363X;

I think introduce CK_36XX should be done seperately.

> +		}
> +
> +		if (omap3_has_192mhz_clk()) {
> +			omap_96m_alwon_fck.parent = &omap_192m_alwon_ck;
> +			omap_96m_alwon_fck.init = &omap2_init_clksel_parent;
> +			omap_96m_alwon_fck.clksel_reg =
> +					OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
> +			omap_96m_alwon_fck.clksel_mask =
> +						OMAP3630_CLKSEL_96M_MASK;
> +			omap_96m_alwon_fck.clksel = omap_96m_alwon_fck_clksel;
> +			omap_96m_alwon_fck.recalc = &omap2_clksel_recalc;
> +		}
> +
>  	}
>  
>  	clk_init(&omap2_clk_functions);
> diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
> index 93c92e5..6fe89df 100644
> --- a/arch/arm/mach-omap2/clock34xx.h
> +++ b/arch/arm/mach-omap2/clock34xx.h
> @@ -654,12 +654,31 @@ static struct clk dpll4_m2x2_ck = {
>  	.recalc		= &omap3_clkoutx2_recalc,
>  };
>  
> +/* Adding 192MHz Clock node needed by SGX */
> +static struct clk omap_192m_alwon_ck = {
> +	.name           = "omap_192m_alwon_ck",
> +	.ops            = &clkops_null,
> +	.parent         = &dpll4_m2x2_ck,
> +	.recalc         = &followparent_recalc,
> +};
> +
>  /*
>   * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
>   * PRM_96M_ALWON_(F)CLK.  Two clocks then emerge from the PRM:
>   * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
>   * CM_96K_(F)CLK.
>   */
> +static const struct clksel_rate omap_96m_alwon_fck_rates[] = {
> +	{ .div = 1, .val = 1, .flags = RATE_IN_363X },
> +	{ .div = 2, .val = 2, .flags = RATE_IN_363X | DEFAULT_RATE },
> +	{ .div = 0 }
> +};
> +
> +static const struct clksel omap_96m_alwon_fck_clksel[] = {
> +	{ .parent = &omap_192m_alwon_ck, .rates = omap_96m_alwon_fck_rates },
> +	{ .parent = NULL }
> +};
> +
>  static struct clk omap_96m_alwon_fck = {
>  	.name		= "omap_96m_alwon_fck",
>  	.ops		= &clkops_null,
> @@ -1223,6 +1242,18 @@ static const struct clksel_rate sgx_core_rates[] = {
>  	{ .div = 3, .val = 0, .flags = RATE_IN_3XXX | DEFAULT_RATE },
>  	{ .div = 4, .val = 1, .flags = RATE_IN_3XXX },
>  	{ .div = 6, .val = 2, .flags = RATE_IN_3XXX },
> +	{ .div = 2, .val = 5, .flags = RATE_IN_363X },
dont we have more options here? thinking: does this mean that all 3XXX 
and 36XX defines are valid ones for SGX?

> +	{ .div = 0 },
> +};
> +
> +static const struct clksel_rate sgx_192m_rates[] = {
> +	{ .div = 1,  .val = 4, .flags = RATE_IN_363X | DEFAULT_RATE },
> +	{ .div = 0 },
> +};
> +
> +static const struct clksel_rate sgx_corex2_rates[] = {
> +	{ .div = 3, .val = 6, .flags = RATE_IN_363X | DEFAULT_RATE },
> +	{ .div = 5, .val = 7, .flags = RATE_IN_363X },
>  	{ .div = 0 },
>  };
>  
> @@ -1234,6 +1265,8 @@ static const struct clksel_rate sgx_96m_rates[] = {
>  static const struct clksel sgx_clksel[] = {
>  	{ .parent = &core_ck,	 .rates = sgx_core_rates },
>  	{ .parent = &cm_96m_fck, .rates = sgx_96m_rates },
> +	{ .parent = &omap_192m_alwon_ck, .rates = sgx_192m_rates },
> +	{ .parent = &corex2_fck, .rates = sgx_corex2_rates },
>  	{ .parent = NULL },
>  };
>  
> diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h
> index a6383f9..39b3399 100644
> --- a/arch/arm/mach-omap2/cm-regbits-34xx.h
> +++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
> @@ -336,6 +336,8 @@
>  #define OMAP3430_CLKSEL_L4_MASK				(0x3 << 2)
>  #define OMAP3430_CLKSEL_L3_SHIFT			0
>  #define OMAP3430_CLKSEL_L3_MASK				(0x3 << 0)
> +#define OMAP3630_CLKSEL_96M_SHIFT                      12
> +#define OMAP3630_CLKSEL_96M_MASK                       (0x3 << 12)
>  
>  /* CM_CLKSTCTRL_CORE */
>  #define OMAP3430ES1_CLKTRCTRL_D2D_SHIFT			4
> diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
> index 3c1194c..b1bc79d 100644
> --- a/arch/arm/mach-omap2/id.c
> +++ b/arch/arm/mach-omap2/id.c
> @@ -176,8 +176,10 @@ void __init omap3_check_features(void)
>  	OMAP3_CHECK_FEATURE(status, NEON);
>  	OMAP3_CHECK_FEATURE(status, ISP);
>  
> -	if (cpu_is_omap3630())
> -		omap3_features |= OMAP3_HAS_JTYPE_DPLL4;
> +	if (cpu_is_omap3630()) {
> +		omap3_features |= OMAP3_HAS_JTYPE_DPLL4 |
> +							OMAP3_HAS_192MHZ_CLK;
might be better to do this as a next entry -> you may want other chips 
having 192Mhz to also use it..

Please Ref: http://patchwork.kernel.org/patch/61671/ to see how it is 
done clean.

> +	}
>  	/*
>  	 * TODO: Get additional info (where applicable)
>  	 *       e.g. Size of L2 cache.
> @@ -319,6 +321,7 @@ void __init omap3_cpuinfo(void)
>  	OMAP3_SHOW_FEATURE(neon);
>  	OMAP3_SHOW_FEATURE(isp);
>  	OMAP3_SHOW_FEATURE(jtype_dpll4);
> +	OMAP3_SHOW_FEATURE(192mhz_clk);
>  	printk(")\n");
>  }
>  
> diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
> index 65c08d5..1dffe25 100644
> --- a/arch/arm/plat-omap/include/plat/cpu.h
> +++ b/arch/arm/plat-omap/include/plat/cpu.h
> @@ -498,6 +498,7 @@ extern u32 omap3_features;
>  #define OMAP3_HAS_NEON			BIT(3)
>  #define OMAP3_HAS_ISP			BIT(4)
>  #define OMAP3_HAS_JTYPE_DPLL4		BIT(5)
> +#define OMAP3_HAS_192MHZ_CLK		BIT(6)
>  
>  #define OMAP3_HAS_FEATURE(feat,flag)			\
>  static inline unsigned int omap3_has_ ##feat(void)	\
> @@ -511,4 +512,6 @@ OMAP3_HAS_FEATURE(iva, IVA)
>  OMAP3_HAS_FEATURE(neon, NEON)
>  OMAP3_HAS_FEATURE(isp, ISP)
>  OMAP3_HAS_FEATURE(jtype_dpll4, JTYPE_DPLL4)
> +OMAP3_HAS_FEATURE(192mhz_clk, 192MHZ_CLK)
> +
EOL
>  #endif


-- 
Regards,
Nishanth Menon

^ permalink raw reply	[flat|nested] 12+ messages in thread

* RE: [PATCHV2 3/4] OMAP3: Correct width for CLKSEL Fields
  2009-11-20 15:57       ` [PATCHV2 3/4] OMAP3: Correct width for CLKSEL Fields Aguirre, Sergio
@ 2009-11-23  8:15         ` Sripathy, Vishwanath
  0 siblings, 0 replies; 12+ messages in thread
From: Sripathy, Vishwanath @ 2009-11-23  8:15 UTC (permalink / raw)
  To: Aguirre, Sergio, linux-omap@vger.kernel.org

Sergio,

> -----Original Message-----
> From: Aguirre, Sergio
> Sent: Friday, November 20, 2009 9:28 PM
> To: Sripathy, Vishwanath; linux-omap@vger.kernel.org
> Subject: RE: [PATCHV2 3/4] OMAP3: Correct width for CLKSEL Fields
> 
> Vishwa,
> 
> > -----Original Message-----
> > From: linux-omap-owner@vger.kernel.org
> > [mailto:linux-omap-owner@vger.kernel.org] On Behalf Of
> > Sripathy, Vishwanath
> > Sent: Friday, November 20, 2009 9:29 AM
> > To: linux-omap@vger.kernel.org; Sripathy, Vishwanath
> > Subject: [PATCHV2 3/4] OMAP3: Correct width for CLKSEL Fields
> >
> > DPLL4 M, M3, M4, M5 and M6 field width has been increased by 1 bit in
> > 3630.This patch has changes to accommodate this in CM
> > dynamically based on
> > chip version.
> >
> > Signed-off-by: Vishwanath BS <vishwanath.bs@ti.com>
> > ---
> >  arch/arm/mach-omap2/clock34xx.c         |   18 ++++++++--
> >  arch/arm/mach-omap2/clock34xx.h         |   53
> > ++++++++++++++++++++++++++++--
> >  arch/arm/mach-omap2/cm-regbits-34xx.h   |    7 +++-
> >  arch/arm/plat-omap/include/plat/clock.h |    4 +-
> >  4 files changed, 71 insertions(+), 11 deletions(-)
> >  mode change 100644 => 100755 arch/arm/mach-omap2/clock34xx.c
> 
> No file mode changes, please.

Ack

> 
> >
> > diff --git a/arch/arm/mach-omap2/clock34xx.c
> > b/arch/arm/mach-omap2/clock34xx.c
> > index 167f075..1e35f9a
> > --- a/arch/arm/mach-omap2/clock34xx.c
> > +++ b/arch/arm/mach-omap2/clock34xx.c
> > @@ -43,6 +43,7 @@
> >  #include "prm-regbits-34xx.h"
> >  #include "cm.h"
> >  #include "cm-regbits-34xx.h"
> > +#include <plat/cpu.h>
> >
> >  static const struct clkops clkops_noncore_dpll_ops;
> >
> > @@ -97,6 +98,7 @@ struct omap_clk {
> >  #define CK_3XXX		(1 << 0)
> >  #define CK_3430ES1	(1 << 1)
> >  #define CK_3430ES2	(1 << 2)
> > +#define CK_363X		(1 << 3)
> >
> >  static struct omap_clk omap34xx_clks[] = {
> >  	CLK(NULL,	"omap_32k_fck",	&omap_32k_fck,	CK_3XXX),
> > @@ -134,13 +136,13 @@ static struct omap_clk omap34xx_clks[] = {
> >  	CLK(NULL,	"omap_12m_fck",	&omap_12m_fck,	CK_3XXX),
> >  	CLK(NULL,	"dpll4_m2_ck",	&dpll4_m2_ck,	CK_3XXX),
> >  	CLK(NULL,	"dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_3XXX),
> > -	CLK(NULL,	"dpll4_m3_ck",	&dpll4_m3_ck,	CK_3XXX),
> > +	CLK(NULL,	"dpll4_m3_ck",	&dpll4_m3_ck,	CK_3XXX
> > | CK_363X),
> 
> Shouldn't CK_363X replace CK_3XXX?
> 
> CK_363X is always inside the CK_3XXX scope, but not the other way around.

Not really. If you see the intention of adding CK_363X, it is to indicate that this particular clock node has some changes specific to 3630 and it needs special handling. So we cannot replace CK_363X with CK_3XXX

> 
> >  	CLK(NULL,	"dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_3XXX),
> > -	CLK(NULL,	"dpll4_m4_ck",	&dpll4_m4_ck,	CK_3XXX),
> > +	CLK(NULL,	"dpll4_m4_ck",	&dpll4_m4_ck,	CK_3XXX
> > | CK_363X),
> >  	CLK(NULL,	"dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_3XXX),
> > -	CLK(NULL,	"dpll4_m5_ck",	&dpll4_m5_ck,	CK_3XXX),
> > +	CLK(NULL,	"dpll4_m5_ck",	&dpll4_m5_ck,	CK_3XXX
> > | CK_363X),
> >  	CLK(NULL,	"dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_3XXX),
> > -	CLK(NULL,	"dpll4_m6_ck",	&dpll4_m6_ck,	CK_3XXX),
> > +	CLK(NULL,	"dpll4_m6_ck",	&dpll4_m6_ck,	CK_3XXX
> > | CK_363X),
> >  	CLK(NULL,	"dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX),
> >  	CLK(NULL,	"emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX),
> >  	CLK(NULL,	"dpll5_ck",	&dpll5_ck,	CK_3430ES2),
> > @@ -1222,6 +1224,8 @@ int __init omap2_clk_init(void)
> >  				OMAP3630_PERIPH_DPLL_DCO_SEL_MASK;
> >  			dpll4_ck.dpll_data->sd_div_mask =
> >  				OMAP3630_PERIPH_DPLL_SD_DIV_MASK;
> > +			dpll4_dd.mult_mask =
> > OMAP3630_PERIPH_DPLL_MULT_MASK;
> > +			cpu_mask |= RATE_IN_363X;
> >  			}
> >  	}
> >
> > @@ -1232,6 +1236,12 @@ int __init omap2_clk_init(void)
> >
> >  	for (c = omap34xx_clks; c < omap34xx_clks +
> > ARRAY_SIZE(omap34xx_clks); c++)
> >  		if (c->cpu & cpu_clkflg) {
> > +			/* for 3630, change the mask value for
> > clocks which are
> > +				marked as CK_363X*/
> > +			if (cpu_is_omap3630() && (c->cpu & CK_363X)) {
> > +				c->lk.clk->clksel_mask =
> > +
> > c->lk.clk->clksel_mask_3630;
> > +			}
> >  			clkdev_add(&c->lk);
> >  			clk_register(c->lk.clk);
> >  			omap2_init_clk_clkdm(c->lk.clk);
> > diff --git a/arch/arm/mach-omap2/clock34xx.h
> > b/arch/arm/mach-omap2/clock34xx.h
> > index 813a83e..93c92e5 100644
> > --- a/arch/arm/mach-omap2/clock34xx.h
> > +++ b/arch/arm/mach-omap2/clock34xx.h
> > @@ -243,6 +243,42 @@ static const struct clksel_rate
> > div16_dpll_rates[] = {
> >  	{ .div = 0 }
> >  };
> >
> > +static const struct clksel_rate div32_dpll_rates[] = {
> > +	{ .div = 1, .val = 1, .flags = RATE_IN_3XXX | DEFAULT_RATE },
> > +	{ .div = 2, .val = 2, .flags = RATE_IN_3XXX },
> > +	{ .div = 3, .val = 3, .flags = RATE_IN_3XXX },
> > +	{ .div = 4, .val = 4, .flags = RATE_IN_3XXX },
> > +	{ .div = 5, .val = 5, .flags = RATE_IN_3XXX },
> > +	{ .div = 6, .val = 6, .flags = RATE_IN_3XXX },
> > +	{ .div = 7, .val = 7, .flags = RATE_IN_3XXX },
> > +	{ .div = 8, .val = 8, .flags = RATE_IN_3XXX },
> > +	{ .div = 9, .val = 9, .flags = RATE_IN_3XXX },
> > +	{ .div = 10, .val = 10, .flags = RATE_IN_3XXX },
> > +	{ .div = 11, .val = 11, .flags = RATE_IN_3XXX },
> > +	{ .div = 12, .val = 12, .flags = RATE_IN_3XXX },
> > +	{ .div = 13, .val = 13, .flags = RATE_IN_3XXX },
> > +	{ .div = 14, .val = 14, .flags = RATE_IN_3XXX },
> > +	{ .div = 15, .val = 15, .flags = RATE_IN_3XXX },
> > +	{ .div = 16, .val = 16, .flags = RATE_IN_3XXX },
> > +	{ .div = 17, .val = 17, .flags = RATE_IN_363X },
> > +	{ .div = 18, .val = 18, .flags = RATE_IN_363X },
> > +	{ .div = 19, .val = 19, .flags = RATE_IN_363X },
> > +	{ .div = 20, .val = 20, .flags = RATE_IN_363X },
> > +	{ .div = 21, .val = 21, .flags = RATE_IN_363X },
> > +	{ .div = 22, .val = 22, .flags = RATE_IN_363X },
> > +	{ .div = 23, .val = 23, .flags = RATE_IN_363X },
> > +	{ .div = 24, .val = 24, .flags = RATE_IN_363X },
> > +	{ .div = 25, .val = 25, .flags = RATE_IN_363X },
> > +	{ .div = 26, .val = 26, .flags = RATE_IN_363X },
> > +	{ .div = 27, .val = 27, .flags = RATE_IN_363X },
> > +	{ .div = 28, .val = 28, .flags = RATE_IN_363X },
> > +	{ .div = 29, .val = 29, .flags = RATE_IN_363X },
> > +	{ .div = 30, .val = 30, .flags = RATE_IN_363X },
> > +	{ .div = 31, .val = 31, .flags = RATE_IN_363X },
> > +	{ .div = 32, .val = 32, .flags = RATE_IN_363X },
> > +	{ .div = 0 }
> > +};
> > +
> >  /* DPLL1 */
> >  /* MPU clock source */
> >  /* Type: DPLL */
> > @@ -588,6 +624,11 @@ static const struct clksel
> > div16_dpll4_clksel[] = {
> >  	{ .parent = NULL }
> >  };
> >
> > +static const struct clksel div32_dpll4_clksel[] = {
> > +	{ .parent = &dpll4_ck, .rates = div32_dpll_rates },
> > +	{ .parent = NULL }
> > +};
> > +
> >  /* This virtual clock is the source for dpll4_m2x2_ck */
> >  static struct clk dpll4_m2_ck = {
> >  	.name		= "dpll4_m2_ck",
> > @@ -668,7 +709,8 @@ static struct clk dpll4_m3_ck = {
> >  	.init		= &omap2_init_clksel_parent,
> >  	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
> >  	.clksel_mask	= OMAP3430_CLKSEL_TV_MASK,
> > -	.clksel		= div16_dpll4_clksel,
> > +	.clksel_mask_3630 = OMAP3630_CLKSEL_TV_MASK,
> > +	.clksel		= div32_dpll4_clksel,
> >  	.clkdm_name	= "dpll4_clkdm",
> >  	.recalc		= &omap2_clksel_recalc,
> >  };
> > @@ -754,7 +796,8 @@ static struct clk dpll4_m4_ck = {
> >  	.init		= &omap2_init_clksel_parent,
> >  	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
> >  	.clksel_mask	= OMAP3430_CLKSEL_DSS1_MASK,
> > -	.clksel		= div16_dpll4_clksel,
> > +	.clksel_mask_3630 = OMAP3630_CLKSEL_DSS1_MASK,
> > +	.clksel		= div32_dpll4_clksel,
> >  	.clkdm_name	= "dpll4_clkdm",
> >  	.recalc		= &omap2_clksel_recalc,
> >  	.set_rate	= &omap2_clksel_set_rate,
> > @@ -781,7 +824,8 @@ static struct clk dpll4_m5_ck = {
> >  	.init		= &omap2_init_clksel_parent,
> >  	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
> >  	.clksel_mask	= OMAP3430_CLKSEL_CAM_MASK,
> > -	.clksel		= div16_dpll4_clksel,
> > +	.clksel_mask_3630 = OMAP3630_CLKSEL_CAM_MASK,
> > +	.clksel		= div32_dpll4_clksel,
> >  	.clkdm_name	= "dpll4_clkdm",
> >  	.recalc		= &omap2_clksel_recalc,
> >  };
> > @@ -806,7 +850,8 @@ static struct clk dpll4_m6_ck = {
> >  	.init		= &omap2_init_clksel_parent,
> >  	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
> >  	.clksel_mask	= OMAP3430_DIV_DPLL4_MASK,
> > -	.clksel		= div16_dpll4_clksel,
> > +	.clksel_mask_3630 = OMAP3630_DIV_DPLL4_MASK,
> > +	.clksel		= div32_dpll4_clksel,
> >  	.clkdm_name	= "dpll4_clkdm",
> >  	.recalc		= &omap2_clksel_recalc,
> >  };
> > diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h
> > b/arch/arm/mach-omap2/cm-regbits-34xx.h
> > index 6f2802b..a6383f9 100644
> > --- a/arch/arm/mach-omap2/cm-regbits-34xx.h
> > +++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
> > @@ -516,7 +516,8 @@
> >
> >  /* CM_CLKSEL2_PLL */
> >  #define OMAP3430_PERIPH_DPLL_MULT_SHIFT			8
> > -#define OMAP3430_PERIPH_DPLL_MULT_MASK
> > (0xfff << 8)
> > +#define OMAP3430_PERIPH_DPLL_MULT_MASK
> > (0x7ff << 8)
> > +#define OMAP3630_PERIPH_DPLL_MULT_MASK
> > (0xfff << 8)
> >  #define OMAP3430_PERIPH_DPLL_DIV_SHIFT			0
> >  #define OMAP3430_PERIPH_DPLL_DIV_MASK
> > (0x7f << 0)
> >  #define OMAP3630_PERIPH_DPLL_DCO_SEL_SHIFT		21
> > @@ -573,8 +574,10 @@
> >  /* CM_CLKSEL_DSS */
> >  #define OMAP3430_CLKSEL_TV_SHIFT			8
> >  #define OMAP3430_CLKSEL_TV_MASK
> > (0x1f << 8)
> > +#define OMAP3630_CLKSEL_TV_MASK
> > (0x3f << 8)
> >  #define OMAP3430_CLKSEL_DSS1_SHIFT			0
> >  #define OMAP3430_CLKSEL_DSS1_MASK			(0x1f << 0)
> > +#define OMAP3630_CLKSEL_DSS1_MASK			(0x3f << 0)
> >
> >  /* CM_SLEEPDEP_DSS specific bits */
> >
> > @@ -602,6 +605,7 @@
> >  /* CM_CLKSEL_CAM */
> >  #define OMAP3430_CLKSEL_CAM_SHIFT			0
> >  #define OMAP3430_CLKSEL_CAM_MASK			(0x1f << 0)
> > +#define OMAP3630_CLKSEL_CAM_MASK			(0x3f << 0)
> >
> >  /* CM_SLEEPDEP_CAM specific bits */
> >
> > @@ -697,6 +701,7 @@
> >  /* CM_CLKSEL1_EMU */
> >  #define OMAP3430_DIV_DPLL4_SHIFT			24
> >  #define OMAP3430_DIV_DPLL4_MASK
> > (0x1f << 24)
> > +#define OMAP3630_DIV_DPLL4_MASK
> > (0x3f << 24)
> >  #define OMAP3430_DIV_DPLL3_SHIFT			16
> >  #define OMAP3430_DIV_DPLL3_MASK
> > (0x1f << 16)
> >  #define OMAP3430_CLKSEL_TRACECLK_SHIFT			11
> > diff --git a/arch/arm/plat-omap/include/plat/clock.h
> > b/arch/arm/plat-omap/include/plat/clock.h
> > index 359ccb4..0e0a5cc 100644
> > --- a/arch/arm/plat-omap/include/plat/clock.h
> > +++ b/arch/arm/plat-omap/include/plat/clock.h
> > @@ -93,7 +93,7 @@ struct clk {
> >  		defined(CONFIG_ARCH_OMAP4)
> >  	u8			fixed_div;
> >  	void __iomem		*clksel_reg;
> > -	u32			clksel_mask;
> > +	u32			clksel_mask, clksel_mask_3630;
> >  	const struct clksel	*clksel;
> >  	struct dpll_data	*dpll_data;
> >  	const char		*clkdm_name;
> > @@ -159,7 +159,7 @@ extern const struct clkops clkops_null;
> >  #define RATE_IN_243X		(1 << 2)
> >  #define RATE_IN_3XXX		(1 << 3)	/* rates common
> > to all 343X */
> >  #define RATE_IN_3430ES2		(1 << 4)	/*
> > 3430ES2 rates only */
> > -
> > +#define RATE_IN_363X		(1 << 5)        /* rates common
> > to all 343X */
> 
> Bad comment? Please revisit.
> 
> Regards,
> Sergio
> 
> >  #define RATE_IN_24XX		(RATE_IN_242X | RATE_IN_243X)
> >
> >
> > --
> > 1.5.6.3
> >
> > --
> > To unsubscribe from this list: send the line "unsubscribe
> > linux-omap" in
> > the body of a message to majordomo@vger.kernel.org
> > More majordomo info at  http://vger.kernel.org/majordomo-info.html
> >
> >

^ permalink raw reply	[flat|nested] 12+ messages in thread

* RE: [PATCHV2 3/4] OMAP3: Correct width for CLKSEL Fields
  2009-11-20 16:00       ` Nishanth Menon
@ 2009-11-23  9:12         ` Sripathy, Vishwanath
  0 siblings, 0 replies; 12+ messages in thread
From: Sripathy, Vishwanath @ 2009-11-23  9:12 UTC (permalink / raw)
  To: Menon, Nishanth; +Cc: linux-omap@vger.kernel.org

Nishant

> -----Original Message-----
> From: Menon, Nishanth
> Sent: Friday, November 20, 2009 9:30 PM
> To: Sripathy, Vishwanath
> Cc: linux-omap@vger.kernel.org
> Subject: Re: [PATCHV2 3/4] OMAP3: Correct width for CLKSEL Fields
> 
> Hi Vishwa,
> Thanks for the patch, few comments follow:
> Sripathy, Vishwanath had written, on 11/20/2009 09:28 AM, the following:
> > DPLL4 M, M3, M4, M5 and M6 field width has been increased by 1 bit in
> > 3630.This patch has changes to accommodate this in CM dynamically based on
> > chip version.
> >
> > Signed-off-by: Vishwanath BS <vishwanath.bs@ti.com>
> > ---
> >  arch/arm/mach-omap2/clock34xx.c         |   18 ++++++++--
> >  arch/arm/mach-omap2/clock34xx.h         |   53
> ++++++++++++++++++++++++++++--
> >  arch/arm/mach-omap2/cm-regbits-34xx.h   |    7 +++-
> >  arch/arm/plat-omap/include/plat/clock.h |    4 +-
> >  4 files changed, 71 insertions(+), 11 deletions(-)
> >  mode change 100644 => 100755 arch/arm/mach-omap2/clock34xx.c
> >
> > diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-
> omap2/clock34xx.c
> > index 167f075..1e35f9a
> > --- a/arch/arm/mach-omap2/clock34xx.c
> > +++ b/arch/arm/mach-omap2/clock34xx.c
> > @@ -43,6 +43,7 @@
> >  #include "prm-regbits-34xx.h"
> >  #include "cm.h"
> >  #include "cm-regbits-34xx.h"
> > +#include <plat/cpu.h>
> >
> >  static const struct clkops clkops_noncore_dpll_ops;
> >
> > @@ -97,6 +98,7 @@ struct omap_clk {
> >  #define CK_3XXX		(1 << 0)
> >  #define CK_3430ES1	(1 << 1)
> >  #define CK_3430ES2	(1 << 2)
> > +#define CK_363X		(1 << 3)
> 
> The patch subject/commit msg and actual action here seem to differ
> unfortunately ->  you are in reality introducing the CK_36XX deltas
> here, you may want to fix the commit message OR split this patch into two:
> a) introduce 36XX clocks - You may want to consider these in multiple
> patches each introducing one specific change -> clock wise perhaps.
> b) introduce the DPLL4 Mx changes
> this will allow:
> 1. Later traceability when we do a git bisect to know a specific change
> if we are tracking a bug at a later date.
> 2. easier review for us as each would be one smaller chunk topic to review

Only DPLL4Mx specific changes are added under CK_363X flag. There are no other 3630 Clock changes. May be I can add few more details in Commit message to describe the changes better.

> 
> >
> >  static struct omap_clk omap34xx_clks[] = {
> >  	CLK(NULL,	"omap_32k_fck",	&omap_32k_fck,	CK_3XXX),
> > @@ -134,13 +136,13 @@ static struct omap_clk omap34xx_clks[] = {
> >  	CLK(NULL,	"omap_12m_fck",	&omap_12m_fck,	CK_3XXX),
> >  	CLK(NULL,	"dpll4_m2_ck",	&dpll4_m2_ck,	CK_3XXX),
> >  	CLK(NULL,	"dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_3XXX),
> > -	CLK(NULL,	"dpll4_m3_ck",	&dpll4_m3_ck,	CK_3XXX),
> > +	CLK(NULL,	"dpll4_m3_ck",	&dpll4_m3_ck,	CK_3XXX | CK_363X),
> 
> >  	CLK(NULL,	"dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_3XXX),
> > -	CLK(NULL,	"dpll4_m4_ck",	&dpll4_m4_ck,	CK_3XXX),
> > +	CLK(NULL,	"dpll4_m4_ck",	&dpll4_m4_ck,	CK_3XXX | CK_363X),
> >  	CLK(NULL,	"dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_3XXX),
> > -	CLK(NULL,	"dpll4_m5_ck",	&dpll4_m5_ck,	CK_3XXX),
> > +	CLK(NULL,	"dpll4_m5_ck",	&dpll4_m5_ck,	CK_3XXX | CK_363X),
> >  	CLK(NULL,	"dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_3XXX),
> > -	CLK(NULL,	"dpll4_m6_ck",	&dpll4_m6_ck,	CK_3XXX),
> > +	CLK(NULL,	"dpll4_m6_ck",	&dpll4_m6_ck,	CK_3XXX | CK_363X),
> >  	CLK(NULL,	"dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX),
> >  	CLK(NULL,	"emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX),
> >  	CLK(NULL,	"dpll5_ck",	&dpll5_ck,	CK_3430ES2),
> > @@ -1222,6 +1224,8 @@ int __init omap2_clk_init(void)
> >  				OMAP3630_PERIPH_DPLL_DCO_SEL_MASK;
> >  			dpll4_ck.dpll_data->sd_div_mask =
> >  				OMAP3630_PERIPH_DPLL_SD_DIV_MASK;
> > +			dpll4_dd.mult_mask = OMAP3630_PERIPH_DPLL_MULT_MASK;
> > +			cpu_mask |= RATE_IN_363X;
> these two things probably are different actions..
> 
Not really. It is just to mark that 3630 specific Clock changes (DPLL4Mx) are under flag RATE_IN_363X
> >  			}
> >  	}
> >
> > @@ -1232,6 +1236,12 @@ int __init omap2_clk_init(void)
> >
> >  	for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks);
> c++)
> >  		if (c->cpu & cpu_clkflg) {
> > +			/* for 3630, change the mask value for clocks which are
> > +				marked as CK_363X*/
> > +			if (cpu_is_omap3630() && (c->cpu & CK_363X)) {
> > +				c->lk.clk->clksel_mask =
> > +						c->lk.clk->clksel_mask_3630;
> > +			}
> >  			clkdev_add(&c->lk);
> >  			clk_register(c->lk.clk);
> >  			omap2_init_clk_clkdm(c->lk.clk);
> > diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-
> omap2/clock34xx.h
> > index 813a83e..93c92e5 100644
> > --- a/arch/arm/mach-omap2/clock34xx.h
> > +++ b/arch/arm/mach-omap2/clock34xx.h
> > @@ -243,6 +243,42 @@ static const struct clksel_rate div16_dpll_rates[] = {
> >  	{ .div = 0 }
> >  };
> >
> > +static const struct clksel_rate div32_dpll_rates[] = {
> > +	{ .div = 1, .val = 1, .flags = RATE_IN_3XXX | DEFAULT_RATE },
> > +	{ .div = 2, .val = 2, .flags = RATE_IN_3XXX },
> > +	{ .div = 3, .val = 3, .flags = RATE_IN_3XXX },
> > +	{ .div = 4, .val = 4, .flags = RATE_IN_3XXX },
> > +	{ .div = 5, .val = 5, .flags = RATE_IN_3XXX },
> > +	{ .div = 6, .val = 6, .flags = RATE_IN_3XXX },
> > +	{ .div = 7, .val = 7, .flags = RATE_IN_3XXX },
> > +	{ .div = 8, .val = 8, .flags = RATE_IN_3XXX },
> > +	{ .div = 9, .val = 9, .flags = RATE_IN_3XXX },
> > +	{ .div = 10, .val = 10, .flags = RATE_IN_3XXX },
> > +	{ .div = 11, .val = 11, .flags = RATE_IN_3XXX },
> > +	{ .div = 12, .val = 12, .flags = RATE_IN_3XXX },
> > +	{ .div = 13, .val = 13, .flags = RATE_IN_3XXX },
> > +	{ .div = 14, .val = 14, .flags = RATE_IN_3XXX },
> > +	{ .div = 15, .val = 15, .flags = RATE_IN_3XXX },
> > +	{ .div = 16, .val = 16, .flags = RATE_IN_3XXX },
> > +	{ .div = 17, .val = 17, .flags = RATE_IN_363X },
> > +	{ .div = 18, .val = 18, .flags = RATE_IN_363X },
> > +	{ .div = 19, .val = 19, .flags = RATE_IN_363X },
> > +	{ .div = 20, .val = 20, .flags = RATE_IN_363X },
> > +	{ .div = 21, .val = 21, .flags = RATE_IN_363X },
> > +	{ .div = 22, .val = 22, .flags = RATE_IN_363X },
> > +	{ .div = 23, .val = 23, .flags = RATE_IN_363X },
> > +	{ .div = 24, .val = 24, .flags = RATE_IN_363X },
> > +	{ .div = 25, .val = 25, .flags = RATE_IN_363X },
> > +	{ .div = 26, .val = 26, .flags = RATE_IN_363X },
> > +	{ .div = 27, .val = 27, .flags = RATE_IN_363X },
> > +	{ .div = 28, .val = 28, .flags = RATE_IN_363X },
> > +	{ .div = 29, .val = 29, .flags = RATE_IN_363X },
> > +	{ .div = 30, .val = 30, .flags = RATE_IN_363X },
> > +	{ .div = 31, .val = 31, .flags = RATE_IN_363X },
> > +	{ .div = 32, .val = 32, .flags = RATE_IN_363X },
> > +	{ .div = 0 }
> > +};
> > +
> 
> I this this change deserves it's own patch.. as it introduces something
> for 34xx and 36xx in one shot - which I think was the intention of your
> original patch.

Again this change is required only for DPLL4MX change. For me it does not make much sense to split into a separate patch since it does not add any functionally on it's own without other changes.

> 
> >  /* DPLL1 */
> >  /* MPU clock source */
> >  /* Type: DPLL */
> > @@ -588,6 +624,11 @@ static const struct clksel div16_dpll4_clksel[] = {
> >  	{ .parent = NULL }
> >  };
> >
> > +static const struct clksel div32_dpll4_clksel[] = {
> > +	{ .parent = &dpll4_ck, .rates = div32_dpll_rates },
> > +	{ .parent = NULL }
> > +};
> > +
> >  /* This virtual clock is the source for dpll4_m2x2_ck */
> >  static struct clk dpll4_m2_ck = {
> >  	.name		= "dpll4_m2_ck",
> > @@ -668,7 +709,8 @@ static struct clk dpll4_m3_ck = {
> >  	.init		= &omap2_init_clksel_parent,
> >  	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
> >  	.clksel_mask	= OMAP3430_CLKSEL_TV_MASK,
> > -	.clksel		= div16_dpll4_clksel,
> > +	.clksel_mask_3630 = OMAP3630_CLKSEL_TV_MASK,
> > +	.clksel		= div32_dpll4_clksel,
> >  	.clkdm_name	= "dpll4_clkdm",
> >  	.recalc		= &omap2_clksel_recalc,
> >  };
> > @@ -754,7 +796,8 @@ static struct clk dpll4_m4_ck = {
> >  	.init		= &omap2_init_clksel_parent,
> >  	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
> >  	.clksel_mask	= OMAP3430_CLKSEL_DSS1_MASK,
> > -	.clksel		= div16_dpll4_clksel,
> > +	.clksel_mask_3630 = OMAP3630_CLKSEL_DSS1_MASK,
> > +	.clksel		= div32_dpll4_clksel,
> >  	.clkdm_name	= "dpll4_clkdm",
> >  	.recalc		= &omap2_clksel_recalc,
> >  	.set_rate	= &omap2_clksel_set_rate,
> > @@ -781,7 +824,8 @@ static struct clk dpll4_m5_ck = {
> >  	.init		= &omap2_init_clksel_parent,
> >  	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
> >  	.clksel_mask	= OMAP3430_CLKSEL_CAM_MASK,
> > -	.clksel		= div16_dpll4_clksel,
> > +	.clksel_mask_3630 = OMAP3630_CLKSEL_CAM_MASK,
> > +	.clksel		= div32_dpll4_clksel,
> >  	.clkdm_name	= "dpll4_clkdm",
> >  	.recalc		= &omap2_clksel_recalc,
> >  };
> > @@ -806,7 +850,8 @@ static struct clk dpll4_m6_ck = {
> >  	.init		= &omap2_init_clksel_parent,
> >  	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
> >  	.clksel_mask	= OMAP3430_DIV_DPLL4_MASK,
> > -	.clksel		= div16_dpll4_clksel,
> > +	.clksel_mask_3630 = OMAP3630_DIV_DPLL4_MASK,
> > +	.clksel		= div32_dpll4_clksel,
> >  	.clkdm_name	= "dpll4_clkdm",
> >  	.recalc		= &omap2_clksel_recalc,
> >  };
> > diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-
> regbits-34xx.h
> > index 6f2802b..a6383f9 100644
> > --- a/arch/arm/mach-omap2/cm-regbits-34xx.h
> > +++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
> > @@ -516,7 +516,8 @@
> >
> >  /* CM_CLKSEL2_PLL */
> >  #define OMAP3430_PERIPH_DPLL_MULT_SHIFT			8
> > -#define OMAP3430_PERIPH_DPLL_MULT_MASK			(0xfff << 8)
> > +#define OMAP3430_PERIPH_DPLL_MULT_MASK			(0x7ff << 8)
> > +#define OMAP3630_PERIPH_DPLL_MULT_MASK			(0xfff << 8)
> >  #define OMAP3430_PERIPH_DPLL_DIV_SHIFT			0
> >  #define OMAP3430_PERIPH_DPLL_DIV_MASK			(0x7f << 0)
> >  #define OMAP3630_PERIPH_DPLL_DCO_SEL_SHIFT		21
> > @@ -573,8 +574,10 @@
> >  /* CM_CLKSEL_DSS */
> >  #define OMAP3430_CLKSEL_TV_SHIFT			8
> >  #define OMAP3430_CLKSEL_TV_MASK				(0x1f << 8)
> > +#define OMAP3630_CLKSEL_TV_MASK				(0x3f << 8)
> >  #define OMAP3430_CLKSEL_DSS1_SHIFT			0
> >  #define OMAP3430_CLKSEL_DSS1_MASK			(0x1f << 0)
> > +#define OMAP3630_CLKSEL_DSS1_MASK			(0x3f << 0)
> >
> >  /* CM_SLEEPDEP_DSS specific bits */
> >
> > @@ -602,6 +605,7 @@
> >  /* CM_CLKSEL_CAM */
> >  #define OMAP3430_CLKSEL_CAM_SHIFT			0
> >  #define OMAP3430_CLKSEL_CAM_MASK			(0x1f << 0)
> > +#define OMAP3630_CLKSEL_CAM_MASK			(0x3f << 0)
> >
> >  /* CM_SLEEPDEP_CAM specific bits */
> >
> > @@ -697,6 +701,7 @@
> >  /* CM_CLKSEL1_EMU */
> >  #define OMAP3430_DIV_DPLL4_SHIFT			24
> >  #define OMAP3430_DIV_DPLL4_MASK				(0x1f << 24)
> > +#define OMAP3630_DIV_DPLL4_MASK				(0x3f << 24)
> >  #define OMAP3430_DIV_DPLL3_SHIFT			16
> >  #define OMAP3430_DIV_DPLL3_MASK				(0x1f << 16)
> >  #define OMAP3430_CLKSEL_TRACECLK_SHIFT			11
> > diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-
> omap/include/plat/clock.h
> > index 359ccb4..0e0a5cc 100644
> > --- a/arch/arm/plat-omap/include/plat/clock.h
> > +++ b/arch/arm/plat-omap/include/plat/clock.h
> > @@ -93,7 +93,7 @@ struct clk {
> >  		defined(CONFIG_ARCH_OMAP4)
> >  	u8			fixed_div;
> >  	void __iomem		*clksel_reg;
> > -	u32			clksel_mask;
> > +	u32			clksel_mask, clksel_mask_3630;
> 
> why cant we use clksel_mask instead of introducing mask_3630? from my
> reading, you have specific dividers marked with 3XX and 36XX masks anyways..

We can avoid using clksel_mask_3630 by overwriting clksel_mask with 3630 mask MACRO. However this approach is not generic and will not scale if we have more dplls with clksel changes in future. Having separate clksel will make it more generic. 
> 
> >  	const struct clksel	*clksel;
> >  	struct dpll_data	*dpll_data;
> >  	const char		*clkdm_name;
> > @@ -159,7 +159,7 @@ extern const struct clkops clkops_null;
> >  #define RATE_IN_243X		(1 << 2)
> >  #define RATE_IN_3XXX		(1 << 3)	/* rates common to all 343X */
> >  #define RATE_IN_3430ES2		(1 << 4)	/* 3430ES2 rates only */
> > -
> > +#define RATE_IN_363X		(1 << 5)        /* rates common to all 343X */
> >  #define RATE_IN_24XX		(RATE_IN_242X | RATE_IN_243X)
> >
> >
> 
> 
> --
> Regards,
> Nishanth Menon

^ permalink raw reply	[flat|nested] 12+ messages in thread

* RE: [PATCHV2 4/4] OMAP3: add support for 192Mhz sgx clock
  2009-11-20 16:19         ` Nishanth Menon
@ 2009-11-23  9:30           ` Sripathy, Vishwanath
  0 siblings, 0 replies; 12+ messages in thread
From: Sripathy, Vishwanath @ 2009-11-23  9:30 UTC (permalink / raw)
  To: Menon, Nishanth; +Cc: linux-omap@vger.kernel.org



> -----Original Message-----
> From: Menon, Nishanth
> Sent: Friday, November 20, 2009 9:49 PM
> To: Sripathy, Vishwanath
> Cc: linux-omap@vger.kernel.org
> Subject: Re: [PATCHV2 4/4] OMAP3: add support for 192Mhz sgx clock
> 
> unrelated to this patch comment: we might want to consider thinking in
> terms of optimizing the memory as OMAP4 also kicks in.. some sort of
> dynamic clock tree traversal and __initdata method perhaps??


> 
> Hi Vishwa,
> Thanks for the patch, few minor comments follow:
> 
> Sripathy, Vishwanath had written, on 11/20/2009 09:28 AM, the following:
> > SGX can run at 192MHz on 3630 and this patch has changes to support this
> > feature. Basically DPLL4 M2 will be 192Mhz which will be used as SGX
> > Clock. 192Mhz clock is divided by 2 (using CM_CLKSEL_CORE) to generate
> > 96Mh clock
>    ^^^^ <- you probably intended 96Mhz

Yes, is should be 96Mhz.
> >
> > Signed-off-by: Vishwanath BS <Vishwanath.bs@ti.com>
> > ---
> >  arch/arm/mach-omap2/clock34xx.c       |   16 +++++++++++++++-
> >  arch/arm/mach-omap2/clock34xx.h       |   33
> +++++++++++++++++++++++++++++++++
> >  arch/arm/mach-omap2/cm-regbits-34xx.h |    2 ++
> >  arch/arm/mach-omap2/id.c              |    7 +++++--
> >  arch/arm/plat-omap/include/plat/cpu.h |    3 +++
> >  5 files changed, 58 insertions(+), 3 deletions(-)
> >
> > diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-
> omap2/clock34xx.c
> > index 1e35f9a..bce7e46 100755
> > --- a/arch/arm/mach-omap2/clock34xx.c
> > +++ b/arch/arm/mach-omap2/clock34xx.c
> > @@ -128,6 +128,7 @@ static struct omap_clk omap34xx_clks[] = {
> >  	CLK(NULL,	"emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX),
> >  	CLK(NULL,	"dpll4_ck",	&dpll4_ck,	CK_3XXX),
> >  	CLK(NULL,	"dpll4_x2_ck",	&dpll4_x2_ck,	CK_3XXX),
> > +       CLK(NULL,       "omap_192m_alwon_ck", &omap_192m_alwon_ck,
> CK_363X),
> >  	CLK(NULL,	"omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_3XXX),
> >  	CLK(NULL,	"omap_96m_fck",	&omap_96m_fck,	CK_3XXX),
> >  	CLK(NULL,	"cm_96m_fck",	&cm_96m_fck,	CK_3XXX),
> > @@ -1226,7 +1227,20 @@ int __init omap2_clk_init(void)
> >  				OMAP3630_PERIPH_DPLL_SD_DIV_MASK;
> >  			dpll4_dd.mult_mask = OMAP3630_PERIPH_DPLL_MULT_MASK;
> >  			cpu_mask |= RATE_IN_363X;
> > -			}
> > +			cpu_clkflg |= CK_363X;
> 
> I think introduce CK_36XX should be done seperately.

Ack. It should have been part of patch3.
> 
> > +		}
> > +
> > +		if (omap3_has_192mhz_clk()) {
> > +			omap_96m_alwon_fck.parent = &omap_192m_alwon_ck;
> > +			omap_96m_alwon_fck.init = &omap2_init_clksel_parent;
> > +			omap_96m_alwon_fck.clksel_reg =
> > +					OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
> > +			omap_96m_alwon_fck.clksel_mask =
> > +						OMAP3630_CLKSEL_96M_MASK;
> > +			omap_96m_alwon_fck.clksel = omap_96m_alwon_fck_clksel;
> > +			omap_96m_alwon_fck.recalc = &omap2_clksel_recalc;
> > +		}
> > +
> >  	}
> >
> >  	clk_init(&omap2_clk_functions);
> > diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-
> omap2/clock34xx.h
> > index 93c92e5..6fe89df 100644
> > --- a/arch/arm/mach-omap2/clock34xx.h
> > +++ b/arch/arm/mach-omap2/clock34xx.h
> > @@ -654,12 +654,31 @@ static struct clk dpll4_m2x2_ck = {
> >  	.recalc		= &omap3_clkoutx2_recalc,
> >  };
> >
> > +/* Adding 192MHz Clock node needed by SGX */
> > +static struct clk omap_192m_alwon_ck = {
> > +	.name           = "omap_192m_alwon_ck",
> > +	.ops            = &clkops_null,
> > +	.parent         = &dpll4_m2x2_ck,
> > +	.recalc         = &followparent_recalc,
> > +};
> > +
> >  /*
> >   * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
> >   * PRM_96M_ALWON_(F)CLK.  Two clocks then emerge from the PRM:
> >   * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
> >   * CM_96K_(F)CLK.
> >   */
> > +static const struct clksel_rate omap_96m_alwon_fck_rates[] = {
> > +	{ .div = 1, .val = 1, .flags = RATE_IN_363X },
> > +	{ .div = 2, .val = 2, .flags = RATE_IN_363X | DEFAULT_RATE },
> > +	{ .div = 0 }
> > +};
> > +
> > +static const struct clksel omap_96m_alwon_fck_clksel[] = {
> > +	{ .parent = &omap_192m_alwon_ck, .rates = omap_96m_alwon_fck_rates },
> > +	{ .parent = NULL }
> > +};
> > +
> >  static struct clk omap_96m_alwon_fck = {
> >  	.name		= "omap_96m_alwon_fck",
> >  	.ops		= &clkops_null,
> > @@ -1223,6 +1242,18 @@ static const struct clksel_rate sgx_core_rates[] = {
> >  	{ .div = 3, .val = 0, .flags = RATE_IN_3XXX | DEFAULT_RATE },
> >  	{ .div = 4, .val = 1, .flags = RATE_IN_3XXX },
> >  	{ .div = 6, .val = 2, .flags = RATE_IN_3XXX },
> > +	{ .div = 2, .val = 5, .flags = RATE_IN_363X },
> dont we have more options here? thinking: does this mean that all 3XXX
> and 36XX defines are valid ones for SGX?

>From PRCM point of view all 3XXX configurations are valid for 3430. All 3XXX and 363X are valid for 3630. May be SGX driver not use all these configurations, however Clock node should support all. 

> 
> > +	{ .div = 0 },
> > +};
> > +
> > +static const struct clksel_rate sgx_192m_rates[] = {
> > +	{ .div = 1,  .val = 4, .flags = RATE_IN_363X | DEFAULT_RATE },
> > +	{ .div = 0 },
> > +};
> > +
> > +static const struct clksel_rate sgx_corex2_rates[] = {
> > +	{ .div = 3, .val = 6, .flags = RATE_IN_363X | DEFAULT_RATE },
> > +	{ .div = 5, .val = 7, .flags = RATE_IN_363X },
> >  	{ .div = 0 },
> >  };
> >
> > @@ -1234,6 +1265,8 @@ static const struct clksel_rate sgx_96m_rates[] = {
> >  static const struct clksel sgx_clksel[] = {
> >  	{ .parent = &core_ck,	 .rates = sgx_core_rates },
> >  	{ .parent = &cm_96m_fck, .rates = sgx_96m_rates },
> > +	{ .parent = &omap_192m_alwon_ck, .rates = sgx_192m_rates },
> > +	{ .parent = &corex2_fck, .rates = sgx_corex2_rates },
> >  	{ .parent = NULL },
> >  };
> >
> > diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-
> regbits-34xx.h
> > index a6383f9..39b3399 100644
> > --- a/arch/arm/mach-omap2/cm-regbits-34xx.h
> > +++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
> > @@ -336,6 +336,8 @@
> >  #define OMAP3430_CLKSEL_L4_MASK				(0x3 << 2)
> >  #define OMAP3430_CLKSEL_L3_SHIFT			0
> >  #define OMAP3430_CLKSEL_L3_MASK				(0x3 << 0)
> > +#define OMAP3630_CLKSEL_96M_SHIFT                      12
> > +#define OMAP3630_CLKSEL_96M_MASK                       (0x3 << 12)
> >
> >  /* CM_CLKSTCTRL_CORE */
> >  #define OMAP3430ES1_CLKTRCTRL_D2D_SHIFT			4
> > diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
> > index 3c1194c..b1bc79d 100644
> > --- a/arch/arm/mach-omap2/id.c
> > +++ b/arch/arm/mach-omap2/id.c
> > @@ -176,8 +176,10 @@ void __init omap3_check_features(void)
> >  	OMAP3_CHECK_FEATURE(status, NEON);
> >  	OMAP3_CHECK_FEATURE(status, ISP);
> >
> > -	if (cpu_is_omap3630())
> > -		omap3_features |= OMAP3_HAS_JTYPE_DPLL4;
> > +	if (cpu_is_omap3630()) {
> > +		omap3_features |= OMAP3_HAS_JTYPE_DPLL4 |
> > +							OMAP3_HAS_192MHZ_CLK;
> might be better to do this as a next entry -> you may want other chips
> having 192Mhz to also use it..
> 
> Please Ref: http://patchwork.kernel.org/patch/61671/ to see how it is
> done clean.

Ack. Will do it as part of V3
> 
> > +	}
> >  	/*
> >  	 * TODO: Get additional info (where applicable)
> >  	 *       e.g. Size of L2 cache.
> > @@ -319,6 +321,7 @@ void __init omap3_cpuinfo(void)
> >  	OMAP3_SHOW_FEATURE(neon);
> >  	OMAP3_SHOW_FEATURE(isp);
> >  	OMAP3_SHOW_FEATURE(jtype_dpll4);
> > +	OMAP3_SHOW_FEATURE(192mhz_clk);
> >  	printk(")\n");
> >  }
> >
> > diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-
> omap/include/plat/cpu.h
> > index 65c08d5..1dffe25 100644
> > --- a/arch/arm/plat-omap/include/plat/cpu.h
> > +++ b/arch/arm/plat-omap/include/plat/cpu.h
> > @@ -498,6 +498,7 @@ extern u32 omap3_features;
> >  #define OMAP3_HAS_NEON			BIT(3)
> >  #define OMAP3_HAS_ISP			BIT(4)
> >  #define OMAP3_HAS_JTYPE_DPLL4		BIT(5)
> > +#define OMAP3_HAS_192MHZ_CLK		BIT(6)
> >
> >  #define OMAP3_HAS_FEATURE(feat,flag)			\
> >  static inline unsigned int omap3_has_ ##feat(void)	\
> > @@ -511,4 +512,6 @@ OMAP3_HAS_FEATURE(iva, IVA)
> >  OMAP3_HAS_FEATURE(neon, NEON)
> >  OMAP3_HAS_FEATURE(isp, ISP)
> >  OMAP3_HAS_FEATURE(jtype_dpll4, JTYPE_DPLL4)
> > +OMAP3_HAS_FEATURE(192mhz_clk, 192MHZ_CLK)
> > +
> EOL
> >  #endif
> 
> 
> --
> Regards,
> Nishanth Menon

^ permalink raw reply	[flat|nested] 12+ messages in thread

end of thread, other threads:[~2009-11-23  9:30 UTC | newest]

Thread overview: 12+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2009-11-20 15:28 [PATCHV2 0/4] OMAP3: Clock changes for OMAP3630 Vishwanath BS
2009-11-20 15:28 ` [PATCHV2 1/4] OMAP3: introduce DPLL4 Jtype Vishwanath BS
2009-11-20 15:28   ` [PATCHV2 2/4] OMAP3: Clock Type change for OMAP3 Clocks Vishwanath BS
2009-11-20 15:28     ` [PATCHV2 3/4] OMAP3: Correct width for CLKSEL Fields Vishwanath BS
2009-11-20 15:28       ` [PATCHV2 4/4] OMAP3: add support for 192Mhz sgx clock Vishwanath BS
2009-11-20 16:19         ` Nishanth Menon
2009-11-23  9:30           ` Sripathy, Vishwanath
2009-11-20 15:57       ` [PATCHV2 3/4] OMAP3: Correct width for CLKSEL Fields Aguirre, Sergio
2009-11-23  8:15         ` Sripathy, Vishwanath
2009-11-20 16:00       ` Nishanth Menon
2009-11-23  9:12         ` Sripathy, Vishwanath
2009-11-20 15:44     ` [PATCHV2 2/4] OMAP3: Clock Type change for OMAP3 Clocks Nishanth Menon

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