Re: [PATCH] OMAP3: PM: Dynamic calculation of SDRC clock stabilization delay

[Nishanth Menon <nm@ti.com>]

Menon, Nishanth had written, on 12/11/2009 07:42 AM, the following:
> Dasgupta, Romit had written, on 12/11/2009 06:31 AM, the following:
>>> Also Richard indicated that there might be a few tricky things with perf
>>> Counters with specific devices - like EMU/HS/GP devices. It might need EMU
>>> Domain for the values to pass through and there might be a yet-not-measured increase In power which could impact usage numbers and may need additional 
>>> Code to switch off the domain correctly while hitting OFF/RET..
>>>
>> Yes someone with EMU/HS could run and let us know. OTOH there won't be any
>> increase in power as it is done only once during boot time after which the
>> perfcounters are stopped.
>>
>> By the way can you run this in 3630 and help us find what is the SRAM access
>> delay? I am sure it should be lesser since it has a process improvement over 34xx.
>>
>>
> will try on SDP3630 among the boards that I have around. meanwhile, 
> would like an explanation to my previous comments also esp on the black 
> magic "6" ;) - thanks.
> 
Just realized -> clock framework changes are not in yet, anyways, with 
3630SDP (without my OPP series and on pm branch):
Clocking rate (Crystal/Core/MPU): 26.0/400/600 MHz
SRAM delay: 54 

Reprogramming SDRC clock to 400000000 Hz

-- 
Regards,
Nishanth Menon