* [PATCH 0/7] OMAP4: mux: Add the OMAP4430 ES1.0 & ES2.x support
@ 2010-11-11 21:35 Benoit Cousson
2010-11-11 21:35 ` [PATCH 1/7] OMAP: mux: Replace printk with pr_xxx macros Benoit Cousson
` (6 more replies)
0 siblings, 7 replies; 14+ messages in thread
From: Benoit Cousson @ 2010-11-11 21:35 UTC (permalink / raw)
To: tony; +Cc: linux-omap, Benoit Cousson
Hi Tony,
Here is the version updated with your fixes.
This is the first non RFC version to make Nishant M. happy;-)
Thanks to you, the RX-51 is now handled properly and the low level API
is still public like before for dynamic mux use.
The pandaboard is now supported thanks to Sricharan, and a couple of bugs
are fixed, thanks to Dan who reported them.
The series is based on mainline (2.6.37-rc1) and is available here:
git://gitorious.org/omap-pm/linux.git ctrl-wip/mux-omap4-v3
Tested on SDP4430 ES1.0, ES2.0 and ES2.1 with omap2plus_defconfig.
Still require some test on OMAP3 and OMAP2.
Thanks,
Benoit
RFC v2:
http://www.spinics.net/lists/linux-omap/msg38995.html
- Take into account Tony's proposal to store partition information
in a partition structure instead of inside every pad entries.
- Remove some cpu_is_xxx calls from the core code by adding a
couple of flags during partition init.
RFC v1:
http://www.spinics.net/lists/linux-omap/msg37158.html
Benoit Cousson (6):
OMAP: mux: Replace printk with pr_xxx macros
OMAP: mux: Add support for control module split in several partitions
OMAP4: mux: Add CBL package data for OMAP4430 ES1
OMAP4: sdp4430: Select CBL package for ES1 and initialize mux
OMAP4: mux: Add CBS package data for OMAP4430 ES2
OMAP4: sdp4430: Select CBS package for ES2
sricharan (1):
OMAP4: pandaboard: Select CBL & CBS package and initialize mux
arch/arm/mach-omap2/Kconfig | 10 +
arch/arm/mach-omap2/Makefile | 1 +
arch/arm/mach-omap2/board-4430sdp.c | 14 +
arch/arm/mach-omap2/board-omap4panda.c | 16 +
arch/arm/mach-omap2/board-rx51-peripherals.c | 12 +-
arch/arm/mach-omap2/mux.c | 342 ++++--
arch/arm/mach-omap2/mux.h | 84 ++-
arch/arm/mach-omap2/mux2420.c | 7 +-
arch/arm/mach-omap2/mux2430.c | 7 +-
arch/arm/mach-omap2/mux34xx.c | 7 +-
arch/arm/mach-omap2/mux44xx.c | 1625 ++++++++++++++++++++++++++
arch/arm/mach-omap2/mux44xx.h | 298 +++++
12 files changed, 2279 insertions(+), 144 deletions(-)
create mode 100644 arch/arm/mach-omap2/mux44xx.c
create mode 100644 arch/arm/mach-omap2/mux44xx.h
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 1/7] OMAP: mux: Replace printk with pr_xxx macros
2010-11-11 21:35 [PATCH 0/7] OMAP4: mux: Add the OMAP4430 ES1.0 & ES2.x support Benoit Cousson
@ 2010-11-11 21:35 ` Benoit Cousson
2010-11-11 21:35 ` [PATCH 2/7] OMAP: mux: Add support for control module split in several partitions Benoit Cousson
` (5 subsequent siblings)
6 siblings, 0 replies; 14+ messages in thread
From: Benoit Cousson @ 2010-11-11 21:35 UTC (permalink / raw)
To: tony; +Cc: linux-omap, Benoit Cousson, Paul Walmsley, Kevin Hilman
Replace all the printk(KERN_XXX... with pr_xxx macros.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
---
arch/arm/mach-omap2/mux.c | 38 +++++++++++++++++++-------------------
1 files changed, 19 insertions(+), 19 deletions(-)
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 074536a..979e9d1 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -102,13 +102,13 @@ int __init omap_mux_init_gpio(int gpio, int val)
}
if (found == 0) {
- printk(KERN_ERR "mux: Could not set gpio%i\n", gpio);
+ pr_err("mux: Could not set gpio%i\n", gpio);
return -ENODEV;
}
if (found > 1) {
- printk(KERN_INFO "mux: Multiple gpio paths (%d) for gpio%i\n",
- found, gpio);
+ pr_info("mux: Multiple gpio paths (%d) for gpio%i\n",
+ found, gpio);
return -EINVAL;
}
@@ -118,8 +118,8 @@ int __init omap_mux_init_gpio(int gpio, int val)
mux_mode |= OMAP_MUX_MODE3;
else
mux_mode |= OMAP_MUX_MODE4;
- printk(KERN_DEBUG "mux: Setting signal %s.gpio%i 0x%04x -> 0x%04x\n",
- gpio_mux->muxnames[0], gpio, old_mode, mux_mode);
+ pr_debug("mux: Setting signal %s.gpio%i 0x%04x -> 0x%04x\n",
+ gpio_mux->muxnames[0], gpio, old_mode, mux_mode);
omap_mux_write(mux_mode, gpio_mux->reg_offset);
return 0;
@@ -161,9 +161,9 @@ int __init omap_mux_init_signal(const char *muxname, int val)
old_mode = omap_mux_read(m->reg_offset);
mux_mode = val | i;
- printk(KERN_DEBUG "mux: Setting signal "
- "%s.%s 0x%04x -> 0x%04x\n",
- m0_entry, muxname, old_mode, mux_mode);
+ pr_debug("mux: Setting signal "
+ "%s.%s 0x%04x -> 0x%04x\n",
+ m0_entry, muxname, old_mode, mux_mode);
omap_mux_write(mux_mode, m->reg_offset);
found++;
}
@@ -174,12 +174,12 @@ int __init omap_mux_init_signal(const char *muxname, int val)
return 0;
if (found > 1) {
- printk(KERN_ERR "mux: Multiple signal paths (%i) for %s\n",
- found, muxname);
+ pr_err("mux: Multiple signal paths (%i) for %s\n",
+ found, muxname);
return -EINVAL;
}
- printk(KERN_ERR "mux: Could not set signal %s\n", muxname);
+ pr_err("mux: Could not set signal %s\n", muxname);
return -ENODEV;
}
@@ -462,8 +462,8 @@ static void __init omap_mux_package_fixup(struct omap_mux *p,
s++;
}
if (!found)
- printk(KERN_ERR "mux: Unknown entry offset 0x%x\n",
- p->reg_offset);
+ pr_err("mux: Unknown entry offset 0x%x\n",
+ p->reg_offset);
p++;
}
}
@@ -487,8 +487,8 @@ static void __init omap_mux_package_init_balls(struct omap_ball *b,
s++;
}
if (!found)
- printk(KERN_ERR "mux: Unknown ball offset 0x%x\n",
- b->reg_offset);
+ pr_err("mux: Unknown ball offset 0x%x\n",
+ b->reg_offset);
b++;
}
}
@@ -615,7 +615,7 @@ u16 omap_mux_get_gpio(int gpio)
offset = omap_mux_get_by_gpio(gpio);
if (offset == OMAP_MUX_TERMINATOR) {
- printk(KERN_ERR "mux: Could not get gpio%i\n", gpio);
+ pr_err("mux: Could not get gpio%i\n", gpio);
return offset;
}
@@ -629,7 +629,7 @@ void omap_mux_set_gpio(u16 val, int gpio)
offset = omap_mux_get_by_gpio(gpio);
if (offset == OMAP_MUX_TERMINATOR) {
- printk(KERN_ERR "mux: Could not set gpio%i\n", gpio);
+ pr_err("mux: Could not set gpio%i\n", gpio);
return;
}
@@ -687,7 +687,7 @@ static void __init omap_mux_init_list(struct omap_mux *superset)
entry = omap_mux_list_add(superset);
if (!entry) {
- printk(KERN_ERR "mux: Could not add entry\n");
+ pr_err("mux: Could not add entry\n");
return;
}
superset++;
@@ -738,7 +738,7 @@ int __init omap_mux_init(u32 mux_pbase, u32 mux_size,
mux_phys = mux_pbase;
mux_base = ioremap(mux_pbase, mux_size);
if (!mux_base) {
- printk(KERN_ERR "mux: Could not ioremap\n");
+ pr_err("mux: Could not ioremap\n");
return -ENODEV;
}
--
1.7.0.4
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 2/7] OMAP: mux: Add support for control module split in several partitions
2010-11-11 21:35 [PATCH 0/7] OMAP4: mux: Add the OMAP4430 ES1.0 & ES2.x support Benoit Cousson
2010-11-11 21:35 ` [PATCH 1/7] OMAP: mux: Replace printk with pr_xxx macros Benoit Cousson
@ 2010-11-11 21:35 ` Benoit Cousson
2010-11-15 20:03 ` Tony Lindgren
2010-11-11 21:35 ` [PATCH 3/7] OMAP4: mux: Add CBL package data for OMAP4430 ES1 Benoit Cousson
` (4 subsequent siblings)
6 siblings, 1 reply; 14+ messages in thread
From: Benoit Cousson @ 2010-11-11 21:35 UTC (permalink / raw)
To: tony
Cc: linux-omap, Benoit Cousson, Paul Walmsley, Kevin Hilman,
Santosh Shilimkar
Starting on OMAP4, the pin mux configuration is located in two
different partitions of the control module (CODE_PAD and WKUP_PAD).
The first one is inside the core power domain whereas the second
one is inside the wakeup.
- Add the capability to add any number of partition during board init
time depending of Soc partitioning.
- Add some init flags as well in order to avoid explicit Soc version
check inside the mux core code.
- Add a comment with mux0 mode on top of omap_mux/board/<partition>
if the current mux mode is not the default one.
Thanks to Tony Lindgren <tony@atomide.com> for the following improvements:
- Add omap_mux_get for getting the partition data so platform level
device code can use it.
- Fix the rx51 board code to use the new API.
Thanks to Dan Murphy <dmurphy@ti.com> for testing on OMAP4 and reporting
a couple of bugs.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Tested-by: Murphy Dan <dmurphy@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
arch/arm/mach-omap2/board-rx51-peripherals.c | 12 +-
arch/arm/mach-omap2/mux.c | 310 +++++++++++++++++---------
arch/arm/mach-omap2/mux.h | 71 +++++-
arch/arm/mach-omap2/mux2420.c | 7 +-
arch/arm/mach-omap2/mux2430.c | 7 +-
arch/arm/mach-omap2/mux34xx.c | 7 +-
6 files changed, 286 insertions(+), 128 deletions(-)
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index 3fec4d6..3fda20d 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -293,6 +293,8 @@ static struct omap_board_mux rx51_mmc2_off_mux[] = {
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
+static struct omap_mux_partition *partition;
+
/*
* Current flows to eMMC when eMMC is off and the data lines are pulled up,
* so pull them down. N.B. we pull 8 lines because we are using 8 lines.
@@ -300,9 +302,9 @@ static struct omap_board_mux rx51_mmc2_off_mux[] = {
static void rx51_mmc2_remux(struct device *dev, int slot, int power_on)
{
if (power_on)
- omap_mux_write_array(rx51_mmc2_on_mux);
+ omap_mux_write_array(partition, rx51_mmc2_on_mux);
else
- omap_mux_write_array(rx51_mmc2_off_mux);
+ omap_mux_write_array(partition, rx51_mmc2_off_mux);
}
static struct omap2_hsmmc_info mmc[] __initdata = {
@@ -922,7 +924,11 @@ void __init rx51_peripherals_init(void)
rx51_init_wl1251();
spi_register_board_info(rx51_peripherals_spi_board_info,
ARRAY_SIZE(rx51_peripherals_spi_board_info));
- omap2_hsmmc_init(mmc);
+
+ partition = omap_mux_get("core");
+ if (partition)
+ omap2_hsmmc_init(mmc);
+
platform_device_register(&rx51_charger_device);
}
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 979e9d1..fa139ff 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -1,9 +1,9 @@
/*
* linux/arch/arm/mach-omap2/mux.c
*
- * OMAP2 and OMAP3 pin multiplexing configurations
+ * OMAP2, OMAP3 and OMAP4 pin multiplexing configurations
*
- * Copyright (C) 2004 - 2008 Texas Instruments Inc.
+ * Copyright (C) 2004 - 2010 Texas Instruments Inc.
* Copyright (C) 2003 - 2008 Nokia Corporation
*
* Written by Tony Lindgren
@@ -40,60 +40,72 @@
#define OMAP_MUX_BASE_OFFSET 0x30 /* Offset from CTRL_BASE */
#define OMAP_MUX_BASE_SZ 0x5ca
-#define MUXABLE_GPIO_MODE3 BIT(0)
struct omap_mux_entry {
struct omap_mux mux;
struct list_head node;
};
-static unsigned long mux_phys;
-static void __iomem *mux_base;
-static u8 omap_mux_flags;
+static LIST_HEAD(mux_partitions);
+static DEFINE_MUTEX(muxmode_mutex);
+
+struct omap_mux_partition *omap_mux_get(const char *name)
+{
+ struct omap_mux_partition *partition;
+
+ list_for_each_entry(partition, &mux_partitions, node) {
+ if (!strcmp(name, partition->name))
+ return partition;
+ }
+
+ return NULL;
+}
-u16 omap_mux_read(u16 reg)
+u16 omap_mux_read(struct omap_mux_partition *partition, u16 reg)
{
- if (cpu_is_omap24xx())
- return __raw_readb(mux_base + reg);
+ if (partition->flags & OMAP_MUX_REG_8BIT)
+ return __raw_readb(partition->base + reg);
else
- return __raw_readw(mux_base + reg);
+ return __raw_readw(partition->base + reg);
}
-void omap_mux_write(u16 val, u16 reg)
+void omap_mux_write(struct omap_mux_partition *partition, u16 val,
+ u16 reg)
{
- if (cpu_is_omap24xx())
- __raw_writeb(val, mux_base + reg);
+ if (partition->flags & OMAP_MUX_REG_8BIT)
+ __raw_writeb(val, partition->base + reg);
else
- __raw_writew(val, mux_base + reg);
+ __raw_writew(val, partition->base + reg);
}
-void omap_mux_write_array(struct omap_board_mux *board_mux)
+void omap_mux_write_array(struct omap_mux_partition *partition,
+ struct omap_board_mux *board_mux)
{
- while (board_mux->reg_offset != OMAP_MUX_TERMINATOR) {
- omap_mux_write(board_mux->value, board_mux->reg_offset);
+ while (board_mux->reg_offset != OMAP_MUX_TERMINATOR) {
+ omap_mux_write(partition, board_mux->value,
+ board_mux->reg_offset);
board_mux++;
}
}
-static LIST_HEAD(muxmodes);
-static DEFINE_MUTEX(muxmode_mutex);
-
#ifdef CONFIG_OMAP_MUX
static char *omap_mux_options;
-int __init omap_mux_init_gpio(int gpio, int val)
+static int __init _omap_mux_init_gpio(struct omap_mux_partition *partition,
+ int gpio, int val)
{
struct omap_mux_entry *e;
struct omap_mux *gpio_mux = NULL;
u16 old_mode;
u16 mux_mode;
int found = 0;
+ struct list_head *muxmodes = &partition->muxmodes;
if (!gpio)
return -EINVAL;
- list_for_each_entry(e, &muxmodes, node) {
+ list_for_each_entry(e, muxmodes, node) {
struct omap_mux *m = &e->mux;
if (gpio == m->gpio) {
gpio_mux = m;
@@ -112,24 +124,40 @@ int __init omap_mux_init_gpio(int gpio, int val)
return -EINVAL;
}
- old_mode = omap_mux_read(gpio_mux->reg_offset);
+ old_mode = omap_mux_read(partition, gpio_mux->reg_offset);
mux_mode = val & ~(OMAP_MUX_NR_MODES - 1);
- if (omap_mux_flags & MUXABLE_GPIO_MODE3)
+ if (partition->flags & OMAP_MUX_GPIO_IN_MODE3)
mux_mode |= OMAP_MUX_MODE3;
else
mux_mode |= OMAP_MUX_MODE4;
pr_debug("mux: Setting signal %s.gpio%i 0x%04x -> 0x%04x\n",
gpio_mux->muxnames[0], gpio, old_mode, mux_mode);
- omap_mux_write(mux_mode, gpio_mux->reg_offset);
+ omap_mux_write(partition, mux_mode, gpio_mux->reg_offset);
return 0;
}
-int __init omap_mux_init_signal(const char *muxname, int val)
+int __init omap_mux_init_gpio(int gpio, int val)
+{
+ struct omap_mux_partition *partition;
+ int ret;
+
+ list_for_each_entry(partition, &mux_partitions, node) {
+ ret = _omap_mux_init_gpio(partition, gpio, val);
+ if (!ret)
+ return ret;
+ }
+
+ return -ENODEV;
+}
+
+static int __init _omap_mux_init_signal(struct omap_mux_partition *partition,
+ const char *muxname, int val)
{
struct omap_mux_entry *e;
const char *mode_name;
int found = 0, mode0_len = 0;
+ struct list_head *muxmodes = &partition->muxmodes;
mode_name = strchr(muxname, '.');
if (mode_name) {
@@ -139,7 +167,7 @@ int __init omap_mux_init_signal(const char *muxname, int val)
mode_name = muxname;
}
- list_for_each_entry(e, &muxmodes, node) {
+ list_for_each_entry(e, muxmodes, node) {
struct omap_mux *m = &e->mux;
char *m0_entry = m->muxnames[0];
int i;
@@ -159,12 +187,14 @@ int __init omap_mux_init_signal(const char *muxname, int val)
u16 old_mode;
u16 mux_mode;
- old_mode = omap_mux_read(m->reg_offset);
+ old_mode = omap_mux_read(partition,
+ m->reg_offset);
mux_mode = val | i;
pr_debug("mux: Setting signal "
"%s.%s 0x%04x -> 0x%04x\n",
m0_entry, muxname, old_mode, mux_mode);
- omap_mux_write(mux_mode, m->reg_offset);
+ omap_mux_write(partition, mux_mode,
+ m->reg_offset);
found++;
}
}
@@ -184,6 +214,21 @@ int __init omap_mux_init_signal(const char *muxname, int val)
return -ENODEV;
}
+int __init omap_mux_init_signal(const char *muxname, int val)
+{
+ struct omap_mux_partition *partition;
+ int ret;
+
+ list_for_each_entry(partition, &mux_partitions, node) {
+ ret = _omap_mux_init_signal(partition, muxname, val);
+ if (!ret)
+ return ret;
+ }
+
+ return -ENODEV;
+
+}
+
#ifdef CONFIG_DEBUG_FS
#define OMAP_MUX_MAX_NR_FLAGS 10
@@ -248,13 +293,15 @@ static inline void omap_mux_decode(struct seq_file *s, u16 val)
} while (i-- > 0);
}
-#define OMAP_MUX_DEFNAME_LEN 16
+#define OMAP_MUX_DEFNAME_LEN 32
static int omap_mux_dbg_board_show(struct seq_file *s, void *unused)
{
+ struct omap_mux_partition *partition = s->private;
struct omap_mux_entry *e;
+ u8 omap_gen = omap_rev() >> 28;
- list_for_each_entry(e, &muxmodes, node) {
+ list_for_each_entry(e, &partition->muxmodes, node) {
struct omap_mux *m = &e->mux;
char m0_def[OMAP_MUX_DEFNAME_LEN];
char *m0_name = m->muxnames[0];
@@ -272,11 +319,16 @@ static int omap_mux_dbg_board_show(struct seq_file *s, void *unused)
}
m0_def[i] = toupper(m0_name[i]);
}
- val = omap_mux_read(m->reg_offset);
+ val = omap_mux_read(partition, m->reg_offset);
mode = val & OMAP_MUX_MODE7;
-
- seq_printf(s, "OMAP%i_MUX(%s, ",
- cpu_is_omap34xx() ? 3 : 0, m0_def);
+ if (mode != 0)
+ seq_printf(s, "/* %s */\n", m->muxnames[mode]);
+
+ /*
+ * XXX: Might be revisited to support differences accross
+ * same OMAP generation.
+ */
+ seq_printf(s, "OMAP%d_MUX(%s, ", omap_gen, m0_def);
omap_mux_decode(s, val);
seq_printf(s, "),\n");
}
@@ -286,7 +338,7 @@ static int omap_mux_dbg_board_show(struct seq_file *s, void *unused)
static int omap_mux_dbg_board_open(struct inode *inode, struct file *file)
{
- return single_open(file, omap_mux_dbg_board_show, &inode->i_private);
+ return single_open(file, omap_mux_dbg_board_show, inode->i_private);
}
static const struct file_operations omap_mux_dbg_board_fops = {
@@ -299,16 +351,17 @@ static const struct file_operations omap_mux_dbg_board_fops = {
static int omap_mux_dbg_signal_show(struct seq_file *s, void *unused)
{
struct omap_mux *m = s->private;
+ struct omap_mux_partition *partition = m->partition;
const char *none = "NA";
u16 val;
int mode;
- val = omap_mux_read(m->reg_offset);
+ val = omap_mux_read(partition, m->reg_offset);
mode = val & OMAP_MUX_MODE7;
- seq_printf(s, "name: %s.%s (0x%08lx/0x%03x = 0x%04x), b %s, t %s\n",
+ seq_printf(s, "name: %s.%s (0x%08x/0x%03x = 0x%04x), b %s, t %s\n",
m->muxnames[0], m->muxnames[mode],
- mux_phys + m->reg_offset, m->reg_offset, val,
+ partition->phys + m->reg_offset, m->reg_offset, val,
m->balls[0] ? m->balls[0] : none,
m->balls[1] ? m->balls[1] : none);
seq_printf(s, "mode: ");
@@ -330,8 +383,8 @@ static int omap_mux_dbg_signal_show(struct seq_file *s, void *unused)
#define OMAP_MUX_MAX_ARG_CHAR 7
static ssize_t omap_mux_dbg_signal_write(struct file *file,
- const char __user *user_buf,
- size_t count, loff_t *ppos)
+ const char __user *user_buf,
+ size_t count, loff_t *ppos)
{
char buf[OMAP_MUX_MAX_ARG_CHAR];
struct seq_file *seqf;
@@ -358,7 +411,7 @@ static ssize_t omap_mux_dbg_signal_write(struct file *file,
seqf = file->private_data;
m = seqf->private;
- omap_mux_write((u16)val, m->reg_offset);
+ omap_mux_write(m->partition, (u16)val, m->reg_offset);
*ppos += count;
return count;
@@ -379,22 +432,39 @@ static const struct file_operations omap_mux_dbg_signal_fops = {
static struct dentry *mux_dbg_dir;
-static void __init omap_mux_dbg_init(void)
+static void __init omap_mux_dbg_create_entry(
+ struct omap_mux_partition *partition,
+ struct dentry *mux_dbg_dir)
{
struct omap_mux_entry *e;
+ list_for_each_entry(e, &partition->muxmodes, node) {
+ struct omap_mux *m = &e->mux;
+ m->partition = partition;
+
+ (void)debugfs_create_file(m->muxnames[0], S_IWUGO, mux_dbg_dir,
+ m, &omap_mux_dbg_signal_fops);
+ }
+}
+
+static void __init omap_mux_dbg_init(void)
+{
+ struct omap_mux_partition *partition;
+ static struct dentry *mux_dbg_board_dir;
+
mux_dbg_dir = debugfs_create_dir("omap_mux", NULL);
if (!mux_dbg_dir)
return;
- (void)debugfs_create_file("board", S_IRUGO, mux_dbg_dir,
- NULL, &omap_mux_dbg_board_fops);
-
- list_for_each_entry(e, &muxmodes, node) {
- struct omap_mux *m = &e->mux;
+ mux_dbg_board_dir = debugfs_create_dir("board", mux_dbg_dir);
+ if (!mux_dbg_board_dir)
+ return;
- (void)debugfs_create_file(m->muxnames[0], S_IWUGO, mux_dbg_dir,
- m, &omap_mux_dbg_signal_fops);
+ list_for_each_entry(partition, &mux_partitions, node) {
+ omap_mux_dbg_create_entry(partition, mux_dbg_dir);
+ (void)debugfs_create_file(partition->name, S_IRUGO,
+ mux_dbg_board_dir, partition,
+ &omap_mux_dbg_board_fops);
}
}
@@ -421,23 +491,25 @@ static void __init omap_mux_free_names(struct omap_mux *m)
/* Free all data except for GPIO pins unless CONFIG_DEBUG_FS is set */
static int __init omap_mux_late_init(void)
{
- struct omap_mux_entry *e, *tmp;
+ struct omap_mux_partition *partition;
- list_for_each_entry_safe(e, tmp, &muxmodes, node) {
- struct omap_mux *m = &e->mux;
- u16 mode = omap_mux_read(m->reg_offset);
+ list_for_each_entry(partition, &mux_partitions, node) {
+ struct omap_mux_entry *e, *tmp;
+ list_for_each_entry_safe(e, tmp, &partition->muxmodes, node) {
+ struct omap_mux *m = &e->mux;
+ u16 mode = omap_mux_read(partition, m->reg_offset);
- if (OMAP_MODE_GPIO(mode))
- continue;
+ if (OMAP_MODE_GPIO(mode))
+ continue;
#ifndef CONFIG_DEBUG_FS
- mutex_lock(&muxmode_mutex);
- list_del(&e->node);
- mutex_unlock(&muxmode_mutex);
- omap_mux_free_names(m);
- kfree(m);
+ mutex_lock(&muxmode_mutex);
+ list_del(&e->node);
+ mutex_unlock(&muxmode_mutex);
+ omap_mux_free_names(m);
+ kfree(m);
#endif
-
+ }
}
omap_mux_dbg_init();
@@ -554,7 +626,7 @@ static void __init omap_mux_set_cmdline_signals(void)
}
static int __init omap_mux_copy_names(struct omap_mux *src,
- struct omap_mux *dst)
+ struct omap_mux *dst)
{
int i;
@@ -592,51 +664,63 @@ free:
#endif /* CONFIG_OMAP_MUX */
-static u16 omap_mux_get_by_gpio(int gpio)
+static struct omap_mux *omap_mux_get_by_gpio(
+ struct omap_mux_partition *partition,
+ int gpio)
{
struct omap_mux_entry *e;
- u16 offset = OMAP_MUX_TERMINATOR;
+ struct omap_mux *ret = NULL;
- list_for_each_entry(e, &muxmodes, node) {
+ list_for_each_entry(e, &partition->muxmodes, node) {
struct omap_mux *m = &e->mux;
if (m->gpio == gpio) {
- offset = m->reg_offset;
+ ret = m;
break;
}
}
- return offset;
+ return ret;
}
/* Needed for dynamic muxing of GPIO pins for off-idle */
u16 omap_mux_get_gpio(int gpio)
{
- u16 offset;
+ struct omap_mux_partition *partition;
+ struct omap_mux *m;
- offset = omap_mux_get_by_gpio(gpio);
- if (offset == OMAP_MUX_TERMINATOR) {
- pr_err("mux: Could not get gpio%i\n", gpio);
- return offset;
+ list_for_each_entry(partition, &mux_partitions, node) {
+ m = omap_mux_get_by_gpio(partition, gpio);
+ if (m)
+ return omap_mux_read(partition, m->reg_offset);
}
- return omap_mux_read(offset);
+ if (!m || m->reg_offset == OMAP_MUX_TERMINATOR)
+ pr_err("mux: Could not get gpio%i\n", gpio);
+
+ return OMAP_MUX_TERMINATOR;
}
/* Needed for dynamic muxing of GPIO pins for off-idle */
void omap_mux_set_gpio(u16 val, int gpio)
{
- u16 offset;
+ struct omap_mux_partition *partition;
+ struct omap_mux *m = NULL;
- offset = omap_mux_get_by_gpio(gpio);
- if (offset == OMAP_MUX_TERMINATOR) {
- pr_err("mux: Could not set gpio%i\n", gpio);
- return;
+ list_for_each_entry(partition, &mux_partitions, node) {
+ m = omap_mux_get_by_gpio(partition, gpio);
+ if (m) {
+ omap_mux_write(partition, val, m->reg_offset);
+ return;
+ }
}
- omap_mux_write(val, offset);
+ if (!m || m->reg_offset == OMAP_MUX_TERMINATOR)
+ pr_err("mux: Could not set gpio%i\n", gpio);
}
-static struct omap_mux * __init omap_mux_list_add(struct omap_mux *src)
+static struct omap_mux * __init omap_mux_list_add(
+ struct omap_mux_partition *partition,
+ struct omap_mux *src)
{
struct omap_mux_entry *entry;
struct omap_mux *m;
@@ -656,7 +740,7 @@ static struct omap_mux * __init omap_mux_list_add(struct omap_mux *src)
#endif
mutex_lock(&muxmode_mutex);
- list_add_tail(&entry->node, &muxmodes);
+ list_add_tail(&entry->node, &partition->muxmodes);
mutex_unlock(&muxmode_mutex);
return m;
@@ -667,7 +751,8 @@ static struct omap_mux * __init omap_mux_list_add(struct omap_mux *src)
* the GPIO to mux offset mapping that is needed for dynamic muxing
* of GPIO pins for off-idle.
*/
-static void __init omap_mux_init_list(struct omap_mux *superset)
+static void __init omap_mux_init_list(struct omap_mux_partition *partition,
+ struct omap_mux *superset)
{
while (superset->reg_offset != OMAP_MUX_TERMINATOR) {
struct omap_mux *entry;
@@ -679,13 +764,14 @@ static void __init omap_mux_init_list(struct omap_mux *superset)
}
#else
/* Skip pins that are not muxed as GPIO by bootloader */
- if (!OMAP_MODE_GPIO(omap_mux_read(superset->reg_offset))) {
+ if (!OMAP_MODE_GPIO(omap_mux_read(partition,
+ superset->reg_offset))) {
superset++;
continue;
}
#endif
- entry = omap_mux_list_add(superset);
+ entry = omap_mux_list_add(partition, superset);
if (!entry) {
pr_err("mux: Could not add entry\n");
return;
@@ -706,10 +792,11 @@ static void omap_mux_init_package(struct omap_mux *superset,
omap_mux_package_init_balls(package_balls, superset);
}
-static void omap_mux_init_signals(struct omap_board_mux *board_mux)
+static void omap_mux_init_signals(struct omap_mux_partition *partition,
+ struct omap_board_mux *board_mux)
{
omap_mux_set_cmdline_signals();
- omap_mux_write_array(board_mux);
+ omap_mux_write_array(partition->base, board_mux);
}
#else
@@ -720,34 +807,49 @@ static void omap_mux_init_package(struct omap_mux *superset,
{
}
-static void omap_mux_init_signals(struct omap_board_mux *board_mux)
+static void omap_mux_init_signals(struct omap_mux_partition *partition,
+ struct omap_board_mux *board_mux)
{
}
#endif
-int __init omap_mux_init(u32 mux_pbase, u32 mux_size,
- struct omap_mux *superset,
- struct omap_mux *package_subset,
- struct omap_board_mux *board_mux,
- struct omap_ball *package_balls)
-{
- if (mux_base)
- return -EBUSY;
+static u32 mux_partitions_cnt;
- mux_phys = mux_pbase;
- mux_base = ioremap(mux_pbase, mux_size);
- if (!mux_base) {
- pr_err("mux: Could not ioremap\n");
+int __init omap_mux_init(const char * name, u32 flags,
+ u32 mux_pbase, u32 mux_size,
+ struct omap_mux *superset,
+ struct omap_mux *package_subset,
+ struct omap_board_mux *board_mux,
+ struct omap_ball *package_balls)
+{
+ struct omap_mux_partition *partition;
+
+ partition = kzalloc(sizeof(struct omap_mux_partition), GFP_KERNEL);
+ if (!partition)
+ return -ENOMEM;
+
+ partition->name = name;
+ partition->flags = flags;
+ partition->size = mux_size;
+ partition->phys = mux_pbase;
+ partition->base = ioremap(mux_pbase, mux_size);
+ if (!partition->base) {
+ pr_err("mux: Could not ioremap mux partition at 0x%08x\n",
+ partition->phys);
return -ENODEV;
}
- if (cpu_is_omap24xx())
- omap_mux_flags = MUXABLE_GPIO_MODE3;
+ INIT_LIST_HEAD(&partition->muxmodes);
+
+ list_add_tail(&partition->node, &mux_partitions);
+ mux_partitions_cnt++;
+ pr_info("MUX: Add partition: #%d: %s, flags: %x\n",
+ mux_partitions_cnt, partition->name, partition->flags);
omap_mux_init_package(superset, package_subset, package_balls);
- omap_mux_init_list(superset);
- omap_mux_init_signals(board_mux);
+ omap_mux_init_list(partition, superset);
+ omap_mux_init_signals(partition, board_mux);
return 0;
}
diff --git a/arch/arm/mach-omap2/mux.h b/arch/arm/mach-omap2/mux.h
index 350c04f..46c1aab 100644
--- a/arch/arm/mach-omap2/mux.h
+++ b/arch/arm/mach-omap2/mux.h
@@ -1,6 +1,6 @@
/*
* Copyright (C) 2009 Nokia
- * Copyright (C) 2009 Texas Instruments
+ * Copyright (C) 2009-2010 Texas Instruments
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@@ -56,7 +56,7 @@
#define OMAP_MODE_GPIO(x) (((x) & OMAP_MUX_MODE7) == OMAP_MUX_MODE4)
-/* Flags for omap_mux_init */
+/* Flags for omapX_mux_init */
#define OMAP_PACKAGE_MASK 0xffff
#define OMAP_PACKAGE_CBP 6 /* 515-pin 0.40 0.50 */
#define OMAP_PACKAGE_CUS 5 /* 423-pin 0.65 */
@@ -66,14 +66,47 @@
#define OMAP_PACKAGE_ZAF 1 /* 2420 447-pin SIP */
-#define OMAP_MUX_NR_MODES 8 /* Available modes */
-#define OMAP_MUX_NR_SIDES 2 /* Bottom & top */
+#define OMAP_MUX_NR_MODES 8 /* Available modes */
+#define OMAP_MUX_NR_SIDES 2 /* Bottom & top */
+
+/*
+ * omap_mux_init flags definition:
+ *
+ * OMAP_MUX_REG_8BIT: Ensure that access to padconf is done in 8 bits.
+ * The default value is 16 bits.
+ * OMAP_MUX_GPIO_IN_MODE3: The GPIO is selected in mode3.
+ * The default is mode4.
+ */
+#define OMAP_MUX_REG_8BIT (1 << 0)
+#define OMAP_MUX_GPIO_IN_MODE3 (1 << 1)
+
+/**
+ * struct mux_partition - contain partition related information
+ * @name: name of the current partition
+ * @flags: flags specific to this partition
+ * @phys: physical address
+ * @size: partition size
+ * @base: virtual address after ioremap
+ * @muxmodes: list of nodes that belong to a partition
+ * @node: list node for the partitions linked list
+ */
+struct omap_mux_partition {
+ const char *name;
+ u32 flags;
+ u32 phys;
+ u32 size;
+ void __iomem *base;
+ struct list_head muxmodes;
+ struct list_head node;
+};
/**
* struct omap_mux - data for omap mux register offset and it's value
* @reg_offset: mux register offset from the mux base
* @gpio: GPIO number
* @muxnames: available signal modes for a ball
+ * @balls: available balls on the package
+ * @partition: mux partition
*/
struct omap_mux {
u16 reg_offset;
@@ -82,6 +115,7 @@ struct omap_mux {
char *muxnames[OMAP_MUX_NR_MODES];
#ifdef CONFIG_DEBUG_FS
char *balls[OMAP_MUX_NR_SIDES];
+ struct omap_mux_partition *partition;
#endif
#endif
};
@@ -151,28 +185,39 @@ u16 omap_mux_get_gpio(int gpio);
void omap_mux_set_gpio(u16 val, int gpio);
/**
+ * omap_mux_get() - get a mux partition by name
+ * @name: Name of the mux partition
+ *
+ */
+struct omap_mux_partition *omap_mux_get(const char *name);
+
+/**
* omap_mux_read() - read mux register
+ * @partition: Mux partition
* @mux_offset: Offset of the mux register
*
*/
-u16 omap_mux_read(u16 mux_offset);
+u16 omap_mux_read(struct omap_mux_partition *p, u16 mux_offset);
/**
* omap_mux_write() - write mux register
+ * @partition: Mux partition
* @val: New mux register value
* @mux_offset: Offset of the mux register
*
* This should be only needed for dynamic remuxing of non-gpio signals.
*/
-void omap_mux_write(u16 val, u16 mux_offset);
+void omap_mux_write(struct omap_mux_partition *p, u16 val, u16 mux_offset);
/**
* omap_mux_write_array() - write an array of mux registers
+ * @partition: Mux partition
* @board_mux: Array of mux registers terminated by MAP_MUX_TERMINATOR
*
* This should be only needed for dynamic remuxing of non-gpio signals.
*/
-void omap_mux_write_array(struct omap_board_mux *board_mux);
+void omap_mux_write_array(struct omap_mux_partition *p,
+ struct omap_board_mux *board_mux);
/**
* omap2420_mux_init() - initialize mux system with board specific set
@@ -198,8 +243,10 @@ int omap3_mux_init(struct omap_board_mux *board_mux, int flags);
/**
* omap_mux_init - private mux init function, do not call
*/
-int omap_mux_init(u32 mux_pbase, u32 mux_size,
- struct omap_mux *superset,
- struct omap_mux *package_subset,
- struct omap_board_mux *board_mux,
- struct omap_ball *package_balls);
+int omap_mux_init(const char *name, u32 flags,
+ u32 mux_pbase, u32 mux_size,
+ struct omap_mux *superset,
+ struct omap_mux *package_subset,
+ struct omap_board_mux *board_mux,
+ struct omap_ball *package_balls);
+
diff --git a/arch/arm/mach-omap2/mux2420.c b/arch/arm/mach-omap2/mux2420.c
index 414af54..8231f0a 100644
--- a/arch/arm/mach-omap2/mux2420.c
+++ b/arch/arm/mach-omap2/mux2420.c
@@ -681,8 +681,9 @@ int __init omap2420_mux_init(struct omap_board_mux *board_subset, int flags)
pr_warning("mux: No ball data available for omap2420 package\n");
}
- return omap_mux_init(OMAP2420_CONTROL_PADCONF_MUX_PBASE,
+ return omap_mux_init("core", OMAP_MUX_REG_8BIT | OMAP_MUX_GPIO_IN_MODE3,
+ OMAP2420_CONTROL_PADCONF_MUX_PBASE,
OMAP2420_CONTROL_PADCONF_MUX_SIZE,
- omap2420_muxmodes, NULL, board_subset,
- package_balls);
+ omap2420_muxmodes, NULL, board_subset,
+ package_balls);
}
diff --git a/arch/arm/mach-omap2/mux2430.c b/arch/arm/mach-omap2/mux2430.c
index 84d2c5a..cb6b404 100644
--- a/arch/arm/mach-omap2/mux2430.c
+++ b/arch/arm/mach-omap2/mux2430.c
@@ -784,8 +784,9 @@ int __init omap2430_mux_init(struct omap_board_mux *board_subset, int flags)
pr_warning("mux: No ball data available for omap2420 package\n");
}
- return omap_mux_init(OMAP2430_CONTROL_PADCONF_MUX_PBASE,
+ return omap_mux_init("core", OMAP_MUX_REG_8BIT | OMAP_MUX_GPIO_IN_MODE3,
+ OMAP2430_CONTROL_PADCONF_MUX_PBASE,
OMAP2430_CONTROL_PADCONF_MUX_SIZE,
- omap2430_muxmodes, NULL, board_subset,
- package_balls);
+ omap2430_muxmodes, NULL, board_subset,
+ package_balls);
}
diff --git a/arch/arm/mach-omap2/mux34xx.c b/arch/arm/mach-omap2/mux34xx.c
index 574e54e..4113c93 100644
--- a/arch/arm/mach-omap2/mux34xx.c
+++ b/arch/arm/mach-omap2/mux34xx.c
@@ -2053,8 +2053,9 @@ int __init omap3_mux_init(struct omap_board_mux *board_subset, int flags)
return -EINVAL;
}
- return omap_mux_init(OMAP3_CONTROL_PADCONF_MUX_PBASE,
+ return omap_mux_init("core", 0,
+ OMAP3_CONTROL_PADCONF_MUX_PBASE,
OMAP3_CONTROL_PADCONF_MUX_SIZE,
- omap3_muxmodes, package_subset, board_subset,
- package_balls);
+ omap3_muxmodes, package_subset, board_subset,
+ package_balls);
}
--
1.7.0.4
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 3/7] OMAP4: mux: Add CBL package data for OMAP4430 ES1
2010-11-11 21:35 [PATCH 0/7] OMAP4: mux: Add the OMAP4430 ES1.0 & ES2.x support Benoit Cousson
2010-11-11 21:35 ` [PATCH 1/7] OMAP: mux: Replace printk with pr_xxx macros Benoit Cousson
2010-11-11 21:35 ` [PATCH 2/7] OMAP: mux: Add support for control module split in several partitions Benoit Cousson
@ 2010-11-11 21:35 ` Benoit Cousson
2010-11-11 21:35 ` [PATCH 4/7] OMAP4: sdp4430: Select CBL package for ES1 and initialize mux Benoit Cousson
` (3 subsequent siblings)
6 siblings, 0 replies; 14+ messages in thread
From: Benoit Cousson @ 2010-11-11 21:35 UTC (permalink / raw)
To: tony; +Cc: linux-omap, Benoit Cousson, Paul Walmsley, Kevin Hilman
Add data for OMAP4430 generated from HW pinout & register database.
The data set is split in two partitions for both core and wkup.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
---
arch/arm/mach-omap2/Kconfig | 3 +
arch/arm/mach-omap2/Makefile | 1 +
arch/arm/mach-omap2/mux.h | 12 +
arch/arm/mach-omap2/mux44xx.c | 900 +++++++++++++++++++++++++++++++++++++++++
arch/arm/mach-omap2/mux44xx.h | 277 +++++++++++++
5 files changed, 1193 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-omap2/mux44xx.c
create mode 100644 arch/arm/mach-omap2/mux44xx.h
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index ab784bf..e14c73d 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -85,6 +85,9 @@ config OMAP_PACKAGE_CUS
config OMAP_PACKAGE_CBP
bool
+config OMAP_PACKAGE_CBL
+ bool
+
comment "OMAP Board Type"
depends on ARCH_OMAP2PLUS
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 60e51bc..d32d660 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -42,6 +42,7 @@ AFLAGS_sram34xx.o :=-Wa,-march=armv7-a
obj-$(CONFIG_ARCH_OMAP2420) += mux2420.o
obj-$(CONFIG_ARCH_OMAP2430) += mux2430.o
obj-$(CONFIG_ARCH_OMAP3) += mux34xx.o
+obj-$(CONFIG_ARCH_OMAP4) += mux44xx.o
# SMS/SDRC
obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o
diff --git a/arch/arm/mach-omap2/mux.h b/arch/arm/mach-omap2/mux.h
index 46c1aab..58e4913 100644
--- a/arch/arm/mach-omap2/mux.h
+++ b/arch/arm/mach-omap2/mux.h
@@ -10,6 +10,7 @@
#include "mux2420.h"
#include "mux2430.h"
#include "mux34xx.h"
+#include "mux44xx.h"
#define OMAP_MUX_TERMINATOR 0xffff
@@ -37,6 +38,9 @@
#define OMAP_OFF_PULL_UP (1 << 13)
#define OMAP_WAKEUP_EN (1 << 14)
+/* 44xx specific mux bit defines */
+#define OMAP_WAKEUP_EVENT (1 << 15)
+
/* Active pin states */
#define OMAP_PIN_OUTPUT 0
#define OMAP_PIN_INPUT OMAP_INPUT_EN
@@ -58,6 +62,7 @@
/* Flags for omapX_mux_init */
#define OMAP_PACKAGE_MASK 0xffff
+#define OMAP_PACKAGE_CBL 7 /* 547-pin 0.40 0.40 */
#define OMAP_PACKAGE_CBP 6 /* 515-pin 0.40 0.50 */
#define OMAP_PACKAGE_CUS 5 /* 423-pin 0.65 */
#define OMAP_PACKAGE_CBB 4 /* 515-pin 0.40 0.50 */
@@ -241,6 +246,13 @@ int omap2430_mux_init(struct omap_board_mux *board_mux, int flags);
int omap3_mux_init(struct omap_board_mux *board_mux, int flags);
/**
+ * omap4_mux_init() - initialize mux system with board specific set
+ * @board_mux: Board specific mux table
+ * @flags: OMAP package type used for the board
+ */
+int omap4_mux_init(struct omap_board_mux *board_mux, int flags);
+
+/**
* omap_mux_init - private mux init function, do not call
*/
int omap_mux_init(const char *name, u32 flags,
diff --git a/arch/arm/mach-omap2/mux44xx.c b/arch/arm/mach-omap2/mux44xx.c
new file mode 100644
index 0000000..5e9d60a
--- /dev/null
+++ b/arch/arm/mach-omap2/mux44xx.c
@@ -0,0 +1,900 @@
+/*
+ * OMAP44xx ES1.0 pin mux definition
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ *
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * - Based on mux34xx.c done by Tony Lindgren <tony@atomide.com>
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/module.h>
+#include <linux/init.h>
+
+#include "mux.h"
+
+#ifdef CONFIG_OMAP_MUX
+
+#define _OMAP4_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \
+{ \
+ .reg_offset = (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET), \
+ .gpio = (g), \
+ .muxnames = { m0, m1, m2, m3, m4, m5, m6, m7 }, \
+}
+
+#else
+
+#define _OMAP4_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \
+{ \
+ .reg_offset = (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET), \
+ .gpio = (g), \
+}
+
+#endif
+
+#define _OMAP4_BALLENTRY(M0, bb, bt) \
+{ \
+ .reg_offset = (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET), \
+ .balls = { bb, bt }, \
+}
+
+/*
+ * Superset of all mux modes for omap4
+ */
+static struct omap_mux __initdata omap4_core_muxmodes[] = {
+ _OMAP4_MUXENTRY(GPMC_AD0, 0, "gpmc_ad0", "sdmmc2_dat0", NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD1, 0, "gpmc_ad1", "sdmmc2_dat1", NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD2, 0, "gpmc_ad2", "sdmmc2_dat2", NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD3, 0, "gpmc_ad3", "sdmmc2_dat3", NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD4, 0, "gpmc_ad4", "sdmmc2_dat4",
+ "sdmmc2_dir_dat0", NULL, NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD5, 0, "gpmc_ad5", "sdmmc2_dat5",
+ "sdmmc2_dir_dat1", NULL, NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD6, 0, "gpmc_ad6", "sdmmc2_dat6",
+ "sdmmc2_dir_cmd", NULL, NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD7, 0, "gpmc_ad7", "sdmmc2_dat7",
+ "sdmmc2_clk_fdbk", NULL, NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD8, 32, "gpmc_ad8", "kpd_row0", "c2c_data15",
+ "gpio_32", NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD9, 33, "gpmc_ad9", "kpd_row1", "c2c_data14",
+ "gpio_33", NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD10, 34, "gpmc_ad10", "kpd_row2", "c2c_data13",
+ "gpio_34", NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD11, 35, "gpmc_ad11", "kpd_row3", "c2c_data12",
+ "gpio_35", NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD12, 36, "gpmc_ad12", "kpd_col0", "c2c_data11",
+ "gpio_36", NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD13, 37, "gpmc_ad13", "kpd_col1", "c2c_data10",
+ "gpio_37", NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD14, 38, "gpmc_ad14", "kpd_col2", "c2c_data9",
+ "gpio_38", NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD15, 39, "gpmc_ad15", "kpd_col3", "c2c_data8",
+ "gpio_39", NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_A16, 40, "gpmc_a16", "kpd_row4", "c2c_datain0",
+ "gpio_40", "venc_656_data0", NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_A17, 41, "gpmc_a17", "kpd_row5", "c2c_datain1",
+ "gpio_41", "venc_656_data1", NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_A18, 42, "gpmc_a18", "kpd_row6", "c2c_datain2",
+ "gpio_42", "venc_656_data2", NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_A19, 43, "gpmc_a19", "kpd_row7", "c2c_datain3",
+ "gpio_43", "venc_656_data3", NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_A20, 44, "gpmc_a20", "kpd_col4", "c2c_datain4",
+ "gpio_44", "venc_656_data4", NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_A21, 45, "gpmc_a21", "kpd_col5", "c2c_datain5",
+ "gpio_45", "venc_656_data5", NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_A22, 46, "gpmc_a22", "kpd_col6", "c2c_datain6",
+ "gpio_46", "venc_656_data6", NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_A23, 47, "gpmc_a23", "kpd_col7", "c2c_datain7",
+ "gpio_47", "venc_656_data7", NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_A24, 48, "gpmc_a24", NULL, "c2c_clkout0",
+ "gpio_48", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_A25, 49, "gpmc_a25", NULL, "c2c_clkout1",
+ "gpio_49", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_NCS0, 50, "gpmc_ncs0", NULL, NULL, "gpio_50",
+ "sys_ndmareq0", NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_NCS1, 51, "gpmc_ncs1", NULL, "c2c_dataout6",
+ "gpio_51", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_NCS2, 52, "gpmc_ncs2", NULL, "c2c_dataout7",
+ "gpio_52", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_NCS3, 53, "gpmc_ncs3", "gpmc_dir",
+ "c2c_dataout4", "gpio_53", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_NWP, 54, "gpmc_nwp", "dsi1_te0", NULL, "gpio_54",
+ "sys_ndmareq1", NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_CLK, 55, "gpmc_clk", NULL, NULL, "gpio_55",
+ "sys_ndmareq2", NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_NADV_ALE, 56, "gpmc_nadv_ale", "dsi1_te1", NULL,
+ "gpio_56", "sys_ndmareq3", NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_NOE, 0, "gpmc_noe", "sdmmc2_clk", NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_NWE, 0, "gpmc_nwe", "sdmmc2_cmd", NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_NBE0_CLE, 59, "gpmc_nbe0_cle", "dsi2_te0", NULL,
+ "gpio_59", NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_NBE1, 60, "gpmc_nbe1", NULL, "c2c_dataout5",
+ "gpio_60", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_WAIT0, 61, "gpmc_wait0", "dsi2_te1", NULL,
+ "gpio_61", NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_WAIT1, 62, "gpmc_wait1", NULL, "c2c_dataout2",
+ "gpio_62", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(C2C_DATA11, 100, "c2c_data11", "usbc1_icusb_txen",
+ "c2c_dataout3", "gpio_100", "sys_ndmareq0", NULL,
+ NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(C2C_DATA12, 101, "c2c_data12", "dsi1_te0",
+ "c2c_clkin0", "gpio_101", "sys_ndmareq1", NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(C2C_DATA13, 102, "c2c_data13", "dsi1_te1",
+ "c2c_clkin1", "gpio_102", "sys_ndmareq2", NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(C2C_DATA14, 103, "c2c_data14", "dsi2_te0",
+ "c2c_dataout0", "gpio_103", "sys_ndmareq3", NULL,
+ NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(C2C_DATA15, 104, "c2c_data15", "dsi2_te1",
+ "c2c_dataout1", "gpio_104", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(HDMI_HPD, 63, "hdmi_hpd", NULL, NULL, "gpio_63", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(HDMI_CEC, 64, "hdmi_cec", NULL, NULL, "gpio_64", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(HDMI_DDC_SCL, 65, "hdmi_ddc_scl", NULL, NULL,
+ "gpio_65", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(HDMI_DDC_SDA, 66, "hdmi_ddc_sda", NULL, NULL,
+ "gpio_66", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CSI21_DX0, 0, "csi21_dx0", NULL, NULL, "gpi_67", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CSI21_DY0, 0, "csi21_dy0", NULL, NULL, "gpi_68", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CSI21_DX1, 0, "csi21_dx1", NULL, NULL, "gpi_69", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CSI21_DY1, 0, "csi21_dy1", NULL, NULL, "gpi_70", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CSI21_DX2, 0, "csi21_dx2", NULL, NULL, "gpi_71", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CSI21_DY2, 0, "csi21_dy2", NULL, NULL, "gpi_72", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CSI21_DX3, 0, "csi21_dx3", NULL, NULL, "gpi_73", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CSI21_DY3, 0, "csi21_dy3", NULL, NULL, "gpi_74", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CSI21_DX4, 0, "csi21_dx4", NULL, NULL, "gpi_75", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CSI21_DY4, 0, "csi21_dy4", NULL, NULL, "gpi_76", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CSI22_DX0, 0, "csi22_dx0", NULL, NULL, "gpi_77", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CSI22_DY0, 0, "csi22_dy0", NULL, NULL, "gpi_78", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CSI22_DX1, 0, "csi22_dx1", NULL, NULL, "gpi_79", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CSI22_DY1, 0, "csi22_dy1", NULL, NULL, "gpi_80", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CAM_SHUTTER, 81, "cam_shutter", NULL, NULL, "gpio_81",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CAM_STROBE, 82, "cam_strobe", NULL, NULL, "gpio_82",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CAM_GLOBALRESET, 83, "cam_globalreset", NULL, NULL,
+ "gpio_83", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(USBB1_ULPITLL_CLK, 84, "usbb1_ulpitll_clk",
+ "hsi1_cawake", NULL, "gpio_84", "usbb1_ulpiphy_clk",
+ NULL, "hw_dbg20", "safe_mode"),
+ _OMAP4_MUXENTRY(USBB1_ULPITLL_STP, 85, "usbb1_ulpitll_stp",
+ "hsi1_cadata", "mcbsp4_clkr", "gpio_85",
+ "usbb1_ulpiphy_stp", "usbb1_mm_rxdp", "hw_dbg21",
+ "safe_mode"),
+ _OMAP4_MUXENTRY(USBB1_ULPITLL_DIR, 86, "usbb1_ulpitll_dir",
+ "hsi1_caflag", "mcbsp4_fsr", "gpio_86",
+ "usbb1_ulpiphy_dir", NULL, "hw_dbg22", "safe_mode"),
+ _OMAP4_MUXENTRY(USBB1_ULPITLL_NXT, 87, "usbb1_ulpitll_nxt",
+ "hsi1_acready", "mcbsp4_fsx", "gpio_87",
+ "usbb1_ulpiphy_nxt", "usbb1_mm_rxdm", "hw_dbg23",
+ "safe_mode"),
+ _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT0, 88, "usbb1_ulpitll_dat0",
+ "hsi1_acwake", "mcbsp4_clkx", "gpio_88",
+ "usbb1_ulpiphy_dat0", "usbb1_mm_rxrcv", "hw_dbg24",
+ "safe_mode"),
+ _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT1, 89, "usbb1_ulpitll_dat1",
+ "hsi1_acdata", "mcbsp4_dx", "gpio_89",
+ "usbb1_ulpiphy_dat1", "usbb1_mm_txse0", "hw_dbg25",
+ "safe_mode"),
+ _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT2, 90, "usbb1_ulpitll_dat2",
+ "hsi1_acflag", "mcbsp4_dr", "gpio_90",
+ "usbb1_ulpiphy_dat2", "usbb1_mm_txdat", "hw_dbg26",
+ "safe_mode"),
+ _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT3, 91, "usbb1_ulpitll_dat3",
+ "hsi1_caready", NULL, "gpio_91", "usbb1_ulpiphy_dat3",
+ "usbb1_mm_txen", "hw_dbg27", "safe_mode"),
+ _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT4, 92, "usbb1_ulpitll_dat4",
+ "dmtimer8_pwm_evt", "abe_mcbsp3_dr", "gpio_92",
+ "usbb1_ulpiphy_dat4", NULL, "hw_dbg28", "safe_mode"),
+ _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT5, 93, "usbb1_ulpitll_dat5",
+ "dmtimer9_pwm_evt", "abe_mcbsp3_dx", "gpio_93",
+ "usbb1_ulpiphy_dat5", NULL, "hw_dbg29", "safe_mode"),
+ _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT6, 94, "usbb1_ulpitll_dat6",
+ "dmtimer10_pwm_evt", "abe_mcbsp3_clkx", "gpio_94",
+ "usbb1_ulpiphy_dat6", "abe_dmic_din3", "hw_dbg30",
+ "safe_mode"),
+ _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT7, 95, "usbb1_ulpitll_dat7",
+ "dmtimer11_pwm_evt", "abe_mcbsp3_fsx", "gpio_95",
+ "usbb1_ulpiphy_dat7", "abe_dmic_clk3", "hw_dbg31",
+ "safe_mode"),
+ _OMAP4_MUXENTRY(USBB1_HSIC_DATA, 96, "usbb1_hsic_data", NULL, NULL,
+ "gpio_96", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(USBB1_HSIC_STROBE, 97, "usbb1_hsic_strobe", NULL,
+ NULL, "gpio_97", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(USBC1_ICUSB_DP, 98, "usbc1_icusb_dp", NULL, NULL,
+ "gpio_98", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(USBC1_ICUSB_DM, 99, "usbc1_icusb_dm", NULL, NULL,
+ "gpio_99", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC1_CLK, 100, "sdmmc1_clk", NULL, "dpm_emu19",
+ "gpio_100", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC1_CMD, 101, "sdmmc1_cmd", NULL, "uart1_rx",
+ "gpio_101", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC1_DAT0, 102, "sdmmc1_dat0", NULL, "dpm_emu18",
+ "gpio_102", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC1_DAT1, 103, "sdmmc1_dat1", NULL, "dpm_emu17",
+ "gpio_103", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC1_DAT2, 104, "sdmmc1_dat2", NULL, "dpm_emu16",
+ "gpio_104", "jtag_tms_tmsc", NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC1_DAT3, 105, "sdmmc1_dat3", NULL, "dpm_emu15",
+ "gpio_105", "jtag_tck", NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC1_DAT4, 106, "sdmmc1_dat4", NULL, NULL,
+ "gpio_106", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC1_DAT5, 107, "sdmmc1_dat5", NULL, NULL,
+ "gpio_107", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC1_DAT6, 108, "sdmmc1_dat6", NULL, NULL,
+ "gpio_108", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC1_DAT7, 109, "sdmmc1_dat7", NULL, NULL,
+ "gpio_109", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_MCBSP2_CLKX, 110, "abe_mcbsp2_clkx", "mcspi2_clk",
+ "abe_mcasp_ahclkx", "gpio_110", "usbb2_mm_rxdm",
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_MCBSP2_DR, 111, "abe_mcbsp2_dr", "mcspi2_somi",
+ "abe_mcasp_axr", "gpio_111", "usbb2_mm_rxdp", NULL,
+ NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_MCBSP2_DX, 112, "abe_mcbsp2_dx", "mcspi2_simo",
+ "abe_mcasp_amute", "gpio_112", "usbb2_mm_rxrcv", NULL,
+ NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_MCBSP2_FSX, 113, "abe_mcbsp2_fsx", "mcspi2_cs0",
+ "abe_mcasp_afsx", "gpio_113", "usbb2_mm_txen", NULL,
+ NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_MCBSP1_CLKX, 114, "abe_mcbsp1_clkx",
+ "abe_slimbus1_clock", NULL, "gpio_114", NULL, NULL,
+ NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_MCBSP1_DR, 115, "abe_mcbsp1_dr",
+ "abe_slimbus1_data", NULL, "gpio_115", NULL, NULL,
+ NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_MCBSP1_DX, 116, "abe_mcbsp1_dx", "sdmmc3_dat2",
+ "abe_mcasp_aclkx", "gpio_116", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_MCBSP1_FSX, 117, "abe_mcbsp1_fsx", "sdmmc3_dat3",
+ "abe_mcasp_amutein", "gpio_117", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_PDM_UL_DATA, 0, "abe_pdm_ul_data",
+ "abe_mcbsp3_dr", NULL, NULL, NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_PDM_DL_DATA, 0, "abe_pdm_dl_data",
+ "abe_mcbsp3_dx", NULL, NULL, NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_PDM_FRAME, 0, "abe_pdm_frame", "abe_mcbsp3_clkx",
+ NULL, NULL, NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_PDM_LB_CLK, 0, "abe_pdm_lb_clk", "abe_mcbsp3_fsx",
+ NULL, NULL, NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_CLKS, 118, "abe_clks", NULL, NULL, "gpio_118",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_DMIC_CLK1, 119, "abe_dmic_clk1", NULL, NULL,
+ "gpio_119", "usbb2_mm_txse0", NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_DMIC_DIN1, 120, "abe_dmic_din1", NULL, NULL,
+ "gpio_120", "usbb2_mm_txdat", NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_DMIC_DIN2, 121, "abe_dmic_din2", "slimbus2_clock",
+ NULL, "gpio_121", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_DMIC_DIN3, 122, "abe_dmic_din3", "slimbus2_data",
+ "abe_dmic_clk2", "gpio_122", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(UART2_CTS, 123, "uart2_cts", "sdmmc3_clk", NULL,
+ "gpio_123", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(UART2_RTS, 124, "uart2_rts", "sdmmc3_cmd", NULL,
+ "gpio_124", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(UART2_RX, 125, "uart2_rx", "sdmmc3_dat0", NULL,
+ "gpio_125", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(UART2_TX, 126, "uart2_tx", "sdmmc3_dat1", NULL,
+ "gpio_126", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(HDQ_SIO, 127, "hdq_sio", "i2c3_sccb", "i2c2_sccb",
+ "gpio_127", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(I2C1_SCL, 0, "i2c1_scl", NULL, NULL, NULL, NULL, NULL,
+ NULL, NULL),
+ _OMAP4_MUXENTRY(I2C1_SDA, 0, "i2c1_sda", NULL, NULL, NULL, NULL, NULL,
+ NULL, NULL),
+ _OMAP4_MUXENTRY(I2C2_SCL, 128, "i2c2_scl", "uart1_rx", NULL,
+ "gpio_128", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(I2C2_SDA, 129, "i2c2_sda", "uart1_tx", NULL,
+ "gpio_129", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(I2C3_SCL, 130, "i2c3_scl", NULL, NULL, "gpio_130",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(I2C3_SDA, 131, "i2c3_sda", NULL, NULL, "gpio_131",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(I2C4_SCL, 132, "i2c4_scl", NULL, NULL, "gpio_132",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(I2C4_SDA, 133, "i2c4_sda", NULL, NULL, "gpio_133",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(MCSPI1_CLK, 134, "mcspi1_clk", NULL, NULL, "gpio_134",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(MCSPI1_SOMI, 135, "mcspi1_somi", NULL, NULL,
+ "gpio_135", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(MCSPI1_SIMO, 136, "mcspi1_simo", NULL, NULL,
+ "gpio_136", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(MCSPI1_CS0, 137, "mcspi1_cs0", NULL, NULL, "gpio_137",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(MCSPI1_CS1, 138, "mcspi1_cs1", "uart1_rx", NULL,
+ "gpio_138", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(MCSPI1_CS2, 139, "mcspi1_cs2", "uart1_cts",
+ "slimbus2_clock", "gpio_139", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(MCSPI1_CS3, 140, "mcspi1_cs3", "uart1_rts",
+ "slimbus2_data", "gpio_140", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(UART3_CTS_RCTX, 141, "uart3_cts_rctx", "uart1_tx",
+ NULL, "gpio_141", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(UART3_RTS_SD, 142, "uart3_rts_sd", NULL, NULL,
+ "gpio_142", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(UART3_RX_IRRX, 143, "uart3_rx_irrx",
+ "dmtimer8_pwm_evt", NULL, "gpio_143", NULL, NULL,
+ NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(UART3_TX_IRTX, 144, "uart3_tx_irtx",
+ "dmtimer9_pwm_evt", NULL, "gpio_144", NULL, NULL,
+ NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC5_CLK, 145, "sdmmc5_clk", "mcspi2_clk",
+ "usbc1_icusb_dp", "gpio_145", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC5_CMD, 146, "sdmmc5_cmd", "mcspi2_simo",
+ "usbc1_icusb_dm", "gpio_146", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC5_DAT0, 147, "sdmmc5_dat0", "mcspi2_somi",
+ "usbc1_icusb_rcv", "gpio_147", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC5_DAT1, 148, "sdmmc5_dat1", NULL,
+ "usbc1_icusb_txen", "gpio_148", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC5_DAT2, 149, "sdmmc5_dat2", "mcspi2_cs1", NULL,
+ "gpio_149", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC5_DAT3, 150, "sdmmc5_dat3", "mcspi2_cs0", NULL,
+ "gpio_150", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(MCSPI4_CLK, 151, "mcspi4_clk", "sdmmc4_clk", NULL,
+ "gpio_151", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(MCSPI4_SIMO, 152, "mcspi4_simo", "sdmmc4_cmd", NULL,
+ "gpio_152", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(MCSPI4_SOMI, 153, "mcspi4_somi", "sdmmc4_dat0", NULL,
+ "gpio_153", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(MCSPI4_CS0, 154, "mcspi4_cs0", "sdmmc4_dat3", NULL,
+ "gpio_154", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(UART4_RX, 155, "uart4_rx", "sdmmc4_dat2", NULL,
+ "gpio_155", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(UART4_TX, 156, "uart4_tx", "sdmmc4_dat1", NULL,
+ "gpio_156", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(USBB2_ULPITLL_CLK, 157, "usbb2_ulpitll_clk",
+ "usbb2_ulpiphy_clk", "sdmmc4_cmd", "gpio_157",
+ "hsi2_cawake", NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(USBB2_ULPITLL_STP, 158, "usbb2_ulpitll_stp",
+ "usbb2_ulpiphy_stp", "sdmmc4_clk", "gpio_158",
+ "hsi2_cadata", "dispc2_data23", NULL, "reserved"),
+ _OMAP4_MUXENTRY(USBB2_ULPITLL_DIR, 159, "usbb2_ulpitll_dir",
+ "usbb2_ulpiphy_dir", "sdmmc4_dat0", "gpio_159",
+ "hsi2_caflag", "dispc2_data22", NULL, "reserved"),
+ _OMAP4_MUXENTRY(USBB2_ULPITLL_NXT, 160, "usbb2_ulpitll_nxt",
+ "usbb2_ulpiphy_nxt", "sdmmc4_dat1", "gpio_160",
+ "hsi2_acready", "dispc2_data21", NULL, "reserved"),
+ _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT0, 161, "usbb2_ulpitll_dat0",
+ "usbb2_ulpiphy_dat0", "sdmmc4_dat2", "gpio_161",
+ "hsi2_acwake", "dispc2_data20", NULL, "reserved"),
+ _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT1, 162, "usbb2_ulpitll_dat1",
+ "usbb2_ulpiphy_dat1", "sdmmc4_dat3", "gpio_162",
+ "hsi2_acdata", "dispc2_data19", NULL, "reserved"),
+ _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT2, 163, "usbb2_ulpitll_dat2",
+ "usbb2_ulpiphy_dat2", "sdmmc3_dat2", "gpio_163",
+ "hsi2_acflag", "dispc2_data18", NULL, "reserved"),
+ _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT3, 164, "usbb2_ulpitll_dat3",
+ "usbb2_ulpiphy_dat3", "sdmmc3_dat1", "gpio_164",
+ "hsi2_caready", "dispc2_data15", NULL, "reserved"),
+ _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT4, 165, "usbb2_ulpitll_dat4",
+ "usbb2_ulpiphy_dat4", "sdmmc3_dat0", "gpio_165",
+ "mcspi3_somi", "dispc2_data14", NULL, "reserved"),
+ _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT5, 166, "usbb2_ulpitll_dat5",
+ "usbb2_ulpiphy_dat5", "sdmmc3_dat3", "gpio_166",
+ "mcspi3_cs0", "dispc2_data13", NULL, "reserved"),
+ _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT6, 167, "usbb2_ulpitll_dat6",
+ "usbb2_ulpiphy_dat6", "sdmmc3_cmd", "gpio_167",
+ "mcspi3_simo", "dispc2_data12", NULL, "reserved"),
+ _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT7, 168, "usbb2_ulpitll_dat7",
+ "usbb2_ulpiphy_dat7", "sdmmc3_clk", "gpio_168",
+ "mcspi3_clk", "dispc2_data11", NULL, "reserved"),
+ _OMAP4_MUXENTRY(USBB2_HSIC_DATA, 169, "usbb2_hsic_data", NULL, NULL,
+ "gpio_169", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(USBB2_HSIC_STROBE, 170, "usbb2_hsic_strobe", NULL,
+ NULL, "gpio_170", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(UNIPRO_TX0, 171, "unipro_tx0", "kpd_col0", NULL,
+ "gpio_171", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(UNIPRO_TY0, 172, "unipro_ty0", "kpd_col1", NULL,
+ "gpio_172", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(UNIPRO_TX1, 173, "unipro_tx1", "kpd_col2", NULL,
+ "gpio_173", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(UNIPRO_TY1, 174, "unipro_ty1", "kpd_col3", NULL,
+ "gpio_174", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(UNIPRO_TX2, 0, "unipro_tx2", "kpd_col4", NULL,
+ "gpio_0", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(UNIPRO_TY2, 1, "unipro_ty2", "kpd_col5", NULL,
+ "gpio_1", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(UNIPRO_RX0, 0, "unipro_rx0", "kpd_row0", NULL,
+ "gpi_175", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(UNIPRO_RY0, 0, "unipro_ry0", "kpd_row1", NULL,
+ "gpi_176", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(UNIPRO_RX1, 0, "unipro_rx1", "kpd_row2", NULL,
+ "gpi_177", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(UNIPRO_RY1, 0, "unipro_ry1", "kpd_row3", NULL,
+ "gpi_178", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(UNIPRO_RX2, 0, "unipro_rx2", "kpd_row4", NULL,
+ "gpi_2", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(UNIPRO_RY2, 0, "unipro_ry2", "kpd_row5", NULL,
+ "gpi_3", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(USBA0_OTG_CE, 0, "usba0_otg_ce", NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(USBA0_OTG_DP, 179, "usba0_otg_dp", "uart3_rx_irrx",
+ "uart2_rx", "gpio_179", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(USBA0_OTG_DM, 180, "usba0_otg_dm", "uart3_tx_irtx",
+ "uart2_tx", "gpio_180", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(FREF_CLK1_OUT, 181, "fref_clk1_out", NULL, NULL,
+ "gpio_181", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(FREF_CLK2_OUT, 182, "fref_clk2_out", NULL, NULL,
+ "gpio_182", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SYS_NIRQ1, 0, "sys_nirq1", NULL, NULL, NULL, NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SYS_NIRQ2, 183, "sys_nirq2", NULL, NULL, "gpio_183",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SYS_BOOT0, 184, "sys_boot0", NULL, NULL, "gpio_184",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SYS_BOOT1, 185, "sys_boot1", NULL, NULL, "gpio_185",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SYS_BOOT2, 186, "sys_boot2", NULL, NULL, "gpio_186",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SYS_BOOT3, 187, "sys_boot3", NULL, NULL, "gpio_187",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SYS_BOOT4, 188, "sys_boot4", NULL, NULL, "gpio_188",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SYS_BOOT5, 189, "sys_boot5", NULL, NULL, "gpio_189",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(DPM_EMU0, 11, "dpm_emu0", NULL, NULL, "gpio_11", NULL,
+ NULL, "hw_dbg0", "safe_mode"),
+ _OMAP4_MUXENTRY(DPM_EMU1, 12, "dpm_emu1", NULL, NULL, "gpio_12", NULL,
+ NULL, "hw_dbg1", "safe_mode"),
+ _OMAP4_MUXENTRY(DPM_EMU2, 13, "dpm_emu2", "usba0_ulpiphy_clk", NULL,
+ "gpio_13", NULL, "dispc2_fid", "hw_dbg2", "reserved"),
+ _OMAP4_MUXENTRY(DPM_EMU3, 14, "dpm_emu3", "usba0_ulpiphy_stp", NULL,
+ "gpio_14", NULL, "dispc2_data10", "hw_dbg3",
+ "reserved"),
+ _OMAP4_MUXENTRY(DPM_EMU4, 15, "dpm_emu4", "usba0_ulpiphy_dir", NULL,
+ "gpio_15", NULL, "dispc2_data9", "hw_dbg4",
+ "reserved"),
+ _OMAP4_MUXENTRY(DPM_EMU5, 16, "dpm_emu5", "usba0_ulpiphy_nxt", NULL,
+ "gpio_16", "rfbi_te_vsync0", "dispc2_data16",
+ "hw_dbg5", "reserved"),
+ _OMAP4_MUXENTRY(DPM_EMU6, 17, "dpm_emu6", "usba0_ulpiphy_dat0",
+ "uart3_tx_irtx", "gpio_17", "rfbi_hsync0",
+ "dispc2_data17", "hw_dbg6", "reserved"),
+ _OMAP4_MUXENTRY(DPM_EMU7, 18, "dpm_emu7", "usba0_ulpiphy_dat1",
+ "uart3_rx_irrx", "gpio_18", "rfbi_cs0",
+ "dispc2_hsync", "hw_dbg7", "reserved"),
+ _OMAP4_MUXENTRY(DPM_EMU8, 19, "dpm_emu8", "usba0_ulpiphy_dat2",
+ "uart3_rts_sd", "gpio_19", "rfbi_re", "dispc2_pclk",
+ "hw_dbg8", "reserved"),
+ _OMAP4_MUXENTRY(DPM_EMU9, 20, "dpm_emu9", "usba0_ulpiphy_dat3",
+ "uart3_cts_rctx", "gpio_20", "rfbi_we",
+ "dispc2_vsync", "hw_dbg9", "reserved"),
+ _OMAP4_MUXENTRY(DPM_EMU10, 21, "dpm_emu10", "usba0_ulpiphy_dat4",
+ NULL, "gpio_21", "rfbi_a0", "dispc2_de", "hw_dbg10",
+ "reserved"),
+ _OMAP4_MUXENTRY(DPM_EMU11, 22, "dpm_emu11", "usba0_ulpiphy_dat5",
+ NULL, "gpio_22", "rfbi_data8", "dispc2_data8",
+ "hw_dbg11", "reserved"),
+ _OMAP4_MUXENTRY(DPM_EMU12, 23, "dpm_emu12", "usba0_ulpiphy_dat6",
+ NULL, "gpio_23", "rfbi_data7", "dispc2_data7",
+ "hw_dbg12", "reserved"),
+ _OMAP4_MUXENTRY(DPM_EMU13, 24, "dpm_emu13", "usba0_ulpiphy_dat7",
+ NULL, "gpio_24", "rfbi_data6", "dispc2_data6",
+ "hw_dbg13", "reserved"),
+ _OMAP4_MUXENTRY(DPM_EMU14, 25, "dpm_emu14", "sys_drm_msecure",
+ "uart1_rx", "gpio_25", "rfbi_data5", "dispc2_data5",
+ "hw_dbg14", "reserved"),
+ _OMAP4_MUXENTRY(DPM_EMU15, 26, "dpm_emu15", "sys_secure_indicator",
+ NULL, "gpio_26", "rfbi_data4", "dispc2_data4",
+ "hw_dbg15", "reserved"),
+ _OMAP4_MUXENTRY(DPM_EMU16, 27, "dpm_emu16", "dmtimer8_pwm_evt",
+ "dsi1_te0", "gpio_27", "rfbi_data3", "dispc2_data3",
+ "hw_dbg16", "reserved"),
+ _OMAP4_MUXENTRY(DPM_EMU17, 28, "dpm_emu17", "dmtimer9_pwm_evt",
+ "dsi1_te1", "gpio_28", "rfbi_data2", "dispc2_data2",
+ "hw_dbg17", "reserved"),
+ _OMAP4_MUXENTRY(DPM_EMU18, 190, "dpm_emu18", "dmtimer10_pwm_evt",
+ "dsi2_te0", "gpio_190", "rfbi_data1", "dispc2_data1",
+ "hw_dbg18", "reserved"),
+ _OMAP4_MUXENTRY(DPM_EMU19, 191, "dpm_emu19", "dmtimer11_pwm_evt",
+ "dsi2_te1", "gpio_191", "rfbi_data0", "dispc2_data0",
+ "hw_dbg19", "reserved"),
+ { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+
+/*
+ * Balls for 44XX CBL package
+ * 547-pin CBL ES1.0 S-FPGA-N547, 0.40mm Ball Pitch (Top),
+ * 0.40mm Ball Pitch (Bottom)
+ */
+#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \
+ && defined(CONFIG_OMAP_PACKAGE_CBL)
+struct omap_ball __initdata omap4_core_cbl_ball[] = {
+ _OMAP4_BALLENTRY(GPMC_AD0, "c12", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD1, "d12", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD2, "c13", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD3, "d13", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD4, "c15", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD5, "d15", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD6, "a16", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD7, "b16", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD8, "c16", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD9, "d16", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD10, "c17", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD11, "d17", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD12, "c18", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD13, "d18", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD14, "c19", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD15, "d19", NULL),
+ _OMAP4_BALLENTRY(GPMC_A16, "b17", NULL),
+ _OMAP4_BALLENTRY(GPMC_A17, "a18", NULL),
+ _OMAP4_BALLENTRY(GPMC_A18, "b18", NULL),
+ _OMAP4_BALLENTRY(GPMC_A19, "a19", NULL),
+ _OMAP4_BALLENTRY(GPMC_A20, "b19", NULL),
+ _OMAP4_BALLENTRY(GPMC_A21, "b20", NULL),
+ _OMAP4_BALLENTRY(GPMC_A22, "a21", NULL),
+ _OMAP4_BALLENTRY(GPMC_A23, "b21", NULL),
+ _OMAP4_BALLENTRY(GPMC_A24, "c20", NULL),
+ _OMAP4_BALLENTRY(GPMC_A25, "d20", NULL),
+ _OMAP4_BALLENTRY(GPMC_NCS0, "b25", NULL),
+ _OMAP4_BALLENTRY(GPMC_NCS1, "c21", NULL),
+ _OMAP4_BALLENTRY(GPMC_NCS2, "d21", NULL),
+ _OMAP4_BALLENTRY(GPMC_NCS3, "c22", NULL),
+ _OMAP4_BALLENTRY(GPMC_NWP, "c25", NULL),
+ _OMAP4_BALLENTRY(GPMC_CLK, "b22", NULL),
+ _OMAP4_BALLENTRY(GPMC_NADV_ALE, "d25", NULL),
+ _OMAP4_BALLENTRY(GPMC_NOE, "b11", NULL),
+ _OMAP4_BALLENTRY(GPMC_NWE, "b12", NULL),
+ _OMAP4_BALLENTRY(GPMC_NBE0_CLE, "c23", NULL),
+ _OMAP4_BALLENTRY(GPMC_NBE1, "d22", NULL),
+ _OMAP4_BALLENTRY(GPMC_WAIT0, "b26", NULL),
+ _OMAP4_BALLENTRY(GPMC_WAIT1, "b23", NULL),
+ _OMAP4_BALLENTRY(C2C_DATA11, "d23", NULL),
+ _OMAP4_BALLENTRY(C2C_DATA12, "a24", NULL),
+ _OMAP4_BALLENTRY(C2C_DATA13, "b24", NULL),
+ _OMAP4_BALLENTRY(C2C_DATA14, "c24", NULL),
+ _OMAP4_BALLENTRY(C2C_DATA15, "d24", NULL),
+ _OMAP4_BALLENTRY(HDMI_HPD, "b9", NULL),
+ _OMAP4_BALLENTRY(HDMI_CEC, "b10", NULL),
+ _OMAP4_BALLENTRY(HDMI_DDC_SCL, "a8", NULL),
+ _OMAP4_BALLENTRY(HDMI_DDC_SDA, "b8", NULL),
+ _OMAP4_BALLENTRY(CSI21_DX0, "r26", NULL),
+ _OMAP4_BALLENTRY(CSI21_DY0, "r25", NULL),
+ _OMAP4_BALLENTRY(CSI21_DX1, "t26", NULL),
+ _OMAP4_BALLENTRY(CSI21_DY1, "t25", NULL),
+ _OMAP4_BALLENTRY(CSI21_DX2, "u26", NULL),
+ _OMAP4_BALLENTRY(CSI21_DY2, "u25", NULL),
+ _OMAP4_BALLENTRY(CSI21_DX3, "v26", NULL),
+ _OMAP4_BALLENTRY(CSI21_DY3, "v25", NULL),
+ _OMAP4_BALLENTRY(CSI21_DX4, "w26", NULL),
+ _OMAP4_BALLENTRY(CSI21_DY4, "w25", NULL),
+ _OMAP4_BALLENTRY(CSI22_DX0, "m26", NULL),
+ _OMAP4_BALLENTRY(CSI22_DY0, "m25", NULL),
+ _OMAP4_BALLENTRY(CSI22_DX1, "n26", NULL),
+ _OMAP4_BALLENTRY(CSI22_DY1, "n25", NULL),
+ _OMAP4_BALLENTRY(CAM_SHUTTER, "t27", NULL),
+ _OMAP4_BALLENTRY(CAM_STROBE, "u27", NULL),
+ _OMAP4_BALLENTRY(CAM_GLOBALRESET, "v27", NULL),
+ _OMAP4_BALLENTRY(USBB1_ULPITLL_CLK, "ae18", NULL),
+ _OMAP4_BALLENTRY(USBB1_ULPITLL_STP, "ag19", NULL),
+ _OMAP4_BALLENTRY(USBB1_ULPITLL_DIR, "af19", NULL),
+ _OMAP4_BALLENTRY(USBB1_ULPITLL_NXT, "ae19", NULL),
+ _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT0, "af18", NULL),
+ _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT1, "ag18", NULL),
+ _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT2, "ae17", NULL),
+ _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT3, "af17", NULL),
+ _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT4, "ah17", NULL),
+ _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT5, "ae16", NULL),
+ _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT6, "af16", NULL),
+ _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT7, "ag16", NULL),
+ _OMAP4_BALLENTRY(USBB1_HSIC_DATA, "af14", NULL),
+ _OMAP4_BALLENTRY(USBB1_HSIC_STROBE, "ae14", NULL),
+ _OMAP4_BALLENTRY(USBC1_ICUSB_DP, "h2", NULL),
+ _OMAP4_BALLENTRY(USBC1_ICUSB_DM, "h3", NULL),
+ _OMAP4_BALLENTRY(SDMMC1_CLK, "d2", NULL),
+ _OMAP4_BALLENTRY(SDMMC1_CMD, "e3", NULL),
+ _OMAP4_BALLENTRY(SDMMC1_DAT0, "e4", NULL),
+ _OMAP4_BALLENTRY(SDMMC1_DAT1, "e2", NULL),
+ _OMAP4_BALLENTRY(SDMMC1_DAT2, "e1", NULL),
+ _OMAP4_BALLENTRY(SDMMC1_DAT3, "f4", NULL),
+ _OMAP4_BALLENTRY(SDMMC1_DAT4, "f3", NULL),
+ _OMAP4_BALLENTRY(SDMMC1_DAT5, "f1", NULL),
+ _OMAP4_BALLENTRY(SDMMC1_DAT6, "g4", NULL),
+ _OMAP4_BALLENTRY(SDMMC1_DAT7, "g3", NULL),
+ _OMAP4_BALLENTRY(ABE_MCBSP2_CLKX, "ad27", NULL),
+ _OMAP4_BALLENTRY(ABE_MCBSP2_DR, "ad26", NULL),
+ _OMAP4_BALLENTRY(ABE_MCBSP2_DX, "ad25", NULL),
+ _OMAP4_BALLENTRY(ABE_MCBSP2_FSX, "ac28", NULL),
+ _OMAP4_BALLENTRY(ABE_MCBSP1_CLKX, "ac26", NULL),
+ _OMAP4_BALLENTRY(ABE_MCBSP1_DR, "ac25", NULL),
+ _OMAP4_BALLENTRY(ABE_MCBSP1_DX, "ab25", NULL),
+ _OMAP4_BALLENTRY(ABE_MCBSP1_FSX, "ac27", NULL),
+ _OMAP4_BALLENTRY(ABE_PDM_UL_DATA, "ag25", NULL),
+ _OMAP4_BALLENTRY(ABE_PDM_DL_DATA, "af25", NULL),
+ _OMAP4_BALLENTRY(ABE_PDM_FRAME, "ae25", NULL),
+ _OMAP4_BALLENTRY(ABE_PDM_LB_CLK, "af26", NULL),
+ _OMAP4_BALLENTRY(ABE_CLKS, "ah26", NULL),
+ _OMAP4_BALLENTRY(ABE_DMIC_CLK1, "ae24", NULL),
+ _OMAP4_BALLENTRY(ABE_DMIC_DIN1, "af24", NULL),
+ _OMAP4_BALLENTRY(ABE_DMIC_DIN2, "ag24", NULL),
+ _OMAP4_BALLENTRY(ABE_DMIC_DIN3, "ah24", NULL),
+ _OMAP4_BALLENTRY(UART2_CTS, "ab26", NULL),
+ _OMAP4_BALLENTRY(UART2_RTS, "ab27", NULL),
+ _OMAP4_BALLENTRY(UART2_RX, "aa25", NULL),
+ _OMAP4_BALLENTRY(UART2_TX, "aa26", NULL),
+ _OMAP4_BALLENTRY(HDQ_SIO, "aa27", NULL),
+ _OMAP4_BALLENTRY(I2C1_SCL, "ae28", NULL),
+ _OMAP4_BALLENTRY(I2C1_SDA, "ae26", NULL),
+ _OMAP4_BALLENTRY(I2C2_SCL, "c26", NULL),
+ _OMAP4_BALLENTRY(I2C2_SDA, "d26", NULL),
+ _OMAP4_BALLENTRY(I2C3_SCL, "w27", NULL),
+ _OMAP4_BALLENTRY(I2C3_SDA, "y27", NULL),
+ _OMAP4_BALLENTRY(I2C4_SCL, "ag21", NULL),
+ _OMAP4_BALLENTRY(I2C4_SDA, "ah22", NULL),
+ _OMAP4_BALLENTRY(MCSPI1_CLK, "af22", NULL),
+ _OMAP4_BALLENTRY(MCSPI1_SOMI, "ae22", NULL),
+ _OMAP4_BALLENTRY(MCSPI1_SIMO, "ag22", NULL),
+ _OMAP4_BALLENTRY(MCSPI1_CS0, "ae23", NULL),
+ _OMAP4_BALLENTRY(MCSPI1_CS1, "af23", NULL),
+ _OMAP4_BALLENTRY(MCSPI1_CS2, "ag23", NULL),
+ _OMAP4_BALLENTRY(MCSPI1_CS3, "ah23", NULL),
+ _OMAP4_BALLENTRY(UART3_CTS_RCTX, "f27", NULL),
+ _OMAP4_BALLENTRY(UART3_RTS_SD, "f28", NULL),
+ _OMAP4_BALLENTRY(UART3_RX_IRRX, "g27", NULL),
+ _OMAP4_BALLENTRY(UART3_TX_IRTX, "g28", NULL),
+ _OMAP4_BALLENTRY(SDMMC5_CLK, "ae5", NULL),
+ _OMAP4_BALLENTRY(SDMMC5_CMD, "af5", NULL),
+ _OMAP4_BALLENTRY(SDMMC5_DAT0, "ae4", NULL),
+ _OMAP4_BALLENTRY(SDMMC5_DAT1, "af4", NULL),
+ _OMAP4_BALLENTRY(SDMMC5_DAT2, "ag3", NULL),
+ _OMAP4_BALLENTRY(SDMMC5_DAT3, "af3", NULL),
+ _OMAP4_BALLENTRY(MCSPI4_CLK, "ae21", NULL),
+ _OMAP4_BALLENTRY(MCSPI4_SIMO, "af20", NULL),
+ _OMAP4_BALLENTRY(MCSPI4_SOMI, "af21", NULL),
+ _OMAP4_BALLENTRY(MCSPI4_CS0, "ae20", NULL),
+ _OMAP4_BALLENTRY(UART4_RX, "ag20", NULL),
+ _OMAP4_BALLENTRY(UART4_TX, "ah19", NULL),
+ _OMAP4_BALLENTRY(USBB2_ULPITLL_CLK, "ag12", NULL),
+ _OMAP4_BALLENTRY(USBB2_ULPITLL_STP, "af12", NULL),
+ _OMAP4_BALLENTRY(USBB2_ULPITLL_DIR, "ae12", NULL),
+ _OMAP4_BALLENTRY(USBB2_ULPITLL_NXT, "ag13", NULL),
+ _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT0, "ae11", NULL),
+ _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT1, "af11", NULL),
+ _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT2, "ag11", NULL),
+ _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT3, "ah11", NULL),
+ _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT4, "ae10", NULL),
+ _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT5, "af10", NULL),
+ _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT6, "ag10", NULL),
+ _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT7, "ae9", NULL),
+ _OMAP4_BALLENTRY(USBB2_HSIC_DATA, "af13", NULL),
+ _OMAP4_BALLENTRY(USBB2_HSIC_STROBE, "ae13", NULL),
+ _OMAP4_BALLENTRY(UNIPRO_TX0, "g26", NULL),
+ _OMAP4_BALLENTRY(UNIPRO_TY0, "g25", NULL),
+ _OMAP4_BALLENTRY(UNIPRO_TX1, "h26", NULL),
+ _OMAP4_BALLENTRY(UNIPRO_TY1, "h25", NULL),
+ _OMAP4_BALLENTRY(UNIPRO_TX2, "j27", NULL),
+ _OMAP4_BALLENTRY(UNIPRO_TY2, "h27", NULL),
+ _OMAP4_BALLENTRY(UNIPRO_RX0, "j26", NULL),
+ _OMAP4_BALLENTRY(UNIPRO_RY0, "j25", NULL),
+ _OMAP4_BALLENTRY(UNIPRO_RX1, "k26", NULL),
+ _OMAP4_BALLENTRY(UNIPRO_RY1, "k25", NULL),
+ _OMAP4_BALLENTRY(UNIPRO_RX2, "l27", NULL),
+ _OMAP4_BALLENTRY(UNIPRO_RY2, "k27", NULL),
+ _OMAP4_BALLENTRY(USBA0_OTG_CE, "c3", NULL),
+ _OMAP4_BALLENTRY(USBA0_OTG_DP, "b5", NULL),
+ _OMAP4_BALLENTRY(USBA0_OTG_DM, "b4", NULL),
+ _OMAP4_BALLENTRY(FREF_CLK1_OUT, "aa28", NULL),
+ _OMAP4_BALLENTRY(FREF_CLK2_OUT, "y28", NULL),
+ _OMAP4_BALLENTRY(SYS_NIRQ1, "ae6", NULL),
+ _OMAP4_BALLENTRY(SYS_NIRQ2, "af6", NULL),
+ _OMAP4_BALLENTRY(SYS_BOOT0, "f26", NULL),
+ _OMAP4_BALLENTRY(SYS_BOOT1, "e27", NULL),
+ _OMAP4_BALLENTRY(SYS_BOOT2, "e26", NULL),
+ _OMAP4_BALLENTRY(SYS_BOOT3, "e25", NULL),
+ _OMAP4_BALLENTRY(SYS_BOOT4, "d28", NULL),
+ _OMAP4_BALLENTRY(SYS_BOOT5, "d27", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU0, "m2", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU1, "n2", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU2, "p2", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU3, "v1", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU4, "v2", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU5, "w1", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU6, "w2", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU7, "w3", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU8, "w4", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU9, "y2", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU10, "y3", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU11, "y4", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU12, "aa1", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU13, "aa2", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU14, "aa3", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU15, "aa4", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU16, "ab2", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU17, "ab3", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU18, "ab4", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU19, "ac4", NULL),
+ { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define omap4_core_cbl_ball NULL
+#endif
+
+/*
+ * Superset of all mux modes for omap4
+ */
+static struct omap_mux __initdata omap4_wkup_muxmodes[] = {
+ _OMAP4_MUXENTRY(SIM_IO, 0, "sim_io", NULL, NULL, "gpio_wk0", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SIM_CLK, 1, "sim_clk", NULL, NULL, "gpio_wk1", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SIM_RESET, 2, "sim_reset", NULL, NULL, "gpio_wk2",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SIM_CD, 3, "sim_cd", NULL, NULL, "gpio_wk3", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SIM_PWRCTRL, 4, "sim_pwrctrl", NULL, NULL, "gpio_wk4",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SR_SCL, 0, "sr_scl", NULL, NULL, NULL, NULL, NULL,
+ NULL, NULL),
+ _OMAP4_MUXENTRY(SR_SDA, 0, "sr_sda", NULL, NULL, NULL, NULL, NULL,
+ NULL, NULL),
+ _OMAP4_MUXENTRY(FREF_XTAL_IN, 0, "fref_xtal_in", NULL, NULL, NULL,
+ "c2c_wakereqin", NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(FREF_SLICER_IN, 0, "fref_slicer_in", NULL, NULL,
+ "gpi_wk5", "c2c_wakereqin", NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(FREF_CLK_IOREQ, 0, "fref_clk_ioreq", NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(FREF_CLK0_OUT, 6, "fref_clk0_out", "fref_clk1_req",
+ "sys_drm_msecure", "gpio_wk6", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(FREF_CLK3_REQ, 30, "fref_clk3_req", "fref_clk1_req",
+ "sys_drm_msecure", "gpio_wk30", "c2c_wakereqin", NULL,
+ NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(FREF_CLK3_OUT, 31, "fref_clk3_out", "fref_clk2_req",
+ "sys_secure_indicator", "gpio_wk31", "c2c_wakereqout",
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(FREF_CLK4_REQ, 7, "fref_clk4_req", "fref_clk5_out",
+ NULL, "gpio_wk7", NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(FREF_CLK4_OUT, 8, "fref_clk4_out", NULL, NULL,
+ "gpio_wk8", NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(SYS_32K, 0, "sys_32k", NULL, NULL, NULL, NULL, NULL,
+ NULL, NULL),
+ _OMAP4_MUXENTRY(SYS_NRESPWRON, 0, "sys_nrespwron", NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(SYS_NRESWARM, 0, "sys_nreswarm", NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(SYS_PWR_REQ, 0, "sys_pwr_req", NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(SYS_PWRON_RESET_OUT, 29, "sys_pwron_reset_out", NULL,
+ NULL, "gpio_wk29", NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(SYS_BOOT6, 9, "sys_boot6", "dpm_emu18", NULL,
+ "gpio_wk9", "c2c_wakereqout", NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(SYS_BOOT7, 10, "sys_boot7", "dpm_emu19", NULL,
+ "gpio_wk10", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(JTAG_NTRST, 0, "jtag_ntrst", NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(JTAG_TCK, 0, "jtag_tck", NULL, NULL, NULL, NULL, NULL,
+ NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(JTAG_RTCK, 0, "jtag_rtck", NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(JTAG_TMS_TMSC, 0, "jtag_tms_tmsc", NULL, NULL, NULL,
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(JTAG_TDI, 0, "jtag_tdi", NULL, NULL, NULL, NULL, NULL,
+ NULL, NULL),
+ _OMAP4_MUXENTRY(JTAG_TDO, 0, "jtag_tdo", NULL, NULL, NULL, NULL, NULL,
+ NULL, NULL),
+ { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+
+/*
+ * Balls for 44XX CBL package
+ * 547-pin CBL ES1.0 S-FPGA-N547, 0.40mm Ball Pitch (Top),
+ * 0.40mm Ball Pitch (Bottom)
+ */
+#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \
+ && defined(CONFIG_OMAP_PACKAGE_CBL)
+struct omap_ball __initdata omap4_wkup_cbl_ball[] = {
+ _OMAP4_BALLENTRY(SIM_IO, "h4", NULL),
+ _OMAP4_BALLENTRY(SIM_CLK, "j2", NULL),
+ _OMAP4_BALLENTRY(SIM_RESET, "g2", NULL),
+ _OMAP4_BALLENTRY(SIM_CD, "j1", NULL),
+ _OMAP4_BALLENTRY(SIM_PWRCTRL, "k1", NULL),
+ _OMAP4_BALLENTRY(SR_SCL, "ag9", NULL),
+ _OMAP4_BALLENTRY(SR_SDA, "af9", NULL),
+ _OMAP4_BALLENTRY(FREF_XTAL_IN, "ah6", NULL),
+ _OMAP4_BALLENTRY(FREF_SLICER_IN, "ag8", NULL),
+ _OMAP4_BALLENTRY(FREF_CLK_IOREQ, "ad1", NULL),
+ _OMAP4_BALLENTRY(FREF_CLK0_OUT, "ad2", NULL),
+ _OMAP4_BALLENTRY(FREF_CLK3_REQ, "ad3", NULL),
+ _OMAP4_BALLENTRY(FREF_CLK3_OUT, "ad4", NULL),
+ _OMAP4_BALLENTRY(FREF_CLK4_REQ, "ac2", NULL),
+ _OMAP4_BALLENTRY(FREF_CLK4_OUT, "ac3", NULL),
+ _OMAP4_BALLENTRY(SYS_32K, "ag7", NULL),
+ _OMAP4_BALLENTRY(SYS_NRESPWRON, "ae7", NULL),
+ _OMAP4_BALLENTRY(SYS_NRESWARM, "af7", NULL),
+ _OMAP4_BALLENTRY(SYS_PWR_REQ, "ah7", NULL),
+ _OMAP4_BALLENTRY(SYS_PWRON_RESET_OUT, "ag6", NULL),
+ _OMAP4_BALLENTRY(SYS_BOOT6, "af8", NULL),
+ _OMAP4_BALLENTRY(SYS_BOOT7, "ae8", NULL),
+ _OMAP4_BALLENTRY(JTAG_NTRST, "ah2", NULL),
+ _OMAP4_BALLENTRY(JTAG_TCK, "ag1", NULL),
+ _OMAP4_BALLENTRY(JTAG_RTCK, "ae3", NULL),
+ _OMAP4_BALLENTRY(JTAG_TMS_TMSC, "ah1", NULL),
+ _OMAP4_BALLENTRY(JTAG_TDI, "ae1", NULL),
+ _OMAP4_BALLENTRY(JTAG_TDO, "ae2", NULL),
+ { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define omap4_wkup_cbl_ball NULL
+#endif
+
+
+int __init omap4_mux_init(struct omap_board_mux *board_subset, int flags)
+{
+ struct omap_ball *package_balls_core, *package_balls_wkup;
+ int ret;
+
+ switch (flags & OMAP_PACKAGE_MASK) {
+ case OMAP_PACKAGE_CBL:
+ package_balls_core = omap4_core_cbl_ball;
+ package_balls_wkup = omap4_wkup_cbl_ball;
+ break;
+ default:
+ pr_err("mux: Unknown omap package, mux disabled\n");
+ return -EINVAL;
+ }
+
+ ret = omap_mux_init("core",
+ OMAP_MUX_GPIO_IN_MODE3,
+ OMAP4_CTRL_MODULE_PAD_CORE_MUX_PBASE,
+ OMAP4_CTRL_MODULE_PAD_CORE_MUX_SIZE,
+ omap4_core_muxmodes, NULL, board_subset,
+ package_balls_core);
+ if (ret)
+ return ret;
+
+ ret = omap_mux_init("wkup",
+ OMAP_MUX_GPIO_IN_MODE3,
+ OMAP4_CTRL_MODULE_PAD_WKUP_MUX_PBASE,
+ OMAP4_CTRL_MODULE_PAD_WKUP_MUX_SIZE,
+ omap4_wkup_muxmodes, NULL, board_subset,
+ package_balls_wkup);
+
+ return ret;
+}
+
diff --git a/arch/arm/mach-omap2/mux44xx.h b/arch/arm/mach-omap2/mux44xx.h
new file mode 100644
index 0000000..ea8b235
--- /dev/null
+++ b/arch/arm/mach-omap2/mux44xx.h
@@ -0,0 +1,277 @@
+/*
+ * OMAP44xx MUX registers and bitfields
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ *
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_MUX_44XX_H
+#define __ARCH_ARM_MACH_OMAP2_MUX_44XX_H
+
+#define OMAP4_MUX(M0, mux_value) \
+{ \
+ .reg_offset = (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET), \
+ .value = (mux_value), \
+}
+
+/* ctrl_module_pad_core base address */
+#define OMAP4_CTRL_MODULE_PAD_CORE_MUX_PBASE 0x4a100000
+
+/* ctrl_module_pad_core registers offset */
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD0_OFFSET 0x0040
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD1_OFFSET 0x0042
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD2_OFFSET 0x0044
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD3_OFFSET 0x0046
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD4_OFFSET 0x0048
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD5_OFFSET 0x004a
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD6_OFFSET 0x004c
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD7_OFFSET 0x004e
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD8_OFFSET 0x0050
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD9_OFFSET 0x0052
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD10_OFFSET 0x0054
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD11_OFFSET 0x0056
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD12_OFFSET 0x0058
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD13_OFFSET 0x005a
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD14_OFFSET 0x005c
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD15_OFFSET 0x005e
+#define OMAP4_CTRL_MODULE_PAD_GPMC_A16_OFFSET 0x0060
+#define OMAP4_CTRL_MODULE_PAD_GPMC_A17_OFFSET 0x0062
+#define OMAP4_CTRL_MODULE_PAD_GPMC_A18_OFFSET 0x0064
+#define OMAP4_CTRL_MODULE_PAD_GPMC_A19_OFFSET 0x0066
+#define OMAP4_CTRL_MODULE_PAD_GPMC_A20_OFFSET 0x0068
+#define OMAP4_CTRL_MODULE_PAD_GPMC_A21_OFFSET 0x006a
+#define OMAP4_CTRL_MODULE_PAD_GPMC_A22_OFFSET 0x006c
+#define OMAP4_CTRL_MODULE_PAD_GPMC_A23_OFFSET 0x006e
+#define OMAP4_CTRL_MODULE_PAD_GPMC_A24_OFFSET 0x0070
+#define OMAP4_CTRL_MODULE_PAD_GPMC_A25_OFFSET 0x0072
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS0_OFFSET 0x0074
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS1_OFFSET 0x0076
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS2_OFFSET 0x0078
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS3_OFFSET 0x007a
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NWP_OFFSET 0x007c
+#define OMAP4_CTRL_MODULE_PAD_GPMC_CLK_OFFSET 0x007e
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NADV_ALE_OFFSET 0x0080
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NOE_OFFSET 0x0082
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NWE_OFFSET 0x0084
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NBE0_CLE_OFFSET 0x0086
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NBE1_OFFSET 0x0088
+#define OMAP4_CTRL_MODULE_PAD_GPMC_WAIT0_OFFSET 0x008a
+#define OMAP4_CTRL_MODULE_PAD_GPMC_WAIT1_OFFSET 0x008c
+#define OMAP4_CTRL_MODULE_PAD_C2C_DATA11_OFFSET 0x008e
+#define OMAP4_CTRL_MODULE_PAD_C2C_DATA12_OFFSET 0x0090
+#define OMAP4_CTRL_MODULE_PAD_C2C_DATA13_OFFSET 0x0092
+#define OMAP4_CTRL_MODULE_PAD_C2C_DATA14_OFFSET 0x0094
+#define OMAP4_CTRL_MODULE_PAD_C2C_DATA15_OFFSET 0x0096
+#define OMAP4_CTRL_MODULE_PAD_HDMI_HPD_OFFSET 0x0098
+#define OMAP4_CTRL_MODULE_PAD_HDMI_CEC_OFFSET 0x009a
+#define OMAP4_CTRL_MODULE_PAD_HDMI_DDC_SCL_OFFSET 0x009c
+#define OMAP4_CTRL_MODULE_PAD_HDMI_DDC_SDA_OFFSET 0x009e
+#define OMAP4_CTRL_MODULE_PAD_CSI21_DX0_OFFSET 0x00a0
+#define OMAP4_CTRL_MODULE_PAD_CSI21_DY0_OFFSET 0x00a2
+#define OMAP4_CTRL_MODULE_PAD_CSI21_DX1_OFFSET 0x00a4
+#define OMAP4_CTRL_MODULE_PAD_CSI21_DY1_OFFSET 0x00a6
+#define OMAP4_CTRL_MODULE_PAD_CSI21_DX2_OFFSET 0x00a8
+#define OMAP4_CTRL_MODULE_PAD_CSI21_DY2_OFFSET 0x00aa
+#define OMAP4_CTRL_MODULE_PAD_CSI21_DX3_OFFSET 0x00ac
+#define OMAP4_CTRL_MODULE_PAD_CSI21_DY3_OFFSET 0x00ae
+#define OMAP4_CTRL_MODULE_PAD_CSI21_DX4_OFFSET 0x00b0
+#define OMAP4_CTRL_MODULE_PAD_CSI21_DY4_OFFSET 0x00b2
+#define OMAP4_CTRL_MODULE_PAD_CSI22_DX0_OFFSET 0x00b4
+#define OMAP4_CTRL_MODULE_PAD_CSI22_DY0_OFFSET 0x00b6
+#define OMAP4_CTRL_MODULE_PAD_CSI22_DX1_OFFSET 0x00b8
+#define OMAP4_CTRL_MODULE_PAD_CSI22_DY1_OFFSET 0x00ba
+#define OMAP4_CTRL_MODULE_PAD_CAM_SHUTTER_OFFSET 0x00bc
+#define OMAP4_CTRL_MODULE_PAD_CAM_STROBE_OFFSET 0x00be
+#define OMAP4_CTRL_MODULE_PAD_CAM_GLOBALRESET_OFFSET 0x00c0
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_CLK_OFFSET 0x00c2
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_STP_OFFSET 0x00c4
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DIR_OFFSET 0x00c6
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_NXT_OFFSET 0x00c8
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT0_OFFSET 0x00ca
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT1_OFFSET 0x00cc
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT2_OFFSET 0x00ce
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT3_OFFSET 0x00d0
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT4_OFFSET 0x00d2
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT5_OFFSET 0x00d4
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT6_OFFSET 0x00d6
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT7_OFFSET 0x00d8
+#define OMAP4_CTRL_MODULE_PAD_USBB1_HSIC_DATA_OFFSET 0x00da
+#define OMAP4_CTRL_MODULE_PAD_USBB1_HSIC_STROBE_OFFSET 0x00dc
+#define OMAP4_CTRL_MODULE_PAD_USBC1_ICUSB_DP_OFFSET 0x00de
+#define OMAP4_CTRL_MODULE_PAD_USBC1_ICUSB_DM_OFFSET 0x00e0
+#define OMAP4_CTRL_MODULE_PAD_SDMMC1_CLK_OFFSET 0x00e2
+#define OMAP4_CTRL_MODULE_PAD_SDMMC1_CMD_OFFSET 0x00e4
+#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT0_OFFSET 0x00e6
+#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT1_OFFSET 0x00e8
+#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT2_OFFSET 0x00ea
+#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT3_OFFSET 0x00ec
+#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT4_OFFSET 0x00ee
+#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT5_OFFSET 0x00f0
+#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT6_OFFSET 0x00f2
+#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT7_OFFSET 0x00f4
+#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_CLKX_OFFSET 0x00f6
+#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_DR_OFFSET 0x00f8
+#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_DX_OFFSET 0x00fa
+#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_FSX_OFFSET 0x00fc
+#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_CLKX_OFFSET 0x00fe
+#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_DR_OFFSET 0x0100
+#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_DX_OFFSET 0x0102
+#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_FSX_OFFSET 0x0104
+#define OMAP4_CTRL_MODULE_PAD_ABE_PDM_UL_DATA_OFFSET 0x0106
+#define OMAP4_CTRL_MODULE_PAD_ABE_PDM_DL_DATA_OFFSET 0x0108
+#define OMAP4_CTRL_MODULE_PAD_ABE_PDM_FRAME_OFFSET 0x010a
+#define OMAP4_CTRL_MODULE_PAD_ABE_PDM_LB_CLK_OFFSET 0x010c
+#define OMAP4_CTRL_MODULE_PAD_ABE_CLKS_OFFSET 0x010e
+#define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_CLK1_OFFSET 0x0110
+#define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_DIN1_OFFSET 0x0112
+#define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_DIN2_OFFSET 0x0114
+#define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_DIN3_OFFSET 0x0116
+#define OMAP4_CTRL_MODULE_PAD_UART2_CTS_OFFSET 0x0118
+#define OMAP4_CTRL_MODULE_PAD_UART2_RTS_OFFSET 0x011a
+#define OMAP4_CTRL_MODULE_PAD_UART2_RX_OFFSET 0x011c
+#define OMAP4_CTRL_MODULE_PAD_UART2_TX_OFFSET 0x011e
+#define OMAP4_CTRL_MODULE_PAD_HDQ_SIO_OFFSET 0x0120
+#define OMAP4_CTRL_MODULE_PAD_I2C1_SCL_OFFSET 0x0122
+#define OMAP4_CTRL_MODULE_PAD_I2C1_SDA_OFFSET 0x0124
+#define OMAP4_CTRL_MODULE_PAD_I2C2_SCL_OFFSET 0x0126
+#define OMAP4_CTRL_MODULE_PAD_I2C2_SDA_OFFSET 0x0128
+#define OMAP4_CTRL_MODULE_PAD_I2C3_SCL_OFFSET 0x012a
+#define OMAP4_CTRL_MODULE_PAD_I2C3_SDA_OFFSET 0x012c
+#define OMAP4_CTRL_MODULE_PAD_I2C4_SCL_OFFSET 0x012e
+#define OMAP4_CTRL_MODULE_PAD_I2C4_SDA_OFFSET 0x0130
+#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CLK_OFFSET 0x0132
+#define OMAP4_CTRL_MODULE_PAD_MCSPI1_SOMI_OFFSET 0x0134
+#define OMAP4_CTRL_MODULE_PAD_MCSPI1_SIMO_OFFSET 0x0136
+#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS0_OFFSET 0x0138
+#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS1_OFFSET 0x013a
+#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS2_OFFSET 0x013c
+#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS3_OFFSET 0x013e
+#define OMAP4_CTRL_MODULE_PAD_UART3_CTS_RCTX_OFFSET 0x0140
+#define OMAP4_CTRL_MODULE_PAD_UART3_RTS_SD_OFFSET 0x0142
+#define OMAP4_CTRL_MODULE_PAD_UART3_RX_IRRX_OFFSET 0x0144
+#define OMAP4_CTRL_MODULE_PAD_UART3_TX_IRTX_OFFSET 0x0146
+#define OMAP4_CTRL_MODULE_PAD_SDMMC5_CLK_OFFSET 0x0148
+#define OMAP4_CTRL_MODULE_PAD_SDMMC5_CMD_OFFSET 0x014a
+#define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT0_OFFSET 0x014c
+#define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT1_OFFSET 0x014e
+#define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT2_OFFSET 0x0150
+#define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT3_OFFSET 0x0152
+#define OMAP4_CTRL_MODULE_PAD_MCSPI4_CLK_OFFSET 0x0154
+#define OMAP4_CTRL_MODULE_PAD_MCSPI4_SIMO_OFFSET 0x0156
+#define OMAP4_CTRL_MODULE_PAD_MCSPI4_SOMI_OFFSET 0x0158
+#define OMAP4_CTRL_MODULE_PAD_MCSPI4_CS0_OFFSET 0x015a
+#define OMAP4_CTRL_MODULE_PAD_UART4_RX_OFFSET 0x015c
+#define OMAP4_CTRL_MODULE_PAD_UART4_TX_OFFSET 0x015e
+#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_CLK_OFFSET 0x0160
+#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_STP_OFFSET 0x0162
+#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DIR_OFFSET 0x0164
+#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_NXT_OFFSET 0x0166
+#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT0_OFFSET 0x0168
+#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT1_OFFSET 0x016a
+#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT2_OFFSET 0x016c
+#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT3_OFFSET 0x016e
+#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT4_OFFSET 0x0170
+#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT5_OFFSET 0x0172
+#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT6_OFFSET 0x0174
+#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT7_OFFSET 0x0176
+#define OMAP4_CTRL_MODULE_PAD_USBB2_HSIC_DATA_OFFSET 0x0178
+#define OMAP4_CTRL_MODULE_PAD_USBB2_HSIC_STROBE_OFFSET 0x017a
+#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TX0_OFFSET 0x017c
+#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TY0_OFFSET 0x017e
+#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TX1_OFFSET 0x0180
+#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TY1_OFFSET 0x0182
+#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TX2_OFFSET 0x0184
+#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TY2_OFFSET 0x0186
+#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RX0_OFFSET 0x0188
+#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RY0_OFFSET 0x018a
+#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RX1_OFFSET 0x018c
+#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RY1_OFFSET 0x018e
+#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RX2_OFFSET 0x0190
+#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RY2_OFFSET 0x0192
+#define OMAP4_CTRL_MODULE_PAD_USBA0_OTG_CE_OFFSET 0x0194
+#define OMAP4_CTRL_MODULE_PAD_USBA0_OTG_DP_OFFSET 0x0196
+#define OMAP4_CTRL_MODULE_PAD_USBA0_OTG_DM_OFFSET 0x0198
+#define OMAP4_CTRL_MODULE_PAD_FREF_CLK1_OUT_OFFSET 0x019a
+#define OMAP4_CTRL_MODULE_PAD_FREF_CLK2_OUT_OFFSET 0x019c
+#define OMAP4_CTRL_MODULE_PAD_SYS_NIRQ1_OFFSET 0x019e
+#define OMAP4_CTRL_MODULE_PAD_SYS_NIRQ2_OFFSET 0x01a0
+#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT0_OFFSET 0x01a2
+#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT1_OFFSET 0x01a4
+#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT2_OFFSET 0x01a6
+#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT3_OFFSET 0x01a8
+#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT4_OFFSET 0x01aa
+#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT5_OFFSET 0x01ac
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU0_OFFSET 0x01ae
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU1_OFFSET 0x01b0
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU2_OFFSET 0x01b2
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU3_OFFSET 0x01b4
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU4_OFFSET 0x01b6
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU5_OFFSET 0x01b8
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU6_OFFSET 0x01ba
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU7_OFFSET 0x01bc
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU8_OFFSET 0x01be
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU9_OFFSET 0x01c0
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU10_OFFSET 0x01c2
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU11_OFFSET 0x01c4
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU12_OFFSET 0x01c6
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU13_OFFSET 0x01c8
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU14_OFFSET 0x01ca
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU15_OFFSET 0x01cc
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU16_OFFSET 0x01ce
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU17_OFFSET 0x01d0
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU18_OFFSET 0x01d2
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU19_OFFSET 0x01d4
+
+#define OMAP4_CTRL_MODULE_PAD_CORE_MUX_SIZE \
+ (OMAP4_CTRL_MODULE_PAD_DPM_EMU19_OFFSET \
+ - OMAP4_CTRL_MODULE_PAD_GPMC_AD0_OFFSET + 2)
+
+/* ctrl_module_pad_wkup base address */
+#define OMAP4_CTRL_MODULE_PAD_WKUP_MUX_PBASE 0x4a31e000
+
+/* ctrl_module_pad_wkup registers offset */
+#define OMAP4_CTRL_MODULE_PAD_SIM_IO_OFFSET 0x0040
+#define OMAP4_CTRL_MODULE_PAD_SIM_CLK_OFFSET 0x0042
+#define OMAP4_CTRL_MODULE_PAD_SIM_RESET_OFFSET 0x0044
+#define OMAP4_CTRL_MODULE_PAD_SIM_CD_OFFSET 0x0046
+#define OMAP4_CTRL_MODULE_PAD_SIM_PWRCTRL_OFFSET 0x0048
+#define OMAP4_CTRL_MODULE_PAD_SR_SCL_OFFSET 0x004a
+#define OMAP4_CTRL_MODULE_PAD_SR_SDA_OFFSET 0x004c
+#define OMAP4_CTRL_MODULE_PAD_FREF_XTAL_IN_OFFSET 0x004e
+#define OMAP4_CTRL_MODULE_PAD_FREF_SLICER_IN_OFFSET 0x0050
+#define OMAP4_CTRL_MODULE_PAD_FREF_CLK_IOREQ_OFFSET 0x0052
+#define OMAP4_CTRL_MODULE_PAD_FREF_CLK0_OUT_OFFSET 0x0054
+#define OMAP4_CTRL_MODULE_PAD_FREF_CLK3_REQ_OFFSET 0x0056
+#define OMAP4_CTRL_MODULE_PAD_FREF_CLK3_OUT_OFFSET 0x0058
+#define OMAP4_CTRL_MODULE_PAD_FREF_CLK4_REQ_OFFSET 0x005a
+#define OMAP4_CTRL_MODULE_PAD_FREF_CLK4_OUT_OFFSET 0x005c
+#define OMAP4_CTRL_MODULE_PAD_SYS_32K_OFFSET 0x005e
+#define OMAP4_CTRL_MODULE_PAD_SYS_NRESPWRON_OFFSET 0x0060
+#define OMAP4_CTRL_MODULE_PAD_SYS_NRESWARM_OFFSET 0x0062
+#define OMAP4_CTRL_MODULE_PAD_SYS_PWR_REQ_OFFSET 0x0064
+#define OMAP4_CTRL_MODULE_PAD_SYS_PWRON_RESET_OUT_OFFSET 0x0066
+#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT6_OFFSET 0x0068
+#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT7_OFFSET 0x006a
+#define OMAP4_CTRL_MODULE_PAD_JTAG_NTRST_OFFSET 0x006c
+#define OMAP4_CTRL_MODULE_PAD_JTAG_TCK_OFFSET 0x006e
+#define OMAP4_CTRL_MODULE_PAD_JTAG_RTCK_OFFSET 0x0070
+#define OMAP4_CTRL_MODULE_PAD_JTAG_TMS_TMSC_OFFSET 0x0072
+#define OMAP4_CTRL_MODULE_PAD_JTAG_TDI_OFFSET 0x0074
+#define OMAP4_CTRL_MODULE_PAD_JTAG_TDO_OFFSET 0x0076
+
+#define OMAP4_CTRL_MODULE_PAD_WKUP_MUX_SIZE \
+ (OMAP4_CTRL_MODULE_PAD_JTAG_TDO_OFFSET \
+ - OMAP4_CTRL_MODULE_PAD_SIM_IO_OFFSET + 2)
+
+#endif
--
1.7.0.4
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 4/7] OMAP4: sdp4430: Select CBL package for ES1 and initialize mux
2010-11-11 21:35 [PATCH 0/7] OMAP4: mux: Add the OMAP4430 ES1.0 & ES2.x support Benoit Cousson
` (2 preceding siblings ...)
2010-11-11 21:35 ` [PATCH 3/7] OMAP4: mux: Add CBL package data for OMAP4430 ES1 Benoit Cousson
@ 2010-11-11 21:35 ` Benoit Cousson
2010-11-11 21:35 ` [PATCH 5/7] OMAP4: mux: Add CBS package data for OMAP4430 ES2 Benoit Cousson
` (2 subsequent siblings)
6 siblings, 0 replies; 14+ messages in thread
From: Benoit Cousson @ 2010-11-11 21:35 UTC (permalink / raw)
To: tony; +Cc: linux-omap, Benoit Cousson, Paul Walmsley, Kevin Hilman
Select the CBL package if SDP4430 is enabled during config.
Initialize the mux framework during the board init.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
---
arch/arm/mach-omap2/Kconfig | 1 +
arch/arm/mach-omap2/board-4430sdp.c | 10 ++++++++++
2 files changed, 11 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index e14c73d..7efb256 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -280,6 +280,7 @@ config MACH_OMAP_4430SDP
bool "OMAP 4430 SDP board"
default y
depends on ARCH_OMAP4
+ select OMAP_PACKAGE_CBL
config MACH_OMAP4_PANDA
bool "OMAP4 Panda Board"
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index df5a425..e4f1726 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -35,6 +35,7 @@
#include <plat/usb.h>
#include <plat/mmc.h>
+#include "mux.h"
#include "hsmmc.h"
#include "timer-gp.h"
#include "control.h"
@@ -505,10 +506,19 @@ static void __init omap_sfh7741prox_init(void)
}
}
+#ifdef CONFIG_OMAP_MUX
+static struct omap_board_mux board_mux[] __initdata = {
+ { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define board_mux NULL
+#endif
+
static void __init omap_4430sdp_init(void)
{
int status;
+ omap4_mux_init(board_mux, OMAP_PACKAGE_CBL);
omap4_i2c_init();
omap_sfh7741prox_init();
platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices));
--
1.7.0.4
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 5/7] OMAP4: mux: Add CBS package data for OMAP4430 ES2
2010-11-11 21:35 [PATCH 0/7] OMAP4: mux: Add the OMAP4430 ES1.0 & ES2.x support Benoit Cousson
` (3 preceding siblings ...)
2010-11-11 21:35 ` [PATCH 4/7] OMAP4: sdp4430: Select CBL package for ES1 and initialize mux Benoit Cousson
@ 2010-11-11 21:35 ` Benoit Cousson
2010-11-11 21:35 ` [PATCH 6/7] OMAP4: sdp4430: Select CBS package for ES2 Benoit Cousson
2010-11-11 21:35 ` [PATCH 7/7] OMAP4: pandaboard: Select CBL & CBS package and initialize mux Benoit Cousson
6 siblings, 0 replies; 14+ messages in thread
From: Benoit Cousson @ 2010-11-11 21:35 UTC (permalink / raw)
To: tony
Cc: linux-omap, Benoit Cousson, Paul Walmsley, Santosh Shilimkar,
Anand Gadiyar
Please note that the full muxmodes are re-defined for ES2 instead
of using the subset. There are 81 differences among 204 pins.
The subset fixup will have to iterate over the whole list for each
subset entry, which can lead to an important number of iteration.
On the other hand, it will take much more memory at boot time.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Anand Gadiyar <gadiyar@ti.com>
---
arch/arm/mach-omap2/Kconfig | 3 +
arch/arm/mach-omap2/mux.h | 1 +
arch/arm/mach-omap2/mux44xx.c | 741 ++++++++++++++++++++++++++++++++++++++++-
arch/arm/mach-omap2/mux44xx.h | 21 ++
4 files changed, 758 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 7efb256..92fea63 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -88,6 +88,9 @@ config OMAP_PACKAGE_CBP
config OMAP_PACKAGE_CBL
bool
+config OMAP_PACKAGE_CBS
+ bool
+
comment "OMAP Board Type"
depends on ARCH_OMAP2PLUS
diff --git a/arch/arm/mach-omap2/mux.h b/arch/arm/mach-omap2/mux.h
index 58e4913..e2b7dbc 100644
--- a/arch/arm/mach-omap2/mux.h
+++ b/arch/arm/mach-omap2/mux.h
@@ -62,6 +62,7 @@
/* Flags for omapX_mux_init */
#define OMAP_PACKAGE_MASK 0xffff
+#define OMAP_PACKAGE_CBS 8 /* 547-pin 0.40 0.40 */
#define OMAP_PACKAGE_CBL 7 /* 547-pin 0.40 0.40 */
#define OMAP_PACKAGE_CBP 6 /* 515-pin 0.40 0.50 */
#define OMAP_PACKAGE_CUS 5 /* 423-pin 0.65 */
diff --git a/arch/arm/mach-omap2/mux44xx.c b/arch/arm/mach-omap2/mux44xx.c
index 5e9d60a..80335f3 100644
--- a/arch/arm/mach-omap2/mux44xx.c
+++ b/arch/arm/mach-omap2/mux44xx.c
@@ -48,7 +48,7 @@
}
/*
- * Superset of all mux modes for omap4
+ * Superset of all mux modes for omap4 ES1.0
*/
static struct omap_mux __initdata omap4_core_muxmodes[] = {
_OMAP4_MUXENTRY(GPMC_AD0, 0, "gpmc_ad0", "sdmmc2_dat0", NULL, NULL,
@@ -755,6 +755,724 @@ struct omap_ball __initdata omap4_core_cbl_ball[] = {
#endif
/*
+ * Superset of all mux modes for omap4 ES2.0
+ */
+static struct omap_mux __initdata omap4_es2_core_muxmodes[] = {
+ _OMAP4_MUXENTRY(GPMC_AD0, 0, "gpmc_ad0", "sdmmc2_dat0", NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD1, 0, "gpmc_ad1", "sdmmc2_dat1", NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD2, 0, "gpmc_ad2", "sdmmc2_dat2", NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD3, 0, "gpmc_ad3", "sdmmc2_dat3", NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD4, 0, "gpmc_ad4", "sdmmc2_dat4",
+ "sdmmc2_dir_dat0", NULL, NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD5, 0, "gpmc_ad5", "sdmmc2_dat5",
+ "sdmmc2_dir_dat1", NULL, NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD6, 0, "gpmc_ad6", "sdmmc2_dat6",
+ "sdmmc2_dir_cmd", NULL, NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD7, 0, "gpmc_ad7", "sdmmc2_dat7",
+ "sdmmc2_clk_fdbk", NULL, NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD8, 32, "gpmc_ad8", "kpd_row0", "c2c_data15",
+ "gpio_32", NULL, "sdmmc1_dat0", NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD9, 33, "gpmc_ad9", "kpd_row1", "c2c_data14",
+ "gpio_33", NULL, "sdmmc1_dat1", NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD10, 34, "gpmc_ad10", "kpd_row2", "c2c_data13",
+ "gpio_34", NULL, "sdmmc1_dat2", NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD11, 35, "gpmc_ad11", "kpd_row3", "c2c_data12",
+ "gpio_35", NULL, "sdmmc1_dat3", NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD12, 36, "gpmc_ad12", "kpd_col0", "c2c_data11",
+ "gpio_36", NULL, "sdmmc1_dat4", NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD13, 37, "gpmc_ad13", "kpd_col1", "c2c_data10",
+ "gpio_37", NULL, "sdmmc1_dat5", NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD14, 38, "gpmc_ad14", "kpd_col2", "c2c_data9",
+ "gpio_38", NULL, "sdmmc1_dat6", NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD15, 39, "gpmc_ad15", "kpd_col3", "c2c_data8",
+ "gpio_39", NULL, "sdmmc1_dat7", NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_A16, 40, "gpmc_a16", "kpd_row4", "c2c_datain0",
+ "gpio_40", "venc_656_data0", NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_A17, 41, "gpmc_a17", "kpd_row5", "c2c_datain1",
+ "gpio_41", "venc_656_data1", NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_A18, 42, "gpmc_a18", "kpd_row6", "c2c_datain2",
+ "gpio_42", "venc_656_data2", NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_A19, 43, "gpmc_a19", "kpd_row7", "c2c_datain3",
+ "gpio_43", "venc_656_data3", NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_A20, 44, "gpmc_a20", "kpd_col4", "c2c_datain4",
+ "gpio_44", "venc_656_data4", NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_A21, 45, "gpmc_a21", "kpd_col5", "c2c_datain5",
+ "gpio_45", "venc_656_data5", NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_A22, 46, "gpmc_a22", "kpd_col6", "c2c_datain6",
+ "gpio_46", "venc_656_data6", NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_A23, 47, "gpmc_a23", "kpd_col7", "c2c_datain7",
+ "gpio_47", "venc_656_data7", NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_A24, 48, "gpmc_a24", "kpd_col8", "c2c_clkout0",
+ "gpio_48", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_A25, 49, "gpmc_a25", NULL, "c2c_clkout1",
+ "gpio_49", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_NCS0, 50, "gpmc_ncs0", NULL, NULL, "gpio_50",
+ "sys_ndmareq0", NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_NCS1, 51, "gpmc_ncs1", NULL, "c2c_dataout6",
+ "gpio_51", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_NCS2, 52, "gpmc_ncs2", "kpd_row8",
+ "c2c_dataout7", "gpio_52", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_NCS3, 53, "gpmc_ncs3", "gpmc_dir",
+ "c2c_dataout4", "gpio_53", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_NWP, 54, "gpmc_nwp", "dsi1_te0", NULL, "gpio_54",
+ "sys_ndmareq1", NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_CLK, 55, "gpmc_clk", NULL, NULL, "gpio_55",
+ "sys_ndmareq2", "sdmmc1_cmd", NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_NADV_ALE, 56, "gpmc_nadv_ale", "dsi1_te1", NULL,
+ "gpio_56", "sys_ndmareq3", "sdmmc1_clk", NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_NOE, 0, "gpmc_noe", "sdmmc2_clk", NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_NWE, 0, "gpmc_nwe", "sdmmc2_cmd", NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_NBE0_CLE, 59, "gpmc_nbe0_cle", "dsi2_te0", NULL,
+ "gpio_59", NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_NBE1, 60, "gpmc_nbe1", NULL, "c2c_dataout5",
+ "gpio_60", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_WAIT0, 61, "gpmc_wait0", "dsi2_te1", NULL,
+ "gpio_61", NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_WAIT1, 62, "gpmc_wait1", NULL, "c2c_dataout2",
+ "gpio_62", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_WAIT2, 100, "gpmc_wait2", "usbc1_icusb_txen",
+ "c2c_dataout3", "gpio_100", "sys_ndmareq0", NULL,
+ NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_NCS4, 101, "gpmc_ncs4", "dsi1_te0", "c2c_clkin0",
+ "gpio_101", "sys_ndmareq1", NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_NCS5, 102, "gpmc_ncs5", "dsi1_te1", "c2c_clkin1",
+ "gpio_102", "sys_ndmareq2", NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_NCS6, 103, "gpmc_ncs6", "dsi2_te0",
+ "c2c_dataout0", "gpio_103", "sys_ndmareq3", NULL,
+ NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_NCS7, 104, "gpmc_ncs7", "dsi2_te1",
+ "c2c_dataout1", "gpio_104", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(HDMI_HPD, 63, "hdmi_hpd", NULL, NULL, "gpio_63", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(HDMI_CEC, 64, "hdmi_cec", NULL, NULL, "gpio_64", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(HDMI_DDC_SCL, 65, "hdmi_ddc_scl", NULL, NULL,
+ "gpio_65", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(HDMI_DDC_SDA, 66, "hdmi_ddc_sda", NULL, NULL,
+ "gpio_66", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CSI21_DX0, 0, "csi21_dx0", NULL, NULL, "gpi_67", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CSI21_DY0, 0, "csi21_dy0", NULL, NULL, "gpi_68", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CSI21_DX1, 0, "csi21_dx1", NULL, NULL, "gpi_69", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CSI21_DY1, 0, "csi21_dy1", NULL, NULL, "gpi_70", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CSI21_DX2, 0, "csi21_dx2", NULL, NULL, "gpi_71", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CSI21_DY2, 0, "csi21_dy2", NULL, NULL, "gpi_72", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CSI21_DX3, 0, "csi21_dx3", NULL, NULL, "gpi_73", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CSI21_DY3, 0, "csi21_dy3", NULL, NULL, "gpi_74", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CSI21_DX4, 0, "csi21_dx4", NULL, NULL, "gpi_75", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CSI21_DY4, 0, "csi21_dy4", NULL, NULL, "gpi_76", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CSI22_DX0, 0, "csi22_dx0", NULL, NULL, "gpi_77", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CSI22_DY0, 0, "csi22_dy0", NULL, NULL, "gpi_78", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CSI22_DX1, 0, "csi22_dx1", NULL, NULL, "gpi_79", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CSI22_DY1, 0, "csi22_dy1", NULL, NULL, "gpi_80", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CAM_SHUTTER, 81, "cam_shutter", NULL, NULL, "gpio_81",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CAM_STROBE, 82, "cam_strobe", NULL, NULL, "gpio_82",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CAM_GLOBALRESET, 83, "cam_globalreset", NULL, NULL,
+ "gpio_83", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(USBB1_ULPITLL_CLK, 84, "usbb1_ulpitll_clk",
+ "hsi1_cawake", NULL, "gpio_84", "usbb1_ulpiphy_clk",
+ NULL, "hw_dbg20", "safe_mode"),
+ _OMAP4_MUXENTRY(USBB1_ULPITLL_STP, 85, "usbb1_ulpitll_stp",
+ "hsi1_cadata", "mcbsp4_clkr", "gpio_85",
+ "usbb1_ulpiphy_stp", "usbb1_mm_rxdp", "hw_dbg21",
+ "safe_mode"),
+ _OMAP4_MUXENTRY(USBB1_ULPITLL_DIR, 86, "usbb1_ulpitll_dir",
+ "hsi1_caflag", "mcbsp4_fsr", "gpio_86",
+ "usbb1_ulpiphy_dir", NULL, "hw_dbg22", "safe_mode"),
+ _OMAP4_MUXENTRY(USBB1_ULPITLL_NXT, 87, "usbb1_ulpitll_nxt",
+ "hsi1_acready", "mcbsp4_fsx", "gpio_87",
+ "usbb1_ulpiphy_nxt", "usbb1_mm_rxdm", "hw_dbg23",
+ "safe_mode"),
+ _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT0, 88, "usbb1_ulpitll_dat0",
+ "hsi1_acwake", "mcbsp4_clkx", "gpio_88",
+ "usbb1_ulpiphy_dat0", "usbb1_mm_txen", "hw_dbg24",
+ "safe_mode"),
+ _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT1, 89, "usbb1_ulpitll_dat1",
+ "hsi1_acdata", "mcbsp4_dx", "gpio_89",
+ "usbb1_ulpiphy_dat1", "usbb1_mm_txdat", "hw_dbg25",
+ "safe_mode"),
+ _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT2, 90, "usbb1_ulpitll_dat2",
+ "hsi1_acflag", "mcbsp4_dr", "gpio_90",
+ "usbb1_ulpiphy_dat2", "usbb1_mm_txse0", "hw_dbg26",
+ "safe_mode"),
+ _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT3, 91, "usbb1_ulpitll_dat3",
+ "hsi1_caready", NULL, "gpio_91", "usbb1_ulpiphy_dat3",
+ "usbb1_mm_rxrcv", "hw_dbg27", "safe_mode"),
+ _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT4, 92, "usbb1_ulpitll_dat4",
+ "dmtimer8_pwm_evt", "abe_mcbsp3_dr", "gpio_92",
+ "usbb1_ulpiphy_dat4", NULL, "hw_dbg28", "safe_mode"),
+ _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT5, 93, "usbb1_ulpitll_dat5",
+ "dmtimer9_pwm_evt", "abe_mcbsp3_dx", "gpio_93",
+ "usbb1_ulpiphy_dat5", NULL, "hw_dbg29", "safe_mode"),
+ _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT6, 94, "usbb1_ulpitll_dat6",
+ "dmtimer10_pwm_evt", "abe_mcbsp3_clkx", "gpio_94",
+ "usbb1_ulpiphy_dat6", "abe_dmic_din3", "hw_dbg30",
+ "safe_mode"),
+ _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT7, 95, "usbb1_ulpitll_dat7",
+ "dmtimer11_pwm_evt", "abe_mcbsp3_fsx", "gpio_95",
+ "usbb1_ulpiphy_dat7", "abe_dmic_clk3", "hw_dbg31",
+ "safe_mode"),
+ _OMAP4_MUXENTRY(USBB1_HSIC_DATA, 96, "usbb1_hsic_data", NULL, NULL,
+ "gpio_96", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(USBB1_HSIC_STROBE, 97, "usbb1_hsic_strobe", NULL,
+ NULL, "gpio_97", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(USBC1_ICUSB_DP, 98, "usbc1_icusb_dp", NULL, NULL,
+ "gpio_98", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(USBC1_ICUSB_DM, 99, "usbc1_icusb_dm", NULL, NULL,
+ "gpio_99", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC1_CLK, 100, "sdmmc1_clk", NULL, "dpm_emu19",
+ "gpio_100", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC1_CMD, 101, "sdmmc1_cmd", NULL, "uart1_rx",
+ "gpio_101", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC1_DAT0, 102, "sdmmc1_dat0", NULL, "dpm_emu18",
+ "gpio_102", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC1_DAT1, 103, "sdmmc1_dat1", NULL, "dpm_emu17",
+ "gpio_103", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC1_DAT2, 104, "sdmmc1_dat2", NULL, "dpm_emu16",
+ "gpio_104", "jtag_tms_tmsc", NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC1_DAT3, 105, "sdmmc1_dat3", NULL, "dpm_emu15",
+ "gpio_105", "jtag_tck", NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC1_DAT4, 106, "sdmmc1_dat4", NULL, NULL,
+ "gpio_106", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC1_DAT5, 107, "sdmmc1_dat5", NULL, NULL,
+ "gpio_107", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC1_DAT6, 108, "sdmmc1_dat6", NULL, NULL,
+ "gpio_108", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC1_DAT7, 109, "sdmmc1_dat7", NULL, NULL,
+ "gpio_109", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_MCBSP2_CLKX, 110, "abe_mcbsp2_clkx", "mcspi2_clk",
+ "abe_mcasp_ahclkx", "gpio_110", "usbb2_mm_rxdm",
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_MCBSP2_DR, 111, "abe_mcbsp2_dr", "mcspi2_somi",
+ "abe_mcasp_axr", "gpio_111", "usbb2_mm_rxdp", NULL,
+ NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_MCBSP2_DX, 112, "abe_mcbsp2_dx", "mcspi2_simo",
+ "abe_mcasp_amute", "gpio_112", "usbb2_mm_rxrcv", NULL,
+ NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_MCBSP2_FSX, 113, "abe_mcbsp2_fsx", "mcspi2_cs0",
+ "abe_mcasp_afsx", "gpio_113", "usbb2_mm_txen", NULL,
+ NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_MCBSP1_CLKX, 114, "abe_mcbsp1_clkx",
+ "abe_slimbus1_clock", NULL, "gpio_114", NULL, NULL,
+ NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_MCBSP1_DR, 115, "abe_mcbsp1_dr",
+ "abe_slimbus1_data", NULL, "gpio_115", NULL, NULL,
+ NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_MCBSP1_DX, 116, "abe_mcbsp1_dx", "sdmmc3_dat2",
+ "abe_mcasp_aclkx", "gpio_116", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_MCBSP1_FSX, 117, "abe_mcbsp1_fsx", "sdmmc3_dat3",
+ "abe_mcasp_amutein", "gpio_117", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_PDM_UL_DATA, 0, "abe_pdm_ul_data",
+ "abe_mcbsp3_dr", NULL, NULL, NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_PDM_DL_DATA, 0, "abe_pdm_dl_data",
+ "abe_mcbsp3_dx", NULL, NULL, NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_PDM_FRAME, 0, "abe_pdm_frame", "abe_mcbsp3_clkx",
+ NULL, NULL, NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_PDM_LB_CLK, 0, "abe_pdm_lb_clk", "abe_mcbsp3_fsx",
+ NULL, NULL, NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_CLKS, 118, "abe_clks", NULL, NULL, "gpio_118",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_DMIC_CLK1, 119, "abe_dmic_clk1", NULL, NULL,
+ "gpio_119", "usbb2_mm_txse0", "uart4_cts", NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_DMIC_DIN1, 120, "abe_dmic_din1", NULL, NULL,
+ "gpio_120", "usbb2_mm_txdat", "uart4_rts", NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_DMIC_DIN2, 121, "abe_dmic_din2", "slimbus2_clock",
+ "abe_mcasp_axr", "gpio_121", NULL,
+ "dmtimer11_pwm_evt", NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_DMIC_DIN3, 122, "abe_dmic_din3", "slimbus2_data",
+ "abe_dmic_clk2", "gpio_122", NULL, "dmtimer9_pwm_evt",
+ NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(UART2_CTS, 123, "uart2_cts", "sdmmc3_clk", NULL,
+ "gpio_123", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(UART2_RTS, 124, "uart2_rts", "sdmmc3_cmd", NULL,
+ "gpio_124", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(UART2_RX, 125, "uart2_rx", "sdmmc3_dat0", NULL,
+ "gpio_125", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(UART2_TX, 126, "uart2_tx", "sdmmc3_dat1", NULL,
+ "gpio_126", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(HDQ_SIO, 127, "hdq_sio", "i2c3_sccb", "i2c2_sccb",
+ "gpio_127", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(I2C1_SCL, 0, "i2c1_scl", NULL, NULL, NULL, NULL, NULL,
+ NULL, NULL),
+ _OMAP4_MUXENTRY(I2C1_SDA, 0, "i2c1_sda", NULL, NULL, NULL, NULL, NULL,
+ NULL, NULL),
+ _OMAP4_MUXENTRY(I2C2_SCL, 128, "i2c2_scl", "uart1_rx", NULL,
+ "gpio_128", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(I2C2_SDA, 129, "i2c2_sda", "uart1_tx", NULL,
+ "gpio_129", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(I2C3_SCL, 130, "i2c3_scl", NULL, NULL, "gpio_130",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(I2C3_SDA, 131, "i2c3_sda", NULL, NULL, "gpio_131",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(I2C4_SCL, 132, "i2c4_scl", NULL, NULL, "gpio_132",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(I2C4_SDA, 133, "i2c4_sda", NULL, NULL, "gpio_133",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(MCSPI1_CLK, 134, "mcspi1_clk", NULL, NULL, "gpio_134",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(MCSPI1_SOMI, 135, "mcspi1_somi", NULL, NULL,
+ "gpio_135", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(MCSPI1_SIMO, 136, "mcspi1_simo", NULL, NULL,
+ "gpio_136", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(MCSPI1_CS0, 137, "mcspi1_cs0", NULL, NULL, "gpio_137",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(MCSPI1_CS1, 138, "mcspi1_cs1", "uart1_rx", NULL,
+ "gpio_138", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(MCSPI1_CS2, 139, "mcspi1_cs2", "uart1_cts",
+ "slimbus2_clock", "gpio_139", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(MCSPI1_CS3, 140, "mcspi1_cs3", "uart1_rts",
+ "slimbus2_data", "gpio_140", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(UART3_CTS_RCTX, 141, "uart3_cts_rctx", "uart1_tx",
+ NULL, "gpio_141", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(UART3_RTS_SD, 142, "uart3_rts_sd", NULL, NULL,
+ "gpio_142", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(UART3_RX_IRRX, 143, "uart3_rx_irrx",
+ "dmtimer8_pwm_evt", NULL, "gpio_143", NULL, NULL,
+ NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(UART3_TX_IRTX, 144, "uart3_tx_irtx",
+ "dmtimer9_pwm_evt", NULL, "gpio_144", NULL, NULL,
+ NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC5_CLK, 145, "sdmmc5_clk", "mcspi2_clk",
+ "usbc1_icusb_dp", "gpio_145", NULL, "sdmmc2_clk",
+ NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC5_CMD, 146, "sdmmc5_cmd", "mcspi2_simo",
+ "usbc1_icusb_dm", "gpio_146", NULL, "sdmmc2_cmd",
+ NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC5_DAT0, 147, "sdmmc5_dat0", "mcspi2_somi",
+ "usbc1_icusb_rcv", "gpio_147", NULL, "sdmmc2_dat0",
+ NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC5_DAT1, 148, "sdmmc5_dat1", NULL,
+ "usbc1_icusb_txen", "gpio_148", NULL, "sdmmc2_dat1",
+ NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC5_DAT2, 149, "sdmmc5_dat2", "mcspi2_cs1", NULL,
+ "gpio_149", NULL, "sdmmc2_dat2", NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC5_DAT3, 150, "sdmmc5_dat3", "mcspi2_cs0", NULL,
+ "gpio_150", NULL, "sdmmc2_dat3", NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(MCSPI4_CLK, 151, "mcspi4_clk", "sdmmc4_clk",
+ "kpd_col6", "gpio_151", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(MCSPI4_SIMO, 152, "mcspi4_simo", "sdmmc4_cmd",
+ "kpd_col7", "gpio_152", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(MCSPI4_SOMI, 153, "mcspi4_somi", "sdmmc4_dat0",
+ "kpd_row6", "gpio_153", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(MCSPI4_CS0, 154, "mcspi4_cs0", "sdmmc4_dat3",
+ "kpd_row7", "gpio_154", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(UART4_RX, 155, "uart4_rx", "sdmmc4_dat2", "kpd_row8",
+ "gpio_155", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(UART4_TX, 156, "uart4_tx", "sdmmc4_dat1", "kpd_col8",
+ "gpio_156", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(USBB2_ULPITLL_CLK, 157, "usbb2_ulpitll_clk",
+ "usbb2_ulpiphy_clk", "sdmmc4_cmd", "gpio_157",
+ "hsi2_cawake", NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(USBB2_ULPITLL_STP, 158, "usbb2_ulpitll_stp",
+ "usbb2_ulpiphy_stp", "sdmmc4_clk", "gpio_158",
+ "hsi2_cadata", "dispc2_data23", NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(USBB2_ULPITLL_DIR, 159, "usbb2_ulpitll_dir",
+ "usbb2_ulpiphy_dir", "sdmmc4_dat0", "gpio_159",
+ "hsi2_caflag", "dispc2_data22", NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(USBB2_ULPITLL_NXT, 160, "usbb2_ulpitll_nxt",
+ "usbb2_ulpiphy_nxt", "sdmmc4_dat1", "gpio_160",
+ "hsi2_acready", "dispc2_data21", NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT0, 161, "usbb2_ulpitll_dat0",
+ "usbb2_ulpiphy_dat0", "sdmmc4_dat2", "gpio_161",
+ "hsi2_acwake", "dispc2_data20", "usbb2_mm_txen",
+ "safe_mode"),
+ _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT1, 162, "usbb2_ulpitll_dat1",
+ "usbb2_ulpiphy_dat1", "sdmmc4_dat3", "gpio_162",
+ "hsi2_acdata", "dispc2_data19", "usbb2_mm_txdat",
+ "safe_mode"),
+ _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT2, 163, "usbb2_ulpitll_dat2",
+ "usbb2_ulpiphy_dat2", "sdmmc3_dat2", "gpio_163",
+ "hsi2_acflag", "dispc2_data18", "usbb2_mm_txse0",
+ "safe_mode"),
+ _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT3, 164, "usbb2_ulpitll_dat3",
+ "usbb2_ulpiphy_dat3", "sdmmc3_dat1", "gpio_164",
+ "hsi2_caready", "dispc2_data15", "rfbi_data15",
+ "safe_mode"),
+ _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT4, 165, "usbb2_ulpitll_dat4",
+ "usbb2_ulpiphy_dat4", "sdmmc3_dat0", "gpio_165",
+ "mcspi3_somi", "dispc2_data14", "rfbi_data14",
+ "safe_mode"),
+ _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT5, 166, "usbb2_ulpitll_dat5",
+ "usbb2_ulpiphy_dat5", "sdmmc3_dat3", "gpio_166",
+ "mcspi3_cs0", "dispc2_data13", "rfbi_data13",
+ "safe_mode"),
+ _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT6, 167, "usbb2_ulpitll_dat6",
+ "usbb2_ulpiphy_dat6", "sdmmc3_cmd", "gpio_167",
+ "mcspi3_simo", "dispc2_data12", "rfbi_data12",
+ "safe_mode"),
+ _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT7, 168, "usbb2_ulpitll_dat7",
+ "usbb2_ulpiphy_dat7", "sdmmc3_clk", "gpio_168",
+ "mcspi3_clk", "dispc2_data11", "rfbi_data11",
+ "safe_mode"),
+ _OMAP4_MUXENTRY(USBB2_HSIC_DATA, 169, "usbb2_hsic_data", NULL, NULL,
+ "gpio_169", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(USBB2_HSIC_STROBE, 170, "usbb2_hsic_strobe", NULL,
+ NULL, "gpio_170", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(KPD_COL3, 171, "kpd_col3", "kpd_col0", NULL,
+ "gpio_171", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(KPD_COL4, 172, "kpd_col4", "kpd_col1", NULL,
+ "gpio_172", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(KPD_COL5, 173, "kpd_col5", "kpd_col2", NULL,
+ "gpio_173", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(KPD_COL0, 174, "kpd_col0", "kpd_col3", NULL,
+ "gpio_174", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(KPD_COL1, 0, "kpd_col1", "kpd_col4", NULL, "gpio_0",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(KPD_COL2, 1, "kpd_col2", "kpd_col5", NULL, "gpio_1",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(KPD_ROW3, 175, "kpd_row3", "kpd_row0", NULL,
+ "gpio_175", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(KPD_ROW4, 176, "kpd_row4", "kpd_row1", NULL,
+ "gpio_176", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(KPD_ROW5, 177, "kpd_row5", "kpd_row2", NULL,
+ "gpio_177", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(KPD_ROW0, 178, "kpd_row0", "kpd_row3", NULL,
+ "gpio_178", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(KPD_ROW1, 2, "kpd_row1", "kpd_row4", NULL, "gpio_2",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(KPD_ROW2, 3, "kpd_row2", "kpd_row5", NULL, "gpio_3",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(USBA0_OTG_CE, 0, "usba0_otg_ce", NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(USBA0_OTG_DP, 0, "usba0_otg_dp", "uart3_rx_irrx",
+ "uart2_rx", NULL, NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(USBA0_OTG_DM, 0, "usba0_otg_dm", "uart3_tx_irtx",
+ "uart2_tx", NULL, NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(FREF_CLK1_OUT, 181, "fref_clk1_out", NULL, NULL,
+ "gpio_181", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(FREF_CLK2_OUT, 182, "fref_clk2_out", NULL, NULL,
+ "gpio_182", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SYS_NIRQ1, 0, "sys_nirq1", NULL, NULL, NULL, NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SYS_NIRQ2, 183, "sys_nirq2", NULL, NULL, "gpio_183",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SYS_BOOT0, 184, "sys_boot0", NULL, NULL, "gpio_184",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SYS_BOOT1, 185, "sys_boot1", NULL, NULL, "gpio_185",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SYS_BOOT2, 186, "sys_boot2", NULL, NULL, "gpio_186",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SYS_BOOT3, 187, "sys_boot3", NULL, NULL, "gpio_187",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SYS_BOOT4, 188, "sys_boot4", NULL, NULL, "gpio_188",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SYS_BOOT5, 189, "sys_boot5", NULL, NULL, "gpio_189",
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(DPM_EMU0, 11, "dpm_emu0", NULL, NULL, "gpio_11", NULL,
+ NULL, "hw_dbg0", "safe_mode"),
+ _OMAP4_MUXENTRY(DPM_EMU1, 12, "dpm_emu1", NULL, NULL, "gpio_12", NULL,
+ NULL, "hw_dbg1", "safe_mode"),
+ _OMAP4_MUXENTRY(DPM_EMU2, 13, "dpm_emu2", "usba0_ulpiphy_clk", NULL,
+ "gpio_13", NULL, "dispc2_fid", "hw_dbg2",
+ "safe_mode"),
+ _OMAP4_MUXENTRY(DPM_EMU3, 14, "dpm_emu3", "usba0_ulpiphy_stp", NULL,
+ "gpio_14", "rfbi_data10", "dispc2_data10", "hw_dbg3",
+ "safe_mode"),
+ _OMAP4_MUXENTRY(DPM_EMU4, 15, "dpm_emu4", "usba0_ulpiphy_dir", NULL,
+ "gpio_15", "rfbi_data9", "dispc2_data9", "hw_dbg4",
+ "safe_mode"),
+ _OMAP4_MUXENTRY(DPM_EMU5, 16, "dpm_emu5", "usba0_ulpiphy_nxt", NULL,
+ "gpio_16", "rfbi_te_vsync0", "dispc2_data16",
+ "hw_dbg5", "safe_mode"),
+ _OMAP4_MUXENTRY(DPM_EMU6, 17, "dpm_emu6", "usba0_ulpiphy_dat0",
+ "uart3_tx_irtx", "gpio_17", "rfbi_hsync0",
+ "dispc2_data17", "hw_dbg6", "safe_mode"),
+ _OMAP4_MUXENTRY(DPM_EMU7, 18, "dpm_emu7", "usba0_ulpiphy_dat1",
+ "uart3_rx_irrx", "gpio_18", "rfbi_cs0",
+ "dispc2_hsync", "hw_dbg7", "safe_mode"),
+ _OMAP4_MUXENTRY(DPM_EMU8, 19, "dpm_emu8", "usba0_ulpiphy_dat2",
+ "uart3_rts_sd", "gpio_19", "rfbi_re", "dispc2_pclk",
+ "hw_dbg8", "safe_mode"),
+ _OMAP4_MUXENTRY(DPM_EMU9, 20, "dpm_emu9", "usba0_ulpiphy_dat3",
+ "uart3_cts_rctx", "gpio_20", "rfbi_we",
+ "dispc2_vsync", "hw_dbg9", "safe_mode"),
+ _OMAP4_MUXENTRY(DPM_EMU10, 21, "dpm_emu10", "usba0_ulpiphy_dat4",
+ NULL, "gpio_21", "rfbi_a0", "dispc2_de", "hw_dbg10",
+ "safe_mode"),
+ _OMAP4_MUXENTRY(DPM_EMU11, 22, "dpm_emu11", "usba0_ulpiphy_dat5",
+ NULL, "gpio_22", "rfbi_data8", "dispc2_data8",
+ "hw_dbg11", "safe_mode"),
+ _OMAP4_MUXENTRY(DPM_EMU12, 23, "dpm_emu12", "usba0_ulpiphy_dat6",
+ NULL, "gpio_23", "rfbi_data7", "dispc2_data7",
+ "hw_dbg12", "safe_mode"),
+ _OMAP4_MUXENTRY(DPM_EMU13, 24, "dpm_emu13", "usba0_ulpiphy_dat7",
+ NULL, "gpio_24", "rfbi_data6", "dispc2_data6",
+ "hw_dbg13", "safe_mode"),
+ _OMAP4_MUXENTRY(DPM_EMU14, 25, "dpm_emu14", "sys_drm_msecure",
+ "uart1_rx", "gpio_25", "rfbi_data5", "dispc2_data5",
+ "hw_dbg14", "safe_mode"),
+ _OMAP4_MUXENTRY(DPM_EMU15, 26, "dpm_emu15", "sys_secure_indicator",
+ NULL, "gpio_26", "rfbi_data4", "dispc2_data4",
+ "hw_dbg15", "safe_mode"),
+ _OMAP4_MUXENTRY(DPM_EMU16, 27, "dpm_emu16", "dmtimer8_pwm_evt",
+ "dsi1_te0", "gpio_27", "rfbi_data3", "dispc2_data3",
+ "hw_dbg16", "safe_mode"),
+ _OMAP4_MUXENTRY(DPM_EMU17, 28, "dpm_emu17", "dmtimer9_pwm_evt",
+ "dsi1_te1", "gpio_28", "rfbi_data2", "dispc2_data2",
+ "hw_dbg17", "safe_mode"),
+ _OMAP4_MUXENTRY(DPM_EMU18, 190, "dpm_emu18", "dmtimer10_pwm_evt",
+ "dsi2_te0", "gpio_190", "rfbi_data1", "dispc2_data1",
+ "hw_dbg18", "safe_mode"),
+ _OMAP4_MUXENTRY(DPM_EMU19, 191, "dpm_emu19", "dmtimer11_pwm_evt",
+ "dsi2_te1", "gpio_191", "rfbi_data0", "dispc2_data0",
+ "hw_dbg19", "safe_mode"),
+ { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+
+/*
+ * Balls for 44XX CBS package
+ * 547-pin CBL ES2.0 S-FPGA-N547, 0.40mm Ball Pitch (Top),
+ * 0.40mm Ball Pitch (Bottom)
+ */
+#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \
+ && defined(CONFIG_OMAP_PACKAGE_CBS)
+struct omap_ball __initdata omap4_core_cbs_ball[] = {
+ _OMAP4_BALLENTRY(GPMC_AD0, "c12", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD1, "d12", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD2, "c13", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD3, "d13", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD4, "c15", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD5, "d15", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD6, "a16", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD7, "b16", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD8, "c16", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD9, "d16", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD10, "c17", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD11, "d17", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD12, "c18", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD13, "d18", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD14, "c19", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD15, "d19", NULL),
+ _OMAP4_BALLENTRY(GPMC_A16, "b17", NULL),
+ _OMAP4_BALLENTRY(GPMC_A17, "a18", NULL),
+ _OMAP4_BALLENTRY(GPMC_A18, "b18", NULL),
+ _OMAP4_BALLENTRY(GPMC_A19, "a19", NULL),
+ _OMAP4_BALLENTRY(GPMC_A20, "b19", NULL),
+ _OMAP4_BALLENTRY(GPMC_A21, "b20", NULL),
+ _OMAP4_BALLENTRY(GPMC_A22, "a21", NULL),
+ _OMAP4_BALLENTRY(GPMC_A23, "b21", NULL),
+ _OMAP4_BALLENTRY(GPMC_A24, "c20", NULL),
+ _OMAP4_BALLENTRY(GPMC_A25, "d20", NULL),
+ _OMAP4_BALLENTRY(GPMC_NCS0, "b25", NULL),
+ _OMAP4_BALLENTRY(GPMC_NCS1, "c21", NULL),
+ _OMAP4_BALLENTRY(GPMC_NCS2, "d21", NULL),
+ _OMAP4_BALLENTRY(GPMC_NCS3, "c22", NULL),
+ _OMAP4_BALLENTRY(GPMC_NWP, "c25", NULL),
+ _OMAP4_BALLENTRY(GPMC_CLK, "b22", NULL),
+ _OMAP4_BALLENTRY(GPMC_NADV_ALE, "d25", NULL),
+ _OMAP4_BALLENTRY(GPMC_NOE, "b11", NULL),
+ _OMAP4_BALLENTRY(GPMC_NWE, "b12", NULL),
+ _OMAP4_BALLENTRY(GPMC_NBE0_CLE, "c23", NULL),
+ _OMAP4_BALLENTRY(GPMC_NBE1, "d22", NULL),
+ _OMAP4_BALLENTRY(GPMC_WAIT0, "b26", NULL),
+ _OMAP4_BALLENTRY(GPMC_WAIT1, "b23", NULL),
+ _OMAP4_BALLENTRY(GPMC_WAIT2, "d23", NULL),
+ _OMAP4_BALLENTRY(GPMC_NCS4, "a24", NULL),
+ _OMAP4_BALLENTRY(GPMC_NCS5, "b24", NULL),
+ _OMAP4_BALLENTRY(GPMC_NCS6, "c24", NULL),
+ _OMAP4_BALLENTRY(GPMC_NCS7, "d24", NULL),
+ _OMAP4_BALLENTRY(HDMI_HPD, "b9", NULL),
+ _OMAP4_BALLENTRY(HDMI_CEC, "b10", NULL),
+ _OMAP4_BALLENTRY(HDMI_DDC_SCL, "a8", NULL),
+ _OMAP4_BALLENTRY(HDMI_DDC_SDA, "b8", NULL),
+ _OMAP4_BALLENTRY(CSI21_DX0, "r26", NULL),
+ _OMAP4_BALLENTRY(CSI21_DY0, "r25", NULL),
+ _OMAP4_BALLENTRY(CSI21_DX1, "t26", NULL),
+ _OMAP4_BALLENTRY(CSI21_DY1, "t25", NULL),
+ _OMAP4_BALLENTRY(CSI21_DX2, "u26", NULL),
+ _OMAP4_BALLENTRY(CSI21_DY2, "u25", NULL),
+ _OMAP4_BALLENTRY(CSI21_DX3, "v26", NULL),
+ _OMAP4_BALLENTRY(CSI21_DY3, "v25", NULL),
+ _OMAP4_BALLENTRY(CSI21_DX4, "w26", NULL),
+ _OMAP4_BALLENTRY(CSI21_DY4, "w25", NULL),
+ _OMAP4_BALLENTRY(CSI22_DX0, "m26", NULL),
+ _OMAP4_BALLENTRY(CSI22_DY0, "m25", NULL),
+ _OMAP4_BALLENTRY(CSI22_DX1, "n26", NULL),
+ _OMAP4_BALLENTRY(CSI22_DY1, "n25", NULL),
+ _OMAP4_BALLENTRY(CAM_SHUTTER, "t27", NULL),
+ _OMAP4_BALLENTRY(CAM_STROBE, "u27", NULL),
+ _OMAP4_BALLENTRY(CAM_GLOBALRESET, "v27", NULL),
+ _OMAP4_BALLENTRY(USBB1_ULPITLL_CLK, "ae18", NULL),
+ _OMAP4_BALLENTRY(USBB1_ULPITLL_STP, "ag19", NULL),
+ _OMAP4_BALLENTRY(USBB1_ULPITLL_DIR, "af19", NULL),
+ _OMAP4_BALLENTRY(USBB1_ULPITLL_NXT, "ae19", NULL),
+ _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT0, "af18", NULL),
+ _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT1, "ag18", NULL),
+ _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT2, "ae17", NULL),
+ _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT3, "af17", NULL),
+ _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT4, "ah17", NULL),
+ _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT5, "ae16", NULL),
+ _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT6, "af16", NULL),
+ _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT7, "ag16", NULL),
+ _OMAP4_BALLENTRY(USBB1_HSIC_DATA, "af14", NULL),
+ _OMAP4_BALLENTRY(USBB1_HSIC_STROBE, "ae14", NULL),
+ _OMAP4_BALLENTRY(USBC1_ICUSB_DP, "h2", NULL),
+ _OMAP4_BALLENTRY(USBC1_ICUSB_DM, "h3", NULL),
+ _OMAP4_BALLENTRY(SDMMC1_CLK, "d2", NULL),
+ _OMAP4_BALLENTRY(SDMMC1_CMD, "e3", NULL),
+ _OMAP4_BALLENTRY(SDMMC1_DAT0, "e4", NULL),
+ _OMAP4_BALLENTRY(SDMMC1_DAT1, "e2", NULL),
+ _OMAP4_BALLENTRY(SDMMC1_DAT2, "e1", NULL),
+ _OMAP4_BALLENTRY(SDMMC1_DAT3, "f4", NULL),
+ _OMAP4_BALLENTRY(SDMMC1_DAT4, "f3", NULL),
+ _OMAP4_BALLENTRY(SDMMC1_DAT5, "f1", NULL),
+ _OMAP4_BALLENTRY(SDMMC1_DAT6, "g4", NULL),
+ _OMAP4_BALLENTRY(SDMMC1_DAT7, "g3", NULL),
+ _OMAP4_BALLENTRY(ABE_MCBSP2_CLKX, "ad27", NULL),
+ _OMAP4_BALLENTRY(ABE_MCBSP2_DR, "ad26", NULL),
+ _OMAP4_BALLENTRY(ABE_MCBSP2_DX, "ad25", NULL),
+ _OMAP4_BALLENTRY(ABE_MCBSP2_FSX, "ac28", NULL),
+ _OMAP4_BALLENTRY(ABE_MCBSP1_CLKX, "ac26", NULL),
+ _OMAP4_BALLENTRY(ABE_MCBSP1_DR, "ac25", NULL),
+ _OMAP4_BALLENTRY(ABE_MCBSP1_DX, "ab25", NULL),
+ _OMAP4_BALLENTRY(ABE_MCBSP1_FSX, "ac27", NULL),
+ _OMAP4_BALLENTRY(ABE_PDM_UL_DATA, "ag25", NULL),
+ _OMAP4_BALLENTRY(ABE_PDM_DL_DATA, "af25", NULL),
+ _OMAP4_BALLENTRY(ABE_PDM_FRAME, "ae25", NULL),
+ _OMAP4_BALLENTRY(ABE_PDM_LB_CLK, "af26", NULL),
+ _OMAP4_BALLENTRY(ABE_CLKS, "ah26", NULL),
+ _OMAP4_BALLENTRY(ABE_DMIC_CLK1, "ae24", NULL),
+ _OMAP4_BALLENTRY(ABE_DMIC_DIN1, "af24", NULL),
+ _OMAP4_BALLENTRY(ABE_DMIC_DIN2, "ag24", NULL),
+ _OMAP4_BALLENTRY(ABE_DMIC_DIN3, "ah24", NULL),
+ _OMAP4_BALLENTRY(UART2_CTS, "ab26", NULL),
+ _OMAP4_BALLENTRY(UART2_RTS, "ab27", NULL),
+ _OMAP4_BALLENTRY(UART2_RX, "aa25", NULL),
+ _OMAP4_BALLENTRY(UART2_TX, "aa26", NULL),
+ _OMAP4_BALLENTRY(HDQ_SIO, "aa27", NULL),
+ _OMAP4_BALLENTRY(I2C1_SCL, "ae28", NULL),
+ _OMAP4_BALLENTRY(I2C1_SDA, "ae26", NULL),
+ _OMAP4_BALLENTRY(I2C2_SCL, "c26", NULL),
+ _OMAP4_BALLENTRY(I2C2_SDA, "d26", NULL),
+ _OMAP4_BALLENTRY(I2C3_SCL, "w27", NULL),
+ _OMAP4_BALLENTRY(I2C3_SDA, "y27", NULL),
+ _OMAP4_BALLENTRY(I2C4_SCL, "ag21", NULL),
+ _OMAP4_BALLENTRY(I2C4_SDA, "ah22", NULL),
+ _OMAP4_BALLENTRY(MCSPI1_CLK, "af22", NULL),
+ _OMAP4_BALLENTRY(MCSPI1_SOMI, "ae22", NULL),
+ _OMAP4_BALLENTRY(MCSPI1_SIMO, "ag22", NULL),
+ _OMAP4_BALLENTRY(MCSPI1_CS0, "ae23", NULL),
+ _OMAP4_BALLENTRY(MCSPI1_CS1, "af23", NULL),
+ _OMAP4_BALLENTRY(MCSPI1_CS2, "ag23", NULL),
+ _OMAP4_BALLENTRY(MCSPI1_CS3, "ah23", NULL),
+ _OMAP4_BALLENTRY(UART3_CTS_RCTX, "f27", NULL),
+ _OMAP4_BALLENTRY(UART3_RTS_SD, "f28", NULL),
+ _OMAP4_BALLENTRY(UART3_RX_IRRX, "g27", NULL),
+ _OMAP4_BALLENTRY(UART3_TX_IRTX, "g28", NULL),
+ _OMAP4_BALLENTRY(SDMMC5_CLK, "ae5", NULL),
+ _OMAP4_BALLENTRY(SDMMC5_CMD, "af5", NULL),
+ _OMAP4_BALLENTRY(SDMMC5_DAT0, "ae4", NULL),
+ _OMAP4_BALLENTRY(SDMMC5_DAT1, "af4", NULL),
+ _OMAP4_BALLENTRY(SDMMC5_DAT2, "ag3", NULL),
+ _OMAP4_BALLENTRY(SDMMC5_DAT3, "af3", NULL),
+ _OMAP4_BALLENTRY(MCSPI4_CLK, "ae21", NULL),
+ _OMAP4_BALLENTRY(MCSPI4_SIMO, "af20", NULL),
+ _OMAP4_BALLENTRY(MCSPI4_SOMI, "af21", NULL),
+ _OMAP4_BALLENTRY(MCSPI4_CS0, "ae20", NULL),
+ _OMAP4_BALLENTRY(UART4_RX, "ag20", NULL),
+ _OMAP4_BALLENTRY(UART4_TX, "ah19", NULL),
+ _OMAP4_BALLENTRY(USBB2_ULPITLL_CLK, "ag12", NULL),
+ _OMAP4_BALLENTRY(USBB2_ULPITLL_STP, "af12", NULL),
+ _OMAP4_BALLENTRY(USBB2_ULPITLL_DIR, "ae12", NULL),
+ _OMAP4_BALLENTRY(USBB2_ULPITLL_NXT, "ag13", NULL),
+ _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT0, "ae11", NULL),
+ _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT1, "af11", NULL),
+ _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT2, "ag11", NULL),
+ _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT3, "ah11", NULL),
+ _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT4, "ae10", NULL),
+ _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT5, "af10", NULL),
+ _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT6, "ag10", NULL),
+ _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT7, "ae9", NULL),
+ _OMAP4_BALLENTRY(USBB2_HSIC_DATA, "af13", NULL),
+ _OMAP4_BALLENTRY(USBB2_HSIC_STROBE, "ae13", NULL),
+ _OMAP4_BALLENTRY(KPD_COL3, "g26", NULL),
+ _OMAP4_BALLENTRY(KPD_COL4, "g25", NULL),
+ _OMAP4_BALLENTRY(KPD_COL5, "h26", NULL),
+ _OMAP4_BALLENTRY(KPD_COL0, "h25", NULL),
+ _OMAP4_BALLENTRY(KPD_COL1, "j27", NULL),
+ _OMAP4_BALLENTRY(KPD_COL2, "h27", NULL),
+ _OMAP4_BALLENTRY(KPD_ROW3, "j26", NULL),
+ _OMAP4_BALLENTRY(KPD_ROW4, "j25", NULL),
+ _OMAP4_BALLENTRY(KPD_ROW5, "k26", NULL),
+ _OMAP4_BALLENTRY(KPD_ROW0, "k25", NULL),
+ _OMAP4_BALLENTRY(KPD_ROW1, "l27", NULL),
+ _OMAP4_BALLENTRY(KPD_ROW2, "k27", NULL),
+ _OMAP4_BALLENTRY(USBA0_OTG_CE, "c3", NULL),
+ _OMAP4_BALLENTRY(USBA0_OTG_DP, "b5", NULL),
+ _OMAP4_BALLENTRY(USBA0_OTG_DM, "b4", NULL),
+ _OMAP4_BALLENTRY(FREF_CLK1_OUT, "aa28", NULL),
+ _OMAP4_BALLENTRY(FREF_CLK2_OUT, "y28", NULL),
+ _OMAP4_BALLENTRY(SYS_NIRQ1, "ae6", NULL),
+ _OMAP4_BALLENTRY(SYS_NIRQ2, "af6", NULL),
+ _OMAP4_BALLENTRY(SYS_BOOT0, "f26", NULL),
+ _OMAP4_BALLENTRY(SYS_BOOT1, "e27", NULL),
+ _OMAP4_BALLENTRY(SYS_BOOT2, "e26", NULL),
+ _OMAP4_BALLENTRY(SYS_BOOT3, "e25", NULL),
+ _OMAP4_BALLENTRY(SYS_BOOT4, "d28", NULL),
+ _OMAP4_BALLENTRY(SYS_BOOT5, "d27", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU0, "m2", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU1, "n2", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU2, "p2", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU3, "v1", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU4, "v2", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU5, "w1", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU6, "w2", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU7, "w3", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU8, "w4", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU9, "y2", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU10, "y3", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU11, "y4", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU12, "aa1", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU13, "aa2", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU14, "aa3", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU15, "aa4", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU16, "ab2", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU17, "ab3", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU18, "ab4", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU19, "ac4", NULL),
+ { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define omap4_core_cbs_ball NULL
+#endif
+
+/*
* Superset of all mux modes for omap4
*/
static struct omap_mux __initdata omap4_wkup_muxmodes[] = {
@@ -822,13 +1540,13 @@ static struct omap_mux __initdata omap4_wkup_muxmodes[] = {
};
/*
- * Balls for 44XX CBL package
+ * Balls for 44XX CBL & CBS package - wakeup partition
* 547-pin CBL ES1.0 S-FPGA-N547, 0.40mm Ball Pitch (Top),
* 0.40mm Ball Pitch (Bottom)
*/
#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \
&& defined(CONFIG_OMAP_PACKAGE_CBL)
-struct omap_ball __initdata omap4_wkup_cbl_ball[] = {
+struct omap_ball __initdata omap4_wkup_cbl_cbs_ball[] = {
_OMAP4_BALLENTRY(SIM_IO, "h4", NULL),
_OMAP4_BALLENTRY(SIM_CLK, "j2", NULL),
_OMAP4_BALLENTRY(SIM_RESET, "g2", NULL),
@@ -860,19 +1578,26 @@ struct omap_ball __initdata omap4_wkup_cbl_ball[] = {
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#else
-#define omap4_wkup_cbl_ball NULL
+#define omap4_wkup_cbl_cbs_ball NULL
#endif
-
int __init omap4_mux_init(struct omap_board_mux *board_subset, int flags)
{
- struct omap_ball *package_balls_core, *package_balls_wkup;
+ struct omap_ball *package_balls_core;
+ struct omap_ball *package_balls_wkup = omap4_wkup_cbl_cbs_ball;
+ struct omap_mux *core_muxmodes;
int ret;
switch (flags & OMAP_PACKAGE_MASK) {
case OMAP_PACKAGE_CBL:
+ pr_debug("mux: OMAP4430 ES1.0 -> OMAP_PACKAGE_CBL\n");
package_balls_core = omap4_core_cbl_ball;
- package_balls_wkup = omap4_wkup_cbl_ball;
+ core_muxmodes = omap4_core_muxmodes;
+ break;
+ case OMAP_PACKAGE_CBS:
+ pr_debug("mux: OMAP4430 ES2.X -> OMAP_PACKAGE_CBS\n");
+ package_balls_core = omap4_core_cbs_ball;
+ core_muxmodes = omap4_es2_core_muxmodes;
break;
default:
pr_err("mux: Unknown omap package, mux disabled\n");
@@ -883,7 +1608,7 @@ int __init omap4_mux_init(struct omap_board_mux *board_subset, int flags)
OMAP_MUX_GPIO_IN_MODE3,
OMAP4_CTRL_MODULE_PAD_CORE_MUX_PBASE,
OMAP4_CTRL_MODULE_PAD_CORE_MUX_SIZE,
- omap4_core_muxmodes, NULL, board_subset,
+ core_muxmodes, NULL, board_subset,
package_balls_core);
if (ret)
return ret;
diff --git a/arch/arm/mach-omap2/mux44xx.h b/arch/arm/mach-omap2/mux44xx.h
index ea8b235..c635026 100644
--- a/arch/arm/mach-omap2/mux44xx.h
+++ b/arch/arm/mach-omap2/mux44xx.h
@@ -233,6 +233,27 @@
#define OMAP4_CTRL_MODULE_PAD_DPM_EMU18_OFFSET 0x01d2
#define OMAP4_CTRL_MODULE_PAD_DPM_EMU19_OFFSET 0x01d4
+/* ES2.0 only */
+#define OMAP4_CTRL_MODULE_PAD_GPMC_WAIT2_OFFSET 0x008e
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS4_OFFSET 0x0090
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS5_OFFSET 0x0092
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS6_OFFSET 0x0094
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS7_OFFSET 0x0096
+
+#define OMAP4_CTRL_MODULE_PAD_KPD_COL3_OFFSET 0x017c
+#define OMAP4_CTRL_MODULE_PAD_KPD_COL4_OFFSET 0x017e
+#define OMAP4_CTRL_MODULE_PAD_KPD_COL5_OFFSET 0x0180
+#define OMAP4_CTRL_MODULE_PAD_KPD_COL0_OFFSET 0x0182
+#define OMAP4_CTRL_MODULE_PAD_KPD_COL1_OFFSET 0x0184
+#define OMAP4_CTRL_MODULE_PAD_KPD_COL2_OFFSET 0x0186
+#define OMAP4_CTRL_MODULE_PAD_KPD_ROW3_OFFSET 0x0188
+#define OMAP4_CTRL_MODULE_PAD_KPD_ROW4_OFFSET 0x018a
+#define OMAP4_CTRL_MODULE_PAD_KPD_ROW5_OFFSET 0x018c
+#define OMAP4_CTRL_MODULE_PAD_KPD_ROW0_OFFSET 0x018e
+#define OMAP4_CTRL_MODULE_PAD_KPD_ROW1_OFFSET 0x0190
+#define OMAP4_CTRL_MODULE_PAD_KPD_ROW2_OFFSET 0x0192
+
+
#define OMAP4_CTRL_MODULE_PAD_CORE_MUX_SIZE \
(OMAP4_CTRL_MODULE_PAD_DPM_EMU19_OFFSET \
- OMAP4_CTRL_MODULE_PAD_GPMC_AD0_OFFSET + 2)
--
1.7.0.4
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 6/7] OMAP4: sdp4430: Select CBS package for ES2
2010-11-11 21:35 [PATCH 0/7] OMAP4: mux: Add the OMAP4430 ES1.0 & ES2.x support Benoit Cousson
` (4 preceding siblings ...)
2010-11-11 21:35 ` [PATCH 5/7] OMAP4: mux: Add CBS package data for OMAP4430 ES2 Benoit Cousson
@ 2010-11-11 21:35 ` Benoit Cousson
2010-11-11 21:35 ` [PATCH 7/7] OMAP4: pandaboard: Select CBL & CBS package and initialize mux Benoit Cousson
6 siblings, 0 replies; 14+ messages in thread
From: Benoit Cousson @ 2010-11-11 21:35 UTC (permalink / raw)
To: tony
Cc: linux-omap, Benoit Cousson, Paul Walmsley, Santosh Shilimkar,
Anand Gadiyar
Select the CBS package if SDP4430 is enabled during config.
Use the proper package (CBL or CBS) based on chip revision.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Anand Gadiyar <gadiyar@ti.com>
---
arch/arm/mach-omap2/Kconfig | 1 +
arch/arm/mach-omap2/board-4430sdp.c | 6 +++++-
2 files changed, 6 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 92fea63..39229cf 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -284,6 +284,7 @@ config MACH_OMAP_4430SDP
default y
depends on ARCH_OMAP4
select OMAP_PACKAGE_CBL
+ select OMAP_PACKAGE_CBS
config MACH_OMAP4_PANDA
bool "OMAP4 Panda Board"
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index e4f1726..94d989b 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -517,8 +517,12 @@ static struct omap_board_mux board_mux[] __initdata = {
static void __init omap_4430sdp_init(void)
{
int status;
+ int package = OMAP_PACKAGE_CBS;
+
+ if (omap_rev() == OMAP4430_REV_ES1_0)
+ package = OMAP_PACKAGE_CBL;
+ omap4_mux_init(board_mux, package);
- omap4_mux_init(board_mux, OMAP_PACKAGE_CBL);
omap4_i2c_init();
omap_sfh7741prox_init();
platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices));
--
1.7.0.4
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 7/7] OMAP4: pandaboard: Select CBL & CBS package and initialize mux
2010-11-11 21:35 [PATCH 0/7] OMAP4: mux: Add the OMAP4430 ES1.0 & ES2.x support Benoit Cousson
` (5 preceding siblings ...)
2010-11-11 21:35 ` [PATCH 6/7] OMAP4: sdp4430: Select CBS package for ES2 Benoit Cousson
@ 2010-11-11 21:35 ` Benoit Cousson
6 siblings, 0 replies; 14+ messages in thread
From: Benoit Cousson @ 2010-11-11 21:35 UTC (permalink / raw)
To: tony; +Cc: linux-omap, sricharan, Benoit Cousson, Santosh Shilimkar
From: sricharan <r.sricharan@ti.com>
The mux framework allows the change of pad configuration by drivers
when needed. Prior to this the mux framework has to be initialised
with all the mux parameters specific to the board. The mux init is
already present in the board file for SDP. Adding the mux init
for panda boards.
Signed-off-by: sricharan <r.sricharan@ti.com>
Acked-by: Anand Gadiyar <gadiyar@ti.com>
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
arch/arm/mach-omap2/Kconfig | 2 ++
arch/arm/mach-omap2/board-omap4panda.c | 16 ++++++++++++++++
2 files changed, 18 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 39229cf..186d270 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -290,6 +290,8 @@ config MACH_OMAP4_PANDA
bool "OMAP4 Panda Board"
default y
depends on ARCH_OMAP4
+ select OMAP_PACKAGE_CBL
+ select OMAP_PACKAGE_CBS
config OMAP3_EMU
bool "OMAP3 debugging peripherals"
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index 1ecd0a6..801f814 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -40,6 +40,7 @@
#include "hsmmc.h"
#include "control.h"
+#include "mux.h"
#define GPIO_HUB_POWER 1
#define GPIO_HUB_NRESET 62
@@ -368,8 +369,23 @@ static int __init omap4_panda_i2c_init(void)
omap_register_i2c_bus(4, 400, NULL, 0);
return 0;
}
+
+#ifdef CONFIG_OMAP_MUX
+static struct omap_board_mux board_mux[] __initdata = {
+ { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define board_mux NULL
+#endif
+
static void __init omap4_panda_init(void)
{
+ int package = OMAP_PACKAGE_CBS;
+
+ if (omap_rev() == OMAP4430_REV_ES1_0)
+ package = OMAP_PACKAGE_CBL;
+ omap4_mux_init(board_mux, package);
+
omap4_panda_i2c_init();
platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices));
omap_serial_init();
--
1.7.0.4
^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH 2/7] OMAP: mux: Add support for control module split in several partitions
2010-11-11 21:35 ` [PATCH 2/7] OMAP: mux: Add support for control module split in several partitions Benoit Cousson
@ 2010-11-15 20:03 ` Tony Lindgren
2010-11-15 21:46 ` Cousson, Benoit
0 siblings, 1 reply; 14+ messages in thread
From: Tony Lindgren @ 2010-11-15 20:03 UTC (permalink / raw)
To: Benoit Cousson; +Cc: linux-omap, Paul Walmsley, Kevin Hilman, Santosh Shilimkar
* Benoit Cousson <b-cousson@ti.com> [101111 13:26]:
> Starting on OMAP4, the pin mux configuration is located in two
> different partitions of the control module (CODE_PAD and WKUP_PAD).
> The first one is inside the core power domain whereas the second
> one is inside the wakeup.
> - Add the capability to add any number of partition during board init
> time depending of Soc partitioning.
> - Add some init flags as well in order to avoid explicit Soc version
> check inside the mux core code.
> - Add a comment with mux0 mode on top of omap_mux/board/<partition>
> if the current mux mode is not the default one.
Here's one more patch that I'd like to merge into this patch to avoid
repeating the partition for each mux entry.
Assuming no more comments, I'll queue these for 2.6.38 merge window.
Regards,
Tony
From: Tony Lindgren <tony@atomide.com>
Date: Mon, 15 Nov 2010 11:52:20 -0800
Subject: [PATCH] omap: mux: Save memory for struct omap_mux
There's no need to repeat the partition for each mux entry.
We can look up the partition for debugfs.
Signed-off-by: Tony Lindgren <tony@atomide.com>
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -348,14 +348,37 @@ static const struct file_operations omap_mux_dbg_board_fops = {
.release = single_release,
};
+static struct omap_mux_partition * omap_mux_get_partition(struct omap_mux *mux)
+{
+ struct omap_mux_partition *partition;
+
+ list_for_each_entry(partition, &mux_partitions, node) {
+ struct list_head *muxmodes = &partition->muxmodes;
+ struct omap_mux_entry *e;
+
+ list_for_each_entry(e, muxmodes, node) {
+ struct omap_mux *m = &e->mux;
+
+ if (m == mux)
+ return partition;
+ }
+ }
+
+ return NULL;
+}
+
static int omap_mux_dbg_signal_show(struct seq_file *s, void *unused)
{
struct omap_mux *m = s->private;
- struct omap_mux_partition *partition = m->partition;
+ struct omap_mux_partition *partition;
const char *none = "NA";
u16 val;
int mode;
+ partition = omap_mux_get_partition(m);
+ if (!partition)
+ return 0;
+
val = omap_mux_read(partition, m->reg_offset);
mode = val & OMAP_MUX_MODE7;
@@ -391,6 +414,7 @@ static ssize_t omap_mux_dbg_signal_write(struct file *file,
struct omap_mux *m;
unsigned long val;
int buf_size, ret;
+ struct omap_mux_partition *partition;
if (count > OMAP_MUX_MAX_ARG_CHAR)
return -EINVAL;
@@ -411,7 +435,11 @@ static ssize_t omap_mux_dbg_signal_write(struct file *file,
seqf = file->private_data;
m = seqf->private;
- omap_mux_write(m->partition, (u16)val, m->reg_offset);
+ partition = omap_mux_get_partition(m);
+ if (!partition)
+ return -ENODEV;
+
+ omap_mux_write(partition, (u16)val, m->reg_offset);
*ppos += count;
return count;
@@ -440,7 +468,6 @@ static void __init omap_mux_dbg_create_entry(
list_for_each_entry(e, &partition->muxmodes, node) {
struct omap_mux *m = &e->mux;
- m->partition = partition;
(void)debugfs_create_file(m->muxnames[0], S_IWUGO, mux_dbg_dir,
m, &omap_mux_dbg_signal_fops);
--- a/arch/arm/mach-omap2/mux.h
+++ b/arch/arm/mach-omap2/mux.h
@@ -121,7 +121,6 @@ struct omap_mux {
char *muxnames[OMAP_MUX_NR_MODES];
#ifdef CONFIG_DEBUG_FS
char *balls[OMAP_MUX_NR_SIDES];
- struct omap_mux_partition *partition;
#endif
#endif
};
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 2/7] OMAP: mux: Add support for control module split in several partitions
2010-11-15 20:03 ` Tony Lindgren
@ 2010-11-15 21:46 ` Cousson, Benoit
2010-11-16 16:41 ` Tony Lindgren
0 siblings, 1 reply; 14+ messages in thread
From: Cousson, Benoit @ 2010-11-15 21:46 UTC (permalink / raw)
To: Tony Lindgren
Cc: linux-omap@vger.kernel.org, Paul Walmsley, Kevin Hilman,
Shilimkar, Santosh
Hi Tony,
On 11/15/2010 9:03 PM, Tony Lindgren wrote:
> * Benoit Cousson<b-cousson@ti.com> [101111 13:26]:
>> Starting on OMAP4, the pin mux configuration is located in two
>> different partitions of the control module (CODE_PAD and WKUP_PAD).
>> The first one is inside the core power domain whereas the second
>> one is inside the wakeup.
>> - Add the capability to add any number of partition during board init
>> time depending of Soc partitioning.
>> - Add some init flags as well in order to avoid explicit Soc version
>> check inside the mux core code.
>> - Add a comment with mux0 mode on top of omap_mux/board/<partition>
>> if the current mux mode is not the default one.
>
> Here's one more patch that I'd like to merge into this patch to avoid
> repeating the partition for each mux entry.
The memory vendors will not like you ;-)
> Assuming no more comments, I'll queue these for 2.6.38 merge window.
I'll update the series and re-post tomorrow.
Thanks,
Benoit
>
> Regards,
>
> Tony
>
>
> From: Tony Lindgren<tony@atomide.com>
> Date: Mon, 15 Nov 2010 11:52:20 -0800
> Subject: [PATCH] omap: mux: Save memory for struct omap_mux
>
> There's no need to repeat the partition for each mux entry.
> We can look up the partition for debugfs.
>
> Signed-off-by: Tony Lindgren<tony@atomide.com>
>
> --- a/arch/arm/mach-omap2/mux.c
> +++ b/arch/arm/mach-omap2/mux.c
> @@ -348,14 +348,37 @@ static const struct file_operations omap_mux_dbg_board_fops = {
> .release = single_release,
> };
>
> +static struct omap_mux_partition * omap_mux_get_partition(struct omap_mux *mux)
> +{
> + struct omap_mux_partition *partition;
> +
> + list_for_each_entry(partition,&mux_partitions, node) {
> + struct list_head *muxmodes =&partition->muxmodes;
> + struct omap_mux_entry *e;
> +
> + list_for_each_entry(e, muxmodes, node) {
> + struct omap_mux *m =&e->mux;
> +
> + if (m == mux)
> + return partition;
> + }
> + }
> +
> + return NULL;
> +}
> +
> static int omap_mux_dbg_signal_show(struct seq_file *s, void *unused)
> {
> struct omap_mux *m = s->private;
> - struct omap_mux_partition *partition = m->partition;
> + struct omap_mux_partition *partition;
> const char *none = "NA";
> u16 val;
> int mode;
>
> + partition = omap_mux_get_partition(m);
> + if (!partition)
> + return 0;
> +
> val = omap_mux_read(partition, m->reg_offset);
> mode = val& OMAP_MUX_MODE7;
>
> @@ -391,6 +414,7 @@ static ssize_t omap_mux_dbg_signal_write(struct file *file,
> struct omap_mux *m;
> unsigned long val;
> int buf_size, ret;
> + struct omap_mux_partition *partition;
>
> if (count> OMAP_MUX_MAX_ARG_CHAR)
> return -EINVAL;
> @@ -411,7 +435,11 @@ static ssize_t omap_mux_dbg_signal_write(struct file *file,
> seqf = file->private_data;
> m = seqf->private;
>
> - omap_mux_write(m->partition, (u16)val, m->reg_offset);
> + partition = omap_mux_get_partition(m);
> + if (!partition)
> + return -ENODEV;
> +
> + omap_mux_write(partition, (u16)val, m->reg_offset);
> *ppos += count;
>
> return count;
> @@ -440,7 +468,6 @@ static void __init omap_mux_dbg_create_entry(
>
> list_for_each_entry(e,&partition->muxmodes, node) {
> struct omap_mux *m =&e->mux;
> - m->partition = partition;
>
> (void)debugfs_create_file(m->muxnames[0], S_IWUGO, mux_dbg_dir,
> m,&omap_mux_dbg_signal_fops);
> --- a/arch/arm/mach-omap2/mux.h
> +++ b/arch/arm/mach-omap2/mux.h
> @@ -121,7 +121,6 @@ struct omap_mux {
> char *muxnames[OMAP_MUX_NR_MODES];
> #ifdef CONFIG_DEBUG_FS
> char *balls[OMAP_MUX_NR_SIDES];
> - struct omap_mux_partition *partition;
> #endif
> #endif
> };
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 2/7] OMAP: mux: Add support for control module split in several partitions
2010-11-15 21:46 ` Cousson, Benoit
@ 2010-11-16 16:41 ` Tony Lindgren
2010-11-16 17:03 ` Cousson, Benoit
0 siblings, 1 reply; 14+ messages in thread
From: Tony Lindgren @ 2010-11-16 16:41 UTC (permalink / raw)
To: Cousson, Benoit
Cc: linux-omap@vger.kernel.org, Paul Walmsley, Kevin Hilman,
Shilimkar, Santosh
* Cousson, Benoit <b-cousson@ti.com> [101115 13:36]:
> Hi Tony,
>
> On 11/15/2010 9:03 PM, Tony Lindgren wrote:
> >* Benoit Cousson<b-cousson@ti.com> [101111 13:26]:
> >>Starting on OMAP4, the pin mux configuration is located in two
> >>different partitions of the control module (CODE_PAD and WKUP_PAD).
> >>The first one is inside the core power domain whereas the second
> >>one is inside the wakeup.
> >>- Add the capability to add any number of partition during board init
> >>time depending of Soc partitioning.
> >>- Add some init flags as well in order to avoid explicit Soc version
> >>check inside the mux core code.
> >>- Add a comment with mux0 mode on top of omap_mux/board/<partition>
> >>if the current mux mode is not the default one.
> >
> >Here's one more patch that I'd like to merge into this patch to avoid
> >repeating the partition for each mux entry.
>
> The memory vendors will not like you ;-)
>
> >Assuming no more comments, I'll queue these for 2.6.38 merge window.
>
> I'll update the series and re-post tomorrow.
Thanks, no need to post them again, I already have them queued
locally, they will hit for-next and linux-omap master today.
BTW, next time you do a git branch, please base it on Linus recent
-rc tag instead of linux-omap master branch. We don't want the
history of linux-omap master branch merged to the mainline tree..
Only if there are conflicts, then the git branches should be
based on some other static commit that needs to be agreed separately.
Regards,
Tony
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 2/7] OMAP: mux: Add support for control module split in several partitions
2010-11-16 16:41 ` Tony Lindgren
@ 2010-11-16 17:03 ` Cousson, Benoit
2010-11-16 17:37 ` Tony Lindgren
0 siblings, 1 reply; 14+ messages in thread
From: Cousson, Benoit @ 2010-11-16 17:03 UTC (permalink / raw)
To: Tony Lindgren
Cc: linux-omap@vger.kernel.org, Paul Walmsley, Kevin Hilman,
Shilimkar, Santosh
Hi Tony,
On 11/16/2010 5:41 PM, Tony Lindgren wrote:
> * Cousson, Benoit<b-cousson@ti.com> [101115 13:36]:
>> Hi Tony,
>>
>> On 11/15/2010 9:03 PM, Tony Lindgren wrote:
>>> * Benoit Cousson<b-cousson@ti.com> [101111 13:26]:
>>>> Starting on OMAP4, the pin mux configuration is located in two
>>>> different partitions of the control module (CODE_PAD and WKUP_PAD).
>>>> The first one is inside the core power domain whereas the second
>>>> one is inside the wakeup.
>>>> - Add the capability to add any number of partition during board init
>>>> time depending of Soc partitioning.
>>>> - Add some init flags as well in order to avoid explicit Soc version
>>>> check inside the mux core code.
>>>> - Add a comment with mux0 mode on top of omap_mux/board/<partition>
>>>> if the current mux mode is not the default one.
>>>
>>> Here's one more patch that I'd like to merge into this patch to avoid
>>> repeating the partition for each mux entry.
>>
>> The memory vendors will not like you ;-)
>>
>>> Assuming no more comments, I'll queue these for 2.6.38 merge window.
>>
>> I'll update the series and re-post tomorrow.
>
> Thanks, no need to post them again, I already have them queued
> locally, they will hit for-next and linux-omap master today.
OK, but I already did it because there is a checkpatch issue in your
first patch and I received another patch from Dan to add __func__ in the
pr_xxx macros.
I can repost, or you can get the update in my GIT (ctrl-wip/mux-omap4-v4).
> BTW, next time you do a git branch, please base it on Linus recent
> -rc tag instead of linux-omap master branch. We don't want the
> history of linux-omap master branch merged to the mainline tree..
Euh, this is what I already did for this series. Quoting myself:
"The series is based on mainline (2.6.37-rc1) and is available here:
git://gitorious.org/omap-pm/linux.git ctrl-wip/mux-omap4-v3"
Did I messed up something?
Regards,
Benoit
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 2/7] OMAP: mux: Add support for control module split in several partitions
2010-11-16 17:03 ` Cousson, Benoit
@ 2010-11-16 17:37 ` Tony Lindgren
2010-11-16 18:37 ` Cousson, Benoit
0 siblings, 1 reply; 14+ messages in thread
From: Tony Lindgren @ 2010-11-16 17:37 UTC (permalink / raw)
To: Cousson, Benoit
Cc: linux-omap@vger.kernel.org, Paul Walmsley, Kevin Hilman,
Shilimkar, Santosh
* Cousson, Benoit <b-cousson@ti.com> [101116 08:53]:
> Hi Tony,
>
> On 11/16/2010 5:41 PM, Tony Lindgren wrote:
> >* Cousson, Benoit<b-cousson@ti.com> [101115 13:36]:
> >>Hi Tony,
> >>
> >>On 11/15/2010 9:03 PM, Tony Lindgren wrote:
> >>>* Benoit Cousson<b-cousson@ti.com> [101111 13:26]:
> >>>>Starting on OMAP4, the pin mux configuration is located in two
> >>>>different partitions of the control module (CODE_PAD and WKUP_PAD).
> >>>>The first one is inside the core power domain whereas the second
> >>>>one is inside the wakeup.
> >>>>- Add the capability to add any number of partition during board init
> >>>>time depending of Soc partitioning.
> >>>>- Add some init flags as well in order to avoid explicit Soc version
> >>>>check inside the mux core code.
> >>>>- Add a comment with mux0 mode on top of omap_mux/board/<partition>
> >>>>if the current mux mode is not the default one.
> >>>
> >>>Here's one more patch that I'd like to merge into this patch to avoid
> >>>repeating the partition for each mux entry.
> >>
> >>The memory vendors will not like you ;-)
> >>
> >>>Assuming no more comments, I'll queue these for 2.6.38 merge window.
> >>
> >>I'll update the series and re-post tomorrow.
> >
> >Thanks, no need to post them again, I already have them queued
> >locally, they will hit for-next and linux-omap master today.
>
> OK, but I already did it because there is a checkpatch issue in your
> first patch and I received another patch from Dan to add __func__ in
> the pr_xxx macros.
> I can repost, or you can get the update in my GIT (ctrl-wip/mux-omap4-v4).
OK, if they're changed maybe repost the whole series one more time,
and then I'll merge in your branch assuming no more comments.
> >BTW, next time you do a git branch, please base it on Linus recent
> >-rc tag instead of linux-omap master branch. We don't want the
> >history of linux-omap master branch merged to the mainline tree..
>
> Euh, this is what I already did for this series. Quoting myself:
>
> "The series is based on mainline (2.6.37-rc1) and is available here:
> git://gitorious.org/omap-pm/linux.git ctrl-wip/mux-omap4-v3"
>
> Did I messed up something?
No, mux-omap4-v4 branch looks OK. I guess what I tried pulling
was something older.
Regards,
Tony
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 2/7] OMAP: mux: Add support for control module split in several partitions
2010-11-16 17:37 ` Tony Lindgren
@ 2010-11-16 18:37 ` Cousson, Benoit
0 siblings, 0 replies; 14+ messages in thread
From: Cousson, Benoit @ 2010-11-16 18:37 UTC (permalink / raw)
To: Tony Lindgren
Cc: linux-omap@vger.kernel.org, Paul Walmsley, Kevin Hilman,
Shilimkar, Santosh
On 11/16/2010 6:37 PM, Tony Lindgren wrote:
> * Cousson, Benoit<b-cousson@ti.com> [101116 08:53]:
>> Hi Tony,
>>
>> On 11/16/2010 5:41 PM, Tony Lindgren wrote:
>>> * Cousson, Benoit<b-cousson@ti.com> [101115 13:36]:
>>>> Hi Tony,
>>>>
>>>> On 11/15/2010 9:03 PM, Tony Lindgren wrote:
>>>>> * Benoit Cousson<b-cousson@ti.com> [101111 13:26]:
>>>>>> Starting on OMAP4, the pin mux configuration is located in two
>>>>>> different partitions of the control module (CODE_PAD and WKUP_PAD).
>>>>>> The first one is inside the core power domain whereas the second
>>>>>> one is inside the wakeup.
>>>>>> - Add the capability to add any number of partition during board init
>>>>>> time depending of Soc partitioning.
>>>>>> - Add some init flags as well in order to avoid explicit Soc version
>>>>>> check inside the mux core code.
>>>>>> - Add a comment with mux0 mode on top of omap_mux/board/<partition>
>>>>>> if the current mux mode is not the default one.
>>>>>
>>>>> Here's one more patch that I'd like to merge into this patch to avoid
>>>>> repeating the partition for each mux entry.
>>>>
>>>> The memory vendors will not like you ;-)
>>>>
>>>>> Assuming no more comments, I'll queue these for 2.6.38 merge window.
>>>>
>>>> I'll update the series and re-post tomorrow.
>>>
>>> Thanks, no need to post them again, I already have them queued
>>> locally, they will hit for-next and linux-omap master today.
>>
>> OK, but I already did it because there is a checkpatch issue in your
>> first patch and I received another patch from Dan to add __func__ in
>> the pr_xxx macros.
>> I can repost, or you can get the update in my GIT (ctrl-wip/mux-omap4-v4).
>
> OK, if they're changed maybe repost the whole series one more time,
> and then I'll merge in your branch assuming no more comments.
>
>>> BTW, next time you do a git branch, please base it on Linus recent
>>> -rc tag instead of linux-omap master branch. We don't want the
>>> history of linux-omap master branch merged to the mainline tree..
>>
>> Euh, this is what I already did for this series. Quoting myself:
>>
>> "The series is based on mainline (2.6.37-rc1) and is available here:
>> git://gitorious.org/omap-pm/linux.git ctrl-wip/mux-omap4-v3"
>>
>> Did I messed up something?
>
> No, mux-omap4-v4 branch looks OK. I guess what I tried pulling
> was something older.
The v2 was done before the 2.6.37-rc1 and was dependent of the ES2
support that's why it was based on l-o/master. Starting on v3, I rebased
everything on mainline.
I'll post the v4 revision.
Benoit
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2010-11-16 18:37 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2010-11-11 21:35 [PATCH 0/7] OMAP4: mux: Add the OMAP4430 ES1.0 & ES2.x support Benoit Cousson
2010-11-11 21:35 ` [PATCH 1/7] OMAP: mux: Replace printk with pr_xxx macros Benoit Cousson
2010-11-11 21:35 ` [PATCH 2/7] OMAP: mux: Add support for control module split in several partitions Benoit Cousson
2010-11-15 20:03 ` Tony Lindgren
2010-11-15 21:46 ` Cousson, Benoit
2010-11-16 16:41 ` Tony Lindgren
2010-11-16 17:03 ` Cousson, Benoit
2010-11-16 17:37 ` Tony Lindgren
2010-11-16 18:37 ` Cousson, Benoit
2010-11-11 21:35 ` [PATCH 3/7] OMAP4: mux: Add CBL package data for OMAP4430 ES1 Benoit Cousson
2010-11-11 21:35 ` [PATCH 4/7] OMAP4: sdp4430: Select CBL package for ES1 and initialize mux Benoit Cousson
2010-11-11 21:35 ` [PATCH 5/7] OMAP4: mux: Add CBS package data for OMAP4430 ES2 Benoit Cousson
2010-11-11 21:35 ` [PATCH 6/7] OMAP4: sdp4430: Select CBS package for ES2 Benoit Cousson
2010-11-11 21:35 ` [PATCH 7/7] OMAP4: pandaboard: Select CBL & CBS package and initialize mux Benoit Cousson
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