Re: [PATCH 4/5 v2] OMAP3630: PM: Disable L2 cache while invalidating L2 cache

[Nishanth Menon <nm@ti.com>]

Varadarajan, Charulatha had written, on 11/30/2010 12:12 AM, the following:

>> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
>> index bd426cc..e0ade5f 100644
>> --- a/arch/arm/mach-omap2/pm34xx.c
>> +++ b/arch/arm/mach-omap2/pm34xx.c
>> @@ -988,6 +988,9 @@ static void pm_errata_configure(void)
>>        if (cpu_is_omap34xx()) {
>>                if (cpu_is_omap3630())
>>                        pm34xx_errata |= RTA_ERRATUM_i608;
>> +               /* Enable the l2 cache toggling in sleep logic */
>> +               if (cpu_is_omap3630())
>> +                       enable_omap3630_toggle_l2_on_restore();
> 
> 
> This can simply be like this:
> ...
> ...
> -         if (cpu_is_omap3630())
> +         if (cpu_is_omap3630()) {
>                          pm34xx_errata |= RTA_ERRATUM_i608;
> +                        /* Enable the l2 cache toggling in sleep logic */
> +                       enable_omap3630_toggle_l2_on_restore();
> +          }
There are two ways to arrange code there:
a) based on silicon revision enable all erratas
b) arrange it per errata case

In the original series there are additional erratas like the uart one 
which basically makes (a) a dirty implementation. I chose to go with 
(b). but personally, I am open to either and have no strong feeling abt 
it. mebbe others can also comment as to which way you'd like to see this 
organized.


-- 
Regards,
Nishanth Menon