* [PATCH 1/4] OMAP: DSS2: Adding dss_features for independent core clk divider
2011-02-03 14:09 [PATCH 0/4] OMAP: DSS2: Fix for DISPC core functional clock divider Raghuveer Murthy
@ 2011-02-03 14:09 ` Raghuveer Murthy
2011-02-03 14:09 ` [PATCH 2/4] OMAP: DSS2: Renaming register macro DISPC_DIVISOR(ch) Raghuveer Murthy
` (2 subsequent siblings)
3 siblings, 0 replies; 8+ messages in thread
From: Raghuveer Murthy @ 2011-02-03 14:09 UTC (permalink / raw)
To: tomba; +Cc: linux-omap
In OMAP3xxx DISPC_DIVISOR register has a logical clock divisor (lcd_div)
field. The lcd_div is common, for deciding the DISPC core functional clock
frequency, and the final pixel clock frequency for LCD display.
In OMAP4, there are 2 LCD channels, hence two divisor registers, DISPC_DIVISOR1
and DISPC_DIVISOR2. Also, there is a third register DISPC_DIVISOR.
The DISPC_DIVISOR in OMAP4 is used to configure lcd_div exclusively for core
functional clock configuration. For pixel clock configuration of primary and
secondary LCDs, lcd_div of DISPC_DIVISOR1 and DISPC_DIVISOR2 are used
respectively
Signed-off-by: Archit Taneja <archit@ti.com>
Signed-off-by: Raghuveer Murthy <raghuveer.murthy@ti.com>
---
drivers/video/omap2/dss/dss_features.c | 2 +-
drivers/video/omap2/dss/dss_features.h | 2 ++
2 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/drivers/video/omap2/dss/dss_features.c b/drivers/video/omap2/dss/dss_features.c
index 4630f0c..39864f6 100644
--- a/drivers/video/omap2/dss/dss_features.c
+++ b/drivers/video/omap2/dss/dss_features.c
@@ -191,7 +191,7 @@ static struct omap_dss_features omap4_dss_features = {
.has_feature =
FEAT_GLOBAL_ALPHA | FEAT_PRE_MULT_ALPHA |
FEAT_MGR_LCD2 | FEAT_VAR_DPLL_FCK |
- FEAT_DPLL_FCK_32_DIV,
+ FEAT_DPLL_FCK_32_DIV | FEAT_CORE_CLK_DIV,
.num_mgrs = 3,
.num_ovls = 3,
diff --git a/drivers/video/omap2/dss/dss_features.h b/drivers/video/omap2/dss/dss_features.h
index 76b5fce..ed5c880 100644
--- a/drivers/video/omap2/dss/dss_features.h
+++ b/drivers/video/omap2/dss/dss_features.h
@@ -37,6 +37,8 @@ enum dss_feat_id {
FEAT_VAR_DPLL_FCK = 1 << 9, /* Variable DPLL Func CLK */
/* DPLL FCLK has max divider value 32 */
FEAT_DPLL_FCK_32_DIV = 1 << 10,
+ /* Independent core clk divider */
+ FEAT_CORE_CLK_DIV = 1 << 11,
};
/* DSS register field id */
--
1.7.0.4
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH 2/4] OMAP: DSS2: Renaming register macro DISPC_DIVISOR(ch)
2011-02-03 14:09 [PATCH 0/4] OMAP: DSS2: Fix for DISPC core functional clock divider Raghuveer Murthy
2011-02-03 14:09 ` [PATCH 1/4] OMAP: DSS2: Adding dss_features for independent core clk divider Raghuveer Murthy
@ 2011-02-03 14:09 ` Raghuveer Murthy
2011-02-16 15:38 ` [2/4] " Tomi Valkeinen
2011-02-03 14:09 ` [PATCH 3/4] OMAP: DSS2: Adding macro for DISPC_DIVISOR register Raghuveer Murthy
2011-02-03 14:09 ` [PATCH 4/4] OMAP4: DSS2: Using dss_features to set independent core clock divider Raghuveer Murthy
3 siblings, 1 reply; 8+ messages in thread
From: Raghuveer Murthy @ 2011-02-03 14:09 UTC (permalink / raw)
To: tomba; +Cc: linux-omap
Renamed DISPC_DIVISOR(ch) to DISPC_DIVISORo(ch), to facilitate introduction
of DISPC_DIVISOR register, which is specific for OMAP4. OMAP4 has 3 registers
DISPC_DIVISOR, DISPC_DIVISOR1 and DISPC_DIVISOR2.
Also updated, all the usages of DISPC_DIVISOR(ch) to DISPC_DIVISORo(ch).
OMAP4 TRM uses DISPC_DIVISORo generically to refer to DISPC_DIVISOR1 and
DISPC_DIVISOR2
Signed-off-by: Raghuveer Murthy <raghuveer.murthy@ti.com>
---
drivers/video/omap2/dss/dispc.c | 31 ++++++++++++++++++-------------
1 files changed, 18 insertions(+), 13 deletions(-)
diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
index cc58208..e52a413 100644
--- a/drivers/video/omap2/dss/dispc.c
+++ b/drivers/video/omap2/dss/dispc.c
@@ -72,7 +72,12 @@ struct dispc_reg { u16 idx; };
#define DISPC_TIMING_H(ch) DISPC_REG(ch != 2 ? 0x0064 : 0x0400)
#define DISPC_TIMING_V(ch) DISPC_REG(ch != 2 ? 0x0068 : 0x0404)
#define DISPC_POL_FREQ(ch) DISPC_REG(ch != 2 ? 0x006C : 0x0408)
-#define DISPC_DIVISOR(ch) DISPC_REG(ch != 2 ? 0x0070 : 0x040C)
+/*
+ * Use DISPC_DIVISORo(ch) when DISPC_DIVISOR1 or DISPC_DIVISOR2 has to be
+ * configured. OMAP4 TRM uses DISPC_DIVISORo generically to refer DISPC_DIVISOR1
+ * and DISPC_DIVISOR2
+ */
+#define DISPC_DIVISORo(ch) DISPC_REG(ch != 2 ? 0x0070 : 0x040C)
#define DISPC_GLOBAL_ALPHA DISPC_REG(0x0074)
#define DISPC_SIZE_DIG DISPC_REG(0x0078)
#define DISPC_SIZE_LCD(ch) DISPC_REG(ch != 2 ? 0x007C : 0x03CC)
@@ -229,7 +234,7 @@ void dispc_save_context(void)
SR(TIMING_H(0));
SR(TIMING_V(0));
SR(POL_FREQ(0));
- SR(DIVISOR(0));
+ SR(DIVISORo(0));
SR(GLOBAL_ALPHA);
SR(SIZE_DIG);
SR(SIZE_LCD(0));
@@ -241,7 +246,7 @@ void dispc_save_context(void)
SR(TIMING_H(2));
SR(TIMING_V(2));
SR(POL_FREQ(2));
- SR(DIVISOR(2));
+ SR(DIVISORo(2));
SR(CONFIG2);
}
@@ -388,7 +393,7 @@ void dispc_restore_context(void)
RR(TIMING_H(0));
RR(TIMING_V(0));
RR(POL_FREQ(0));
- RR(DIVISOR(0));
+ RR(DIVISORo(0));
RR(GLOBAL_ALPHA);
RR(SIZE_DIG);
RR(SIZE_LCD(0));
@@ -399,7 +404,7 @@ void dispc_restore_context(void)
RR(TIMING_H(2));
RR(TIMING_V(2));
RR(POL_FREQ(2));
- RR(DIVISOR(2));
+ RR(DIVISORo(2));
RR(CONFIG2);
}
@@ -2292,7 +2297,7 @@ static void dispc_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
BUG_ON(pck_div < 2);
enable_clocks(1);
- dispc_write_reg(DISPC_DIVISOR(channel),
+ dispc_write_reg(DISPC_DIVISORo(channel),
FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
enable_clocks(0);
}
@@ -2301,7 +2306,7 @@ static void dispc_get_lcd_divisor(enum omap_channel channel, int *lck_div,
int *pck_div)
{
u32 l;
- l = dispc_read_reg(DISPC_DIVISOR(channel));
+ l = dispc_read_reg(DISPC_DIVISORo(channel));
*lck_div = FLD_GET(l, 23, 16);
*pck_div = FLD_GET(l, 7, 0);
}
@@ -2327,7 +2332,7 @@ unsigned long dispc_lclk_rate(enum omap_channel channel)
unsigned long r;
u32 l;
- l = dispc_read_reg(DISPC_DIVISOR(channel));
+ l = dispc_read_reg(DISPC_DIVISORo(channel));
lcd = FLD_GET(l, 23, 16);
@@ -2342,7 +2347,7 @@ unsigned long dispc_pclk_rate(enum omap_channel channel)
unsigned long r;
u32 l;
- l = dispc_read_reg(DISPC_DIVISOR(channel));
+ l = dispc_read_reg(DISPC_DIVISORo(channel));
lcd = FLD_GET(l, 23, 16);
pcd = FLD_GET(l, 7, 0);
@@ -2458,7 +2463,7 @@ void dispc_dump_regs(struct seq_file *s)
DUMPREG(DISPC_TIMING_H(0));
DUMPREG(DISPC_TIMING_V(0));
DUMPREG(DISPC_POL_FREQ(0));
- DUMPREG(DISPC_DIVISOR(0));
+ DUMPREG(DISPC_DIVISORo(0));
DUMPREG(DISPC_GLOBAL_ALPHA);
DUMPREG(DISPC_SIZE_DIG);
DUMPREG(DISPC_SIZE_LCD(0));
@@ -2470,7 +2475,7 @@ void dispc_dump_regs(struct seq_file *s)
DUMPREG(DISPC_TIMING_H(2));
DUMPREG(DISPC_TIMING_V(2));
DUMPREG(DISPC_POL_FREQ(2));
- DUMPREG(DISPC_DIVISOR(2));
+ DUMPREG(DISPC_DIVISORo(2));
DUMPREG(DISPC_SIZE_LCD(2));
}
@@ -2712,8 +2717,8 @@ int dispc_get_clock_div(enum omap_channel channel,
fck = dispc_fclk_rate();
- cinfo->lck_div = REG_GET(DISPC_DIVISOR(channel), 23, 16);
- cinfo->pck_div = REG_GET(DISPC_DIVISOR(channel), 7, 0);
+ cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
+ cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
cinfo->lck = fck / cinfo->lck_div;
cinfo->pck = cinfo->lck / cinfo->pck_div;
--
1.7.0.4
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [2/4] OMAP: DSS2: Renaming register macro DISPC_DIVISOR(ch)
2011-02-03 14:09 ` [PATCH 2/4] OMAP: DSS2: Renaming register macro DISPC_DIVISOR(ch) Raghuveer Murthy
@ 2011-02-16 15:38 ` Tomi Valkeinen
0 siblings, 0 replies; 8+ messages in thread
From: Tomi Valkeinen @ 2011-02-16 15:38 UTC (permalink / raw)
To: Raghuveer Murthy; +Cc: linux-omap
Hi,
On Thu, 2011-02-03 at 14:09 +0000, Raghuveer Murthy wrote:
> Renamed DISPC_DIVISOR(ch) to DISPC_DIVISORo(ch), to facilitate introduction
> of DISPC_DIVISOR register, which is specific for OMAP4. OMAP4 has 3 registers
> DISPC_DIVISOR, DISPC_DIVISOR1 and DISPC_DIVISOR2.
>
> Also updated, all the usages of DISPC_DIVISOR(ch) to DISPC_DIVISORo(ch).
>
> OMAP4 TRM uses DISPC_DIVISORo generically to refer to DISPC_DIVISOR1 and
> DISPC_DIVISOR2
>
> Signed-off-by: Raghuveer Murthy <raghuveer.murthy@ti.com>
>
> ---
> drivers/video/omap2/dss/dispc.c | 31 ++++++++++++++++++-------------
> 1 files changed, 18 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
> index cc58208..e52a413 100644
> --- a/drivers/video/omap2/dss/dispc.c
> +++ b/drivers/video/omap2/dss/dispc.c
> @@ -72,7 +72,12 @@ struct dispc_reg { u16 idx; };
> #define DISPC_TIMING_H(ch) DISPC_REG(ch != 2 ? 0x0064 : 0x0400)
> #define DISPC_TIMING_V(ch) DISPC_REG(ch != 2 ? 0x0068 : 0x0404)
> #define DISPC_POL_FREQ(ch) DISPC_REG(ch != 2 ? 0x006C : 0x0408)
> -#define DISPC_DIVISOR(ch) DISPC_REG(ch != 2 ? 0x0070 : 0x040C)
> +/*
> + * Use DISPC_DIVISORo(ch) when DISPC_DIVISOR1 or DISPC_DIVISOR2 has to be
> + * configured. OMAP4 TRM uses DISPC_DIVISORo generically to refer DISPC_DIVISOR1
> + * and DISPC_DIVISOR2
> + */
While comments are good, I think this is extra. The purpose of the
register is clear from TRM. I like to keep the code clean of
trivialities =). The same goes for the register comment in the next
patch also.
You could mention this in the patch description though, so that patch
reviewing is easier.
And about DISPC_DIVISORo, I think the TRM writer has typoed it, he meant
to write DISPC_DIVISORi =). But let's stick with the naming from TRM.
Tomi
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 3/4] OMAP: DSS2: Adding macro for DISPC_DIVISOR register
2011-02-03 14:09 [PATCH 0/4] OMAP: DSS2: Fix for DISPC core functional clock divider Raghuveer Murthy
2011-02-03 14:09 ` [PATCH 1/4] OMAP: DSS2: Adding dss_features for independent core clk divider Raghuveer Murthy
2011-02-03 14:09 ` [PATCH 2/4] OMAP: DSS2: Renaming register macro DISPC_DIVISOR(ch) Raghuveer Murthy
@ 2011-02-03 14:09 ` Raghuveer Murthy
2011-02-16 15:43 ` [3/4] " Tomi Valkeinen
2011-02-03 14:09 ` [PATCH 4/4] OMAP4: DSS2: Using dss_features to set independent core clock divider Raghuveer Murthy
3 siblings, 1 reply; 8+ messages in thread
From: Raghuveer Murthy @ 2011-02-03 14:09 UTC (permalink / raw)
To: tomba; +Cc: linux-omap
Added macro for DISPC_DIVISOR. This is different from DISPC_DIVISOR1 and
DISPC_DIVISOR2. OMAP4 supports all the above 3 registers.
DISPC_DIVISOR1 and DISPC_DIVISOR2 registers are accessed through
DISPC_DIVISORo(ch) macro
Signed-off-by: Raghuveer Murthy <raghuveer.murthy@ti.com>
---
drivers/video/omap2/dss/dispc.c | 11 +++++++++++
1 files changed, 11 insertions(+), 0 deletions(-)
diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
index e52a413..6225d12 100644
--- a/drivers/video/omap2/dss/dispc.c
+++ b/drivers/video/omap2/dss/dispc.c
@@ -132,6 +132,17 @@ struct dispc_reg { u16 idx; };
#define DISPC_VID_PRELOAD(n) DISPC_REG(0x230 + (n)*0x04)
+/*
+ * The OMAP4 DISPC_DIVISOR1 is backward compatible to OMAP3xxx DISPC_DIVISOR.
+ * However DISPC_DIVISOR is also provided in OMAP4, to control DISPC_CORE_CLK.
+ * This allows DISPC_CORE_CLK to be independent of logical clock dividers (lcd)
+ * of LCD1 (primary) and LCD2 (secondary) displays.
+ *
+ * To derive pixel clocks for Primary and Secondary LCD channels, configure the
+ * lcd and pcd in DISPC_DIVISOR1 and DISPC_DIVISOR2 respectively, using the
+ * DISPC_DIVISORo(ch).
+ */
+#define DISPC_DIVISOR DISPC_REG(0x0804)
#define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
DISPC_IRQ_OCP_ERR | \
--
1.7.0.4
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [3/4] OMAP: DSS2: Adding macro for DISPC_DIVISOR register
2011-02-03 14:09 ` [PATCH 3/4] OMAP: DSS2: Adding macro for DISPC_DIVISOR register Raghuveer Murthy
@ 2011-02-16 15:43 ` Tomi Valkeinen
2011-02-17 7:17 ` Raghuveer Murthy
0 siblings, 1 reply; 8+ messages in thread
From: Tomi Valkeinen @ 2011-02-16 15:43 UTC (permalink / raw)
To: Raghuveer Murthy; +Cc: linux-omap
On Thu, 2011-02-03 at 14:09 +0000, Raghuveer Murthy wrote:
> Added macro for DISPC_DIVISOR. This is different from DISPC_DIVISOR1 and
> DISPC_DIVISOR2. OMAP4 supports all the above 3 registers.
>
> DISPC_DIVISOR1 and DISPC_DIVISOR2 registers are accessed through
> DISPC_DIVISORo(ch) macro
>
> Signed-off-by: Raghuveer Murthy <raghuveer.murthy@ti.com>
>
> ---
> drivers/video/omap2/dss/dispc.c | 11 +++++++++++
> 1 files changed, 11 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
> index e52a413..6225d12 100644
> --- a/drivers/video/omap2/dss/dispc.c
> +++ b/drivers/video/omap2/dss/dispc.c
> @@ -132,6 +132,17 @@ struct dispc_reg { u16 idx; };
>
> #define DISPC_VID_PRELOAD(n) DISPC_REG(0x230 + (n)*0x04)
>
> +/*
> + * The OMAP4 DISPC_DIVISOR1 is backward compatible to OMAP3xxx DISPC_DIVISOR.
> + * However DISPC_DIVISOR is also provided in OMAP4, to control DISPC_CORE_CLK.
> + * This allows DISPC_CORE_CLK to be independent of logical clock dividers (lcd)
> + * of LCD1 (primary) and LCD2 (secondary) displays.
> + *
> + * To derive pixel clocks for Primary and Secondary LCD channels, configure the
> + * lcd and pcd in DISPC_DIVISOR1 and DISPC_DIVISOR2 respectively, using the
> + * DISPC_DIVISORo(ch).
> + */
> +#define DISPC_DIVISOR DISPC_REG(0x0804)
>
> #define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
> DISPC_IRQ_OCP_ERR | \
See my comment about comments in previous mail.
I think you should merge this and the next patch. There's not much point
in adding a single line define, which is not used (yet).
How about the debug output from debug/omapdss/clk file? Does it print
sensible things on OMAP4 after these patches?
Tomi
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [3/4] OMAP: DSS2: Adding macro for DISPC_DIVISOR register
2011-02-16 15:43 ` [3/4] " Tomi Valkeinen
@ 2011-02-17 7:17 ` Raghuveer Murthy
0 siblings, 0 replies; 8+ messages in thread
From: Raghuveer Murthy @ 2011-02-17 7:17 UTC (permalink / raw)
To: Valkeinen, Tomi; +Cc: Murthy, Raghuveer, linux-omap@vger.kernel.org
On Wednesday 16 February 2011 09:13 PM, Valkeinen, Tomi wrote:
> On Thu, 2011-02-03 at 14:09 +0000, Raghuveer Murthy wrote:
>> Added macro for DISPC_DIVISOR. This is different from DISPC_DIVISOR1 and
>> DISPC_DIVISOR2. OMAP4 supports all the above 3 registers.
>>
>> DISPC_DIVISOR1 and DISPC_DIVISOR2 registers are accessed through
>> DISPC_DIVISORo(ch) macro
>>
>> Signed-off-by: Raghuveer Murthy<raghuveer.murthy@ti.com>
>>
>> ---
>> drivers/video/omap2/dss/dispc.c | 11 +++++++++++
>> 1 files changed, 11 insertions(+), 0 deletions(-)
>>
>> diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
>> index e52a413..6225d12 100644
>> --- a/drivers/video/omap2/dss/dispc.c
>> +++ b/drivers/video/omap2/dss/dispc.c
>> @@ -132,6 +132,17 @@ struct dispc_reg { u16 idx; };
>>
>> #define DISPC_VID_PRELOAD(n) DISPC_REG(0x230 + (n)*0x04)
>>
>> +/*
>> + * The OMAP4 DISPC_DIVISOR1 is backward compatible to OMAP3xxx DISPC_DIVISOR.
>> + * However DISPC_DIVISOR is also provided in OMAP4, to control DISPC_CORE_CLK.
>> + * This allows DISPC_CORE_CLK to be independent of logical clock dividers (lcd)
>> + * of LCD1 (primary) and LCD2 (secondary) displays.
>> + *
>> + * To derive pixel clocks for Primary and Secondary LCD channels, configure the
>> + * lcd and pcd in DISPC_DIVISOR1 and DISPC_DIVISOR2 respectively, using the
>> + * DISPC_DIVISORo(ch).
>> + */
>> +#define DISPC_DIVISOR DISPC_REG(0x0804)
>>
>> #define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
>> DISPC_IRQ_OCP_ERR | \
>
> See my comment about comments in previous mail.
>
> I think you should merge this and the next patch. There's not much point
> in adding a single line define, which is not used (yet).
>
> How about the debug output from debug/omapdss/clk file? Does it print
> sensible things on OMAP4 after these patches?
Will verify this.
>
> Tomi
>
>
Acknowledge the comments for patch 2/4 and 3/4. Will merge them and post
a new series.
Regards,
Raghuveer
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 4/4] OMAP4: DSS2: Using dss_features to set independent core clock divider
2011-02-03 14:09 [PATCH 0/4] OMAP: DSS2: Fix for DISPC core functional clock divider Raghuveer Murthy
` (2 preceding siblings ...)
2011-02-03 14:09 ` [PATCH 3/4] OMAP: DSS2: Adding macro for DISPC_DIVISOR register Raghuveer Murthy
@ 2011-02-03 14:09 ` Raghuveer Murthy
3 siblings, 0 replies; 8+ messages in thread
From: Raghuveer Murthy @ 2011-02-03 14:09 UTC (permalink / raw)
To: tomba; +Cc: linux-omap
Using dss_features to select independent core clock divider and setting
it. Added the register used, to DISPC context save and restore group
-----------------------------------------------------------------------
In OMAP4, the minimum DISPC_CORE_CLK required can be expressed as:
DISPC_CORE_CLK >= max(PCLK1*HSCALE1, PCLK2*HSCALE2, ...)
Where PCLKi is the pixel clock generated by MANAGERi and HSCALEi is the
maximum horizontal downscaling done through MANAGERi
Based on the usecase, core clk can be increased or decreased at runtime
to save power. Such mechanism are not yet implemented. Hence, we set the
core clock divisor to 1, to support maximum range of resolutions
------------------------------------------------------------------------
Signed-off-by: Raghuveer Murthy <raghuveer.murthy@ti.com>
---
drivers/video/omap2/dss/dispc.c | 15 +++++++++++++++
1 files changed, 15 insertions(+), 0 deletions(-)
diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
index 6225d12..cda1d2e 100644
--- a/drivers/video/omap2/dss/dispc.c
+++ b/drivers/video/omap2/dss/dispc.c
@@ -388,6 +388,9 @@ void dispc_save_context(void)
SR(VID_FIR_COEF_V(1, 7));
SR(VID_PRELOAD(1));
+
+ if (dss_has_feature(FEAT_CORE_CLK_DIV))
+ SR(DIVISOR);
}
void dispc_restore_context(void)
@@ -547,6 +550,9 @@ void dispc_restore_context(void)
RR(VID_PRELOAD(1));
+ if (dss_has_feature(FEAT_CORE_CLK_DIV))
+ RR(DIVISOR);
+
/* enable last, because LCD & DIGIT enable are here */
RR(CONTROL);
if (dss_has_feature(FEAT_MGR_LCD2))
@@ -3268,6 +3274,15 @@ static void _omap_dispc_initial_config(void)
l = FLD_MOD(l, 1, 0, 0); /* AUTOIDLE */
dispc_write_reg(DISPC_SYSCONFIG, l);
+ /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
+ if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
+ l = dispc_read_reg(DISPC_DIVISOR);
+ /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
+ l = FLD_MOD(l, 1, 0, 0);
+ l = FLD_MOD(l, 1, 23, 16);
+ dispc_write_reg(DISPC_DIVISOR, l);
+ }
+
/* FUNCGATED */
if (dss_has_feature(FEAT_FUNCGATED))
REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
--
1.7.0.4
^ permalink raw reply related [flat|nested] 8+ messages in thread