[PATCH 0/4] OMAP4: DSS2: Adding fclk support for DPI interface

[PATCH 0/4] OMAP4: DSS2: Adding fclk support for DPI interface

[Raghuveer Murthy]

- Adding dss_feature for DPLL fclk
- Enabling pixel clock generation for DPI interface

-----------------------------------------------------
Base
----
url = git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
branch "master"
commit 1bae4ce27c9c90344f23c65ea6966c50ffeae2f5
tag 2.6.38-rc2

Applies over:
-------------
1.
Patch mentioned in http://www.mail-archive.com/linux-omap@vger.kernel.org/msg42384.html
[PATCH] OMAP: counter_32k: init clocksource as part of machine timer init
(This patch is required for OMAP bootup)

2.
v10 of OMAP2,3 DSS2 HWMOD
https://patchwork.kernel.org/patch/500191/

3.
v3 of DSS2: Generalize clock names
https://patchwork.kernel.org/patch/520191/

4.
v3 of DSS2: OMAP4 DSS HWMOD :
https://patchwork.kernel.org/patch/511211/

5.
OMAP: DSS2: Common IRQ handler for all OMAPs
https://patchwork.kernel.org/patch/526241/
---------------------------------------------------------

Raghuveer Murthy (4):
  OMAP: DSS2: Add dss_feature for variable DPLL fclk
  OMAP: DSS: Renaming the dpll clk pointer in struct dss
  OMAP: DSS2: Using dss_features to clean cpu checks for clocks
  OMAP: DSS2: Get OMAP4 DPLL fclk for DPI interface

 drivers/video/omap2/dss/dss.c          |   85 +++++++++++++++++--------------
 drivers/video/omap2/dss/dss_features.c |    9 ++-
 drivers/video/omap2/dss/dss_features.h |    3 +
 3 files changed, 56 insertions(+), 41 deletions(-)

[PATCH 1/4] OMAP: DSS2: Add dss_feature for variable DPLL fclk

[Raghuveer Murthy]

This patch adds dss_feature for OMAP chips to distinguish between
those having a variable DPLL_PER functional clock (fclk). Additionally,
a feature for distiguishing the number of available dividers, 16 or 32,
for these fclk is added.

Signed-off-by: Archit Taneja <archit@ti.com>
Signed-off-by: Raghuveer Murthy <raghuveer.murthy@ti.com>
---
 drivers/video/omap2/dss/dss_features.c |    9 ++++++---
 drivers/video/omap2/dss/dss_features.h |    3 +++
 2 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/video/omap2/dss/dss_features.c b/drivers/video/omap2/dss/dss_features.c
index f3ef929..4630f0c 100644
--- a/drivers/video/omap2/dss/dss_features.c
+++ b/drivers/video/omap2/dss/dss_features.c
@@ -157,7 +157,8 @@ static struct omap_dss_features omap3430_dss_features = {
 	.has_feature	=
 		FEAT_GLOBAL_ALPHA | FEAT_LCDENABLEPOL |
 		FEAT_LCDENABLESIGNAL | FEAT_PCKFREEENABLE |
-		FEAT_FUNCGATED | FEAT_COMMON_IRQ_DISPC_DSI,
+		FEAT_FUNCGATED | FEAT_COMMON_IRQ_DISPC_DSI |
+		FEAT_VAR_DPLL_FCK,
 
 	.num_mgrs = 2,
 	.num_ovls = 3,
@@ -173,7 +174,8 @@ static struct omap_dss_features omap3630_dss_features = {
 		FEAT_GLOBAL_ALPHA | FEAT_LCDENABLEPOL |
 		FEAT_LCDENABLESIGNAL | FEAT_PCKFREEENABLE |
 		FEAT_PRE_MULT_ALPHA | FEAT_FUNCGATED |
-		FEAT_COMMON_IRQ_DISPC_DSI,
+		FEAT_COMMON_IRQ_DISPC_DSI | FEAT_VAR_DPLL_FCK |
+		FEAT_DPLL_FCK_32_DIV,
 
 	.num_mgrs = 2,
 	.num_ovls = 3,
@@ -188,7 +190,8 @@ static struct omap_dss_features omap4_dss_features = {
 
 	.has_feature	=
 		FEAT_GLOBAL_ALPHA | FEAT_PRE_MULT_ALPHA |
-		FEAT_MGR_LCD2,
+		FEAT_MGR_LCD2 | FEAT_VAR_DPLL_FCK |
+		FEAT_DPLL_FCK_32_DIV,
 
 	.num_mgrs = 3,
 	.num_ovls = 3,
diff --git a/drivers/video/omap2/dss/dss_features.h b/drivers/video/omap2/dss/dss_features.h
index 1c93a49..76b5fce 100644
--- a/drivers/video/omap2/dss/dss_features.h
+++ b/drivers/video/omap2/dss/dss_features.h
@@ -34,6 +34,9 @@ enum dss_feat_id {
 	FEAT_FUNCGATED			= 1 << 6,
 	FEAT_MGR_LCD2			= 1 << 7,
 	FEAT_COMMON_IRQ_DISPC_DSI	= 1 << 8,
+	FEAT_VAR_DPLL_FCK		= 1 << 9, /* Variable DPLL Func CLK */
+	/* DPLL FCLK has max divider value 32 */
+	FEAT_DPLL_FCK_32_DIV		= 1 << 10,
 };
 
 /* DSS register field id */
-- 
1.7.0.4

[PATCH 2/4] OMAP: DSS: Renaming the dpll clk pointer in struct dss

[Raghuveer Murthy]

The dss clk pointer dpll4_m4_ck is renamed to dpll_per_mx_ck, to be
generic for OMAP3xxx and OMAP44xx platforms. Variable and function
names containing dpll4/ dpll4_m4 are also renamed.

Signed-off-by: Raghuveer Murthy <raghuveer.murthy@ti.com>
---
 drivers/video/omap2/dss/dss.c |   43 +++++++++++++++++++++--------------------
 1 files changed, 22 insertions(+), 21 deletions(-)

diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c
index 24d6f98..add82e6 100644
--- a/drivers/video/omap2/dss/dss.c
+++ b/drivers/video/omap2/dss/dss.c
@@ -64,7 +64,8 @@ static struct {
 	int             ctx_id;
 	int		irq;
 
-	struct clk	*dpll4_m4_ck;
+	/* Points to DPLL4_M4 in OMAP3xxx, and DPLL_PER_M5 in OMAP44xx */
+	struct clk	*dpll_per_mx_ck;
 	struct clk	*dss_ick;
 	struct clk	*dss_fck;
 	struct clk	*dss_sys_clk;
@@ -225,27 +226,27 @@ void dss_sdi_disable(void)
 
 void dss_dump_clocks(struct seq_file *s)
 {
-	unsigned long dpll4_ck_rate;
-	unsigned long dpll4_m4_ck_rate;
+	unsigned long dpll_per_ck_rate;
+	unsigned long dpll_per_mx_ck_rate;
 
 	dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
 
-	dpll4_ck_rate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
-	dpll4_m4_ck_rate = clk_get_rate(dss.dpll4_m4_ck);
+	dpll_per_ck_rate = clk_get_rate(clk_get_parent(dss.dpll_per_mx_ck));
+	dpll_per_mx_ck_rate = clk_get_rate(dss.dpll_per_mx_ck);
 
 	seq_printf(s, "- DSS -\n");
 
-	seq_printf(s, "dpll4_ck %lu\n", dpll4_ck_rate);
+	seq_printf(s, "dpll_per_ck %lu\n", dpll_per_ck_rate);
 
 	if (cpu_is_omap3630())
 		seq_printf(s, "dss1_alwon_fclk = %lu / %lu  = %lu\n",
-			dpll4_ck_rate,
-			dpll4_ck_rate / dpll4_m4_ck_rate,
+			dpll_per_ck_rate,
+			dpll_per_ck_rate / dpll_per_mx_ck_rate,
 			dss_clk_get_rate(DSS_CLK_FCK));
 	else
 		seq_printf(s, "dss1_alwon_fclk = %lu / %lu * 2 = %lu\n",
-			dpll4_ck_rate,
-			dpll4_ck_rate / dpll4_m4_ck_rate,
+			dpll_per_ck_rate,
+			dpll_per_ck_rate / dpll_per_mx_ck_rate,
 			dss_clk_get_rate(DSS_CLK_FCK));
 
 	dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
@@ -323,7 +324,7 @@ int dss_calc_clock_rates(struct dss_clock_info *cinfo)
 						cinfo->fck_div == 0)
 		return -EINVAL;
 
-	prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
+	prate = clk_get_rate(clk_get_parent(dss.dpll_per_mx_ck));
 
 	cinfo->fck = prate / cinfo->fck_div;
 
@@ -336,10 +337,10 @@ int dss_set_clock_div(struct dss_clock_info *cinfo)
 	int r;
 
 	if (cpu_is_omap34xx()) {
-		prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
+		prate = clk_get_rate(clk_get_parent(dss.dpll_per_mx_ck));
 		DSSDBG("dpll4_m4 = %ld\n", prate);
 
-		r = clk_set_rate(dss.dpll4_m4_ck, prate / cinfo->fck_div);
+		r = clk_set_rate(dss.dpll_per_mx_ck, prate / cinfo->fck_div);
 		if (r)
 			return r;
 	}
@@ -355,7 +356,7 @@ int dss_get_clock_div(struct dss_clock_info *cinfo)
 
 	if (cpu_is_omap34xx()) {
 		unsigned long prate;
-		prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
+		prate = clk_get_rate(clk_get_parent(dss.dpll_per_mx_ck));
 		if (cpu_is_omap3630())
 			cinfo->fck_div = prate / (cinfo->fck);
 		else
@@ -367,10 +368,10 @@ int dss_get_clock_div(struct dss_clock_info *cinfo)
 	return 0;
 }
 
-unsigned long dss_get_dpll4_rate(void)
+unsigned long dss_get_dpll_per_rate(void)
 {
 	if (cpu_is_omap34xx())
-		return clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
+		return clk_get_rate(clk_get_parent(dss.dpll_per_mx_ck));
 	else
 		return 0;
 }
@@ -390,7 +391,7 @@ int dss_calc_clock_div(bool is_tft, unsigned long req_pck,
 	int match = 0;
 	int min_fck_per_pck;
 
-	prate = dss_get_dpll4_rate();
+	prate = dss_get_dpll_per_rate();
 
 	fck = dss_clk_get_rate(DSS_CLK_FCK);
 	if (req_pck == dss.cache_req_pck &&
@@ -620,10 +621,10 @@ static int dss_init(bool skip_init)
 	}
 
 	if (cpu_is_omap34xx()) {
-		dss.dpll4_m4_ck = clk_get(NULL, "dpll4_m4_ck");
-		if (IS_ERR(dss.dpll4_m4_ck)) {
+		dss.dpll_per_mx_ck = clk_get(NULL, "dpll4_m4_ck");
+		if (IS_ERR(dss.dpll_per_mx_ck)) {
 			DSSERR("Failed to get dpll4_m4_ck\n");
-			r = PTR_ERR(dss.dpll4_m4_ck);
+			r = PTR_ERR(dss.dpll_per_mx_ck);
 			goto fail2;
 		}
 	}
@@ -650,7 +651,7 @@ fail0:
 static void dss_exit(void)
 {
 	if (cpu_is_omap34xx())
-		clk_put(dss.dpll4_m4_ck);
+		clk_put(dss.dpll_per_mx_ck);
 
 	free_irq(dss.irq, NULL);
 
-- 
1.7.0.4

[PATCH 3/4] OMAP: DSS2: Using dss_features to clean cpu checks for clocks

[Raghuveer Murthy]

dss_features are used to substitute cpu_is_xxxx() checks for DPLL clock source

Signed-off-by: Raghuveer Murthy <raghuveer.murthy@ti.com>
---
 drivers/video/omap2/dss/dss.c |   35 ++++++++++++++++++-----------------
 1 files changed, 18 insertions(+), 17 deletions(-)

diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c
index add82e6..654f5e6 100644
--- a/drivers/video/omap2/dss/dss.c
+++ b/drivers/video/omap2/dss/dss.c
@@ -320,8 +320,9 @@ int dss_calc_clock_rates(struct dss_clock_info *cinfo)
 {
 	unsigned long prate;
 
-	if (cinfo->fck_div > (cpu_is_omap3630() ? 32 : 16) ||
-						cinfo->fck_div == 0)
+	if (cinfo->fck_div >
+		(dss_has_feature(FEAT_DPLL_FCK_32_DIV) ? 32 : 16) ||
+			cinfo->fck_div == 0)
 		return -EINVAL;
 
 	prate = clk_get_rate(clk_get_parent(dss.dpll_per_mx_ck));
@@ -336,9 +337,9 @@ int dss_set_clock_div(struct dss_clock_info *cinfo)
 	unsigned long prate;
 	int r;
 
-	if (cpu_is_omap34xx()) {
+	if (dss_has_feature(FEAT_VAR_DPLL_FCK)) {
 		prate = clk_get_rate(clk_get_parent(dss.dpll_per_mx_ck));
-		DSSDBG("dpll4_m4 = %ld\n", prate);
+		DSSDBG("dpll_per_mx parent rate = %ld\n", prate);
 
 		r = clk_set_rate(dss.dpll_per_mx_ck, prate / cinfo->fck_div);
 		if (r)
@@ -354,10 +355,10 @@ int dss_get_clock_div(struct dss_clock_info *cinfo)
 {
 	cinfo->fck = dss_clk_get_rate(DSS_CLK_FCK);
 
-	if (cpu_is_omap34xx()) {
+	if (dss_has_feature(FEAT_VAR_DPLL_FCK)) {
 		unsigned long prate;
 		prate = clk_get_rate(clk_get_parent(dss.dpll_per_mx_ck));
-		if (cpu_is_omap3630())
+		if (dss_has_feature(FEAT_DPLL_FCK_32_DIV))
 			cinfo->fck_div = prate / (cinfo->fck);
 		else
 			cinfo->fck_div = prate / (cinfo->fck / 2);
@@ -370,7 +371,7 @@ int dss_get_clock_div(struct dss_clock_info *cinfo)
 
 unsigned long dss_get_dpll_per_rate(void)
 {
-	if (cpu_is_omap34xx())
+	if (dss_has_feature(FEAT_VAR_DPLL_FCK))
 		return clk_get_rate(clk_get_parent(dss.dpll_per_mx_ck));
 	else
 		return 0;
@@ -395,8 +396,9 @@ int dss_calc_clock_div(bool is_tft, unsigned long req_pck,
 
 	fck = dss_clk_get_rate(DSS_CLK_FCK);
 	if (req_pck == dss.cache_req_pck &&
-			((cpu_is_omap34xx() && prate == dss.cache_prate) ||
-			 dss.cache_dss_cinfo.fck == fck)) {
+		((dss_has_feature(FEAT_VAR_DPLL_FCK) &&
+			prate == dss.cache_prate) ||
+			dss.cache_dss_cinfo.fck == fck)) {
 		DSSDBG("dispc clock info found from cache.\n");
 		*dss_cinfo = dss.cache_dss_cinfo;
 		*dispc_cinfo = dss.cache_dispc_cinfo;
@@ -417,7 +419,7 @@ retry:
 	memset(&best_dss, 0, sizeof(best_dss));
 	memset(&best_dispc, 0, sizeof(best_dispc));
 
-	if (cpu_is_omap24xx()) {
+	if (!dss_has_feature(FEAT_VAR_DPLL_FCK)) {
 		struct dispc_clock_info cur_dispc;
 		/* XXX can we change the clock on omap2? */
 		fck = dss_clk_get_rate(DSS_CLK_FCK);
@@ -432,12 +434,13 @@ retry:
 		best_dispc = cur_dispc;
 
 		goto found;
-	} else if (cpu_is_omap34xx()) {
-		for (fck_div = (cpu_is_omap3630() ? 32 : 16);
-					fck_div > 0; --fck_div) {
+	} else {
+		for (fck_div =
+			(dss_has_feature(FEAT_DPLL_FCK_32_DIV) ? 32 : 16);
+				fck_div > 0; --fck_div) {
 			struct dispc_clock_info cur_dispc;
 
-			if (cpu_is_omap3630())
+			if (dss_has_feature(FEAT_DPLL_FCK_32_DIV))
 				fck = prate / fck_div;
 			else
 				fck = prate / fck_div * 2;
@@ -465,8 +468,6 @@ retry:
 					goto found;
 			}
 		}
-	} else {
-		BUG();
 	}
 
 found:
@@ -650,7 +651,7 @@ fail0:
 
 static void dss_exit(void)
 {
-	if (cpu_is_omap34xx())
+	if (dss_has_feature(FEAT_VAR_DPLL_FCK))
 		clk_put(dss.dpll_per_mx_ck);
 
 	free_irq(dss.irq, NULL);
-- 
1.7.0.4

[PATCH 4/4] OMAP: DSS2: Get OMAP4 DPLL fclk for DPI interface

[Raghuveer Murthy]

DSS DPLL fclk pointer is set, to configure pixel clock for DPI interface.

Signed-off-by: Raghuveer Murthy <raghuveer.murthy@ti.com>
---
 drivers/video/omap2/dss/dss.c |    7 +++++++
 1 files changed, 7 insertions(+), 0 deletions(-)

diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c
index 654f5e6..d76bc26 100644
--- a/drivers/video/omap2/dss/dss.c
+++ b/drivers/video/omap2/dss/dss.c
@@ -628,6 +628,13 @@ static int dss_init(bool skip_init)
 			r = PTR_ERR(dss.dpll_per_mx_ck);
 			goto fail2;
 		}
+	} else if (cpu_is_omap44xx()) {
+		dss.dpll_per_mx_ck = clk_get(NULL, "dpll_per_m5x2_ck");
+		if (IS_ERR(dss.dpll_per_mx_ck)) {
+			DSSERR("Failed to get dpll_per_mx_ck\n");
+			r = PTR_ERR(dss.dpll_per_mx_ck);
+			goto fail2;
+		}
 	}
 
 	dss.dsi_clk_source = DSS_SRC_DSS1_ALWON_FCLK;
-- 
1.7.0.4

Re: [PATCH 0/4] OMAP4: DSS2: Adding fclk support for DPI interface

[Tomi Valkeinen]

Hi,

On Thu, 2011-02-03 at 07:56 -0600, Murthy, Raghuveer wrote:
> - Adding dss_feature for DPLL fclk
> - Enabling pixel clock generation for DPI interface

A bit more description what the patch set is about would be nice. Also,
one line patch descriptions are a bit too short for anything else than
the most trivial patches.

Now to the actual patch contents:

DPLL is not a feature of the DSS, and I don't think we should have
dss_features for that. In fact, I think the whole DPLL code should be
moved from DSS to somewhere under arch/arm.

In a perfect world DSS could just set the dss_fck to whatever rate it
requires, but as the clock rate can only be set to certain rates, and we
need a precise control for the rate, some other method has to be in
place.

I am not sure what this method should be. Perhaps there is something in
the clock framework that could help us here, or perhaps we just need a
bunch of function pointers in the DSS's platform data which can be used
to configure the clock.

 Tomi

Re: [PATCH 0/4] OMAP4: DSS2: Adding fclk support for DPI interface

[Raghuveer Murthy]

On Monday 14 February 2011 09:32 PM, Valkeinen, Tomi wrote:
> Hi,
>
> On Thu, 2011-02-03 at 07:56 -0600, Murthy, Raghuveer wrote:
>> - Adding dss_feature for DPLL fclk
>> - Enabling pixel clock generation for DPI interface
>
> A bit more description what the patch set is about would be nice. Also,
> one line patch descriptions are a bit too short for anything else than
> the most trivial patches.
>
> Now to the actual patch contents:
>
> DPLL is not a feature of the DSS, and I don't think we should have
> dss_features for that. In fact, I think the whole DPLL code should be
> moved from DSS to somewhere under arch/arm.
>
> In a perfect world DSS could just set the dss_fck to whatever rate it
> requires, but as the clock rate can only be set to certain rates, and we
> need a precise control for the rate, some other method has to be in
> place.
>
> I am not sure what this method should be. Perhaps there is something in
> the clock framework that could help us here, or perhaps we just need a
> bunch of function pointers in the DSS's platform data which can be used
> to configure the clock.
>
>   Tomi
>
>

Hi Paul, Benoit,

DPLL_PER post divider output for DSS core functional clock can be 
changed in OMAP3xxx and OMAP4430, based on the requested pixel clock for 
a given display resolution.

Additionally, the number of dividers available for DPLL_PER post 
dividors for DSS has increased from 16 to 32, from OMAP3630 onwards.

Both these are added as dss_features.

Given the above comments from Tomi, can the same be included as part of 
the clock framework?

Regards,
Raghuveer

Re: [PATCH 0/4] OMAP4: DSS2: Adding fclk support for DPI interface

[Cousson, Benoit]

Hi Murthy,

On 2/16/2011 9:57 AM, Murthy, Raghuveer wrote:
> On Monday 14 February 2011 09:32 PM, Valkeinen, Tomi wrote:
>> Hi,
>>
>> On Thu, 2011-02-03 at 07:56 -0600, Murthy, Raghuveer wrote:
>>> - Adding dss_feature for DPLL fclk
>>> - Enabling pixel clock generation for DPI interface
>>
>> A bit more description what the patch set is about would be nice. Also,
>> one line patch descriptions are a bit too short for anything else than
>> the most trivial patches.
>>
>> Now to the actual patch contents:
>>
>> DPLL is not a feature of the DSS, and I don't think we should have
>> dss_features for that. In fact, I think the whole DPLL code should be
>> moved from DSS to somewhere under arch/arm.
>>
>> In a perfect world DSS could just set the dss_fck to whatever rate it
>> requires, but as the clock rate can only be set to certain rates, and we
>> need a precise control for the rate, some other method has to be in
>> place.
>>
>> I am not sure what this method should be. Perhaps there is something in
>> the clock framework that could help us here, or perhaps we just need a
>> bunch of function pointers in the DSS's platform data which can be used
>> to configure the clock.
>>
>>    Tomi
>>
>>
>
> Hi Paul, Benoit,
>
> DPLL_PER post divider output for DSS core functional clock can be
> changed in OMAP3xxx and OMAP4430, based on the requested pixel clock for
> a given display resolution.
>
> Additionally, the number of dividers available for DPLL_PER post
> dividors for DSS has increased from 16 to 32, from OMAP3630 onwards.
>
> Both these are added as dss_features.
>
> Given the above comments from Tomi, can the same be included as part of
> the clock framework?

Yes, I do agree with Tomi, this code has nothing to do in the DSS driver.
We do have similar issue with clock rate that can be changed by 2 
successive clock nodes (DPLL and HS divider for example).

But it might be tricky to handle in a generic manner. We need to tie 
these two clock nodes and thus ensuring that there is no other 
descendant for the parent node and then force a parent rate change if 
the clock rate cannot be achieve by the descendant.

Maybe Paul has some idea about that.

Regards,
Benoit

Re: [PATCH 0/4] OMAP4: DSS2: Adding fclk support for DPI interface

[Paul Walmsley]

On Wed, 16 Feb 2011, Raghuveer Murthy wrote:

> On Monday 14 February 2011 09:32 PM, Valkeinen, Tomi wrote:
> > On Thu, 2011-02-03 at 07:56 -0600, Murthy, Raghuveer wrote:
> > > - Adding dss_feature for DPLL fclk
> > > - Enabling pixel clock generation for DPI interface
> > 
> > A bit more description what the patch set is about would be nice. Also,
> > one line patch descriptions are a bit too short for anything else than
> > the most trivial patches.
> > 
> > Now to the actual patch contents:
> > 
> > DPLL is not a feature of the DSS, and I don't think we should have
> > dss_features for that. In fact, I think the whole DPLL code should be
> > moved from DSS to somewhere under arch/arm.
> > 
> > In a perfect world DSS could just set the dss_fck to whatever rate it
> > requires, but as the clock rate can only be set to certain rates, and we
> > need a precise control for the rate, some other method has to be in
> > place.
> > 
> > I am not sure what this method should be. Perhaps there is something in
> > the clock framework that could help us here, or perhaps we just need a
> > bunch of function pointers in the DSS's platform data which can be used
> > to configure the clock.
> > 
> >   Tomi
> > 
> > 
> 
> Hi Paul, Benoit,
> 
> DPLL_PER post divider output for DSS core functional clock can be changed in
> OMAP3xxx and OMAP4430, based on the requested pixel clock for a given display
> resolution.
> 
> Additionally, the number of dividers available for DPLL_PER post dividors for
> DSS has increased from 16 to 32, from OMAP3630 onwards.
> 
> Both these are added as dss_features.
> 
> Given the above comments from Tomi, can the same be included as part of the
> clock framework?

Have you considered just calling clk_round_rate() on the DPLL_PER's output 
divider and seeing if you can get a rate that you're happy with?


- Paul

Re: [PATCH 0/4] OMAP4: DSS2: Adding fclk support for DPI interface

[Tomi Valkeinen]

On Thu, 2011-02-17 at 08:49 -0600, Paul Walmsley wrote:
> On Wed, 16 Feb 2011, Raghuveer Murthy wrote:
> 

<snip>

> > 
> > DPLL_PER post divider output for DSS core functional clock can be changed in
> > OMAP3xxx and OMAP4430, based on the requested pixel clock for a given display
> > resolution.
> > 
> > Additionally, the number of dividers available for DPLL_PER post dividors for
> > DSS has increased from 16 to 32, from OMAP3630 onwards.
> > 
> > Both these are added as dss_features.
> > 
> > Given the above comments from Tomi, can the same be included as part of the
> > clock framework?
> 
> Have you considered just calling clk_round_rate() on the DPLL_PER's output 
> divider and seeing if you can get a rate that you're happy with?

Hmm, yes, perhaps that would be possible.

Currently we iterate suitable clocks by going through all fck dividers,
then lck dividers and then pck dividers, and checking if one of the
resulting pixel clocks is close to the required one.

But we could start with the required pck, and go "up" from there with
pck dividers, lck dividers, and in the end using clk_round_rate() to see
if the set of dividers is possible.

And we know the maximum allowed fck rate, so we can use that as a
ceiling and forget any divider sets that lead to too high clocks.

This will probably need a bit more iterations, though, as we may be
trying multiple divider sets leading to the same fck rate, because the
code doesn't have any idea what the possible rates are.

I trust clk_round_rate() is quite simple function (ie. fast)?

 Tomi

Re: [PATCH 0/4] OMAP4: DSS2: Adding fclk support for DPI interface

[Raghuveer Murthy]

On Friday 18 February 2011 12:46 AM, Valkeinen, Tomi wrote:
> On Thu, 2011-02-17 at 08:49 -0600, Paul Walmsley wrote:
>> On Wed, 16 Feb 2011, Raghuveer Murthy wrote:
>>
>
> <snip>
>
>>>
>>> DPLL_PER post divider output for DSS core functional clock can be changed in
>>> OMAP3xxx and OMAP4430, based on the requested pixel clock for a given display
>>> resolution.
>>>
>>> Additionally, the number of dividers available for DPLL_PER post dividors for
>>> DSS has increased from 16 to 32, from OMAP3630 onwards.
>>>
>>> Both these are added as dss_features.
>>>
>>> Given the above comments from Tomi, can the same be included as part of the
>>> clock framework?
>>
>> Have you considered just calling clk_round_rate() on the DPLL_PER's output
>> divider and seeing if you can get a rate that you're happy with?
>
> Hmm, yes, perhaps that would be possible.
>
> Currently we iterate suitable clocks by going through all fck dividers,
> then lck dividers and then pck dividers, and checking if one of the
> resulting pixel clocks is close to the required one.
>
> But we could start with the required pck, and go "up" from there with
> pck dividers, lck dividers, and in the end using clk_round_rate() to see
> if the set of dividers is possible.
>
> And we know the maximum allowed fck rate, so we can use that as a
> ceiling and forget any divider sets that lead to too high clocks.
>
> This will probably need a bit more iterations, though, as we may be
> trying multiple divider sets leading to the same fck rate, because the
> code doesn't have any idea what the possible rates are.
>
> I trust clk_round_rate() is quite simple function (ie. fast)?
>
>   Tomi
>
>
I will look into this and come with a solution.

Regards,
Raghuveer