From: Raghuveer Murthy <x0075817@ti.com>
To: "Valkeinen, Tomi" <tomi.valkeinen@ti.com>
Cc: "Murthy, Raghuveer" <raghuveer.murthy@ti.com>,
"linux-omap@vger.kernel.org" <linux-omap@vger.kernel.org>
Subject: Re: [PATCH v1 0/3] OMAP: DSS2: Fix for DISPC core functional clock divider
Date: Thu, 3 Mar 2011 21:04:56 +0530 [thread overview]
Message-ID: <4D6FB520.20407@ti.com> (raw)
In-Reply-To: <1299158197.2615.117.camel@deskari>
On Thursday 03 March 2011 06:46 PM, Valkeinen, Tomi wrote:
> On Thu, 2011-03-03 at 15:25 +0530, Raghuveer Murthy wrote:
>> OMAP4 has 2 LCD channels and corresponding DISPC_DIVISOR1 and DISPC_DIVISOR2
>> registers to configure the pixel clock frequency, for the respective LCD
>> displays.
>>
>> There is also DISPC_DIVISOR register, which by default has the ENABLE bit
>> set to zero, for backward compatibility mode. Hence the logical clock divider of
>> DISPC_DIVISOR1.LCD, gets used for core func clk configuration. The default value
>> of DISPC_DIVISOR1.LCD is 4.
>>
>> If only the secondary LCD is enabled, at high pixel resolutions the core clk
>> lags behind the pixel clock, causing stair-step effect (diagonal lines with
>> tearing) on the display.
>>
>> Hence DISPC_DIVISOR.ENABLE is set to 1, and the core functional clock is set
>> independently and exclusively in DISPC_DIVISOR.LCD.
>
> I think this patch set is ok. However, it doesn't apply with the latest
> master branch from DSS tree, some quite trivial conflicts with dss
> features. Can you rebase and post it?
>
> Also, please send patches to my ti.com address, not iki.fi address.
>
> Tomi
>
>
Hi Tomi,
Resent the after re-basing.
Regards,
Raghuveer
next prev parent reply other threads:[~2011-03-03 15:34 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <1299152316.2615.91.camel@deskari>
2011-03-03 13:16 ` [PATCH v1 0/3] OMAP: DSS2: Fix for DISPC core functional clock divider Tomi Valkeinen
2011-03-03 15:34 ` Raghuveer Murthy [this message]
2011-03-03 9:55 Raghuveer Murthy
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