[PATCH 4/5] am3505/3517: UART4 fclk

[PATCH 4/5] am3505/3517: UART4 fclk

[Raphaël Assénat]

Add support for the AM35xx UART4 fclk. Based on information
found on TI's E2E forum.

Signed-off-by: Raphael Assenat <raph@8d.com>

diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index 75b119b..3706aaa 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -3179,10 +3179,18 @@ static struct clk vpfe_fck = {
 	.recalc		= &followparent_recalc,
 };
 
-/*
- * The UART1/2 functional clock acts as the functional
- * clock for UART4. No separate fclk control available.
- */
+/* Documented as 'reserved' in latest technical manual (July 2010), 
+ * bit 23 in CM_CLKEN1_CORE really seems to control the UART4 fclk.. */
+static struct clk uart4_fck_am35xx = {
+	.name		= "uart4_fck",
+	.ops		= &clkops_omap2_dflt,
+	.parent		= &core_48m_fck,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+	.enable_bit	= AM35XX_EN_UART4_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+	.recalc		= &followparent_recalc,
+};
+
 static struct clk uart4_ick_am35xx = {
 	.name		= "uart4_ick",
 	.ops		= &clkops_omap2_iclk_dflt_wait,
@@ -3462,6 +3470,7 @@ static struct omap_clk omap3xxx_clks[] = {
 	CLK("musb-am35x",	"fck",		&hsotgusb_fck_am35xx,	CK_AM35XX),
 	CLK(NULL,	"hecc_ck",	&hecc_ck,	CK_AM35XX),
 	CLK(NULL,	"uart4_ick",	&uart4_ick_am35xx,	CK_AM35XX),
+	CLK(NULL,	"uart4_fck",	&uart4_fck_am35xx,	CK_AM35XX),
 };