DSI lane configuration

DSI lane configuration

[Jerry Alexander]

Have a new board with the omap4  and toshiba bridge chipset.
The board has two lanes instead of four.
Removed   DSI_COMPLEXIO_CFG1  entries for data3_lane, data3_pol,
data4_lane, and data4_pol.
With 4 lanes configured we see traffic on the scope ,but  the toshiba
drops it since the board has only two lanes.
With 2 lanes configured we see no traffic.
Cannot other fields in the omap required to reconfigure for 2 lanes.
It is also possible that the  omap_dss_device divisors in the board
file are causing the problem.   If this is the case, there is insufficient
data in the TRM on how to reset  for different lane config and different
clocking.
Note, our LVDS is different and requires  82MHZ and not 66MHZ as
with the Blazetablet.

                                                                       Jerry

                         .lck_div        = 1,    /* LCD */
                        .pck_div        = 2,    /* PCD */
                        .regm           = 394,  /* DSI_PLL_REGM */
                        .regn           = 38,   /* DSI_PLL_REGN */
                        .regm_dispc     = 6,    /* PLL_CLK1 (M4) */
                        .regm_dsi       = 9,    /* PLL_CLK2 (M5) */
                        .lp_clk_div     = 5,    /* LPDIV */