[PATCH v3 00/20] GPIO: OMAP: driver cleanup and fixes

[PATCH v3 00/20] GPIO: OMAP: driver cleanup and fixes

[Tarun Kanti DebBarma]

This series is continuation of cleanup of OMAP GPIO driver and fixes.
The cleanup include getting rid of cpu_is_* checks wherever possible,
use of gpio_bank list instead of static array, use of unique platform
specific value associated data member to OMAP platforms to avoid
cpu_is_* checks. The series also include PM runtime support.

Baseline: git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap-pm.git
Branch: wip/gpio-cleanup

Test Details:
- Compile tested for omap1_defconfig and omap2plus_defconfig.
- OMAP1710-H3: Bootup test.
- OMAP2430-SDP, OMAP3430-SDP, OMAP4430-SDP: Functional testing. 
- PM Testing on OMAP3430-SDP: retention, off_mode, system_wide
  suspend and gpio wakeup.

Following patch is required for testing retention and off-mode:
https://patchwork.kernel.org/patch/834372/
OMAP: PM: omap_device: fix device power domain callbacks

v3:
- Avoid use of wkup_set and wkup_clear registers. Instead use wkup_status
  register for all platforms. This is because on OMAP4 it is recommended
  not to use them.

- Remove duplicate code in omap_gpio_mod_init() for handling the same for
  32-bit and 16-bit GPIO bank widths. This is accomplished by having two
  functions to handle each case while assiging a common function pointer
  during initialization.
  
- Remove OMAP16xx specific one time initialization from omap_gpio_mod_init().
  Move it inside omap16xx_gpio_init().

- Avoid usage of USHRT_MAX to indicate undefined values. Use 0 instead.

- In omap_gpio_suspend()/resume() functions remove code that checks
  if the feature is supported. Instead, assign these functions to
  struct platform_driver's suspend & resume function pointers for those
  OMAP platforms whcih support this feature.

- Remove 'suspend_support' flag because it is redundant. Instead use
  wkup_* registers to decode the same information.

- Restore context also when we don't know if the context is lost.

- Make omap_gpio_save_context() and omap_gpio_restore_context()
  static.

v2:
- Do special handling of non-wakeup GPIOs only on OMAP2420. Avoid this
  handling on OMAP3430.
- Isolate cleanups and fixes into separate set of patches. Keep the cleanup
  first followed by the fixes.
- Avoid calling omap_gpio_get_context_loss() directly and instead call it
  through function pointer in pdata initialized during init.
- workaround_enabled flag is not longer needed and is removed.
- Call pwrdm_post_transition() before calling omap_gpio_resume_after_idle().
- In omap2_gpio_resume_after_idle() do context restore before handling
  workaround.
- Use PM runtime framework.
- Modify register offset names to : wkup_status, wkup_clear, wkup_set.
  Also use 'base + offset' for readibility in all relevant places.
- Remove unwanted messages from commit section like TODO, etc.


Charulatha V (15):
  GPIO: OMAP: Remove dependency on gpio_bank_count
  GPIO: OMAP2+: Use flag to identify wakeup domain
  GPIO: OMAP: Make gpio_context part of gpio_bank structure
  GPIO: OMAP: Fix pwrdm_post_transition call sequence
  GPIO: OMAP: Handle save/restore ctx in GPIO driver
  GPIO: OMAP2+: Make non-wakeup GPIO part of pdata
  GPIO: OMAP: Avoid cpu checks during module ena/disable
  GPIO: OMAP: Use wkup regs off/suspend support flag
  GPIO: OMAP: Use level/edge detect reg offsets
  GPIO: OMAP: Clean set_gpio_triggering function
  GPIO: OMAP15xx: Use pinctrl offset instead of macro
  GPIO: OMAP: Use readl in irq_handler for all access
  GPIO: OMAP: Remove bank->method & METHOD_* macros
  GPIO: OMAP: Fix bankwidth for OMAP7xx MPUIO
  GPIO: OMAP: Use PM runtime framework

Tarun Kanti DebBarma (5):
  GPIO: OMAP: Remove hardcoded offsets in ctxt save/restore
  GPIO: OMAP: Use wkup_status for all SoCs
  GPIO: OMAP: Clean omap_gpio_mod_init function
  GPIO: OMAP: optimize suspend and resume functions
  GPIO: OMAP2+: Clean prepare_for_idle and resume_after_idle

 arch/arm/mach-omap1/gpio15xx.c         |    7 +-
 arch/arm/mach-omap1/gpio16xx.c         |   31 +-
 arch/arm/mach-omap1/gpio7xx.c          |   14 +-
 arch/arm/mach-omap2/gpio.c             |   47 ++-
 arch/arm/mach-omap2/pm34xx.c           |   21 +-
 arch/arm/plat-omap/include/plat/gpio.h |   31 +-
 drivers/gpio/gpio-omap.c               | 1070 +++++++++++++-------------------
 7 files changed, 533 insertions(+), 688 deletions(-)

[PATCH v3 01/20] GPIO: OMAP: Remove dependency on gpio_bank_count

[Tarun Kanti DebBarma]

From: Charulatha V <charu@ti.com>

The gpio_bank_count is the count of number of GPIO devices in a SoC. Remove this
dependency from the driver by using list. Also remove the dependency on array of
pointers to gpio_bank struct of all GPIO devices.

Signed-off-by: Charulatha V <charu@ti.com>
---
 arch/arm/mach-omap1/gpio15xx.c         |    1 -
 arch/arm/mach-omap1/gpio16xx.c         |    2 -
 arch/arm/mach-omap1/gpio7xx.c          |    2 -
 arch/arm/mach-omap2/gpio.c             |    1 -
 arch/arm/plat-omap/include/plat/gpio.h |    3 -
 drivers/gpio/gpio-omap.c               |  163 ++++++++++++++++----------------
 6 files changed, 80 insertions(+), 92 deletions(-)

diff --git a/arch/arm/mach-omap1/gpio15xx.c b/arch/arm/mach-omap1/gpio15xx.c
index f79c6ae..e8a3bd9 100644
--- a/arch/arm/mach-omap1/gpio15xx.c
+++ b/arch/arm/mach-omap1/gpio15xx.c
@@ -115,7 +115,6 @@ static int __init omap15xx_gpio_init(void)
 	platform_device_register(&omap15xx_mpu_gpio);
 	platform_device_register(&omap15xx_gpio);
 
-	gpio_bank_count = 2;
 	return 0;
 }
 postcore_initcall(omap15xx_gpio_init);
diff --git a/arch/arm/mach-omap1/gpio16xx.c b/arch/arm/mach-omap1/gpio16xx.c
index c69b3b1..9a97e60 100644
--- a/arch/arm/mach-omap1/gpio16xx.c
+++ b/arch/arm/mach-omap1/gpio16xx.c
@@ -221,8 +221,6 @@ static int __init omap16xx_gpio_init(void)
 	for (i = 0; i < ARRAY_SIZE(omap16xx_gpio_dev); i++)
 		platform_device_register(omap16xx_gpio_dev[i]);
 
-	gpio_bank_count = ARRAY_SIZE(omap16xx_gpio_dev);
-
 	return 0;
 }
 postcore_initcall(omap16xx_gpio_init);
diff --git a/arch/arm/mach-omap1/gpio7xx.c b/arch/arm/mach-omap1/gpio7xx.c
index d7f2ad3..f5d5572 100644
--- a/arch/arm/mach-omap1/gpio7xx.c
+++ b/arch/arm/mach-omap1/gpio7xx.c
@@ -282,8 +282,6 @@ static int __init omap7xx_gpio_init(void)
 	for (i = 0; i < ARRAY_SIZE(omap7xx_gpio_dev); i++)
 		platform_device_register(omap7xx_gpio_dev[i]);
 
-	gpio_bank_count = ARRAY_SIZE(omap7xx_gpio_dev);
-
 	return 0;
 }
 postcore_initcall(omap7xx_gpio_init);
diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c
index 9a46d77..f805cda 100644
--- a/arch/arm/mach-omap2/gpio.c
+++ b/arch/arm/mach-omap2/gpio.c
@@ -119,7 +119,6 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
 		return PTR_ERR(od);
 	}
 
-	gpio_bank_count++;
 	return 0;
 }
 
diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h
index 91e8de3..dd330ed 100644
--- a/arch/arm/plat-omap/include/plat/gpio.h
+++ b/arch/arm/plat-omap/include/plat/gpio.h
@@ -202,9 +202,6 @@ struct omap_gpio_platform_data {
 	struct omap_gpio_reg_offs *regs;
 };
 
-/* TODO: Analyze removing gpio_bank_count usage from driver code */
-extern int gpio_bank_count;
-
 extern void omap2_gpio_prepare_for_idle(int off_mode);
 extern void omap2_gpio_resume_after_idle(void);
 extern void omap_set_gpio_debounce(int gpio, int enable);
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 501ca3d..28b70eb 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -28,7 +28,10 @@
 #include <mach/gpio.h>
 #include <asm/mach/irq.h>
 
+static LIST_HEAD(omap_gpio_list);
+
 struct gpio_bank {
+	struct list_head node;
 	unsigned long pbase;
 	void __iomem *base;
 	u16 irq;
@@ -55,6 +58,7 @@ struct gpio_bank {
 	bool dbck_flag;
 	int stride;
 	u32 width;
+	u16 id;
 
 	void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable);
 
@@ -78,15 +82,6 @@ struct omap3_gpio_regs {
 static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
 #endif
 
-/*
- * TODO: Cleanup gpio_bank usage as it is having information
- * related to all instances of the device
- */
-static struct gpio_bank *gpio_bank;
-
-/* TODO: Analyze removing gpio_bank_count usage from driver code */
-int gpio_bank_count;
-
 #define GPIO_INDEX(bank, gpio) (gpio % bank->width)
 #define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio))
 
@@ -864,9 +859,8 @@ static struct platform_device omap_mpuio_device = {
 	/* could list the /proc/iomem resources */
 };
 
-static inline void mpuio_init(void)
+static inline void mpuio_init(struct gpio_bank *bank)
 {
-	struct gpio_bank *bank = &gpio_bank[0];
 	platform_set_drvdata(&omap_mpuio_device, bank);
 
 	if (platform_driver_register(&omap_mpuio_driver) == 0)
@@ -874,13 +868,13 @@ static inline void mpuio_init(void)
 }
 
 #else
-static inline void mpuio_init(void) {}
+static inline void mpuio_init(struct gpio_bank *bank) {}
 #endif	/* 16xx */
 
 #else
 
 #define bank_is_mpuio(bank)	0
-static inline void mpuio_init(void) {}
+static inline void mpuio_init(struct gpio_bank *bank) {}
 
 #endif
 
@@ -1002,20 +996,8 @@ static void __init omap_gpio_show_rev(struct gpio_bank *bank)
  */
 static struct lock_class_key gpio_lock_class;
 
-static inline int init_gpio_info(struct platform_device *pdev)
-{
-	/* TODO: Analyze removing gpio_bank_count usage from driver code */
-	gpio_bank = kzalloc(gpio_bank_count * sizeof(struct gpio_bank),
-				GFP_KERNEL);
-	if (!gpio_bank) {
-		dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n");
-		return -ENOMEM;
-	}
-	return 0;
-}
-
 /* TODO: Cleanup cpu_is_* checks */
-static void omap_gpio_mod_init(struct gpio_bank *bank, int id)
+static void omap_gpio_mod_init(struct gpio_bank *bank)
 {
 	if (cpu_class_is_omap2()) {
 		if (cpu_is_omap44xx()) {
@@ -1039,13 +1021,16 @@ static void omap_gpio_mod_init(struct gpio_bank *bank, int id)
 			static const u32 non_wakeup_gpios[] = {
 				0xe203ffc0, 0x08700040
 			};
-			if (id < ARRAY_SIZE(non_wakeup_gpios))
-				bank->non_wakeup_gpios = non_wakeup_gpios[id];
+			if (bank->id < ARRAY_SIZE(non_wakeup_gpios))
+				bank->non_wakeup_gpios =
+						non_wakeup_gpios[bank->id];
 		}
 	} else if (cpu_class_is_omap1()) {
-		if (bank_is_mpuio(bank))
+		if (bank_is_mpuio(bank)) {
 			__raw_writew(0xffff, bank->base +
 				OMAP_MPUIO_GPIO_MASKIT / bank->stride);
+			mpuio_init(bank);
+		}
 		if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
 			__raw_writew(0xffff, bank->base
 						+ OMAP1510_GPIO_INT_MASK);
@@ -1151,35 +1136,35 @@ static void __devinit omap_gpio_chip_init(struct gpio_bank *bank)
 
 static int __devinit omap_gpio_probe(struct platform_device *pdev)
 {
-	static int gpio_init_done;
 	struct omap_gpio_platform_data *pdata;
 	struct resource *res;
-	int id;
 	struct gpio_bank *bank;
+	int ret = 0;
 
-	if (!pdev->dev.platform_data)
-		return -EINVAL;
-
-	pdata = pdev->dev.platform_data;
-
-	if (!gpio_init_done) {
-		int ret;
-
-		ret = init_gpio_info(pdev);
-		if (ret)
-			return ret;
+	if (!pdev->dev.platform_data) {
+		ret = -EINVAL;
+		goto err_exit;
 	}
 
-	id = pdev->id;
-	bank = &gpio_bank[id];
+	bank = kzalloc(sizeof(struct gpio_bank), GFP_KERNEL);
+	if (!bank) {
+		dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n");
+		ret = -ENOMEM;
+		goto err_exit;
+	}
 
 	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 	if (unlikely(!res)) {
-		dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n", id);
-		return -ENODEV;
+		dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n",
+				pdev->id);
+		ret = -ENODEV;
+		goto err_free;
 	}
 
 	bank->irq = res->start;
+	bank->id = pdev->id;
+
+	pdata = pdev->dev.platform_data;
 	bank->virtual_irq_start = pdata->virtual_irq_start;
 	bank->method = pdata->bank_type;
 	bank->dev = &pdev->dev;
@@ -1199,39 +1184,46 @@ static int __devinit omap_gpio_probe(struct platform_device *pdev)
 	/* Static mapping, never released */
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (unlikely(!res)) {
-		dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n", id);
-		return -ENODEV;
+		dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n",
+				pdev->id);
+		ret = -ENODEV;
+		goto err_free;
 	}
 
 	bank->base = ioremap(res->start, resource_size(res));
 	if (!bank->base) {
-		dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n", id);
-		return -ENOMEM;
+		dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n",
+				pdev->id);
+		ret = -ENOMEM;
+		goto err_free;
 	}
 
 	pm_runtime_enable(bank->dev);
 	pm_runtime_get_sync(bank->dev);
 
-	omap_gpio_mod_init(bank, id);
+	omap_gpio_mod_init(bank);
 	omap_gpio_chip_init(bank);
 	omap_gpio_show_rev(bank);
 
-	if (!gpio_init_done)
-		gpio_init_done = 1;
+	list_add_tail(&bank->node, &omap_gpio_list);
 
-	return 0;
+	return ret;
+
+err_free:
+	kfree(bank);
+err_exit:
+	return ret;
 }
 
 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
 static int omap_gpio_suspend(void)
 {
-	int i;
+	struct gpio_bank *bank;
 
 	if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
 		return 0;
 
-	for (i = 0; i < gpio_bank_count; i++) {
-		struct gpio_bank *bank = &gpio_bank[i];
+	list_for_each_entry(bank, &omap_gpio_list, node) {
 		void __iomem *wake_status;
 		void __iomem *wake_clear;
 		void __iomem *wake_set;
@@ -1275,13 +1267,12 @@ static int omap_gpio_suspend(void)
 
 static void omap_gpio_resume(void)
 {
-	int i;
+	struct gpio_bank *bank;
 
 	if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
 		return;
 
-	for (i = 0; i < gpio_bank_count; i++) {
-		struct gpio_bank *bank = &gpio_bank[i];
+	list_for_each_entry(bank, &omap_gpio_list, node) {
 		void __iomem *wake_clear;
 		void __iomem *wake_set;
 		unsigned long flags;
@@ -1329,17 +1320,17 @@ static int workaround_enabled;
 
 void omap2_gpio_prepare_for_idle(int off_mode)
 {
-	int i, c = 0;
-	int min = 0;
-
-	if (cpu_is_omap34xx())
-		min = 1;
+	int c = 0;
+	struct gpio_bank *bank;
 
-	for (i = min; i < gpio_bank_count; i++) {
-		struct gpio_bank *bank = &gpio_bank[i];
+	list_for_each_entry(bank, &omap_gpio_list, node) {
 		u32 l1 = 0, l2 = 0;
 		int j;
 
+		/* TODO: Do not use cpu_is_omap34xx */
+		if ((cpu_is_omap34xx()) && (bank->id == 0))
+			continue;
+
 		for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
 			clk_disable(bank->dbck);
 
@@ -1398,16 +1389,16 @@ void omap2_gpio_prepare_for_idle(int off_mode)
 
 void omap2_gpio_resume_after_idle(void)
 {
-	int i;
-	int min = 0;
+	struct gpio_bank *bank;
 
-	if (cpu_is_omap34xx())
-		min = 1;
-	for (i = min; i < gpio_bank_count; i++) {
-		struct gpio_bank *bank = &gpio_bank[i];
+	list_for_each_entry(bank, &omap_gpio_list, node) {
 		u32 l = 0, gen, gen0, gen1;
 		int j;
 
+		/* TODO: Do not use cpu_is_omap34xx */
+		if ((cpu_is_omap34xx()) && (bank->id == 0))
+			continue;
+
 		for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
 			clk_enable(bank->dbck);
 
@@ -1496,14 +1487,17 @@ void omap2_gpio_resume_after_idle(void)
 #endif
 
 #ifdef CONFIG_ARCH_OMAP3
-/* save the registers of bank 2-6 */
 void omap_gpio_save_context(void)
 {
-	int i;
+	struct gpio_bank *bank;
+	int i = 0;
+
+	list_for_each_entry(bank, &omap_gpio_list, node) {
+		i++;
+
+		if (bank->id == 0)
+			continue;
 
-	/* saving banks from 2-6 only since GPIO1 is in WKUP */
-	for (i = 1; i < gpio_bank_count; i++) {
-		struct gpio_bank *bank = &gpio_bank[i];
 		gpio_context[i].irqenable1 =
 			__raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
 		gpio_context[i].irqenable2 =
@@ -1527,13 +1521,17 @@ void omap_gpio_save_context(void)
 	}
 }
 
-/* restore the required registers of bank 2-6 */
 void omap_gpio_restore_context(void)
 {
-	int i;
+	struct gpio_bank *bank;
+	int i = 0;
+
+	list_for_each_entry(bank, &omap_gpio_list, node) {
+		i++;
+
+		if (bank->id == 0)
+			continue;
 
-	for (i = 1; i < gpio_bank_count; i++) {
-		struct gpio_bank *bank = &gpio_bank[i];
 		__raw_writel(gpio_context[i].irqenable1,
 				bank->base + OMAP24XX_GPIO_IRQENABLE1);
 		__raw_writel(gpio_context[i].irqenable2,
@@ -1578,7 +1576,6 @@ postcore_initcall(omap_gpio_drv_reg);
 
 static int __init omap_gpio_sysinit(void)
 {
-	mpuio_init();
 
 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
 	if (cpu_is_omap16xx() || cpu_class_is_omap2())
-- 
1.6.0.4

[PATCH v3 02/20] GPIO: OMAP2+: Use flag to identify wakeup domain

[Tarun Kanti DebBarma]

From: Charulatha V <charu@ti.com>

In omap3, save/restore context is implemented for GPIO banks 2-6 as GPIO bank1
is in wakeup domain. Instead of identifying bank's power domain by bank id,
use 'loses_context' flag which is filled by pwrdm_can_ever_lose_context()
during dev_init.

For getting the powerdomain pointer, omap_hwmod_get_pwrdm() is used.
omap_device_get_pwrdm() could not be used as the pwrdm information needs to be
filled in pdata, whereas omap_device_get_pwrdm() could be used only after
omap_device_build() call.

Signed-off-by: Charulatha V <charu@ti.com>
---
 arch/arm/mach-omap2/gpio.c             |    6 ++++++
 arch/arm/plat-omap/include/plat/gpio.h |    1 +
 drivers/gpio/gpio-omap.c               |   13 ++++++-------
 3 files changed, 13 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c
index f805cda..95195a8 100644
--- a/arch/arm/mach-omap2/gpio.c
+++ b/arch/arm/mach-omap2/gpio.c
@@ -24,6 +24,8 @@
 #include <plat/omap_hwmod.h>
 #include <plat/omap_device.h>
 
+#include "powerdomain.h"
+
 static struct omap_device_pm_latency omap_gpio_latency[] = {
 	[0] = {
 		.deactivate_func = omap_device_idle_hwmods,
@@ -39,6 +41,7 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
 	struct omap_gpio_dev_attr *dev_attr;
 	char *name = "omap_gpio";
 	int id;
+	struct powerdomain *pwrdm;
 
 	/*
 	 * extract the device id from name field available in the
@@ -107,6 +110,9 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
 		return -EINVAL;
 	}
 
+	pwrdm = omap_hwmod_get_pwrdm(oh);
+	pdata->loses_context = pwrdm_can_ever_lose_context(pwrdm);
+
 	od = omap_device_build(name, id - 1, oh, pdata,
 				sizeof(*pdata),	omap_gpio_latency,
 				ARRAY_SIZE(omap_gpio_latency),
diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h
index dd330ed..58d0bf2 100644
--- a/arch/arm/plat-omap/include/plat/gpio.h
+++ b/arch/arm/plat-omap/include/plat/gpio.h
@@ -198,6 +198,7 @@ struct omap_gpio_platform_data {
 	int bank_width;		/* GPIO bank width */
 	int bank_stride;	/* Only needed for omap1 MPUIO */
 	bool dbck_flag;		/* dbck required or not - True for OMAP3&4 */
+	bool loses_context;	/* whether the bank would ever lose context */
 
 	struct omap_gpio_reg_offs *regs;
 };
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 28b70eb..460bcb9 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -56,6 +56,7 @@ struct gpio_bank {
 	u32 dbck_enable_mask;
 	struct device *dev;
 	bool dbck_flag;
+	bool loses_context;
 	int stride;
 	u32 width;
 	u16 id;
@@ -1171,7 +1172,7 @@ static int __devinit omap_gpio_probe(struct platform_device *pdev)
 	bank->dbck_flag = pdata->dbck_flag;
 	bank->stride = pdata->bank_stride;
 	bank->width = pdata->bank_width;
-
+	bank->loses_context = pdata->loses_context;
 	bank->regs = pdata->regs;
 
 	if (bank->regs->set_dataout && bank->regs->clr_dataout)
@@ -1327,8 +1328,7 @@ void omap2_gpio_prepare_for_idle(int off_mode)
 		u32 l1 = 0, l2 = 0;
 		int j;
 
-		/* TODO: Do not use cpu_is_omap34xx */
-		if ((cpu_is_omap34xx()) && (bank->id == 0))
+		if (!bank->loses_context)
 			continue;
 
 		for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
@@ -1395,8 +1395,7 @@ void omap2_gpio_resume_after_idle(void)
 		u32 l = 0, gen, gen0, gen1;
 		int j;
 
-		/* TODO: Do not use cpu_is_omap34xx */
-		if ((cpu_is_omap34xx()) && (bank->id == 0))
+		if (!bank->loses_context)
 			continue;
 
 		for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
@@ -1495,7 +1494,7 @@ void omap_gpio_save_context(void)
 	list_for_each_entry(bank, &omap_gpio_list, node) {
 		i++;
 
-		if (bank->id == 0)
+		if (!bank->loses_context)
 			continue;
 
 		gpio_context[i].irqenable1 =
@@ -1529,7 +1528,7 @@ void omap_gpio_restore_context(void)
 	list_for_each_entry(bank, &omap_gpio_list, node) {
 		i++;
 
-		if (bank->id == 0)
+		if (!bank->loses_context)
 			continue;
 
 		__raw_writel(gpio_context[i].irqenable1,
-- 
1.6.0.4

[PATCH v3 03/20] GPIO: OMAP: Make gpio_context part of gpio_bank structure

[Tarun Kanti DebBarma]

From: Charulatha V <charu@ti.com>

Currently gpio_context array used to save gpio bank's context, is used only for
OMAP3 architecture. Move gpio_context as part of gpio_bank structure so that it
can be specific to each gpio bank and can be used for any OMAP architecture

Signed-off-by: Charulatha V <charu@ti.com>
---
 drivers/gpio/gpio-omap.c |   76 ++++++++++++++++++++-------------------------
 1 files changed, 34 insertions(+), 42 deletions(-)

diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 460bcb9..c01863c 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -30,6 +30,19 @@
 
 static LIST_HEAD(omap_gpio_list);
 
+struct gpio_regs {
+	u32 irqenable1;
+	u32 irqenable2;
+	u32 wake_en;
+	u32 ctrl;
+	u32 oe;
+	u32 leveldetect0;
+	u32 leveldetect1;
+	u32 risingdetect;
+	u32 fallingdetect;
+	u32 dataout;
+};
+
 struct gpio_bank {
 	struct list_head node;
 	unsigned long pbase;
@@ -43,7 +56,7 @@ struct gpio_bank {
 #endif
 	u32 non_wakeup_gpios;
 	u32 enabled_non_wakeup_gpios;
-
+	struct gpio_regs context;
 	u32 saved_datain;
 	u32 saved_fallingdetect;
 	u32 saved_risingdetect;
@@ -66,23 +79,6 @@ struct gpio_bank {
 	struct omap_gpio_reg_offs *regs;
 };
 
-#ifdef CONFIG_ARCH_OMAP3
-struct omap3_gpio_regs {
-	u32 irqenable1;
-	u32 irqenable2;
-	u32 wake_en;
-	u32 ctrl;
-	u32 oe;
-	u32 leveldetect0;
-	u32 leveldetect1;
-	u32 risingdetect;
-	u32 fallingdetect;
-	u32 dataout;
-};
-
-static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
-#endif
-
 #define GPIO_INDEX(bank, gpio) (gpio % bank->width)
 #define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio))
 
@@ -1489,33 +1485,31 @@ void omap2_gpio_resume_after_idle(void)
 void omap_gpio_save_context(void)
 {
 	struct gpio_bank *bank;
-	int i = 0;
 
 	list_for_each_entry(bank, &omap_gpio_list, node) {
-		i++;
 
 		if (!bank->loses_context)
 			continue;
 
-		gpio_context[i].irqenable1 =
+		bank->context.irqenable1 =
 			__raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
-		gpio_context[i].irqenable2 =
+		bank->context.irqenable2 =
 			__raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
-		gpio_context[i].wake_en =
+		bank->context.wake_en =
 			__raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
-		gpio_context[i].ctrl =
+		bank->context.ctrl =
 			__raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
-		gpio_context[i].oe =
+		bank->context.oe =
 			__raw_readl(bank->base + OMAP24XX_GPIO_OE);
-		gpio_context[i].leveldetect0 =
+		bank->context.leveldetect0 =
 			__raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
-		gpio_context[i].leveldetect1 =
+		bank->context.leveldetect1 =
 			__raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
-		gpio_context[i].risingdetect =
+		bank->context.risingdetect =
 			__raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
-		gpio_context[i].fallingdetect =
+		bank->context.fallingdetect =
 			__raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
-		gpio_context[i].dataout =
+		bank->context.dataout =
 			__raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
 	}
 }
@@ -1523,33 +1517,31 @@ void omap_gpio_save_context(void)
 void omap_gpio_restore_context(void)
 {
 	struct gpio_bank *bank;
-	int i = 0;
 
 	list_for_each_entry(bank, &omap_gpio_list, node) {
-		i++;
 
 		if (!bank->loses_context)
 			continue;
 
-		__raw_writel(gpio_context[i].irqenable1,
+		__raw_writel(bank->context.irqenable1,
 				bank->base + OMAP24XX_GPIO_IRQENABLE1);
-		__raw_writel(gpio_context[i].irqenable2,
+		__raw_writel(bank->context.irqenable2,
 				bank->base + OMAP24XX_GPIO_IRQENABLE2);
-		__raw_writel(gpio_context[i].wake_en,
+		__raw_writel(bank->context.wake_en,
 				bank->base + OMAP24XX_GPIO_WAKE_EN);
-		__raw_writel(gpio_context[i].ctrl,
+		__raw_writel(bank->context.ctrl,
 				bank->base + OMAP24XX_GPIO_CTRL);
-		__raw_writel(gpio_context[i].oe,
+		__raw_writel(bank->context.oe,
 				bank->base + OMAP24XX_GPIO_OE);
-		__raw_writel(gpio_context[i].leveldetect0,
+		__raw_writel(bank->context.leveldetect0,
 				bank->base + OMAP24XX_GPIO_LEVELDETECT0);
-		__raw_writel(gpio_context[i].leveldetect1,
+		__raw_writel(bank->context.leveldetect1,
 				bank->base + OMAP24XX_GPIO_LEVELDETECT1);
-		__raw_writel(gpio_context[i].risingdetect,
+		__raw_writel(bank->context.risingdetect,
 				bank->base + OMAP24XX_GPIO_RISINGDETECT);
-		__raw_writel(gpio_context[i].fallingdetect,
+		__raw_writel(bank->context.fallingdetect,
 				bank->base + OMAP24XX_GPIO_FALLINGDETECT);
-		__raw_writel(gpio_context[i].dataout,
+		__raw_writel(bank->context.dataout,
 				bank->base + OMAP24XX_GPIO_DATAOUT);
 	}
 }
-- 
1.6.0.4

[PATCH v3 04/20] GPIO: OMAP: Fix pwrdm_post_transition call sequence

[Tarun Kanti DebBarma]

From: Charulatha V <charu@ti.com>

The context lost count is modified in omap_sram_idle() path when
pwrdm_post_transition() is called. But pwrdm_post_transition() is called
only after omap_gpio_resume_after_idle() is called. Correct this so that
context lost count is modified before calling omap_gpio_resume_after_idle().

This would be useful when OMAP GPIO save/restore context is called by
the OMAP GPIO driver itself.

Signed-off-by: Charulatha V <charu@ti.com>
---
 arch/arm/mach-omap2/pm34xx.c |    7 ++++---
 1 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index c155c9d..51d5a5c 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -375,7 +375,6 @@ void omap_sram_idle(void)
 		printk(KERN_ERR "Invalid mpu state in sram_idle\n");
 		return;
 	}
-	pwrdm_pre_transition();
 
 	/* NEON control */
 	if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
@@ -398,6 +397,8 @@ void omap_sram_idle(void)
 			if (!console_trylock())
 				goto console_still_active;
 
+	pwrdm_pre_transition();
+
 	/* PER */
 	if (per_next_state < PWRDM_POWER_ON) {
 		per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
@@ -467,6 +468,8 @@ void omap_sram_idle(void)
 	}
 	omap3_intc_resume_idle();
 
+	pwrdm_post_transition();
+
 	/* PER */
 	if (per_next_state < PWRDM_POWER_ON) {
 		per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm);
@@ -490,8 +493,6 @@ console_still_active:
 		omap3_disable_io_chain();
 	}
 
-	pwrdm_post_transition();
-
 	clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]);
 }
 
-- 
1.6.0.4

[PATCH v3 05/20] GPIO: OMAP: Handle save/restore ctx in GPIO driver

[Tarun Kanti DebBarma]

From: Charulatha V <charu@ti.com>

Modify omap_gpio_prepare_for_idle() & omap_gpio_resume_after_idle() functions
to handle save context & restore context respectively in the OMAP GPIO driver
itself instead of calling these functions from pm specific files.
For this, in gpio_prepare_for_idle(), call *_get_context_loss_count() and in
gpio_resume_after_idle() call it again. If the count is different, do restore
context. The workaround_enabled flag is no more required and is removed.

Signed-off-by: Charulatha V <charu@ti.com>
---
 arch/arm/mach-omap2/gpio.c             |   12 +++
 arch/arm/mach-omap2/pm34xx.c           |   14 ----
 arch/arm/plat-omap/include/plat/gpio.h |    5 +-
 drivers/gpio/gpio-omap.c               |  131 ++++++++++++++------------------
 4 files changed, 73 insertions(+), 89 deletions(-)

diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c
index 95195a8..2e65377 100644
--- a/arch/arm/mach-omap2/gpio.c
+++ b/arch/arm/mach-omap2/gpio.c
@@ -23,6 +23,7 @@
 
 #include <plat/omap_hwmod.h>
 #include <plat/omap_device.h>
+#include <plat/omap-pm.h>
 
 #include "powerdomain.h"
 
@@ -34,6 +35,16 @@ static struct omap_device_pm_latency omap_gpio_latency[] = {
 	},
 };
 
+#ifdef CONFIG_PM
+static int omap_gpio_get_context_loss(struct device *dev)
+{
+	return omap_pm_get_dev_context_loss_count(dev);
+}
+
+#else
+#define omap_gpio_get_context_loss NULL
+#endif
+
 static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
 {
 	struct omap_device *od;
@@ -63,6 +74,7 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
 	pdata->bank_width = dev_attr->bank_width;
 	pdata->dbck_flag = dev_attr->dbck_flag;
 	pdata->virtual_irq_start = IH_GPIO_BASE + 32 * (id - 1);
+	pdata->get_context_loss_count = omap_gpio_get_context_loss;
 
 	pdata->regs = kzalloc(sizeof(struct omap_gpio_reg_offs), GFP_KERNEL);
 	if (!pdata) {
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 51d5a5c..0aaa32c 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -91,16 +91,6 @@ static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
 static struct powerdomain *core_pwrdm, *per_pwrdm;
 static struct powerdomain *cam_pwrdm;
 
-static inline void omap3_per_save_context(void)
-{
-	omap_gpio_save_context();
-}
-
-static inline void omap3_per_restore_context(void)
-{
-	omap_gpio_restore_context();
-}
-
 static void omap3_enable_io_chain(void)
 {
 	int timeout = 0;
@@ -405,8 +395,6 @@ void omap_sram_idle(void)
 		omap_uart_prepare_idle(2);
 		omap_uart_prepare_idle(3);
 		omap2_gpio_prepare_for_idle(per_going_off);
-		if (per_next_state == PWRDM_POWER_OFF)
-				omap3_per_save_context();
 	}
 
 	/* CORE */
@@ -474,8 +462,6 @@ void omap_sram_idle(void)
 	if (per_next_state < PWRDM_POWER_ON) {
 		per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm);
 		omap2_gpio_resume_after_idle();
-		if (per_prev_state == PWRDM_POWER_OFF)
-			omap3_per_restore_context();
 		omap_uart_resume_idle(2);
 		omap_uart_resume_idle(3);
 	}
diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h
index 58d0bf2..f7798b5 100644
--- a/arch/arm/plat-omap/include/plat/gpio.h
+++ b/arch/arm/plat-omap/include/plat/gpio.h
@@ -201,14 +201,15 @@ struct omap_gpio_platform_data {
 	bool loses_context;	/* whether the bank would ever lose context */
 
 	struct omap_gpio_reg_offs *regs;
+
+	/* Return context loss count due to PM states changing */
+	int (*get_context_loss_count)(struct device *dev);
 };
 
 extern void omap2_gpio_prepare_for_idle(int off_mode);
 extern void omap2_gpio_resume_after_idle(void);
 extern void omap_set_gpio_debounce(int gpio, int enable);
 extern void omap_set_gpio_debounce_time(int gpio, int enable);
-extern void omap_gpio_save_context(void);
-extern void omap_gpio_restore_context(void);
 /*-------------------------------------------------------------------------*/
 
 /* Wrappers for "new style" GPIO calls, using the new infrastructure
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index c01863c..9a6bf8e 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -72,9 +72,11 @@ struct gpio_bank {
 	bool loses_context;
 	int stride;
 	u32 width;
+	u32 ctx_loss_count;
 	u16 id;
 
 	void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable);
+	int (*get_context_loss_count)(struct device *dev);
 
 	struct omap_gpio_reg_offs *regs;
 };
@@ -1169,6 +1171,7 @@ static int __devinit omap_gpio_probe(struct platform_device *pdev)
 	bank->stride = pdata->bank_stride;
 	bank->width = pdata->bank_width;
 	bank->loses_context = pdata->loses_context;
+	bank->get_context_loss_count = pdata->get_context_loss_count;
 	bank->regs = pdata->regs;
 
 	if (bank->regs->set_dataout && bank->regs->clr_dataout)
@@ -1313,11 +1316,11 @@ static struct syscore_ops omap_gpio_syscore_ops = {
 
 #ifdef CONFIG_ARCH_OMAP2PLUS
 
-static int workaround_enabled;
+static void omap_gpio_save_context(struct gpio_bank *bank);
+static void omap_gpio_restore_context(struct gpio_bank *bank);
 
 void omap2_gpio_prepare_for_idle(int off_mode)
 {
-	int c = 0;
 	struct gpio_bank *bank;
 
 	list_for_each_entry(bank, &omap_gpio_list, node) {
@@ -1337,7 +1340,7 @@ void omap2_gpio_prepare_for_idle(int off_mode)
 		 * non-wakeup GPIOs.  Otherwise spurious IRQs will be
 		 * generated.  See OMAP2420 Errata item 1.101. */
 		if (!(bank->enabled_non_wakeup_gpios))
-			continue;
+			goto save_gpio_ctx;
 
 		if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
 			bank->saved_datain = __raw_readl(bank->base +
@@ -1374,13 +1377,13 @@ void omap2_gpio_prepare_for_idle(int off_mode)
 			__raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
 		}
 
-		c++;
-	}
-	if (!c) {
-		workaround_enabled = 0;
-		return;
+save_gpio_ctx:
+		if (bank->get_context_loss_count)
+			bank->ctx_loss_count =
+				bank->get_context_loss_count(bank->dev);
+
+		omap_gpio_save_context(bank);
 	}
-	workaround_enabled = 1;
 }
 
 void omap2_gpio_resume_after_idle(void)
@@ -1388,6 +1391,7 @@ void omap2_gpio_resume_after_idle(void)
 	struct gpio_bank *bank;
 
 	list_for_each_entry(bank, &omap_gpio_list, node) {
+		u32 ctx_lost_cnt_after;
 		u32 l = 0, gen, gen0, gen1;
 		int j;
 
@@ -1397,8 +1401,13 @@ void omap2_gpio_resume_after_idle(void)
 		for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
 			clk_enable(bank->dbck);
 
-		if (!workaround_enabled)
-			continue;
+		if (bank->get_context_loss_count) {
+			ctx_lost_cnt_after =
+				bank->get_context_loss_count(bank->dev);
+			if (ctx_lost_cnt_after != bank->ctx_loss_count ||
+				!ctx_lost_cnt_after)
+				omap_gpio_restore_context(bank);
+		}
 
 		if (!(bank->enabled_non_wakeup_gpios))
 			continue;
@@ -1476,74 +1485,50 @@ void omap2_gpio_resume_after_idle(void)
 			}
 		}
 	}
-
 }
 
-#endif
-
-#ifdef CONFIG_ARCH_OMAP3
-void omap_gpio_save_context(void)
+static void omap_gpio_save_context(struct gpio_bank *bank)
 {
-	struct gpio_bank *bank;
-
-	list_for_each_entry(bank, &omap_gpio_list, node) {
-
-		if (!bank->loses_context)
-			continue;
-
-		bank->context.irqenable1 =
-			__raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
-		bank->context.irqenable2 =
-			__raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
-		bank->context.wake_en =
-			__raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
-		bank->context.ctrl =
-			__raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
-		bank->context.oe =
-			__raw_readl(bank->base + OMAP24XX_GPIO_OE);
-		bank->context.leveldetect0 =
-			__raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
-		bank->context.leveldetect1 =
-			__raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
-		bank->context.risingdetect =
-			__raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
-		bank->context.fallingdetect =
-			__raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
-		bank->context.dataout =
-			__raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
-	}
+	bank->context.irqenable1 =
+		__raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
+	bank->context.irqenable2 =
+		__raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
+	bank->context.wake_en =
+		__raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
+	bank->context.ctrl = __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
+	bank->context.oe = __raw_readl(bank->base + OMAP24XX_GPIO_OE);
+	bank->context.leveldetect0 =
+		__raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
+	bank->context.leveldetect1 =
+		__raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
+	bank->context.risingdetect =
+		__raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
+	bank->context.fallingdetect =
+		__raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
+	bank->context.dataout =
+		__raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
 }
 
-void omap_gpio_restore_context(void)
+static void omap_gpio_restore_context(struct gpio_bank *bank)
 {
-	struct gpio_bank *bank;
-
-	list_for_each_entry(bank, &omap_gpio_list, node) {
-
-		if (!bank->loses_context)
-			continue;
-
-		__raw_writel(bank->context.irqenable1,
-				bank->base + OMAP24XX_GPIO_IRQENABLE1);
-		__raw_writel(bank->context.irqenable2,
-				bank->base + OMAP24XX_GPIO_IRQENABLE2);
-		__raw_writel(bank->context.wake_en,
-				bank->base + OMAP24XX_GPIO_WAKE_EN);
-		__raw_writel(bank->context.ctrl,
-				bank->base + OMAP24XX_GPIO_CTRL);
-		__raw_writel(bank->context.oe,
-				bank->base + OMAP24XX_GPIO_OE);
-		__raw_writel(bank->context.leveldetect0,
-				bank->base + OMAP24XX_GPIO_LEVELDETECT0);
-		__raw_writel(bank->context.leveldetect1,
-				bank->base + OMAP24XX_GPIO_LEVELDETECT1);
-		__raw_writel(bank->context.risingdetect,
-				bank->base + OMAP24XX_GPIO_RISINGDETECT);
-		__raw_writel(bank->context.fallingdetect,
-				bank->base + OMAP24XX_GPIO_FALLINGDETECT);
-		__raw_writel(bank->context.dataout,
-				bank->base + OMAP24XX_GPIO_DATAOUT);
-	}
+	__raw_writel(bank->context.irqenable1,
+			bank->base + OMAP24XX_GPIO_IRQENABLE1);
+	__raw_writel(bank->context.irqenable2,
+			bank->base + OMAP24XX_GPIO_IRQENABLE2);
+	__raw_writel(bank->context.wake_en,
+			bank->base + OMAP24XX_GPIO_WAKE_EN);
+	__raw_writel(bank->context.ctrl, bank->base + OMAP24XX_GPIO_CTRL);
+	__raw_writel(bank->context.oe, bank->base + OMAP24XX_GPIO_OE);
+	__raw_writel(bank->context.leveldetect0,
+			bank->base + OMAP24XX_GPIO_LEVELDETECT0);
+	__raw_writel(bank->context.leveldetect1,
+			bank->base + OMAP24XX_GPIO_LEVELDETECT1);
+	__raw_writel(bank->context.risingdetect,
+			bank->base + OMAP24XX_GPIO_RISINGDETECT);
+	__raw_writel(bank->context.fallingdetect,
+			bank->base + OMAP24XX_GPIO_FALLINGDETECT);
+	__raw_writel(bank->context.dataout,
+			bank->base + OMAP24XX_GPIO_DATAOUT);
 }
 #endif
 
-- 
1.6.0.4

[PATCH v3 06/20] GPIO: OMAP2+: Make non-wakeup GPIO part of pdata

[Tarun Kanti DebBarma]

From: Charulatha V <charu@ti.com>

Non-wakeup GPIOs are available only in OMAP2. Avoid cpu_is checks by making
non_wakeup_gpios as part of pdata.

Signed-off-by: Charulatha V <charu@ti.com>
---
 arch/arm/mach-omap2/gpio.c             |    8 ++++++++
 arch/arm/plat-omap/include/plat/gpio.h |    1 +
 drivers/gpio/gpio-omap.c               |    8 +-------
 3 files changed, 10 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c
index 2e65377..4952a9d 100644
--- a/arch/arm/mach-omap2/gpio.c
+++ b/arch/arm/mach-omap2/gpio.c
@@ -84,6 +84,14 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
 
 	switch (oh->class->rev) {
 	case 0:
+		if (id == 1)
+			/* non-wakeup GPIO pins for OMAP2 Bank1 */
+			pdata->non_wakeup_gpios = 0xe203ffc0;
+		else if (id == 2)
+			/* non-wakeup GPIO pins for OMAP2 Bank2 */
+			pdata->non_wakeup_gpios = 0x08700040;
+		/* fall through */
+
 	case 1:
 		pdata->bank_type = METHOD_GPIO_24XX;
 		pdata->regs->revision = OMAP24XX_GPIO_REVISION;
diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h
index f7798b5..ce417cd 100644
--- a/arch/arm/plat-omap/include/plat/gpio.h
+++ b/arch/arm/plat-omap/include/plat/gpio.h
@@ -199,6 +199,7 @@ struct omap_gpio_platform_data {
 	int bank_stride;	/* Only needed for omap1 MPUIO */
 	bool dbck_flag;		/* dbck required or not - True for OMAP3&4 */
 	bool loses_context;	/* whether the bank would ever lose context */
+	u32 non_wakeup_gpios;
 
 	struct omap_gpio_reg_offs *regs;
 
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 9a6bf8e..76553f8 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -1016,13 +1016,6 @@ static void omap_gpio_mod_init(struct gpio_bank *bank)
 
 			/* Initialize interface clk ungated, module enabled */
 			__raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
-		} else if (cpu_is_omap24xx()) {
-			static const u32 non_wakeup_gpios[] = {
-				0xe203ffc0, 0x08700040
-			};
-			if (bank->id < ARRAY_SIZE(non_wakeup_gpios))
-				bank->non_wakeup_gpios =
-						non_wakeup_gpios[bank->id];
 		}
 	} else if (cpu_class_is_omap1()) {
 		if (bank_is_mpuio(bank)) {
@@ -1170,6 +1163,7 @@ static int __devinit omap_gpio_probe(struct platform_device *pdev)
 	bank->dbck_flag = pdata->dbck_flag;
 	bank->stride = pdata->bank_stride;
 	bank->width = pdata->bank_width;
+	bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
 	bank->loses_context = pdata->loses_context;
 	bank->get_context_loss_count = pdata->get_context_loss_count;
 	bank->regs = pdata->regs;
-- 
1.6.0.4

[PATCH v3 07/20] GPIO: OMAP: Avoid cpu checks during module ena/disable

[Tarun Kanti DebBarma]

From: Charulatha V <charu@ti.com>

Remove cpu-is checks while enabling/disabling OMAP GPIO module during a gpio
request/free.

Signed-off-by: Charulatha V <charu@ti.com>
---
 arch/arm/mach-omap2/gpio.c             |    2 +
 arch/arm/plat-omap/include/plat/gpio.h |    1 +
 drivers/gpio/gpio-omap.c               |   53 ++++++++++++++------------------
 3 files changed, 26 insertions(+), 30 deletions(-)

diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c
index 4952a9d..cdbc728 100644
--- a/arch/arm/mach-omap2/gpio.c
+++ b/arch/arm/mach-omap2/gpio.c
@@ -107,6 +107,7 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
 		pdata->regs->clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1;
 		pdata->regs->debounce = OMAP24XX_GPIO_DEBOUNCE_VAL;
 		pdata->regs->debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN;
+		pdata->regs->ctrl = OMAP24XX_GPIO_CTRL;
 		break;
 	case 2:
 		pdata->bank_type = METHOD_GPIO_44XX;
@@ -123,6 +124,7 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
 		pdata->regs->clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0;
 		pdata->regs->debounce = OMAP4_GPIO_DEBOUNCINGTIME;
 		pdata->regs->debounce_en = OMAP4_GPIO_DEBOUNCENABLE;
+		pdata->regs->ctrl = OMAP4_GPIO_CTRL;
 		break;
 	default:
 		WARN(1, "Invalid gpio bank_type\n");
diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h
index ce417cd..cf41743 100644
--- a/arch/arm/plat-omap/include/plat/gpio.h
+++ b/arch/arm/plat-omap/include/plat/gpio.h
@@ -188,6 +188,7 @@ struct omap_gpio_reg_offs {
 	u16 clr_irqenable;
 	u16 debounce;
 	u16 debounce_en;
+	u16 ctrl;
 
 	bool irqenable_inv;
 };
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 76553f8..621c4f0 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -83,6 +83,7 @@ struct gpio_bank {
 
 #define GPIO_INDEX(bank, gpio) (gpio % bank->width)
 #define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio))
+#define GPIO_MOD_CTRL_BIT	BIT(0)
 
 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
 {
@@ -572,22 +573,18 @@ static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
 		__raw_writel(__raw_readl(reg) | (1 << offset), reg);
 	}
 #endif
-	if (!cpu_class_is_omap1()) {
-		if (!bank->mod_usage) {
-			void __iomem *reg = bank->base;
-			u32 ctrl;
-
-			if (cpu_is_omap24xx() || cpu_is_omap34xx())
-				reg += OMAP24XX_GPIO_CTRL;
-			else if (cpu_is_omap44xx())
-				reg += OMAP4_GPIO_CTRL;
-			ctrl = __raw_readl(reg);
-			/* Module is enabled, clocks are not gated */
-			ctrl &= 0xFFFFFFFE;
-			__raw_writel(ctrl, reg);
-		}
-		bank->mod_usage |= 1 << offset;
+	if (bank->regs->ctrl && !bank->mod_usage) {
+		void __iomem *reg = bank->base + bank->regs->ctrl;
+		u32 ctrl;
+
+		ctrl = __raw_readl(reg);
+		/* Module is enabled, clocks are not gated */
+		ctrl &= ~GPIO_MOD_CTRL_BIT;
+		__raw_writel(ctrl, reg);
 	}
+
+	bank->mod_usage |= 1 << offset;
+
 	spin_unlock_irqrestore(&bank->lock, flags);
 
 	return 0;
@@ -620,22 +617,18 @@ static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
 		__raw_writel(1 << offset, reg);
 	}
 #endif
-	if (!cpu_class_is_omap1()) {
-		bank->mod_usage &= ~(1 << offset);
-		if (!bank->mod_usage) {
-			void __iomem *reg = bank->base;
-			u32 ctrl;
-
-			if (cpu_is_omap24xx() || cpu_is_omap34xx())
-				reg += OMAP24XX_GPIO_CTRL;
-			else if (cpu_is_omap44xx())
-				reg += OMAP4_GPIO_CTRL;
-			ctrl = __raw_readl(reg);
-			/* Module is disabled, clocks are gated */
-			ctrl |= 1;
-			__raw_writel(ctrl, reg);
-		}
+	bank->mod_usage &= ~(1 << offset);
+
+	if (bank->regs->ctrl && !bank->mod_usage) {
+		void __iomem *reg = bank->base + bank->regs->ctrl;
+		u32 ctrl;
+
+		ctrl = __raw_readl(reg);
+		/* Module is disabled, clocks are gated */
+		ctrl |= GPIO_MOD_CTRL_BIT;
+		__raw_writel(ctrl, reg);
 	}
+
 	_reset_gpio(bank, bank->chip.base + offset);
 	spin_unlock_irqrestore(&bank->lock, flags);
 }
-- 
1.6.0.4

[PATCH v3 08/20] GPIO: OMAP: Use wkup regs off/suspend support flag

[Tarun Kanti DebBarma]

From: Charulatha V <charu@ti.com>

Wakeup register offsets are initialized according to OMAP versions
during device registration. These explicit checks are no longer needed.

mpuio_init() function is defined under #ifdefs. It is required only in case
of MPUIO bank type and only when PM operations are supported by it.
This is applicable only in case of OMAP16xx SoC's MPUIO GPIO bank type.
For all the other cases it is a dummy function. Hence clean up the same
and remove all the OMAP SoC specific #ifdefs.

bank_is_mpuio() is defined as a check to identify if the bank type is MPUIO.
It is not required to define it separately as zero for OMAP2plus. Remove this.

Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
Signed-off-by: Charulatha V <charu@ti.com>
---
 arch/arm/mach-omap1/gpio16xx.c         |    3 +
 arch/arm/mach-omap2/gpio.c             |    6 ++
 arch/arm/plat-omap/include/plat/gpio.h |    3 +
 drivers/gpio/gpio-omap.c               |  120 +++++---------------------------
 4 files changed, 31 insertions(+), 101 deletions(-)

diff --git a/arch/arm/mach-omap1/gpio16xx.c b/arch/arm/mach-omap1/gpio16xx.c
index 9a97e60..d81c1e5 100644
--- a/arch/arm/mach-omap1/gpio16xx.c
+++ b/arch/arm/mach-omap1/gpio16xx.c
@@ -89,6 +89,9 @@ static struct omap_gpio_reg_offs omap16xx_gpio_regs = {
 	.irqenable	= OMAP1610_GPIO_IRQENABLE1,
 	.set_irqenable	= OMAP1610_GPIO_SET_IRQENABLE1,
 	.clr_irqenable	= OMAP1610_GPIO_CLEAR_IRQENABLE1,
+	.wkup_status	= OMAP1610_GPIO_WAKEUPENABLE,
+	.wkup_clear	= OMAP1610_GPIO_CLEAR_WAKEUPENA,
+	.wkup_set	= OMAP1610_GPIO_SET_WAKEUPENA,
 };
 
 static struct __initdata omap_gpio_platform_data omap16xx_gpio1_config = {
diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c
index cdbc728..9387496 100644
--- a/arch/arm/mach-omap2/gpio.c
+++ b/arch/arm/mach-omap2/gpio.c
@@ -108,6 +108,9 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
 		pdata->regs->debounce = OMAP24XX_GPIO_DEBOUNCE_VAL;
 		pdata->regs->debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN;
 		pdata->regs->ctrl = OMAP24XX_GPIO_CTRL;
+		pdata->regs->wkup_status = OMAP24XX_GPIO_WAKE_EN;
+		pdata->regs->wkup_clear = OMAP24XX_GPIO_CLEARWKUENA;
+		pdata->regs->wkup_set = OMAP24XX_GPIO_SETWKUENA;
 		break;
 	case 2:
 		pdata->bank_type = METHOD_GPIO_44XX;
@@ -125,6 +128,9 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
 		pdata->regs->debounce = OMAP4_GPIO_DEBOUNCINGTIME;
 		pdata->regs->debounce_en = OMAP4_GPIO_DEBOUNCENABLE;
 		pdata->regs->ctrl = OMAP4_GPIO_CTRL;
+		pdata->regs->wkup_status = OMAP4_GPIO_IRQWAKEN0;
+		pdata->regs->wkup_clear = OMAP4_GPIO_IRQWAKEN0;
+		pdata->regs->wkup_set = OMAP4_GPIO_IRQWAKEN0;
 		break;
 	default:
 		WARN(1, "Invalid gpio bank_type\n");
diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h
index cf41743..d941d92 100644
--- a/arch/arm/plat-omap/include/plat/gpio.h
+++ b/arch/arm/plat-omap/include/plat/gpio.h
@@ -189,6 +189,9 @@ struct omap_gpio_reg_offs {
 	u16 debounce;
 	u16 debounce_en;
 	u16 ctrl;
+	u16 wkup_status;
+	u16 wkup_clear;
+	u16 wkup_set;
 
 	bool irqenable_inv;
 };
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 621c4f0..abb85df 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -50,10 +50,8 @@ struct gpio_bank {
 	u16 irq;
 	u16 virtual_irq_start;
 	int method;
-#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
 	u32 suspend_wakeup;
 	u32 saved_wakeup;
-#endif
 	u32 non_wakeup_gpios;
 	u32 enabled_non_wakeup_gpios;
 	struct gpio_regs context;
@@ -596,27 +594,11 @@ static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
 	unsigned long flags;
 
 	spin_lock_irqsave(&bank->lock, flags);
-#ifdef CONFIG_ARCH_OMAP16XX
-	if (bank->method == METHOD_GPIO_1610) {
-		/* Disable wake-up during idle for dynamic tick */
-		void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
-		__raw_writel(1 << offset, reg);
-	}
-#endif
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
-	if (bank->method == METHOD_GPIO_24XX) {
-		/* Disable wake-up during idle for dynamic tick */
-		void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
-		__raw_writel(1 << offset, reg);
-	}
-#endif
-#ifdef CONFIG_ARCH_OMAP4
-	if (bank->method == METHOD_GPIO_44XX) {
+
+	if (bank->regs->wkup_clear)
 		/* Disable wake-up during idle for dynamic tick */
-		void __iomem *reg = bank->base + OMAP4_GPIO_IRQWAKEN0;
-		__raw_writel(1 << offset, reg);
-	}
-#endif
+		__raw_writel(1 << offset, bank->base + bank->regs->wkup_clear);
+
 	bank->mod_usage &= ~(1 << offset);
 
 	if (bank->regs->ctrl && !bank->mod_usage) {
@@ -789,15 +771,8 @@ static struct irq_chip gpio_irq_chip = {
 };
 
 /*---------------------------------------------------------------------*/
-
-#ifdef CONFIG_ARCH_OMAP1
-
 #define bank_is_mpuio(bank)	((bank)->method == METHOD_MPUIO)
 
-#ifdef CONFIG_ARCH_OMAP16XX
-
-#include <linux/platform_device.h>
-
 static int omap_mpuio_suspend_noirq(struct device *dev)
 {
 	struct platform_device *pdev = to_platform_device(dev);
@@ -859,17 +834,6 @@ static inline void mpuio_init(struct gpio_bank *bank)
 		(void) platform_device_register(&omap_mpuio_device);
 }
 
-#else
-static inline void mpuio_init(struct gpio_bank *bank) {}
-#endif	/* 16xx */
-
-#else
-
-#define bank_is_mpuio(bank)	0
-static inline void mpuio_init(struct gpio_bank *bank) {}
-
-#endif
-
 /*---------------------------------------------------------------------*/
 
 /* REVISIT these are stupid implementations!  replace by ones that
@@ -1061,8 +1025,8 @@ omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start,
 	ct->chip.irq_mask = irq_gc_mask_set_bit;
 	ct->chip.irq_unmask = irq_gc_mask_clr_bit;
 	ct->chip.irq_set_type = gpio_irq_type;
-	/* REVISIT: assuming only 16xx supports MPUIO wake events */
-	if (cpu_is_omap16xx())
+
+	if (bank->regs->wkup_status)
 		ct->chip.irq_set_wake = gpio_wake_enable,
 
 	ct->regs.mask = OMAP_MPUIO_GPIO_INT / bank->stride;
@@ -1090,9 +1054,8 @@ static void __devinit omap_gpio_chip_init(struct gpio_bank *bank)
 	bank->chip.to_irq = gpio_2irq;
 	if (bank_is_mpuio(bank)) {
 		bank->chip.label = "mpuio";
-#ifdef CONFIG_ARCH_OMAP16XX
-		bank->chip.dev = &omap_mpuio_device.dev;
-#endif
+		if (bank->regs->wkup_status)
+			bank->chip.dev = &omap_mpuio_device.dev;
 		bank->chip.base = OMAP_MPUIO(0);
 	} else {
 		bank->chip.label = "gpio";
@@ -1202,45 +1165,22 @@ err_exit:
 	return ret;
 }
 
-#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
 static int omap_gpio_suspend(void)
 {
 	struct gpio_bank *bank;
 
-	if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
-		return 0;
-
 	list_for_each_entry(bank, &omap_gpio_list, node) {
 		void __iomem *wake_status;
 		void __iomem *wake_clear;
 		void __iomem *wake_set;
 		unsigned long flags;
 
-		switch (bank->method) {
-#ifdef CONFIG_ARCH_OMAP16XX
-		case METHOD_GPIO_1610:
-			wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
-			wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
-			wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
-			break;
-#endif
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
-		case METHOD_GPIO_24XX:
-			wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
-			wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
-			wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
-			break;
-#endif
-#ifdef CONFIG_ARCH_OMAP4
-		case METHOD_GPIO_44XX:
-			wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
-			wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
-			wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
-			break;
-#endif
-		default:
-			continue;
-		}
+		if (!bank->regs->wkup_status)
+			return 0;
+
+		wake_status = bank->base + bank->regs->wkup_status;
+		wake_clear = bank->base + bank->regs->wkup_clear;
+		wake_set = bank->base + bank->regs->wkup_set;
 
 		spin_lock_irqsave(&bank->lock, flags);
 		bank->saved_wakeup = __raw_readl(wake_status);
@@ -1256,36 +1196,16 @@ static void omap_gpio_resume(void)
 {
 	struct gpio_bank *bank;
 
-	if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
-		return;
-
 	list_for_each_entry(bank, &omap_gpio_list, node) {
 		void __iomem *wake_clear;
 		void __iomem *wake_set;
 		unsigned long flags;
 
-		switch (bank->method) {
-#ifdef CONFIG_ARCH_OMAP16XX
-		case METHOD_GPIO_1610:
-			wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
-			wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
-			break;
-#endif
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
-		case METHOD_GPIO_24XX:
-			wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
-			wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
-			break;
-#endif
-#ifdef CONFIG_ARCH_OMAP4
-		case METHOD_GPIO_44XX:
-			wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
-			wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
-			break;
-#endif
-		default:
-			continue;
-		}
+		if (!bank->regs->wkup_status)
+			return;
+
+		wake_clear = bank->base + bank->regs->wkup_clear;
+		wake_set = bank->base + bank->regs->wkup_set;
 
 		spin_lock_irqsave(&bank->lock, flags);
 		__raw_writel(0xffffffff, wake_clear);
@@ -1299,8 +1219,6 @@ static struct syscore_ops omap_gpio_syscore_ops = {
 	.resume		= omap_gpio_resume,
 };
 
-#endif
-
 #ifdef CONFIG_ARCH_OMAP2PLUS
 
 static void omap_gpio_save_context(struct gpio_bank *bank);
-- 
1.6.0.4

Re: [PATCH v3 08/20] GPIO: OMAP: Use wkup regs off/suspend support flag

[Kevin Hilman]

Tarun Kanti DebBarma <tarun.kanti@ti.com> writes:

> From: Charulatha V <charu@ti.com>
>
> Wakeup register offsets are initialized according to OMAP versions
> during device registration. These explicit checks are no longer needed.
>
> mpuio_init() function is defined under #ifdefs. It is required only in case
> of MPUIO bank type and only when PM operations are supported by it.
> This is applicable only in case of OMAP16xx SoC's MPUIO GPIO bank type.
> For all the other cases it is a dummy function. Hence clean up the same
> and remove all the OMAP SoC specific #ifdefs.
>
> bank_is_mpuio() is defined as a check to identify if the bank type is MPUIO.
> It is not required to define it separately as zero for OMAP2plus. Remove this.

The MPUIO stuff should really be separated from the wkup register stuff.

[...]

> @@ -596,27 +594,11 @@ static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
>  	unsigned long flags;
>  
>  	spin_lock_irqsave(&bank->lock, flags);
> -#ifdef CONFIG_ARCH_OMAP16XX
> -	if (bank->method == METHOD_GPIO_1610) {
> -		/* Disable wake-up during idle for dynamic tick */
> -		void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
> -		__raw_writel(1 << offset, reg);
> -	}
> -#endif
> -#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
> -	if (bank->method == METHOD_GPIO_24XX) {
> -		/* Disable wake-up during idle for dynamic tick */
> -		void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
> -		__raw_writel(1 << offset, reg);
> -	}
> -#endif
> -#ifdef CONFIG_ARCH_OMAP4
> -	if (bank->method == METHOD_GPIO_44XX) {
> +
> +	if (bank->regs->wkup_clear)
>  		/* Disable wake-up during idle for dynamic tick */
> -		void __iomem *reg = bank->base + OMAP4_GPIO_IRQWAKEN0;
> -		__raw_writel(1 << offset, reg);
> -	}
> -#endif
> +		__raw_writel(1 << offset, bank->base + bank->regs->wkup_clear);
> +

Note that this is not an equivalent change.  The current code is using
IRQWAKEN0 register and you're changing it to use the CLEARWKUPENA
register.

While the current code is clearly broken since it's not doing a
read/modify/write, this change is not very clear either, and not
documented in the changelog.

I think a better approach is to just drop the parts of this patch where
the wkup_set and wkup_clear registers are added.  Since they are removed
in patch 12/20 anyways, maybe moving 12/20 earlier in the series
would make this clearer and avoid unnessary additions followed by
removals.

Kevin

RE: [PATCH v3 08/20] GPIO: OMAP: Use wkup regs off/suspend support flag

[DebBarma, Tarun Kanti]

[...]
> 
> Tarun Kanti DebBarma <tarun.kanti@ti.com> writes:
> 
> > From: Charulatha V <charu@ti.com>
> >
> > Wakeup register offsets are initialized according to OMAP versions
> > during device registration. These explicit checks are no longer needed.
> >
> > mpuio_init() function is defined under #ifdefs. It is required only in
> case
> > of MPUIO bank type and only when PM operations are supported by it.
> > This is applicable only in case of OMAP16xx SoC's MPUIO GPIO bank type.
> > For all the other cases it is a dummy function. Hence clean up the same
> > and remove all the OMAP SoC specific #ifdefs.
> >
> > bank_is_mpuio() is defined as a check to identify if the bank type is
> MPUIO.
> > It is not required to define it separately as zero for OMAP2plus. Remove
> this.
> 
> The MPUIO stuff should really be separated from the wkup register stuff.
Ok.
> 
> [...]
> 
> > @@ -596,27 +594,11 @@ static void omap_gpio_free(struct gpio_chip *chip,
> unsigned offset)
> >  	unsigned long flags;
> >
> >  	spin_lock_irqsave(&bank->lock, flags);
> > -#ifdef CONFIG_ARCH_OMAP16XX
> > -	if (bank->method == METHOD_GPIO_1610) {
> > -		/* Disable wake-up during idle for dynamic tick */
> > -		void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
> > -		__raw_writel(1 << offset, reg);
> > -	}
> > -#endif
> > -#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
> > -	if (bank->method == METHOD_GPIO_24XX) {
> > -		/* Disable wake-up during idle for dynamic tick */
> > -		void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
> > -		__raw_writel(1 << offset, reg);
> > -	}
> > -#endif
> > -#ifdef CONFIG_ARCH_OMAP4
> > -	if (bank->method == METHOD_GPIO_44XX) {
> > +
> > +	if (bank->regs->wkup_clear)
> >  		/* Disable wake-up during idle for dynamic tick */
> > -		void __iomem *reg = bank->base + OMAP4_GPIO_IRQWAKEN0;
> > -		__raw_writel(1 << offset, reg);
> > -	}
> > -#endif
> > +		__raw_writel(1 << offset, bank->base + bank->regs->wkup_clear);
> > +
> 
> Note that this is not an equivalent change.  The current code is using
> IRQWAKEN0 register and you're changing it to use the CLEARWKUPENA
> register.
Ok, I missed that.

> 
> While the current code is clearly broken since it's not doing a
> read/modify/write, this change is not very clear either, and not
> documented in the changelog.
> 
> I think a better approach is to just drop the parts of this patch where
> the wkup_set and wkup_clear registers are added.  Since they are removed
> in patch 12/20 anyways, maybe moving 12/20 earlier in the series
> would make this clearer and avoid unnessary additions followed by
> removals.
I will consolidate. Thanks.
--
Tarun
> 
> Kevin

[PATCH v3 09/20] GPIO: OMAP: Use level/edge detect reg offsets

[Tarun Kanti DebBarma]

From: Charulatha V <charu@ti.com>

By adding level and edge detection register offsets and then initializing them
correctly according to OMAP versions during device registrations we can now remove
lot of revision checks in these functions.

Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
Signed-off-by: Charulatha V <charu@ti.com>
---
 arch/arm/mach-omap2/gpio.c             |    8 ++
 arch/arm/plat-omap/include/plat/gpio.h |    4 +
 drivers/gpio/gpio-omap.c               |  118 ++++++++++----------------------
 3 files changed, 48 insertions(+), 82 deletions(-)

diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c
index 9387496..0c7e403 100644
--- a/arch/arm/mach-omap2/gpio.c
+++ b/arch/arm/mach-omap2/gpio.c
@@ -111,6 +111,10 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
 		pdata->regs->wkup_status = OMAP24XX_GPIO_WAKE_EN;
 		pdata->regs->wkup_clear = OMAP24XX_GPIO_CLEARWKUENA;
 		pdata->regs->wkup_set = OMAP24XX_GPIO_SETWKUENA;
+		pdata->regs->leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0;
+		pdata->regs->leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1;
+		pdata->regs->risingdetect = OMAP24XX_GPIO_RISINGDETECT;
+		pdata->regs->fallingdetect = OMAP24XX_GPIO_FALLINGDETECT;
 		break;
 	case 2:
 		pdata->bank_type = METHOD_GPIO_44XX;
@@ -131,6 +135,10 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
 		pdata->regs->wkup_status = OMAP4_GPIO_IRQWAKEN0;
 		pdata->regs->wkup_clear = OMAP4_GPIO_IRQWAKEN0;
 		pdata->regs->wkup_set = OMAP4_GPIO_IRQWAKEN0;
+		pdata->regs->leveldetect0 = OMAP4_GPIO_LEVELDETECT0;
+		pdata->regs->leveldetect1 = OMAP4_GPIO_LEVELDETECT1;
+		pdata->regs->risingdetect = OMAP4_GPIO_RISINGDETECT;
+		pdata->regs->fallingdetect = OMAP4_GPIO_FALLINGDETECT;
 		break;
 	default:
 		WARN(1, "Invalid gpio bank_type\n");
diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h
index d941d92..a843669 100644
--- a/arch/arm/plat-omap/include/plat/gpio.h
+++ b/arch/arm/plat-omap/include/plat/gpio.h
@@ -192,6 +192,10 @@ struct omap_gpio_reg_offs {
 	u16 wkup_status;
 	u16 wkup_clear;
 	u16 wkup_set;
+	u16 leveldetect0;
+	u16 leveldetect1;
+	u16 risingdetect;
+	u16 fallingdetect;
 
 	bool irqenable_inv;
 };
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index abb85df..66c837f 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -252,15 +252,9 @@ static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
 			bank->enabled_non_wakeup_gpios &= ~gpio_bit;
 	}
 
-	if (cpu_is_omap44xx()) {
-		bank->level_mask =
-			__raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
-			__raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
-	} else {
-		bank->level_mask =
-			__raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
-			__raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
-	}
+	bank->level_mask =
+		__raw_readl(bank->base + bank->regs->leveldetect0) |
+		__raw_readl(bank->base + bank->regs->leveldetect1);
 }
 #endif
 
@@ -400,12 +394,12 @@ static int gpio_irq_type(struct irq_data *d, unsigned type)
 	if (type & ~IRQ_TYPE_SENSE_MASK)
 		return -EINVAL;
 
-	/* OMAP1 allows only only edge triggering */
-	if (!cpu_class_is_omap2()
-			&& (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
+	bank = irq_data_get_irq_chip_data(d);
+
+	if (bank->regs->leveldetect0 && (type &
+			(IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
 		return -EINVAL;
 
-	bank = irq_data_get_irq_chip_data(d);
 	spin_lock_irqsave(&bank->lock, flags);
 	retval = _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), type);
 	spin_unlock_irqrestore(&bank->lock, flags);
@@ -652,9 +646,8 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 		if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
 			isr &= 0x0000ffff;
 
-		if (cpu_class_is_omap2()) {
+		if (bank->level_mask)
 			level_mask = bank->level_mask & enabled;
-		}
 
 		/* clear edge sensitive interrupts before handler(s) are
 		called so that we don't miss any interrupt occurred while
@@ -1247,40 +1240,18 @@ void omap2_gpio_prepare_for_idle(int off_mode)
 		if (!(bank->enabled_non_wakeup_gpios))
 			goto save_gpio_ctx;
 
-		if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
-			bank->saved_datain = __raw_readl(bank->base +
-					OMAP24XX_GPIO_DATAIN);
-			l1 = __raw_readl(bank->base +
-					OMAP24XX_GPIO_FALLINGDETECT);
-			l2 = __raw_readl(bank->base +
-					OMAP24XX_GPIO_RISINGDETECT);
-		}
-
-		if (cpu_is_omap44xx()) {
-			bank->saved_datain = __raw_readl(bank->base +
-						OMAP4_GPIO_DATAIN);
-			l1 = __raw_readl(bank->base +
-						OMAP4_GPIO_FALLINGDETECT);
-			l2 = __raw_readl(bank->base +
-						OMAP4_GPIO_RISINGDETECT);
-		}
+		bank->saved_datain = __raw_readl(bank->base +
+							bank->regs->datain);
+		l1 = __raw_readl(bank->base + bank->regs->fallingdetect);
+		l2 = __raw_readl(bank->base + bank->regs->risingdetect);
 
 		bank->saved_fallingdetect = l1;
 		bank->saved_risingdetect = l2;
 		l1 &= ~bank->enabled_non_wakeup_gpios;
 		l2 &= ~bank->enabled_non_wakeup_gpios;
 
-		if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
-			__raw_writel(l1, bank->base +
-					OMAP24XX_GPIO_FALLINGDETECT);
-			__raw_writel(l2, bank->base +
-					OMAP24XX_GPIO_RISINGDETECT);
-		}
-
-		if (cpu_is_omap44xx()) {
-			__raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
-			__raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
-		}
+		__raw_writel(l1, bank->base + bank->regs->fallingdetect);
+		__raw_writel(l2, bank->base + bank->regs->risingdetect);
 
 save_gpio_ctx:
 		if (bank->get_context_loss_count)
@@ -1317,21 +1288,11 @@ void omap2_gpio_resume_after_idle(void)
 		if (!(bank->enabled_non_wakeup_gpios))
 			continue;
 
-		if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
-			__raw_writel(bank->saved_fallingdetect,
-				 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
-			__raw_writel(bank->saved_risingdetect,
-				 bank->base + OMAP24XX_GPIO_RISINGDETECT);
-			l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
-		}
-
-		if (cpu_is_omap44xx()) {
-			__raw_writel(bank->saved_fallingdetect,
-				 bank->base + OMAP4_GPIO_FALLINGDETECT);
-			__raw_writel(bank->saved_risingdetect,
-				 bank->base + OMAP4_GPIO_RISINGDETECT);
-			l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
-		}
+		__raw_writel(bank->saved_fallingdetect,
+				bank->base + bank->regs->fallingdetect);
+		__raw_writel(bank->saved_risingdetect,
+				bank->base + bank->regs->risingdetect);
+		l = __raw_readl(bank->base + bank->regs->datain);
 
 		/* Check if any of the non-wakeup interrupt GPIOs have changed
 		 * state.  If so, generate an IRQ by software.  This is
@@ -1359,35 +1320,28 @@ void omap2_gpio_resume_after_idle(void)
 		if (gen) {
 			u32 old0, old1;
 
+			old0 = __raw_readl(bank->base +
+						bank->regs->leveldetect0);
+			old1 = __raw_readl(bank->base +
+						bank->regs->leveldetect1);
+
+			__raw_writel(old0, bank->base +
+						bank->regs->leveldetect0);
+			__raw_writel(old1, bank->base +
+						bank->regs->leveldetect1);
 			if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
-				old0 = __raw_readl(bank->base +
-					OMAP24XX_GPIO_LEVELDETECT0);
-				old1 = __raw_readl(bank->base +
-					OMAP24XX_GPIO_LEVELDETECT1);
-				__raw_writel(old0 | gen, bank->base +
-					OMAP24XX_GPIO_LEVELDETECT0);
-				__raw_writel(old1 | gen, bank->base +
-					OMAP24XX_GPIO_LEVELDETECT1);
-				__raw_writel(old0, bank->base +
-					OMAP24XX_GPIO_LEVELDETECT0);
-				__raw_writel(old1, bank->base +
-					OMAP24XX_GPIO_LEVELDETECT1);
+				old0 |= gen;
+				old1 |= gen;
 			}
 
 			if (cpu_is_omap44xx()) {
-				old0 = __raw_readl(bank->base +
-						OMAP4_GPIO_LEVELDETECT0);
-				old1 = __raw_readl(bank->base +
-						OMAP4_GPIO_LEVELDETECT1);
-				__raw_writel(old0 | l, bank->base +
-						OMAP4_GPIO_LEVELDETECT0);
-				__raw_writel(old1 | l, bank->base +
-						OMAP4_GPIO_LEVELDETECT1);
-				__raw_writel(old0, bank->base +
-						OMAP4_GPIO_LEVELDETECT0);
-				__raw_writel(old1, bank->base +
-						OMAP4_GPIO_LEVELDETECT1);
+				old0 |= l;
+				old1 |= l;
 			}
+			__raw_writel(old0, bank->base +
+						bank->regs->leveldetect0);
+			__raw_writel(old1, bank->base +
+						bank->regs->leveldetect1);
 		}
 	}
 }
-- 
1.6.0.4

Re: [PATCH v3 09/20] GPIO: OMAP: Use level/edge detect reg offsets

[Kevin Hilman]

Tarun Kanti DebBarma <tarun.kanti@ti.com> writes:

> From: Charulatha V <charu@ti.com>
>
> By adding level and edge detection register offsets and then initializing them
> correctly according to OMAP versions during device registrations we can now remove
> lot of revision checks in these functions.
>
> Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
> Signed-off-by: Charulatha V <charu@ti.com>

Found the bug causing GPIO IRQ triggering failures for Blaze and Zoom3
GPIO-based network IRQs...

> @@ -400,12 +394,12 @@ static int gpio_irq_type(struct irq_data *d, unsigned type)
>  	if (type & ~IRQ_TYPE_SENSE_MASK)
>  		return -EINVAL;
>  
> -	/* OMAP1 allows only only edge triggering */
> -	if (!cpu_class_is_omap2()
> -			&& (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
> +	bank = irq_data_get_irq_chip_data(d);
> +
> +	if (bank->regs->leveldetect0 && (type &
> +			(IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))

This check is not the same as the one it replaced.  This check should
be:

	if (!bank->regs->leveldetect0 &&
	    (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)))
		return -EINVAL;

Note the formatting changes also for readability, but the bugfix is just
adding the '!' before regs->leveldetect0.

Kevin

RE: [PATCH v3 09/20] GPIO: OMAP: Use level/edge detect reg offsets

[DebBarma, Tarun Kanti]

> -----Original Message-----
> From: Hilman, Kevin
> Sent: Wednesday, July 06, 2011 5:22 AM
> To: DebBarma, Tarun Kanti
> Cc: linux-omap@vger.kernel.org; Shilimkar, Santosh; tony@atomide.com;
> Varadarajan, Charulatha
> Subject: Re: [PATCH v3 09/20] GPIO: OMAP: Use level/edge detect reg
> offsets
> 
> Tarun Kanti DebBarma <tarun.kanti@ti.com> writes:
> 
> > From: Charulatha V <charu@ti.com>
> >
> > By adding level and edge detection register offsets and then
> initializing them
> > correctly according to OMAP versions during device registrations we can
> now remove
> > lot of revision checks in these functions.
> >
> > Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
> > Signed-off-by: Charulatha V <charu@ti.com>
> 
> Found the bug causing GPIO IRQ triggering failures for Blaze and Zoom3
> GPIO-based network IRQs...
> 
> > @@ -400,12 +394,12 @@ static int gpio_irq_type(struct irq_data *d,
> unsigned type)
> >  	if (type & ~IRQ_TYPE_SENSE_MASK)
> >  		return -EINVAL;
> >
> > -	/* OMAP1 allows only only edge triggering */
> > -	if (!cpu_class_is_omap2()
> > -			&& (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
> > +	bank = irq_data_get_irq_chip_data(d);
> > +
> > +	if (bank->regs->leveldetect0 && (type &
> > +			(IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
> 
> This check is not the same as the one it replaced.  This check should
> be:
> 
> 	if (!bank->regs->leveldetect0 &&
> 	    (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)))
> 		return -EINVAL;
> 
> Note the formatting changes also for readability, but the bugfix is just
> adding the '!' before regs->leveldetect0.
Yes, thanks. I will make the correction.
--
Tarun

> 
> Kevin

Re: [PATCH v3 09/20] GPIO: OMAP: Use level/edge detect reg offsets

[Kevin Hilman]

Tarun Kanti DebBarma <tarun.kanti@ti.com> writes:

> From: Charulatha V <charu@ti.com>
>
> By adding level and edge detection register offsets and then initializing them
> correctly according to OMAP versions during device registrations we can now remove
> lot of revision checks in these functions.
>
> Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
> Signed-off-by: Charulatha V <charu@ti.com>

Looks good.   One very minor nit below...

[...]

> @@ -1247,40 +1240,18 @@ void omap2_gpio_prepare_for_idle(int off_mode)
>  		if (!(bank->enabled_non_wakeup_gpios))
>  			goto save_gpio_ctx;
>  
> -		if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
> -			bank->saved_datain = __raw_readl(bank->base +
> -					OMAP24XX_GPIO_DATAIN);
> -			l1 = __raw_readl(bank->base +
> -					OMAP24XX_GPIO_FALLINGDETECT);
> -			l2 = __raw_readl(bank->base +
> -					OMAP24XX_GPIO_RISINGDETECT);
> -		}
> -
> -		if (cpu_is_omap44xx()) {
> -			bank->saved_datain = __raw_readl(bank->base +
> -						OMAP4_GPIO_DATAIN);
> -			l1 = __raw_readl(bank->base +
> -						OMAP4_GPIO_FALLINGDETECT);
> -			l2 = __raw_readl(bank->base +
> -						OMAP4_GPIO_RISINGDETECT);
> -		}
> +		bank->saved_datain = __raw_readl(bank->base +
> +							bank->regs->datain);
> +		l1 = __raw_readl(bank->base + bank->regs->fallingdetect);
> +		l2 = __raw_readl(bank->base + bank->regs->risingdetect);

The l1 = 0, l2 = 0 assignments can now be removed at the beginning of
this function also.  Similarily for the 'l = 0' assignment in the
runtime_resume function.

Kevin

RE: [PATCH v3 09/20] GPIO: OMAP: Use level/edge detect reg offsets

[DebBarma, Tarun Kanti]

[...]
> >
> > By adding level and edge detection register offsets and then
> initializing them
> > correctly according to OMAP versions during device registrations we can
> now remove
> > lot of revision checks in these functions.
> >
> > Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
> > Signed-off-by: Charulatha V <charu@ti.com>
> 
> Looks good.   One very minor nit below...
> 
> [...]
> 
> > @@ -1247,40 +1240,18 @@ void omap2_gpio_prepare_for_idle(int off_mode)
> >  		if (!(bank->enabled_non_wakeup_gpios))
> >  			goto save_gpio_ctx;
> >
> > -		if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
> > -			bank->saved_datain = __raw_readl(bank->base +
> > -					OMAP24XX_GPIO_DATAIN);
> > -			l1 = __raw_readl(bank->base +
> > -					OMAP24XX_GPIO_FALLINGDETECT);
> > -			l2 = __raw_readl(bank->base +
> > -					OMAP24XX_GPIO_RISINGDETECT);
> > -		}
> > -
> > -		if (cpu_is_omap44xx()) {
> > -			bank->saved_datain = __raw_readl(bank->base +
> > -						OMAP4_GPIO_DATAIN);
> > -			l1 = __raw_readl(bank->base +
> > -						OMAP4_GPIO_FALLINGDETECT);
> > -			l2 = __raw_readl(bank->base +
> > -						OMAP4_GPIO_RISINGDETECT);
> > -		}
> > +		bank->saved_datain = __raw_readl(bank->base +
> > +							bank->regs->datain);
> > +		l1 = __raw_readl(bank->base + bank->regs->fallingdetect);
> > +		l2 = __raw_readl(bank->base + bank->regs->risingdetect);
> 
> The l1 = 0, l2 = 0 assignments can now be removed at the beginning of
> this function also.  Similarily for the 'l = 0' assignment in the
> runtime_resume function.
Ok.
--
Tarun
> 
> Kevin

[PATCH v3 10/20] GPIO: OMAP: Remove hardcoded offsets in ctxt save/restore

[Tarun Kanti DebBarma]

It is not required to use hard-coded offsets any more in context save and
restore functions and instead use the generic offsets which have been correctly
initialized during device registration.

Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
Signed-off-by: Charulatha V <charu@ti.com>
---
 arch/arm/mach-omap2/gpio.c             |    2 +
 arch/arm/plat-omap/include/plat/gpio.h |    1 +
 drivers/gpio/gpio-omap.c               |   42 +++++++++++++++----------------
 3 files changed, 23 insertions(+), 22 deletions(-)

diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c
index 0c7e403..54c8328 100644
--- a/arch/arm/mach-omap2/gpio.c
+++ b/arch/arm/mach-omap2/gpio.c
@@ -103,6 +103,7 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
 		pdata->regs->irqstatus = OMAP24XX_GPIO_IRQSTATUS1;
 		pdata->regs->irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2;
 		pdata->regs->irqenable = OMAP24XX_GPIO_IRQENABLE1;
+		pdata->regs->irqenable2 = OMAP24XX_GPIO_IRQENABLE2;
 		pdata->regs->set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1;
 		pdata->regs->clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1;
 		pdata->regs->debounce = OMAP24XX_GPIO_DEBOUNCE_VAL;
@@ -127,6 +128,7 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
 		pdata->regs->irqstatus = OMAP4_GPIO_IRQSTATUS0;
 		pdata->regs->irqstatus2 = OMAP4_GPIO_IRQSTATUS1;
 		pdata->regs->irqenable = OMAP4_GPIO_IRQSTATUSSET0;
+		pdata->regs->irqenable2 = OMAP4_GPIO_IRQSTATUSSET1;
 		pdata->regs->set_irqenable = OMAP4_GPIO_IRQSTATUSSET0;
 		pdata->regs->clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0;
 		pdata->regs->debounce = OMAP4_GPIO_DEBOUNCINGTIME;
diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h
index a843669..1cf13a2 100644
--- a/arch/arm/plat-omap/include/plat/gpio.h
+++ b/arch/arm/plat-omap/include/plat/gpio.h
@@ -184,6 +184,7 @@ struct omap_gpio_reg_offs {
 	u16 irqstatus;
 	u16 irqstatus2;
 	u16 irqenable;
+	u16 irqenable2;
 	u16 set_irqenable;
 	u16 clr_irqenable;
 	u16 debounce;
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 66c837f..2339c29 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -1349,45 +1349,43 @@ void omap2_gpio_resume_after_idle(void)
 static void omap_gpio_save_context(struct gpio_bank *bank)
 {
 	bank->context.irqenable1 =
-		__raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
+			__raw_readl(bank->base + bank->regs->irqenable);
 	bank->context.irqenable2 =
-		__raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
+			__raw_readl(bank->base + bank->regs->irqenable2);
 	bank->context.wake_en =
-		__raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
-	bank->context.ctrl = __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
-	bank->context.oe = __raw_readl(bank->base + OMAP24XX_GPIO_OE);
+			__raw_readl(bank->base + bank->regs->wkup_status);
+	bank->context.ctrl = __raw_readl(bank->base + bank->regs->ctrl);
+	bank->context.oe = __raw_readl(bank->base + bank->regs->direction);
 	bank->context.leveldetect0 =
-		__raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
+			__raw_readl(bank->base + bank->regs->leveldetect0);
 	bank->context.leveldetect1 =
-		__raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
+			__raw_readl(bank->base + bank->regs->leveldetect1);
 	bank->context.risingdetect =
-		__raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
+			__raw_readl(bank->base + bank->regs->risingdetect);
 	bank->context.fallingdetect =
-		__raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
-	bank->context.dataout =
-		__raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
+			__raw_readl(bank->base + bank->regs->fallingdetect);
+	bank->context.dataout = __raw_readl(bank->base + bank->regs->dataout);
 }
 
 static void omap_gpio_restore_context(struct gpio_bank *bank)
 {
 	__raw_writel(bank->context.irqenable1,
-			bank->base + OMAP24XX_GPIO_IRQENABLE1);
+				bank->base + bank->regs->irqenable);
 	__raw_writel(bank->context.irqenable2,
-			bank->base + OMAP24XX_GPIO_IRQENABLE2);
+				bank->base + bank->regs->irqenable2);
 	__raw_writel(bank->context.wake_en,
-			bank->base + OMAP24XX_GPIO_WAKE_EN);
-	__raw_writel(bank->context.ctrl, bank->base + OMAP24XX_GPIO_CTRL);
-	__raw_writel(bank->context.oe, bank->base + OMAP24XX_GPIO_OE);
+				bank->base + bank->regs->wkup_status);
+	__raw_writel(bank->context.ctrl, bank->base + bank->regs->ctrl);
+	__raw_writel(bank->context.oe, bank->base + bank->regs->direction);
 	__raw_writel(bank->context.leveldetect0,
-			bank->base + OMAP24XX_GPIO_LEVELDETECT0);
+				bank->base + bank->regs->leveldetect0);
 	__raw_writel(bank->context.leveldetect1,
-			bank->base + OMAP24XX_GPIO_LEVELDETECT1);
+				bank->base + bank->regs->leveldetect1);
 	__raw_writel(bank->context.risingdetect,
-			bank->base + OMAP24XX_GPIO_RISINGDETECT);
+				bank->base + bank->regs->risingdetect);
 	__raw_writel(bank->context.fallingdetect,
-			bank->base + OMAP24XX_GPIO_FALLINGDETECT);
-	__raw_writel(bank->context.dataout,
-			bank->base + OMAP24XX_GPIO_DATAOUT);
+				bank->base + bank->regs->fallingdetect);
+	__raw_writel(bank->context.dataout, bank->base + bank->regs->dataout);
 }
 #endif
 
-- 
1.6.0.4

[PATCH v3 11/20] GPIO: OMAP: Clean set_gpio_triggering function

[Tarun Kanti DebBarma]

From: Charulatha V <charu@ti.com>

Getting rid of ifdefs within the function by adding register offset intctrl
and associating OMAPXXXX_GPIO_INT_CONTROL in respective SoC specific files.

Signed-off-by: Charulatha V <charu@ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
---
 arch/arm/mach-omap1/gpio15xx.c         |    2 +
 arch/arm/mach-omap1/gpio16xx.c         |    3 +
 arch/arm/mach-omap1/gpio7xx.c          |    2 +
 arch/arm/mach-omap2/gpio.c             |    4 +
 arch/arm/plat-omap/include/plat/gpio.h |    3 +
 drivers/gpio/gpio-omap.c               |  144 ++++++++------------------------
 6 files changed, 50 insertions(+), 108 deletions(-)

diff --git a/arch/arm/mach-omap1/gpio15xx.c b/arch/arm/mach-omap1/gpio15xx.c
index e8a3bd9..fd2fe8f 100644
--- a/arch/arm/mach-omap1/gpio15xx.c
+++ b/arch/arm/mach-omap1/gpio15xx.c
@@ -42,6 +42,7 @@ static struct omap_gpio_reg_offs omap15xx_mpuio_regs = {
 	.irqstatus	= OMAP_MPUIO_GPIO_INT,
 	.irqenable	= OMAP_MPUIO_GPIO_MASKIT,
 	.irqenable_inv	= true,
+	.irqctrl	= OMAP_MPUIO_GPIO_INT_EDGE,
 };
 
 static struct __initdata omap_gpio_platform_data omap15xx_mpu_gpio_config = {
@@ -83,6 +84,7 @@ static struct omap_gpio_reg_offs omap15xx_gpio_regs = {
 	.irqstatus	= OMAP1510_GPIO_INT_STATUS,
 	.irqenable	= OMAP1510_GPIO_INT_MASK,
 	.irqenable_inv	= true,
+	.irqctrl	= OMAP1510_GPIO_INT_CONTROL,
 };
 
 static struct __initdata omap_gpio_platform_data omap15xx_gpio_config = {
diff --git a/arch/arm/mach-omap1/gpio16xx.c b/arch/arm/mach-omap1/gpio16xx.c
index d81c1e5..abde9e9 100644
--- a/arch/arm/mach-omap1/gpio16xx.c
+++ b/arch/arm/mach-omap1/gpio16xx.c
@@ -45,6 +45,7 @@ static struct omap_gpio_reg_offs omap16xx_mpuio_regs = {
 	.irqstatus	= OMAP_MPUIO_GPIO_INT,
 	.irqenable	= OMAP_MPUIO_GPIO_MASKIT,
 	.irqenable_inv	= true,
+	.irqctrl	= OMAP_MPUIO_GPIO_INT_EDGE,
 };
 
 static struct __initdata omap_gpio_platform_data omap16xx_mpu_gpio_config = {
@@ -92,6 +93,8 @@ static struct omap_gpio_reg_offs omap16xx_gpio_regs = {
 	.wkup_status	= OMAP1610_GPIO_WAKEUPENABLE,
 	.wkup_clear	= OMAP1610_GPIO_CLEAR_WAKEUPENA,
 	.wkup_set	= OMAP1610_GPIO_SET_WAKEUPENA,
+	.edgectrl1	= OMAP1610_GPIO_EDGE_CTRL1,
+	.edgectrl2	= OMAP1610_GPIO_EDGE_CTRL2,
 };
 
 static struct __initdata omap_gpio_platform_data omap16xx_gpio1_config = {
diff --git a/arch/arm/mach-omap1/gpio7xx.c b/arch/arm/mach-omap1/gpio7xx.c
index f5d5572..6e439ff 100644
--- a/arch/arm/mach-omap1/gpio7xx.c
+++ b/arch/arm/mach-omap1/gpio7xx.c
@@ -47,6 +47,7 @@ static struct omap_gpio_reg_offs omap7xx_mpuio_regs = {
 	.irqstatus	= OMAP_MPUIO_GPIO_INT / 2,
 	.irqenable	= OMAP_MPUIO_GPIO_MASKIT / 2,
 	.irqenable_inv	= true,
+	.irqctrl	= OMAP_MPUIO_GPIO_INT_EDGE / 2,
 };
 
 static struct __initdata omap_gpio_platform_data omap7xx_mpu_gpio_config = {
@@ -88,6 +89,7 @@ static struct omap_gpio_reg_offs omap7xx_gpio_regs = {
 	.irqstatus	= OMAP7XX_GPIO_INT_STATUS,
 	.irqenable	= OMAP7XX_GPIO_INT_MASK,
 	.irqenable_inv	= true,
+	.irqctrl	= OMAP7XX_GPIO_INT_CONTROL,
 };
 
 static struct __initdata omap_gpio_platform_data omap7xx_gpio1_config = {
diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c
index 54c8328..be5a906 100644
--- a/arch/arm/mach-omap2/gpio.c
+++ b/arch/arm/mach-omap2/gpio.c
@@ -82,6 +82,10 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
 		return -ENOMEM;
 	}
 
+	pdata->regs->irqctrl = 0;
+	pdata->regs->edgectrl1 = 0;
+	pdata->regs->edgectrl2 = 0;
+
 	switch (oh->class->rev) {
 	case 0:
 		if (id == 1)
diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h
index 1cf13a2..6dcbe7d 100644
--- a/arch/arm/plat-omap/include/plat/gpio.h
+++ b/arch/arm/plat-omap/include/plat/gpio.h
@@ -197,6 +197,9 @@ struct omap_gpio_reg_offs {
 	u16 leveldetect1;
 	u16 risingdetect;
 	u16 fallingdetect;
+	u16 irqctrl;
+	u16 edgectrl1;
+	u16 edgectrl2;
 
 	bool irqenable_inv;
 };
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 2339c29..42f0411 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -195,49 +195,24 @@ static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
 	__raw_writel(val, reg);
 }
 
-#ifdef CONFIG_ARCH_OMAP2PLUS
-static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
+static inline void set_gpio_trigger(struct gpio_bank *bank, int gpio,
 						int trigger)
 {
 	void __iomem *base = bank->base;
 	u32 gpio_bit = 1 << gpio;
 
-	if (cpu_is_omap44xx()) {
-		MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit,
+	MOD_REG_BIT(bank->regs->leveldetect0, gpio_bit,
 			trigger & IRQ_TYPE_LEVEL_LOW);
-		MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit,
+	MOD_REG_BIT(bank->regs->leveldetect1, gpio_bit,
 			trigger & IRQ_TYPE_LEVEL_HIGH);
-		MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit,
+	MOD_REG_BIT(bank->regs->risingdetect, gpio_bit,
 			trigger & IRQ_TYPE_EDGE_RISING);
-		MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit,
+	MOD_REG_BIT(bank->regs->fallingdetect, gpio_bit,
 			trigger & IRQ_TYPE_EDGE_FALLING);
-	} else {
-		MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
-			trigger & IRQ_TYPE_LEVEL_LOW);
-		MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
-			trigger & IRQ_TYPE_LEVEL_HIGH);
-		MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
-			trigger & IRQ_TYPE_EDGE_RISING);
-		MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
-			trigger & IRQ_TYPE_EDGE_FALLING);
-	}
-	if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
-		if (cpu_is_omap44xx()) {
-			MOD_REG_BIT(OMAP4_GPIO_IRQWAKEN0, gpio_bit,
-				trigger != 0);
-		} else {
-			/*
-			 * GPIO wakeup request can only be generated on edge
-			 * transitions
-			 */
-			if (trigger & IRQ_TYPE_EDGE_BOTH)
-				__raw_writel(1 << gpio, bank->base
-					+ OMAP24XX_GPIO_SETWKUENA);
-			else
-				__raw_writel(1 << gpio, bank->base
-					+ OMAP24XX_GPIO_CLEARWKUENA);
-		}
-	}
+
+	if (likely(!(bank->non_wakeup_gpios & gpio_bit)))
+		MOD_REG_BIT(bank->regs->wkup_status, gpio_bit, trigger != 0);
+
 	/* This part needs to be executed always for OMAP34xx */
 	if (cpu_is_omap34xx() || (bank->non_wakeup_gpios & gpio_bit)) {
 		/*
@@ -256,7 +231,6 @@ static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
 		__raw_readl(bank->base + bank->regs->leveldetect0) |
 		__raw_readl(bank->base + bank->regs->leveldetect1);
 }
-#endif
 
 #ifdef CONFIG_ARCH_OMAP1
 /*
@@ -268,23 +242,10 @@ static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
 	void __iomem *reg = bank->base;
 	u32 l = 0;
 
-	switch (bank->method) {
-	case METHOD_MPUIO:
-		reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
-		break;
-#ifdef CONFIG_ARCH_OMAP15XX
-	case METHOD_GPIO_1510:
-		reg += OMAP1510_GPIO_INT_CONTROL;
-		break;
-#endif
-#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
-	case METHOD_GPIO_7XX:
-		reg += OMAP7XX_GPIO_INT_CONTROL;
-		break;
-#endif
-	default:
+	if (!bank->regs->irqctrl)
 		return;
-	}
+
+	reg += bank->regs->irqctrl;
 
 	l = __raw_readl(reg);
 	if ((l >> gpio) & 1)
@@ -294,6 +255,8 @@ static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
 
 	__raw_writel(l, reg);
 }
+#else
+static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {}
 #endif
 
 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
@@ -301,24 +264,11 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
 	void __iomem *reg = bank->base;
 	u32 l = 0;
 
-	switch (bank->method) {
-#ifdef CONFIG_ARCH_OMAP1
-	case METHOD_MPUIO:
-		reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
-		l = __raw_readl(reg);
-		if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
-			bank->toggle_mask |= 1 << gpio;
-		if (trigger & IRQ_TYPE_EDGE_RISING)
-			l |= 1 << gpio;
-		else if (trigger & IRQ_TYPE_EDGE_FALLING)
-			l &= ~(1 << gpio);
-		else
-			goto bad;
-		break;
-#endif
-#ifdef CONFIG_ARCH_OMAP15XX
-	case METHOD_GPIO_1510:
-		reg += OMAP1510_GPIO_INT_CONTROL;
+	if (bank->regs->leveldetect0 && bank->regs->wkup_status) {
+		set_gpio_trigger(bank, gpio, trigger);
+	} else if (bank->regs->irqctrl) {
+		reg += bank->regs->irqctrl;
+
 		l = __raw_readl(reg);
 		if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
 			bank->toggle_mask |= 1 << gpio;
@@ -327,15 +277,16 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
 		else if (trigger & IRQ_TYPE_EDGE_FALLING)
 			l &= ~(1 << gpio);
 		else
-			goto bad;
-		break;
-#endif
-#ifdef CONFIG_ARCH_OMAP16XX
-	case METHOD_GPIO_1610:
+			return -EINVAL;
+
+		__raw_writel(l, reg);
+
+	} else if (bank->regs->edgectrl1) {
 		if (gpio & 0x08)
-			reg += OMAP1610_GPIO_EDGE_CTRL2;
+			reg += bank->regs->edgectrl2;
 		else
-			reg += OMAP1610_GPIO_EDGE_CTRL1;
+			reg += bank->regs->edgectrl1;
+
 		gpio &= 0x07;
 		l = __raw_readl(reg);
 		l &= ~(3 << (gpio << 1));
@@ -343,40 +294,19 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
 			l |= 2 << (gpio << 1);
 		if (trigger & IRQ_TYPE_EDGE_FALLING)
 			l |= 1 << (gpio << 1);
+
 		if (trigger)
 			/* Enable wake-up during idle for dynamic tick */
-			__raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
+			__raw_writel(1 << gpio, bank->base
+						+ bank->regs->wkup_set);
 		else
-			__raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
-		break;
-#endif
-#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
-	case METHOD_GPIO_7XX:
-		reg += OMAP7XX_GPIO_INT_CONTROL;
-		l = __raw_readl(reg);
-		if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
-			bank->toggle_mask |= 1 << gpio;
-		if (trigger & IRQ_TYPE_EDGE_RISING)
-			l |= 1 << gpio;
-		else if (trigger & IRQ_TYPE_EDGE_FALLING)
-			l &= ~(1 << gpio);
-		else
-			goto bad;
-		break;
-#endif
-#ifdef CONFIG_ARCH_OMAP2PLUS
-	case METHOD_GPIO_24XX:
-	case METHOD_GPIO_44XX:
-		set_24xx_gpio_triggering(bank, gpio, trigger);
-		return 0;
-#endif
-	default:
-		goto bad;
+			__raw_writel(1 << gpio, bank->base
+						+ bank->regs->wkup_clear);
+
+		__raw_writel(l, reg);
 	}
-	__raw_writel(l, reg);
+
 	return 0;
-bad:
-	return -EINVAL;
 }
 
 static int gpio_irq_type(struct irq_data *d, unsigned type)
@@ -507,7 +437,7 @@ static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
 	unsigned long flags;
 
 	if (bank->non_wakeup_gpios & gpio_bit) {
-		dev_err(bank->dev, 
+		dev_err(bank->dev,
 			"Unable to modify wakeup on non-wakeup GPIO%d\n", gpio);
 		return -EINVAL;
 	}
@@ -675,7 +605,6 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 			if (!(isr & 1))
 				continue;
 
-#ifdef CONFIG_ARCH_OMAP1
 			/*
 			 * Some chips can't respond to both rising and falling
 			 * at the same time.  If this irq was requested with
@@ -685,7 +614,6 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 			 */
 			if (bank->toggle_mask & (1 << gpio_index))
 				_toggle_gpio_edge_triggering(bank, gpio_index);
-#endif
 
 			generic_handle_irq(gpio_irq);
 		}
-- 
1.6.0.4

[PATCH v3 12/20] GPIO: OMAP: Use wkup_status for all SoCs

[Tarun Kanti DebBarma]

On OMAP4 we are not allowed to access wakeup_set/clear registers.
So instead of having additional check and separate logics for
manipulating the status register use wakup_status regisre consistently
for all SoCs wherever applicable. Use the MOD_REG_BIT macro to read,
modify and write the status register.

Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
---
 arch/arm/mach-omap1/gpio16xx.c         |    2 -
 arch/arm/mach-omap2/gpio.c             |    4 ---
 arch/arm/plat-omap/include/plat/gpio.h |    2 -
 drivers/gpio/gpio-omap.c               |   35 +++++++++++---------------------
 4 files changed, 12 insertions(+), 31 deletions(-)

diff --git a/arch/arm/mach-omap1/gpio16xx.c b/arch/arm/mach-omap1/gpio16xx.c
index abde9e9..08dda3c 100644
--- a/arch/arm/mach-omap1/gpio16xx.c
+++ b/arch/arm/mach-omap1/gpio16xx.c
@@ -91,8 +91,6 @@ static struct omap_gpio_reg_offs omap16xx_gpio_regs = {
 	.set_irqenable	= OMAP1610_GPIO_SET_IRQENABLE1,
 	.clr_irqenable	= OMAP1610_GPIO_CLEAR_IRQENABLE1,
 	.wkup_status	= OMAP1610_GPIO_WAKEUPENABLE,
-	.wkup_clear	= OMAP1610_GPIO_CLEAR_WAKEUPENA,
-	.wkup_set	= OMAP1610_GPIO_SET_WAKEUPENA,
 	.edgectrl1	= OMAP1610_GPIO_EDGE_CTRL1,
 	.edgectrl2	= OMAP1610_GPIO_EDGE_CTRL2,
 };
diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c
index be5a906..c99eea4 100644
--- a/arch/arm/mach-omap2/gpio.c
+++ b/arch/arm/mach-omap2/gpio.c
@@ -114,8 +114,6 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
 		pdata->regs->debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN;
 		pdata->regs->ctrl = OMAP24XX_GPIO_CTRL;
 		pdata->regs->wkup_status = OMAP24XX_GPIO_WAKE_EN;
-		pdata->regs->wkup_clear = OMAP24XX_GPIO_CLEARWKUENA;
-		pdata->regs->wkup_set = OMAP24XX_GPIO_SETWKUENA;
 		pdata->regs->leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0;
 		pdata->regs->leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1;
 		pdata->regs->risingdetect = OMAP24XX_GPIO_RISINGDETECT;
@@ -139,8 +137,6 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
 		pdata->regs->debounce_en = OMAP4_GPIO_DEBOUNCENABLE;
 		pdata->regs->ctrl = OMAP4_GPIO_CTRL;
 		pdata->regs->wkup_status = OMAP4_GPIO_IRQWAKEN0;
-		pdata->regs->wkup_clear = OMAP4_GPIO_IRQWAKEN0;
-		pdata->regs->wkup_set = OMAP4_GPIO_IRQWAKEN0;
 		pdata->regs->leveldetect0 = OMAP4_GPIO_LEVELDETECT0;
 		pdata->regs->leveldetect1 = OMAP4_GPIO_LEVELDETECT1;
 		pdata->regs->risingdetect = OMAP4_GPIO_RISINGDETECT;
diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h
index 6dcbe7d..4f584de 100644
--- a/arch/arm/plat-omap/include/plat/gpio.h
+++ b/arch/arm/plat-omap/include/plat/gpio.h
@@ -191,8 +191,6 @@ struct omap_gpio_reg_offs {
 	u16 debounce_en;
 	u16 ctrl;
 	u16 wkup_status;
-	u16 wkup_clear;
-	u16 wkup_set;
 	u16 leveldetect0;
 	u16 leveldetect1;
 	u16 risingdetect;
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 42f0411..769fae7 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -261,10 +261,11 @@ static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {}
 
 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
 {
+	void __iomem *base = bank->base;
 	void __iomem *reg = bank->base;
 	u32 l = 0;
 
-	if (bank->regs->leveldetect0 && bank->regs->wkup_status) {
+	if (bank->regs->leveldetect0) {
 		set_gpio_trigger(bank, gpio, trigger);
 	} else if (bank->regs->irqctrl) {
 		reg += bank->regs->irqctrl;
@@ -295,13 +296,7 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
 		if (trigger & IRQ_TYPE_EDGE_FALLING)
 			l |= 1 << (gpio << 1);
 
-		if (trigger)
-			/* Enable wake-up during idle for dynamic tick */
-			__raw_writel(1 << gpio, bank->base
-						+ bank->regs->wkup_set);
-		else
-			__raw_writel(1 << gpio, bank->base
-						+ bank->regs->wkup_clear);
+		MOD_REG_BIT(bank->regs->wkup_status, 1 << gpio, trigger != 0);
 
 		__raw_writel(l, reg);
 	}
@@ -515,13 +510,14 @@ static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
 {
 	struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
+	void __iomem *base = bank->base;
 	unsigned long flags;
 
 	spin_lock_irqsave(&bank->lock, flags);
 
-	if (bank->regs->wkup_clear)
+	if (bank->regs->wkup_status)
 		/* Disable wake-up during idle for dynamic tick */
-		__raw_writel(1 << offset, bank->base + bank->regs->wkup_clear);
+		MOD_REG_BIT(bank->regs->wkup_status, 1 << offset, 0);
 
 	bank->mod_usage &= ~(1 << offset);
 
@@ -1091,22 +1087,19 @@ static int omap_gpio_suspend(void)
 	struct gpio_bank *bank;
 
 	list_for_each_entry(bank, &omap_gpio_list, node) {
+		void __iomem *base = bank->base;
 		void __iomem *wake_status;
-		void __iomem *wake_clear;
-		void __iomem *wake_set;
 		unsigned long flags;
 
 		if (!bank->regs->wkup_status)
 			return 0;
 
 		wake_status = bank->base + bank->regs->wkup_status;
-		wake_clear = bank->base + bank->regs->wkup_clear;
-		wake_set = bank->base + bank->regs->wkup_set;
 
 		spin_lock_irqsave(&bank->lock, flags);
 		bank->saved_wakeup = __raw_readl(wake_status);
-		__raw_writel(0xffffffff, wake_clear);
-		__raw_writel(bank->suspend_wakeup, wake_set);
+		MOD_REG_BIT(bank->regs->wkup_status, 0xffffffff, 0);
+		MOD_REG_BIT(bank->regs->wkup_status, bank->suspend_wakeup, 1);
 		spin_unlock_irqrestore(&bank->lock, flags);
 	}
 
@@ -1118,19 +1111,15 @@ static void omap_gpio_resume(void)
 	struct gpio_bank *bank;
 
 	list_for_each_entry(bank, &omap_gpio_list, node) {
-		void __iomem *wake_clear;
-		void __iomem *wake_set;
+		void __iomem *base = bank->base;
 		unsigned long flags;
 
 		if (!bank->regs->wkup_status)
 			return;
 
-		wake_clear = bank->base + bank->regs->wkup_clear;
-		wake_set = bank->base + bank->regs->wkup_set;
-
 		spin_lock_irqsave(&bank->lock, flags);
-		__raw_writel(0xffffffff, wake_clear);
-		__raw_writel(bank->saved_wakeup, wake_set);
+		MOD_REG_BIT(bank->regs->wkup_status, 0xffffffff, 0);
+		MOD_REG_BIT(bank->regs->wkup_status, bank->saved_wakeup, 1);
 		spin_unlock_irqrestore(&bank->lock, flags);
 	}
 }
-- 
1.6.0.4

Re: [PATCH v3 12/20] GPIO: OMAP: Use wkup_status for all SoCs

[Kevin Hilman]

Tarun Kanti DebBarma <tarun.kanti@ti.com> writes:

> On OMAP4 we are not allowed to access wakeup_set/clear registers.

We are allowed, it is not recommended.  Probably makes sense to
reference the TRM here.  Basically, these are legacy registers and
starting with OMAP4, the legacy registers should not be used in
combination with the updated regsiters.

> So instead of having additional check and separate logics for
> manipulating the status register use wakup_status regisre consistently

type: regisre

> for all SoCs wherever applicable. Use the MOD_REG_BIT macro to read,
> modify and write the status register.

Good, thanks for including this change.

> Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
> ---
>  arch/arm/mach-omap1/gpio16xx.c         |    2 -
>  arch/arm/mach-omap2/gpio.c             |    4 ---
>  arch/arm/plat-omap/include/plat/gpio.h |    2 -
>  drivers/gpio/gpio-omap.c               |   35 +++++++++++---------------------
>  4 files changed, 12 insertions(+), 31 deletions(-)
>
> diff --git a/arch/arm/mach-omap1/gpio16xx.c b/arch/arm/mach-omap1/gpio16xx.c
> index abde9e9..08dda3c 100644
> --- a/arch/arm/mach-omap1/gpio16xx.c
> +++ b/arch/arm/mach-omap1/gpio16xx.c
> @@ -91,8 +91,6 @@ static struct omap_gpio_reg_offs omap16xx_gpio_regs = {
>  	.set_irqenable	= OMAP1610_GPIO_SET_IRQENABLE1,
>  	.clr_irqenable	= OMAP1610_GPIO_CLEAR_IRQENABLE1,
>  	.wkup_status	= OMAP1610_GPIO_WAKEUPENABLE,
> -	.wkup_clear	= OMAP1610_GPIO_CLEAR_WAKEUPENA,
> -	.wkup_set	= OMAP1610_GPIO_SET_WAKEUPENA,
>  	.edgectrl1	= OMAP1610_GPIO_EDGE_CTRL1,
>  	.edgectrl2	= OMAP1610_GPIO_EDGE_CTRL2,
>  };
> diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c
> index be5a906..c99eea4 100644
> --- a/arch/arm/mach-omap2/gpio.c
> +++ b/arch/arm/mach-omap2/gpio.c
> @@ -114,8 +114,6 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
>  		pdata->regs->debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN;
>  		pdata->regs->ctrl = OMAP24XX_GPIO_CTRL;
>  		pdata->regs->wkup_status = OMAP24XX_GPIO_WAKE_EN;
> -		pdata->regs->wkup_clear = OMAP24XX_GPIO_CLEARWKUENA;
> -		pdata->regs->wkup_set = OMAP24XX_GPIO_SETWKUENA;
>  		pdata->regs->leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0;
>  		pdata->regs->leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1;
>  		pdata->regs->risingdetect = OMAP24XX_GPIO_RISINGDETECT;
> @@ -139,8 +137,6 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
>  		pdata->regs->debounce_en = OMAP4_GPIO_DEBOUNCENABLE;
>  		pdata->regs->ctrl = OMAP4_GPIO_CTRL;
>  		pdata->regs->wkup_status = OMAP4_GPIO_IRQWAKEN0;
> -		pdata->regs->wkup_clear = OMAP4_GPIO_IRQWAKEN0;
> -		pdata->regs->wkup_set = OMAP4_GPIO_IRQWAKEN0;
>  		pdata->regs->leveldetect0 = OMAP4_GPIO_LEVELDETECT0;
>  		pdata->regs->leveldetect1 = OMAP4_GPIO_LEVELDETECT1;
>  		pdata->regs->risingdetect = OMAP4_GPIO_RISINGDETECT;
> diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h
> index 6dcbe7d..4f584de 100644
> --- a/arch/arm/plat-omap/include/plat/gpio.h
> +++ b/arch/arm/plat-omap/include/plat/gpio.h
> @@ -191,8 +191,6 @@ struct omap_gpio_reg_offs {
>  	u16 debounce_en;
>  	u16 ctrl;
>  	u16 wkup_status;
> -	u16 wkup_clear;
> -	u16 wkup_set;
>  	u16 leveldetect0;
>  	u16 leveldetect1;
>  	u16 risingdetect;
> diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
> index 42f0411..769fae7 100644
> --- a/drivers/gpio/gpio-omap.c
> +++ b/drivers/gpio/gpio-omap.c
> @@ -261,10 +261,11 @@ static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {}
>  
>  static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
>  {
> +	void __iomem *base = bank->base;
>  	void __iomem *reg = bank->base;
>  	u32 l = 0;
>  
> -	if (bank->regs->leveldetect0 && bank->regs->wkup_status) {
> +	if (bank->regs->leveldetect0) {

Why is the check for wkup_status removed here?   That field still
exists, and removing it leads to a blind register access below.

>  		set_gpio_trigger(bank, gpio, trigger);
>  	} else if (bank->regs->irqctrl) {
>  		reg += bank->regs->irqctrl;
> @@ -295,13 +296,7 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
>  		if (trigger & IRQ_TYPE_EDGE_FALLING)
>  			l |= 1 << (gpio << 1);
>  
> -		if (trigger)
> -			/* Enable wake-up during idle for dynamic tick */
> -			__raw_writel(1 << gpio, bank->base
> -						+ bank->regs->wkup_set);
> -		else
> -			__raw_writel(1 << gpio, bank->base
> -						+ bank->regs->wkup_clear);
> +		MOD_REG_BIT(bank->regs->wkup_status, 1 << gpio, trigger != 0);

This isn't right, so I'm not sure how this is working. At this point:

     base = bank->base;
     reg = bank->base + bank->regs->edgectrl[12];

but if you look at MOD_REG_BIT(), it does register access using 'base +
reg', but here that will be 'bank->base + bank->base + reg offset',
which will be doing a read/modify/write to who-knows-where.

>  		__raw_writel(l, reg);

Oh, now I see why it works: because you have an additional write here,
which isn't right either because MOD_REG_BIT() already does the read
*and* write.

>  	}
> @@ -515,13 +510,14 @@ static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
>  static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
>  {
>  	struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
> +	void __iomem *base = bank->base;
>  	unsigned long flags;
>  
>  	spin_lock_irqsave(&bank->lock, flags);
>  
> -	if (bank->regs->wkup_clear)
> +	if (bank->regs->wkup_status)
>  		/* Disable wake-up during idle for dynamic tick */
> -		__raw_writel(1 << offset, bank->base + bank->regs->wkup_clear);
> +		MOD_REG_BIT(bank->regs->wkup_status, 1 << offset, 0);
>  
>  	bank->mod_usage &= ~(1 << offset);
>  
> @@ -1091,22 +1087,19 @@ static int omap_gpio_suspend(void)
>  	struct gpio_bank *bank;
>  
>  	list_for_each_entry(bank, &omap_gpio_list, node) {
> +		void __iomem *base = bank->base;
>  		void __iomem *wake_status;
> -		void __iomem *wake_clear;
> -		void __iomem *wake_set;
>  		unsigned long flags;
>  
>  		if (!bank->regs->wkup_status)
>  			return 0;
>  
>  		wake_status = bank->base + bank->regs->wkup_status;
> -		wake_clear = bank->base + bank->regs->wkup_clear;
> -		wake_set = bank->base + bank->regs->wkup_set;
>  
>  		spin_lock_irqsave(&bank->lock, flags);
>  		bank->saved_wakeup = __raw_readl(wake_status);
> -		__raw_writel(0xffffffff, wake_clear);
> -		__raw_writel(bank->suspend_wakeup, wake_set);
> +		MOD_REG_BIT(bank->regs->wkup_status, 0xffffffff, 0);
> +		MOD_REG_BIT(bank->regs->wkup_status, bank->suspend_wakeup, 1);

You don't need two rmw accesses to the wkup_status.  Just do a single write.

>  		spin_unlock_irqrestore(&bank->lock, flags);
>  	}
>  
> @@ -1118,19 +1111,15 @@ static void omap_gpio_resume(void)
>  	struct gpio_bank *bank;
>  
>  	list_for_each_entry(bank, &omap_gpio_list, node) {
> -		void __iomem *wake_clear;
> -		void __iomem *wake_set;
> +		void __iomem *base = bank->base;
>  		unsigned long flags;
>  
>  		if (!bank->regs->wkup_status)
>  			return;
>  
> -		wake_clear = bank->base + bank->regs->wkup_clear;
> -		wake_set = bank->base + bank->regs->wkup_set;
> -
>  		spin_lock_irqsave(&bank->lock, flags);
> -		__raw_writel(0xffffffff, wake_clear);
> -		__raw_writel(bank->saved_wakeup, wake_set);
> +		MOD_REG_BIT(bank->regs->wkup_status, 0xffffffff, 0);
> +		MOD_REG_BIT(bank->regs->wkup_status, bank->saved_wakeup, 1);

ditto

>  		spin_unlock_irqrestore(&bank->lock, flags);
>  	}
>  }

Kevin

RE: [PATCH v3 12/20] GPIO: OMAP: Use wkup_status for all SoCs

[DebBarma, Tarun Kanti]

> -----Original Message-----
> From: Hilman, Kevin
> Sent: Wednesday, July 06, 2011 6:21 AM
> To: DebBarma, Tarun Kanti
> Cc: linux-omap@vger.kernel.org; Shilimkar, Santosh; tony@atomide.com
> Subject: Re: [PATCH v3 12/20] GPIO: OMAP: Use wkup_status for all SoCs
> 
> Tarun Kanti DebBarma <tarun.kanti@ti.com> writes:
> 
> > On OMAP4 we are not allowed to access wakeup_set/clear registers.
> 
> We are allowed, it is not recommended.  Probably makes sense to
> reference the TRM here.  Basically, these are legacy registers and
> starting with OMAP4, the legacy registers should not be used in
> combination with the updated regsiters.
> 
> > So instead of having additional check and separate logics for
> > manipulating the status register use wakup_status regisre consistently
> 
> type: regisre
Ok.

> 
> > for all SoCs wherever applicable. Use the MOD_REG_BIT macro to read,
> > modify and write the status register.
> 
> Good, thanks for including this change.
> 
> > Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
> > ---
> >  arch/arm/mach-omap1/gpio16xx.c         |    2 -
> >  arch/arm/mach-omap2/gpio.c             |    4 ---
> >  arch/arm/plat-omap/include/plat/gpio.h |    2 -
> >  drivers/gpio/gpio-omap.c               |   35 +++++++++++--------------
> -------
> >  4 files changed, 12 insertions(+), 31 deletions(-)
> >
> > diff --git a/arch/arm/mach-omap1/gpio16xx.c b/arch/arm/mach-
> omap1/gpio16xx.c
> > index abde9e9..08dda3c 100644
> > --- a/arch/arm/mach-omap1/gpio16xx.c
> > +++ b/arch/arm/mach-omap1/gpio16xx.c
> > @@ -91,8 +91,6 @@ static struct omap_gpio_reg_offs omap16xx_gpio_regs =
> {
> >  	.set_irqenable	= OMAP1610_GPIO_SET_IRQENABLE1,
> >  	.clr_irqenable	= OMAP1610_GPIO_CLEAR_IRQENABLE1,
> >  	.wkup_status	= OMAP1610_GPIO_WAKEUPENABLE,
> > -	.wkup_clear	= OMAP1610_GPIO_CLEAR_WAKEUPENA,
> > -	.wkup_set	= OMAP1610_GPIO_SET_WAKEUPENA,
> >  	.edgectrl1	= OMAP1610_GPIO_EDGE_CTRL1,
> >  	.edgectrl2	= OMAP1610_GPIO_EDGE_CTRL2,
> >  };
> > diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c
> > index be5a906..c99eea4 100644
> > --- a/arch/arm/mach-omap2/gpio.c
> > +++ b/arch/arm/mach-omap2/gpio.c
> > @@ -114,8 +114,6 @@ static int omap2_gpio_dev_init(struct omap_hwmod
> *oh, void *unused)
> >  		pdata->regs->debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN;
> >  		pdata->regs->ctrl = OMAP24XX_GPIO_CTRL;
> >  		pdata->regs->wkup_status = OMAP24XX_GPIO_WAKE_EN;
> > -		pdata->regs->wkup_clear = OMAP24XX_GPIO_CLEARWKUENA;
> > -		pdata->regs->wkup_set = OMAP24XX_GPIO_SETWKUENA;
> >  		pdata->regs->leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0;
> >  		pdata->regs->leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1;
> >  		pdata->regs->risingdetect = OMAP24XX_GPIO_RISINGDETECT;
> > @@ -139,8 +137,6 @@ static int omap2_gpio_dev_init(struct omap_hwmod
> *oh, void *unused)
> >  		pdata->regs->debounce_en = OMAP4_GPIO_DEBOUNCENABLE;
> >  		pdata->regs->ctrl = OMAP4_GPIO_CTRL;
> >  		pdata->regs->wkup_status = OMAP4_GPIO_IRQWAKEN0;
> > -		pdata->regs->wkup_clear = OMAP4_GPIO_IRQWAKEN0;
> > -		pdata->regs->wkup_set = OMAP4_GPIO_IRQWAKEN0;
> >  		pdata->regs->leveldetect0 = OMAP4_GPIO_LEVELDETECT0;
> >  		pdata->regs->leveldetect1 = OMAP4_GPIO_LEVELDETECT1;
> >  		pdata->regs->risingdetect = OMAP4_GPIO_RISINGDETECT;
> > diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-
> omap/include/plat/gpio.h
> > index 6dcbe7d..4f584de 100644
> > --- a/arch/arm/plat-omap/include/plat/gpio.h
> > +++ b/arch/arm/plat-omap/include/plat/gpio.h
> > @@ -191,8 +191,6 @@ struct omap_gpio_reg_offs {
> >  	u16 debounce_en;
> >  	u16 ctrl;
> >  	u16 wkup_status;
> > -	u16 wkup_clear;
> > -	u16 wkup_set;
> >  	u16 leveldetect0;
> >  	u16 leveldetect1;
> >  	u16 risingdetect;
> > diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
> > index 42f0411..769fae7 100644
> > --- a/drivers/gpio/gpio-omap.c
> > +++ b/drivers/gpio/gpio-omap.c
> > @@ -261,10 +261,11 @@ static void _toggle_gpio_edge_triggering(struct
> gpio_bank *bank, int gpio) {}
> >
> >  static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int
> trigger)
> >  {
> > +	void __iomem *base = bank->base;
> >  	void __iomem *reg = bank->base;
> >  	u32 l = 0;
> >
> > -	if (bank->regs->leveldetect0 && bank->regs->wkup_status) {
> > +	if (bank->regs->leveldetect0) {
> 
> Why is the check for wkup_status removed here?   That field still
> exists, and removing it leads to a blind register access below.
Oh, I mistakenly thought all OMAP2+ has leveldetect0.
I will put back the change.

> 
> >  		set_gpio_trigger(bank, gpio, trigger);
> >  	} else if (bank->regs->irqctrl) {
> >  		reg += bank->regs->irqctrl;
> > @@ -295,13 +296,7 @@ static int _set_gpio_triggering(struct gpio_bank
> *bank, int gpio, int trigger)
> >  		if (trigger & IRQ_TYPE_EDGE_FALLING)
> >  			l |= 1 << (gpio << 1);
> >
> > -		if (trigger)
> > -			/* Enable wake-up during idle for dynamic tick */
> > -			__raw_writel(1 << gpio, bank->base
> > -						+ bank->regs->wkup_set);
> > -		else
> > -			__raw_writel(1 << gpio, bank->base
> > -						+ bank->regs->wkup_clear);
> > +		MOD_REG_BIT(bank->regs->wkup_status, 1 << gpio, trigger != 0);
> 
> This isn't right, so I'm not sure how this is working. At this point:
> 
>      base = bank->base;
>      reg = bank->base + bank->regs->edgectrl[12];
> 
> but if you look at MOD_REG_BIT(), it does register access using 'base +
> reg', but here that will be 'bank->base + bank->base + reg offset',
> which will be doing a read/modify/write to who-knows-where.
> 
> >  		__raw_writel(l, reg);
> 
> Oh, now I see why it works: because you have an additional write here,
> which isn't right either because MOD_REG_BIT() already does the read
> *and* write.
I guess I messed up while simplifying. I will review once again and test.

> 
> >  	}
> > @@ -515,13 +510,14 @@ static int omap_gpio_request(struct gpio_chip
> *chip, unsigned offset)
> >  static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
> >  {
> >  	struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
> > +	void __iomem *base = bank->base;
> >  	unsigned long flags;
> >
> >  	spin_lock_irqsave(&bank->lock, flags);
> >
> > -	if (bank->regs->wkup_clear)
> > +	if (bank->regs->wkup_status)
> >  		/* Disable wake-up during idle for dynamic tick */
> > -		__raw_writel(1 << offset, bank->base + bank->regs->wkup_clear);
> > +		MOD_REG_BIT(bank->regs->wkup_status, 1 << offset, 0);
> >
> >  	bank->mod_usage &= ~(1 << offset);
> >
> > @@ -1091,22 +1087,19 @@ static int omap_gpio_suspend(void)
> >  	struct gpio_bank *bank;
> >
> >  	list_for_each_entry(bank, &omap_gpio_list, node) {
> > +		void __iomem *base = bank->base;
> >  		void __iomem *wake_status;
> > -		void __iomem *wake_clear;
> > -		void __iomem *wake_set;
> >  		unsigned long flags;
> >
> >  		if (!bank->regs->wkup_status)
> >  			return 0;
> >
> >  		wake_status = bank->base + bank->regs->wkup_status;
> > -		wake_clear = bank->base + bank->regs->wkup_clear;
> > -		wake_set = bank->base + bank->regs->wkup_set;
> >
> >  		spin_lock_irqsave(&bank->lock, flags);
> >  		bank->saved_wakeup = __raw_readl(wake_status);
> > -		__raw_writel(0xffffffff, wake_clear);
> > -		__raw_writel(bank->suspend_wakeup, wake_set);
> > +		MOD_REG_BIT(bank->regs->wkup_status, 0xffffffff, 0);
> > +		MOD_REG_BIT(bank->regs->wkup_status, bank->suspend_wakeup, 1);
> 
> You don't need two rmw accesses to the wkup_status.  Just do a single
> write.
Ok.

> 
> >  		spin_unlock_irqrestore(&bank->lock, flags);
> >  	}
> >
> > @@ -1118,19 +1111,15 @@ static void omap_gpio_resume(void)
> >  	struct gpio_bank *bank;
> >
> >  	list_for_each_entry(bank, &omap_gpio_list, node) {
> > -		void __iomem *wake_clear;
> > -		void __iomem *wake_set;
> > +		void __iomem *base = bank->base;
> >  		unsigned long flags;
> >
> >  		if (!bank->regs->wkup_status)
> >  			return;
> >
> > -		wake_clear = bank->base + bank->regs->wkup_clear;
> > -		wake_set = bank->base + bank->regs->wkup_set;
> > -
> >  		spin_lock_irqsave(&bank->lock, flags);
> > -		__raw_writel(0xffffffff, wake_clear);
> > -		__raw_writel(bank->saved_wakeup, wake_set);
> > +		MOD_REG_BIT(bank->regs->wkup_status, 0xffffffff, 0);
> > +		MOD_REG_BIT(bank->regs->wkup_status, bank->saved_wakeup, 1);
> 
> ditto
Ok, thanks.
--
Tarun
> 
> >  		spin_unlock_irqrestore(&bank->lock, flags);
> >  	}
> >  }
> 
> Kevin

RE: [PATCH v3 12/20] GPIO: OMAP: Use wkup_status for all SoCs

[DebBarma, Tarun Kanti]

[..]
> 
> > On OMAP4 we are not allowed to access wakeup_set/clear registers.
> 
> We are allowed, it is not recommended.  Probably makes sense to
> reference the TRM here.  Basically, these are legacy registers and
> starting with OMAP4, the legacy registers should not be used in
> combination with the updated regsiters.
Yes, I will modify the comments.
--
Tarun
[...]

RE: [PATCH v3 12/20] GPIO: OMAP: Use wkup_status for all SoCs

[DebBarma, Tarun Kanti]

Kevin,
[...]
> 
> >  		set_gpio_trigger(bank, gpio, trigger);
> >  	} else if (bank->regs->irqctrl) {
> >  		reg += bank->regs->irqctrl;
> > @@ -295,13 +296,7 @@ static int _set_gpio_triggering(struct gpio_bank
> *bank, int gpio, int trigger)
> >  		if (trigger & IRQ_TYPE_EDGE_FALLING)
> >  			l |= 1 << (gpio << 1);
> >
> > -		if (trigger)
> > -			/* Enable wake-up during idle for dynamic tick */
> > -			__raw_writel(1 << gpio, bank->base
> > -						+ bank->regs->wkup_set);
> > -		else
> > -			__raw_writel(1 << gpio, bank->base
> > -						+ bank->regs->wkup_clear);
> > +		MOD_REG_BIT(bank->regs->wkup_status, 1 << gpio, trigger != 0);
> 
> This isn't right, so I'm not sure how this is working. At this point:
> 
>      base = bank->base;
>      reg = bank->base + bank->regs->edgectrl[12];
Right so far...

> 
> but if you look at MOD_REG_BIT(), it does register access using 'base +
> reg', but here that will be 'bank->base + bank->base + reg offset',
> which will be doing a read/modify/write to who-knows-where.
My understanding was MOD_REG_BIT(bank->regs->wkup_status, ...) translate to:
bank->base + bank->regs->wkup_status, for the following reason:

In the following macro, reg is equivalent to bank->regs->wkup_status.
But this is not the case with base, which remains as bank->base.
Please correct me.

#define MOD_REG_BIT(reg, bit_mask, set) \
do {    \
        int l = __raw_readl(base + reg); \
        if (set) l |= bit_mask; \
        else l &= ~bit_mask; \
        __raw_writel(l, base + reg); \
} while(0)

> 
> >  		__raw_writel(l, reg);
> 
> Oh, now I see why it works: because you have an additional write here,
> which isn't right either because MOD_REG_BIT() already does the read
> *and* write.
This should be writing to following still.
reg = bank->base + bank->regs->edgectrl[12];
--
Tarun
> 
[...]

Re: [PATCH v3 12/20] GPIO: OMAP: Use wkup_status for all SoCs

[Kevin Hilman]

"DebBarma, Tarun Kanti" <tarun.kanti@ti.com> writes:

> Kevin,
> [...]
>> 
>> >  		set_gpio_trigger(bank, gpio, trigger);
>> >  	} else if (bank->regs->irqctrl) {
>> >  		reg += bank->regs->irqctrl;
>> > @@ -295,13 +296,7 @@ static int _set_gpio_triggering(struct gpio_bank
>> *bank, int gpio, int trigger)
>> >  		if (trigger & IRQ_TYPE_EDGE_FALLING)
>> >  			l |= 1 << (gpio << 1);
>> >
>> > -		if (trigger)
>> > -			/* Enable wake-up during idle for dynamic tick */
>> > -			__raw_writel(1 << gpio, bank->base
>> > -						+ bank->regs->wkup_set);
>> > -		else
>> > -			__raw_writel(1 << gpio, bank->base
>> > -						+ bank->regs->wkup_clear);
>> > +		MOD_REG_BIT(bank->regs->wkup_status, 1 << gpio, trigger != 0);
>> 
>> This isn't right, so I'm not sure how this is working. At this point:
>> 
>>      base = bank->base;
>>      reg = bank->base + bank->regs->edgectrl[12];
> Right so far...
>
>> 
>> but if you look at MOD_REG_BIT(), it does register access using 'base +
>> reg', but here that will be 'bank->base + bank->base + reg offset',
>> which will be doing a read/modify/write to who-knows-where.
> My understanding was MOD_REG_BIT(bank->regs->wkup_status, ...) translate to:
> bank->base + bank->regs->wkup_status, for the following reason:
>
> In the following macro, reg is equivalent to bank->regs->wkup_status.
> But this is not the case with base, which remains as bank->base.
> Please correct me.

You're right.  

This is a good example why using macros like this (with some arguments
passed and some arguments implied) leads to confusion.

> #define MOD_REG_BIT(reg, bit_mask, set) \
> do {    \
>         int l = __raw_readl(base + reg); \
>         if (set) l |= bit_mask; \
>         else l &= ~bit_mask; \
>         __raw_writel(l, base + reg); \
> } while(0)
>
>> 
>> >  		__raw_writel(l, reg);
>> 
>> Oh, now I see why it works: because you have an additional write here,
>> which isn't right either because MOD_REG_BIT() already does the read
>> *and* write.
> This should be writing to following still.
> reg = bank->base + bank->regs->edgectrl[12];

Yes, but it is a duplicate write since the MOD_REG_BIT() already does
the write.

A better solution is to just get rid of this macro and use a static inline.

The patch below does just this, and I'm including it into my
gpio-cleanup series (branch: for_3.1/gpio-cleanup-2.)  Please rebase
your updated series on that branch.

Kevin

>From 0c3da6533061f51236743ebaf4bae23561e315fe Mon Sep 17 00:00:00 2001
From: Kevin Hilman <khilman@ti.com>
Date: Tue, 12 Jul 2011 08:18:15 -0700
Subject: [PATCH] gpio/omap: replace MOD_REG_BIT macro with static inline

This macro is ugly and confusing, especially since it passes in most
arguments, but uses an implied 'base' from the caller.

Replace it with an equivalent static inline.

Signed-off-by: Kevin Hilman <khilman@ti.com>
---
 drivers/gpio/gpio-omap.c |   54 ++++++++++++++++++++++++---------------------
 1 files changed, 29 insertions(+), 25 deletions(-)

diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 501ca3d..6d616ee 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -148,13 +148,17 @@ static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
 	return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0;
 }
 
-#define MOD_REG_BIT(reg, bit_mask, set)	\
-do {	\
-	int l = __raw_readl(base + reg); \
-	if (set) l |= bit_mask; \
-	else l &= ~bit_mask; \
-	__raw_writel(l, base + reg); \
-} while(0)
+static inline void _gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)
+{
+	int l = __raw_readl(base + reg);
+
+	if (set) 
+		l |= mask;
+	else
+		l &= ~mask;
+
+	__raw_writel(l, base + reg);
+}
 
 /**
  * _set_gpio_debounce - low level gpio debounce time
@@ -210,28 +214,28 @@ static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
 	u32 gpio_bit = 1 << gpio;
 
 	if (cpu_is_omap44xx()) {
-		MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit,
-			trigger & IRQ_TYPE_LEVEL_LOW);
-		MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit,
-			trigger & IRQ_TYPE_LEVEL_HIGH);
-		MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit,
-			trigger & IRQ_TYPE_EDGE_RISING);
-		MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit,
-			trigger & IRQ_TYPE_EDGE_FALLING);
+		_gpio_rmw(base, OMAP4_GPIO_LEVELDETECT0, gpio_bit,
+			  trigger & IRQ_TYPE_LEVEL_LOW);
+		_gpio_rmw(base, OMAP4_GPIO_LEVELDETECT1, gpio_bit,
+			  trigger & IRQ_TYPE_LEVEL_HIGH);
+		_gpio_rmw(base, OMAP4_GPIO_RISINGDETECT, gpio_bit,
+			  trigger & IRQ_TYPE_EDGE_RISING);
+		_gpio_rmw(base, OMAP4_GPIO_FALLINGDETECT, gpio_bit,
+			  trigger & IRQ_TYPE_EDGE_FALLING);
 	} else {
-		MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
-			trigger & IRQ_TYPE_LEVEL_LOW);
-		MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
-			trigger & IRQ_TYPE_LEVEL_HIGH);
-		MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
-			trigger & IRQ_TYPE_EDGE_RISING);
-		MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
-			trigger & IRQ_TYPE_EDGE_FALLING);
+		_gpio_rmw(base, OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
+			  trigger & IRQ_TYPE_LEVEL_LOW);
+		_gpio_rmw(base, OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
+			  trigger & IRQ_TYPE_LEVEL_HIGH);
+		_gpio_rmw(base, OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
+			  trigger & IRQ_TYPE_EDGE_RISING);
+		_gpio_rmw(base, OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
+			  trigger & IRQ_TYPE_EDGE_FALLING);
 	}
 	if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
 		if (cpu_is_omap44xx()) {
-			MOD_REG_BIT(OMAP4_GPIO_IRQWAKEN0, gpio_bit,
-				trigger != 0);
+			_gpio_rmw(base, OMAP4_GPIO_IRQWAKEN0, gpio_bit,
+				  trigger != 0);
 		} else {
 			/*
 			 * GPIO wakeup request can only be generated on edge
-- 
1.7.6

RE: [PATCH v3 12/20] GPIO: OMAP: Use wkup_status for all SoCs

[DebBarma, Tarun Kanti]

[...] 
> A better solution is to just get rid of this macro and use a static
> inline.
> 
> The patch below does just this, and I'm including it into my
> gpio-cleanup series (branch: for_3.1/gpio-cleanup-2.)  Please rebase
> your updated series on that branch.
Alright! Thanks.
--
Tarun

> 
> Kevin
> 
> From 0c3da6533061f51236743ebaf4bae23561e315fe Mon Sep 17 00:00:00 2001
> From: Kevin Hilman <khilman@ti.com>
> Date: Tue, 12 Jul 2011 08:18:15 -0700
> Subject: [PATCH] gpio/omap: replace MOD_REG_BIT macro with static inline
> 
> This macro is ugly and confusing, especially since it passes in most
> arguments, but uses an implied 'base' from the caller.
> 
> Replace it with an equivalent static inline.
> 
> Signed-off-by: Kevin Hilman <khilman@ti.com>
> ---
>  drivers/gpio/gpio-omap.c |   54 ++++++++++++++++++++++++-----------------
> ----
>  1 files changed, 29 insertions(+), 25 deletions(-)
> 
> diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
> index 501ca3d..6d616ee 100644
> --- a/drivers/gpio/gpio-omap.c
> +++ b/drivers/gpio/gpio-omap.c
> @@ -148,13 +148,17 @@ static int _get_gpio_dataout(struct gpio_bank *bank,
> int gpio)
>  	return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0;
>  }
> 
> -#define MOD_REG_BIT(reg, bit_mask, set)	\
> -do {	\
> -	int l = __raw_readl(base + reg); \
> -	if (set) l |= bit_mask; \
> -	else l &= ~bit_mask; \
> -	__raw_writel(l, base + reg); \
> -} while(0)
> +static inline void _gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool
> set)
> +{
> +	int l = __raw_readl(base + reg);
> +
> +	if (set)
> +		l |= mask;
> +	else
> +		l &= ~mask;
> +
> +	__raw_writel(l, base + reg);
> +}
> 
>  /**
>   * _set_gpio_debounce - low level gpio debounce time
> @@ -210,28 +214,28 @@ static inline void set_24xx_gpio_triggering(struct
> gpio_bank *bank, int gpio,
>  	u32 gpio_bit = 1 << gpio;
> 
>  	if (cpu_is_omap44xx()) {
> -		MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit,
> -			trigger & IRQ_TYPE_LEVEL_LOW);
> -		MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit,
> -			trigger & IRQ_TYPE_LEVEL_HIGH);
> -		MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit,
> -			trigger & IRQ_TYPE_EDGE_RISING);
> -		MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit,
> -			trigger & IRQ_TYPE_EDGE_FALLING);
> +		_gpio_rmw(base, OMAP4_GPIO_LEVELDETECT0, gpio_bit,
> +			  trigger & IRQ_TYPE_LEVEL_LOW);
> +		_gpio_rmw(base, OMAP4_GPIO_LEVELDETECT1, gpio_bit,
> +			  trigger & IRQ_TYPE_LEVEL_HIGH);
> +		_gpio_rmw(base, OMAP4_GPIO_RISINGDETECT, gpio_bit,
> +			  trigger & IRQ_TYPE_EDGE_RISING);
> +		_gpio_rmw(base, OMAP4_GPIO_FALLINGDETECT, gpio_bit,
> +			  trigger & IRQ_TYPE_EDGE_FALLING);
>  	} else {
> -		MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
> -			trigger & IRQ_TYPE_LEVEL_LOW);
> -		MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
> -			trigger & IRQ_TYPE_LEVEL_HIGH);
> -		MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
> -			trigger & IRQ_TYPE_EDGE_RISING);
> -		MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
> -			trigger & IRQ_TYPE_EDGE_FALLING);
> +		_gpio_rmw(base, OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
> +			  trigger & IRQ_TYPE_LEVEL_LOW);
> +		_gpio_rmw(base, OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
> +			  trigger & IRQ_TYPE_LEVEL_HIGH);
> +		_gpio_rmw(base, OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
> +			  trigger & IRQ_TYPE_EDGE_RISING);
> +		_gpio_rmw(base, OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
> +			  trigger & IRQ_TYPE_EDGE_FALLING);
>  	}
>  	if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
>  		if (cpu_is_omap44xx()) {
> -			MOD_REG_BIT(OMAP4_GPIO_IRQWAKEN0, gpio_bit,
> -				trigger != 0);
> +			_gpio_rmw(base, OMAP4_GPIO_IRQWAKEN0, gpio_bit,
> +				  trigger != 0);
>  		} else {
>  			/*
>  			 * GPIO wakeup request can only be generated on edge
> --
> 1.7.6

[PATCH v3 13/20] GPIO: OMAP: Clean omap_gpio_mod_init function

[Tarun Kanti DebBarma]

With register offsets now defined for respective OMAP versions we can get rid
of cpu_class_* checks. This function now has common initialization code for
all OMAP versions. Initialization specific to OMAP16xx has been moved within
omap16xx_gpio_init().

Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
Signed-off-by: Charulatha V <charu@ti.com>
---
 arch/arm/mach-omap1/gpio16xx.c         |   19 ++++++-
 arch/arm/plat-omap/include/plat/gpio.h |    2 +
 drivers/gpio/gpio-omap.c               |   96 +++++++++++++++-----------------
 3 files changed, 64 insertions(+), 53 deletions(-)

diff --git a/arch/arm/mach-omap1/gpio16xx.c b/arch/arm/mach-omap1/gpio16xx.c
index 08dda3c..cfd86b9 100644
--- a/arch/arm/mach-omap1/gpio16xx.c
+++ b/arch/arm/mach-omap1/gpio16xx.c
@@ -93,6 +93,7 @@ static struct omap_gpio_reg_offs omap16xx_gpio_regs = {
 	.wkup_status	= OMAP1610_GPIO_WAKEUPENABLE,
 	.edgectrl1	= OMAP1610_GPIO_EDGE_CTRL1,
 	.edgectrl2	= OMAP1610_GPIO_EDGE_CTRL2,
+	.sysconfig	= OMAP1610_GPIO_SYSCONFIG,
 };
 
 static struct __initdata omap_gpio_platform_data omap16xx_gpio1_config = {
@@ -218,12 +219,28 @@ static struct __initdata platform_device * omap16xx_gpio_dev[] = {
 static int __init omap16xx_gpio_init(void)
 {
 	int i;
+	void __iomem *base;
+	struct resource *res;
+	struct platform_device *pdev;
+	struct omap_gpio_platform_data *pdata;
 
 	if (!cpu_is_omap16xx())
 		return -EINVAL;
 
-	for (i = 0; i < ARRAY_SIZE(omap16xx_gpio_dev); i++)
+	for (i = 0; i < ARRAY_SIZE(omap16xx_gpio_dev); i++) {
+		pdev = omap16xx_gpio_dev[i];
+		pdata = pdev->dev.platform_data;
+		res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+		base = ioremap(res->start, resource_size(res));
+
+		if (pdata->regs->sysconfig)
+			__raw_writew(0x0014, base + OMAP1610_GPIO_SYSCONFIG);
+
+		omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04,
+					ULPD_CAM_CLK_CTRL);
+
 		platform_device_register(omap16xx_gpio_dev[i]);
+	}
 
 	return 0;
 }
diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h
index 4f584de..3f7b028 100644
--- a/arch/arm/plat-omap/include/plat/gpio.h
+++ b/arch/arm/plat-omap/include/plat/gpio.h
@@ -198,6 +198,8 @@ struct omap_gpio_reg_offs {
 	u16 irqctrl;
 	u16 edgectrl1;
 	u16 edgectrl2;
+	/* Not applicable for OMAP2+ as hwmod layer takes care of sysconfig */
+	u16 sysconfig;
 
 	bool irqenable_inv;
 };
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 769fae7..3acbaa9 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -75,6 +75,7 @@ struct gpio_bank {
 
 	void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable);
 	int (*get_context_loss_count)(struct device *dev);
+	void (*do_raw_write)(void __iomem *reg, int set);
 
 	struct omap_gpio_reg_offs *regs;
 };
@@ -864,67 +865,53 @@ static void __init omap_gpio_show_rev(struct gpio_bank *bank)
 	called = true;
 }
 
+static void __do_raw_writel(void __iomem *reg, int set)
+{
+	if (set)
+		__raw_writel(0xffffffff, reg);
+	else
+		__raw_writel(0x00000000, reg);
+
+}
+
+static void __do_raw_writew(void __iomem *reg, int set)
+{
+	if (set)
+		__raw_writew(0xffff, reg);
+	else
+		__raw_writew(0x0000, reg);
+}
+
 /* This lock class tells lockdep that GPIO irqs are in a different
  * category than their parents, so it won't report false recursion.
  */
 static struct lock_class_key gpio_lock_class;
 
-/* TODO: Cleanup cpu_is_* checks */
 static void omap_gpio_mod_init(struct gpio_bank *bank)
 {
-	if (cpu_class_is_omap2()) {
-		if (cpu_is_omap44xx()) {
-			__raw_writel(0xffffffff, bank->base +
-					OMAP4_GPIO_IRQSTATUSCLR0);
-			__raw_writel(0x00000000, bank->base +
-					 OMAP4_GPIO_DEBOUNCENABLE);
-			/* Initialize interface clk ungated, module enabled */
-			__raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
-		} else if (cpu_is_omap34xx()) {
-			__raw_writel(0x00000000, bank->base +
-					OMAP24XX_GPIO_IRQENABLE1);
-			__raw_writel(0xffffffff, bank->base +
-					OMAP24XX_GPIO_IRQSTATUS1);
-			__raw_writel(0x00000000, bank->base +
-					OMAP24XX_GPIO_DEBOUNCE_EN);
-
-			/* Initialize interface clk ungated, module enabled */
-			__raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
-		}
-	} else if (cpu_class_is_omap1()) {
-		if (bank_is_mpuio(bank)) {
-			__raw_writew(0xffff, bank->base +
-				OMAP_MPUIO_GPIO_MASKIT / bank->stride);
+	if (bank_is_mpuio(bank)) {
+		bank->do_raw_write(bank->base + bank->regs->irqenable, 1);
+		if (bank->regs->wkup_status)
 			mpuio_init(bank);
-		}
-		if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
-			__raw_writew(0xffff, bank->base
-						+ OMAP1510_GPIO_INT_MASK);
-			__raw_writew(0x0000, bank->base
-						+ OMAP1510_GPIO_INT_STATUS);
-		}
-		if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
-			__raw_writew(0x0000, bank->base
-						+ OMAP1610_GPIO_IRQENABLE1);
-			__raw_writew(0xffff, bank->base
-						+ OMAP1610_GPIO_IRQSTATUS1);
-			__raw_writew(0x0014, bank->base
-						+ OMAP1610_GPIO_SYSCONFIG);
-
-			/*
-			 * Enable system clock for GPIO module.
-			 * The CAM_CLK_CTRL *is* really the right place.
-			 */
-			omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04,
-						ULPD_CAM_CLK_CTRL);
-		}
-		if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
-			__raw_writel(0xffffffff, bank->base
-						+ OMAP7XX_GPIO_INT_MASK);
-			__raw_writel(0x00000000, bank->base
-						+ OMAP7XX_GPIO_INT_STATUS);
-		}
+		return;
 	}
+
+	if (bank->regs->ctrl)
+		/* Initialize interface clk ungated, module enabled */
+		bank->do_raw_write(bank->base + bank->regs->ctrl, 0);
+
+	if (bank->regs->clr_irqenable && bank->width == 32)
+		bank->do_raw_write(bank->base + bank->regs->clr_irqenable, 1);
+	else if (bank->regs->irqenable)
+		bank->do_raw_write(bank->base + bank->regs->irqenable,
+				bank->regs->irqenable_inv);
+
+	if (bank->regs->irqstatus)
+		bank->do_raw_write(bank->base + bank->regs->irqstatus,
+				bank->regs->irqenable_inv == 0);
+
+	if (bank->regs->debounce_en)
+		bank->do_raw_write(bank->base + bank->regs->debounce_en, 0);
 }
 
 static __init void
@@ -1041,6 +1028,11 @@ static int __devinit omap_gpio_probe(struct platform_device *pdev)
 	bank->get_context_loss_count = pdata->get_context_loss_count;
 	bank->regs = pdata->regs;
 
+	if (bank->width == 32)
+		bank->do_raw_write = __do_raw_writel;
+	else
+		bank->do_raw_write = __do_raw_writew;
+
 	if (bank->regs->set_dataout && bank->regs->clr_dataout)
 		bank->set_dataout = _set_gpio_dataout_reg;
 	else
-- 
1.6.0.4

Re: [PATCH v3 13/20] GPIO: OMAP: Clean omap_gpio_mod_init function

[Kevin Hilman]

Tarun Kanti DebBarma <tarun.kanti@ti.com> writes:

> With register offsets now defined for respective OMAP versions we can get rid
> of cpu_class_* checks. This function now has common initialization code for
> all OMAP versions. Initialization specific to OMAP16xx has been moved within
> omap16xx_gpio_init().

This patch also adds the ->do_raw_write() stuff which is not described
here, and is an unrelated change that wants its own patch.  More on that
below.

> Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
> Signed-off-by: Charulatha V <charu@ti.com>
> ---
>  arch/arm/mach-omap1/gpio16xx.c         |   19 ++++++-
>  arch/arm/plat-omap/include/plat/gpio.h |    2 +
>  drivers/gpio/gpio-omap.c               |   96 +++++++++++++++-----------------
>  3 files changed, 64 insertions(+), 53 deletions(-)
>
> diff --git a/arch/arm/mach-omap1/gpio16xx.c b/arch/arm/mach-omap1/gpio16xx.c
> index 08dda3c..cfd86b9 100644
> --- a/arch/arm/mach-omap1/gpio16xx.c
> +++ b/arch/arm/mach-omap1/gpio16xx.c
> @@ -93,6 +93,7 @@ static struct omap_gpio_reg_offs omap16xx_gpio_regs = {
>  	.wkup_status	= OMAP1610_GPIO_WAKEUPENABLE,
>  	.edgectrl1	= OMAP1610_GPIO_EDGE_CTRL1,
>  	.edgectrl2	= OMAP1610_GPIO_EDGE_CTRL2,
> +	.sysconfig	= OMAP1610_GPIO_SYSCONFIG,
>  };
>  
>  static struct __initdata omap_gpio_platform_data omap16xx_gpio1_config = {
> @@ -218,12 +219,28 @@ static struct __initdata platform_device * omap16xx_gpio_dev[] = {
>  static int __init omap16xx_gpio_init(void)
>  {
>  	int i;
> +	void __iomem *base;
> +	struct resource *res;
> +	struct platform_device *pdev;
> +	struct omap_gpio_platform_data *pdata;
>  
>  	if (!cpu_is_omap16xx())
>  		return -EINVAL;
>  
> -	for (i = 0; i < ARRAY_SIZE(omap16xx_gpio_dev); i++)
> +	for (i = 0; i < ARRAY_SIZE(omap16xx_gpio_dev); i++) {
> +		pdev = omap16xx_gpio_dev[i];
> +		pdata = pdev->dev.platform_data;
> +		res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +		base = ioremap(res->start, resource_size(res));
> +
> +		if (pdata->regs->sysconfig)

using field from regs-> here...

> +			__raw_writew(0x0014, base + OMAP1610_GPIO_SYSCONFIG);

but the #define here.

Since you don't really need this field in reg_offs (because it's not
used in SoC-independent code), just drop the if and always write
sysconfig.

> +		omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04,
> +					ULPD_CAM_CLK_CTRL);

Please preserve the comments from the original code, since the CAM
access does lok rather confusing.

>  		platform_device_register(omap16xx_gpio_dev[i]);
> +	}
>  
>  	return 0;
>  }
> diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h
> index 4f584de..3f7b028 100644
> --- a/arch/arm/plat-omap/include/plat/gpio.h
> +++ b/arch/arm/plat-omap/include/plat/gpio.h
> @@ -198,6 +198,8 @@ struct omap_gpio_reg_offs {
>  	u16 irqctrl;
>  	u16 edgectrl1;
>  	u16 edgectrl2;
> +	/* Not applicable for OMAP2+ as hwmod layer takes care of sysconfig */
> +	u16 sysconfig;
>  
>  	bool irqenable_inv;
>  };
> diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
> index 769fae7..3acbaa9 100644
> --- a/drivers/gpio/gpio-omap.c
> +++ b/drivers/gpio/gpio-omap.c
> @@ -75,6 +75,7 @@ struct gpio_bank {
>  
>  	void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable);
>  	int (*get_context_loss_count)(struct device *dev);
> +	void (*do_raw_write)(void __iomem *reg, int set);
>  
>  	struct omap_gpio_reg_offs *regs;
>  };
> @@ -864,67 +865,53 @@ static void __init omap_gpio_show_rev(struct gpio_bank *bank)
>  	called = true;
>  }
>  
> +static void __do_raw_writel(void __iomem *reg, int set)
> +{
> +	if (set)
> +		__raw_writel(0xffffffff, reg);
> +	else
> +		__raw_writel(0x00000000, reg);
> +
> +}
> +
> +static void __do_raw_writew(void __iomem *reg, int set)
> +{
> +	if (set)
> +		__raw_writew(0xffff, reg);
> +	else
> +		__raw_writew(0x0000, reg);
> +}
> +
>  /* This lock class tells lockdep that GPIO irqs are in a different
>   * category than their parents, so it won't report false recursion.
>   */
>  static struct lock_class_key gpio_lock_class;
>  
> -/* TODO: Cleanup cpu_is_* checks */
>  static void omap_gpio_mod_init(struct gpio_bank *bank)
>  {
> -	if (cpu_class_is_omap2()) {
> -		if (cpu_is_omap44xx()) {
> -			__raw_writel(0xffffffff, bank->base +
> -					OMAP4_GPIO_IRQSTATUSCLR0);
> -			__raw_writel(0x00000000, bank->base +
> -					 OMAP4_GPIO_DEBOUNCENABLE);
> -			/* Initialize interface clk ungated, module enabled */
> -			__raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
> -		} else if (cpu_is_omap34xx()) {
> -			__raw_writel(0x00000000, bank->base +
> -					OMAP24XX_GPIO_IRQENABLE1);
> -			__raw_writel(0xffffffff, bank->base +
> -					OMAP24XX_GPIO_IRQSTATUS1);
> -			__raw_writel(0x00000000, bank->base +
> -					OMAP24XX_GPIO_DEBOUNCE_EN);
> -
> -			/* Initialize interface clk ungated, module enabled */
> -			__raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
> -		}
> -	} else if (cpu_class_is_omap1()) {
> -		if (bank_is_mpuio(bank)) {
> -			__raw_writew(0xffff, bank->base +
> -				OMAP_MPUIO_GPIO_MASKIT / bank->stride);
> +	if (bank_is_mpuio(bank)) {
> +		bank->do_raw_write(bank->base + bank->regs->irqenable, 1);
> +		if (bank->regs->wkup_status)
>  			mpuio_init(bank);
> -		}
> -		if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
> -			__raw_writew(0xffff, bank->base
> -						+ OMAP1510_GPIO_INT_MASK);
> -			__raw_writew(0x0000, bank->base
> -						+ OMAP1510_GPIO_INT_STATUS);
> -		}
> -		if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
> -			__raw_writew(0x0000, bank->base
> -						+ OMAP1610_GPIO_IRQENABLE1);
> -			__raw_writew(0xffff, bank->base
> -						+ OMAP1610_GPIO_IRQSTATUS1);
> -			__raw_writew(0x0014, bank->base
> -						+ OMAP1610_GPIO_SYSCONFIG);
> -
> -			/*
> -			 * Enable system clock for GPIO module.
> -			 * The CAM_CLK_CTRL *is* really the right place.
> -			 */
> -			omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04,
> -						ULPD_CAM_CLK_CTRL);
> -		}
> -		if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
> -			__raw_writel(0xffffffff, bank->base
> -						+ OMAP7XX_GPIO_INT_MASK);
> -			__raw_writel(0x00000000, bank->base
> -						+ OMAP7XX_GPIO_INT_STATUS);
> -		}
> +		return;
>  	}
> +
> +	if (bank->regs->ctrl)
> +		/* Initialize interface clk ungated, module enabled */
> +		bank->do_raw_write(bank->base + bank->regs->ctrl, 0);
> +
> +	if (bank->regs->clr_irqenable && bank->width == 32)
> +		bank->do_raw_write(bank->base + bank->regs->clr_irqenable, 1);
> +	else if (bank->regs->irqenable)
> +		bank->do_raw_write(bank->base + bank->regs->irqenable,
> +				bank->regs->irqenable_inv);
> +
> +	if (bank->regs->irqstatus)
> +		bank->do_raw_write(bank->base + bank->regs->irqstatus,
> +				bank->regs->irqenable_inv == 0);
> +
> +	if (bank->regs->debounce_en)
> +		bank->do_raw_write(bank->base + bank->regs->debounce_en, 0);
>  }
>  
>  static __init void
> @@ -1041,6 +1028,11 @@ static int __devinit omap_gpio_probe(struct platform_device *pdev)
>  	bank->get_context_loss_count = pdata->get_context_loss_count;
>  	bank->regs = pdata->regs;
>  
> +	if (bank->width == 32)
> +		bank->do_raw_write = __do_raw_writel;
> +	else
> +		bank->do_raw_write = __do_raw_writew;
> +
>  	if (bank->regs->set_dataout && bank->regs->clr_dataout)
>  		bank->set_dataout = _set_gpio_dataout_reg;
>  	else

Actually, I think this driver should just be converted so *all* access
are 4-byte accesses.

Current code already uses a mix of readw and readl for register access
OMAP1, so let's just drop all the readw and use readl throughout.  All
registers on OMAP1 are 4-byte aligned.

Kevin

RE: [PATCH v3 13/20] GPIO: OMAP: Clean omap_gpio_mod_init function

[DebBarma, Tarun Kanti]

[...]
> > With register offsets now defined for respective OMAP versions we can
> get rid
> > of cpu_class_* checks. This function now has common initialization code
> for
> > all OMAP versions. Initialization specific to OMAP16xx has been moved
> within
> > omap16xx_gpio_init().
> 
> This patch also adds the ->do_raw_write() stuff which is not described
> here, and is an unrelated change that wants its own patch.  More on that
> below.
Ok.

> 
> > Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
> > Signed-off-by: Charulatha V <charu@ti.com>
> > ---
> >  arch/arm/mach-omap1/gpio16xx.c         |   19 ++++++-
> >  arch/arm/plat-omap/include/plat/gpio.h |    2 +
> >  drivers/gpio/gpio-omap.c               |   96 +++++++++++++++----------
> -------
> >  3 files changed, 64 insertions(+), 53 deletions(-)
> >
> > diff --git a/arch/arm/mach-omap1/gpio16xx.c b/arch/arm/mach-
> omap1/gpio16xx.c
> > index 08dda3c..cfd86b9 100644
> > --- a/arch/arm/mach-omap1/gpio16xx.c
> > +++ b/arch/arm/mach-omap1/gpio16xx.c
> > @@ -93,6 +93,7 @@ static struct omap_gpio_reg_offs omap16xx_gpio_regs =
> {
> >  	.wkup_status	= OMAP1610_GPIO_WAKEUPENABLE,
> >  	.edgectrl1	= OMAP1610_GPIO_EDGE_CTRL1,
> >  	.edgectrl2	= OMAP1610_GPIO_EDGE_CTRL2,
> > +	.sysconfig	= OMAP1610_GPIO_SYSCONFIG,
> >  };
> >
> >  static struct __initdata omap_gpio_platform_data omap16xx_gpio1_config
> = {
> > @@ -218,12 +219,28 @@ static struct __initdata platform_device *
> omap16xx_gpio_dev[] = {
> >  static int __init omap16xx_gpio_init(void)
> >  {
> >  	int i;
> > +	void __iomem *base;
> > +	struct resource *res;
> > +	struct platform_device *pdev;
> > +	struct omap_gpio_platform_data *pdata;
> >
> >  	if (!cpu_is_omap16xx())
> >  		return -EINVAL;
> >
> > -	for (i = 0; i < ARRAY_SIZE(omap16xx_gpio_dev); i++)
> > +	for (i = 0; i < ARRAY_SIZE(omap16xx_gpio_dev); i++) {
> > +		pdev = omap16xx_gpio_dev[i];
> > +		pdata = pdev->dev.platform_data;
> > +		res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > +		base = ioremap(res->start, resource_size(res));
> > +
> > +		if (pdata->regs->sysconfig)
> 
> using field from regs-> here...
> 
> > +			__raw_writew(0x0014, base + OMAP1610_GPIO_SYSCONFIG);
> 
> but the #define here.
> 
> Since you don't really need this field in reg_offs (because it's not
> used in SoC-independent code), just drop the if and always write
> sysconfig.
Yes. In fact I thought the same where it is redundant to add 16xx specific
Register in reg_offs. Thanks.
I will make the change.
> 
> > +		omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04,
> > +					ULPD_CAM_CLK_CTRL);
> 
> Please preserve the comments from the original code, since the CAM
> access does lok rather confusing.
Sure.

> 
> >  		platform_device_register(omap16xx_gpio_dev[i]);
> > +	}
> >
> >  	return 0;
> >  }
> > diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-
> omap/include/plat/gpio.h
> > index 4f584de..3f7b028 100644
> > --- a/arch/arm/plat-omap/include/plat/gpio.h
> > +++ b/arch/arm/plat-omap/include/plat/gpio.h
> > @@ -198,6 +198,8 @@ struct omap_gpio_reg_offs {
> >  	u16 irqctrl;
> >  	u16 edgectrl1;
> >  	u16 edgectrl2;
> > +	/* Not applicable for OMAP2+ as hwmod layer takes care of sysconfig
> */
> > +	u16 sysconfig;
> >
> >  	bool irqenable_inv;
> >  };
> > diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
> > index 769fae7..3acbaa9 100644
> > --- a/drivers/gpio/gpio-omap.c
> > +++ b/drivers/gpio/gpio-omap.c
> > @@ -75,6 +75,7 @@ struct gpio_bank {
> >
> >  	void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable);
> >  	int (*get_context_loss_count)(struct device *dev);
> > +	void (*do_raw_write)(void __iomem *reg, int set);
> >
> >  	struct omap_gpio_reg_offs *regs;
> >  };
> > @@ -864,67 +865,53 @@ static void __init omap_gpio_show_rev(struct
> gpio_bank *bank)
> >  	called = true;
> >  }
> >
> > +static void __do_raw_writel(void __iomem *reg, int set)
> > +{
> > +	if (set)
> > +		__raw_writel(0xffffffff, reg);
> > +	else
> > +		__raw_writel(0x00000000, reg);
> > +
> > +}
> > +
> > +static void __do_raw_writew(void __iomem *reg, int set)
> > +{
> > +	if (set)
> > +		__raw_writew(0xffff, reg);
> > +	else
> > +		__raw_writew(0x0000, reg);
> > +}
> > +
> >  /* This lock class tells lockdep that GPIO irqs are in a different
> >   * category than their parents, so it won't report false recursion.
> >   */
> >  static struct lock_class_key gpio_lock_class;
> >
> > -/* TODO: Cleanup cpu_is_* checks */
> >  static void omap_gpio_mod_init(struct gpio_bank *bank)
> >  {
> > -	if (cpu_class_is_omap2()) {
> > -		if (cpu_is_omap44xx()) {
> > -			__raw_writel(0xffffffff, bank->base +
> > -					OMAP4_GPIO_IRQSTATUSCLR0);
> > -			__raw_writel(0x00000000, bank->base +
> > -					 OMAP4_GPIO_DEBOUNCENABLE);
> > -			/* Initialize interface clk ungated, module enabled */
> > -			__raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
> > -		} else if (cpu_is_omap34xx()) {
> > -			__raw_writel(0x00000000, bank->base +
> > -					OMAP24XX_GPIO_IRQENABLE1);
> > -			__raw_writel(0xffffffff, bank->base +
> > -					OMAP24XX_GPIO_IRQSTATUS1);
> > -			__raw_writel(0x00000000, bank->base +
> > -					OMAP24XX_GPIO_DEBOUNCE_EN);
> > -
> > -			/* Initialize interface clk ungated, module enabled */
> > -			__raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
> > -		}
> > -	} else if (cpu_class_is_omap1()) {
> > -		if (bank_is_mpuio(bank)) {
> > -			__raw_writew(0xffff, bank->base +
> > -				OMAP_MPUIO_GPIO_MASKIT / bank->stride);
> > +	if (bank_is_mpuio(bank)) {
> > +		bank->do_raw_write(bank->base + bank->regs->irqenable, 1);
> > +		if (bank->regs->wkup_status)
> >  			mpuio_init(bank);
> > -		}
> > -		if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
> > -			__raw_writew(0xffff, bank->base
> > -						+ OMAP1510_GPIO_INT_MASK);
> > -			__raw_writew(0x0000, bank->base
> > -						+ OMAP1510_GPIO_INT_STATUS);
> > -		}
> > -		if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
> > -			__raw_writew(0x0000, bank->base
> > -						+ OMAP1610_GPIO_IRQENABLE1);
> > -			__raw_writew(0xffff, bank->base
> > -						+ OMAP1610_GPIO_IRQSTATUS1);
> > -			__raw_writew(0x0014, bank->base
> > -						+ OMAP1610_GPIO_SYSCONFIG);
> > -
> > -			/*
> > -			 * Enable system clock for GPIO module.
> > -			 * The CAM_CLK_CTRL *is* really the right place.
> > -			 */
> > -			omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04,
> > -						ULPD_CAM_CLK_CTRL);
> > -		}
> > -		if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
> > -			__raw_writel(0xffffffff, bank->base
> > -						+ OMAP7XX_GPIO_INT_MASK);
> > -			__raw_writel(0x00000000, bank->base
> > -						+ OMAP7XX_GPIO_INT_STATUS);
> > -		}
> > +		return;
> >  	}
> > +
> > +	if (bank->regs->ctrl)
> > +		/* Initialize interface clk ungated, module enabled */
> > +		bank->do_raw_write(bank->base + bank->regs->ctrl, 0);
> > +
> > +	if (bank->regs->clr_irqenable && bank->width == 32)
> > +		bank->do_raw_write(bank->base + bank->regs->clr_irqenable, 1);
> > +	else if (bank->regs->irqenable)
> > +		bank->do_raw_write(bank->base + bank->regs->irqenable,
> > +				bank->regs->irqenable_inv);
> > +
> > +	if (bank->regs->irqstatus)
> > +		bank->do_raw_write(bank->base + bank->regs->irqstatus,
> > +				bank->regs->irqenable_inv == 0);
> > +
> > +	if (bank->regs->debounce_en)
> > +		bank->do_raw_write(bank->base + bank->regs->debounce_en, 0);
> >  }
> >
> >  static __init void
> > @@ -1041,6 +1028,11 @@ static int __devinit omap_gpio_probe(struct
> platform_device *pdev)
> >  	bank->get_context_loss_count = pdata->get_context_loss_count;
> >  	bank->regs = pdata->regs;
> >
> > +	if (bank->width == 32)
> > +		bank->do_raw_write = __do_raw_writel;
> > +	else
> > +		bank->do_raw_write = __do_raw_writew;
> > +
> >  	if (bank->regs->set_dataout && bank->regs->clr_dataout)
> >  		bank->set_dataout = _set_gpio_dataout_reg;
> >  	else
> 
> Actually, I think this driver should just be converted so *all* access
> are 4-byte accesses.
> 
> Current code already uses a mix of readw and readl for register access
> OMAP1, so let's just drop all the readw and use readl throughout.  All
> registers on OMAP1 are 4-byte aligned.
Yes, you had similar comment on another patch. I will modify.
--
Tarun
> 
> Kevin

[PATCH v3 14/20] GPIO: OMAP15xx: Use pinctrl offset instead of macro

[Tarun Kanti DebBarma]

From: Charulatha V <charu@ti.com>

Use regs->pinctrl field instead of using the macro OMAP1510_GPIO_PIN_CONTROL

Signed-off-by: Charulatha V <charu@ti.com>
---
 arch/arm/mach-omap1/gpio15xx.c         |    1 +
 arch/arm/plat-omap/include/plat/gpio.h |    1 +
 drivers/gpio/gpio-omap.c               |    8 +++-----
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-omap1/gpio15xx.c b/arch/arm/mach-omap1/gpio15xx.c
index fd2fe8f..020725f 100644
--- a/arch/arm/mach-omap1/gpio15xx.c
+++ b/arch/arm/mach-omap1/gpio15xx.c
@@ -85,6 +85,7 @@ static struct omap_gpio_reg_offs omap15xx_gpio_regs = {
 	.irqenable	= OMAP1510_GPIO_INT_MASK,
 	.irqenable_inv	= true,
 	.irqctrl	= OMAP1510_GPIO_INT_CONTROL,
+	.pinctrl	= OMAP1510_GPIO_PIN_CONTROL,
 };
 
 static struct __initdata omap_gpio_platform_data omap15xx_gpio_config = {
diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h
index 3f7b028..e1ef4e4 100644
--- a/arch/arm/plat-omap/include/plat/gpio.h
+++ b/arch/arm/plat-omap/include/plat/gpio.h
@@ -200,6 +200,7 @@ struct omap_gpio_reg_offs {
 	u16 edgectrl2;
 	/* Not applicable for OMAP2+ as hwmod layer takes care of sysconfig */
 	u16 sysconfig;
+	u16 pinctrl;
 
 	bool irqenable_inv;
 };
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 3acbaa9..7f32f7b 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -482,15 +482,13 @@ static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
 	 */
 	_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
 
-#ifdef CONFIG_ARCH_OMAP15XX
-	if (bank->method == METHOD_GPIO_1510) {
-		void __iomem *reg;
+	if (bank->regs->pinctrl) {
+		void __iomem *reg = bank->base + bank->regs->pinctrl;
 
 		/* Claim the pin for MPU */
-		reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
 		__raw_writel(__raw_readl(reg) | (1 << offset), reg);
 	}
-#endif
+
 	if (bank->regs->ctrl && !bank->mod_usage) {
 		void __iomem *reg = bank->base + bank->regs->ctrl;
 		u32 ctrl;
-- 
1.6.0.4

[PATCH v3 15/20] GPIO: OMAP: Use readl in irq_handler for all access

[Tarun Kanti DebBarma]

From: Charulatha V <charu@ti.com>

Even when bank->width is 16, all the OMAP1 registers are 4-byte aligned, so just
use a 4-byte read.  The 'enabled' mask is already taking care to mask for bank width.

Signed-off-by: Charulatha V <charu@ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
---
 drivers/gpio/gpio-omap.c |    2 --
 1 files changed, 0 insertions(+), 2 deletions(-)

diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 7f32f7b..25675a6 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -568,8 +568,6 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 		enabled = _get_gpio_irqbank_mask(bank);
 		isr_saved = isr = __raw_readl(isr_reg) & enabled;
 
-		if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
-			isr &= 0x0000ffff;
 
 		if (bank->level_mask)
 			level_mask = bank->level_mask & enabled;
-- 
1.6.0.4

[PATCH v3 16/20] GPIO: OMAP: Remove bank->method & METHOD_* macros

[Tarun Kanti DebBarma]

From: Charulatha V <charu@ti.com>

The only bank->type (method) used in the OMAP GPIO driver is MPUIO type as they
need to be handled separately. Identify the same using a flag and remove all
METHOD_* macros.

Signed-off-by: Charulatha V <charu@ti.com>
---
 arch/arm/mach-omap1/gpio15xx.c         |    3 +--
 arch/arm/mach-omap1/gpio16xx.c         |    6 +-----
 arch/arm/mach-omap1/gpio7xx.c          |    8 +-------
 arch/arm/mach-omap2/gpio.c             |    2 --
 arch/arm/plat-omap/include/plat/gpio.h |    8 +-------
 drivers/gpio/gpio-omap.c               |   16 +++++-----------
 6 files changed, 9 insertions(+), 34 deletions(-)

diff --git a/arch/arm/mach-omap1/gpio15xx.c b/arch/arm/mach-omap1/gpio15xx.c
index 020725f..c51593c 100644
--- a/arch/arm/mach-omap1/gpio15xx.c
+++ b/arch/arm/mach-omap1/gpio15xx.c
@@ -47,7 +47,7 @@ static struct omap_gpio_reg_offs omap15xx_mpuio_regs = {
 
 static struct __initdata omap_gpio_platform_data omap15xx_mpu_gpio_config = {
 	.virtual_irq_start	= IH_MPUIO_BASE,
-	.bank_type		= METHOD_MPUIO,
+	.is_mpuio		= true,
 	.bank_width		= 16,
 	.bank_stride		= 1,
 	.regs			= &omap15xx_mpuio_regs,
@@ -90,7 +90,6 @@ static struct omap_gpio_reg_offs omap15xx_gpio_regs = {
 
 static struct __initdata omap_gpio_platform_data omap15xx_gpio_config = {
 	.virtual_irq_start	= IH_GPIO_BASE,
-	.bank_type		= METHOD_GPIO_1510,
 	.bank_width		= 16,
 	.regs                   = &omap15xx_gpio_regs,
 };
diff --git a/arch/arm/mach-omap1/gpio16xx.c b/arch/arm/mach-omap1/gpio16xx.c
index cfd86b9..8509155 100644
--- a/arch/arm/mach-omap1/gpio16xx.c
+++ b/arch/arm/mach-omap1/gpio16xx.c
@@ -50,7 +50,7 @@ static struct omap_gpio_reg_offs omap16xx_mpuio_regs = {
 
 static struct __initdata omap_gpio_platform_data omap16xx_mpu_gpio_config = {
 	.virtual_irq_start	= IH_MPUIO_BASE,
-	.bank_type		= METHOD_MPUIO,
+	.is_mpuio		= true,
 	.bank_width		= 16,
 	.bank_stride		= 1,
 	.regs                   = &omap16xx_mpuio_regs,
@@ -98,7 +98,6 @@ static struct omap_gpio_reg_offs omap16xx_gpio_regs = {
 
 static struct __initdata omap_gpio_platform_data omap16xx_gpio1_config = {
 	.virtual_irq_start	= IH_GPIO_BASE,
-	.bank_type		= METHOD_GPIO_1610,
 	.bank_width		= 16,
 	.regs                   = &omap16xx_gpio_regs,
 };
@@ -128,7 +127,6 @@ static struct __initdata resource omap16xx_gpio2_resources[] = {
 
 static struct __initdata omap_gpio_platform_data omap16xx_gpio2_config = {
 	.virtual_irq_start	= IH_GPIO_BASE + 16,
-	.bank_type		= METHOD_GPIO_1610,
 	.bank_width		= 16,
 	.regs                   = &omap16xx_gpio_regs,
 };
@@ -158,7 +156,6 @@ static struct __initdata resource omap16xx_gpio3_resources[] = {
 
 static struct __initdata omap_gpio_platform_data omap16xx_gpio3_config = {
 	.virtual_irq_start	= IH_GPIO_BASE + 32,
-	.bank_type		= METHOD_GPIO_1610,
 	.bank_width		= 16,
 	.regs                   = &omap16xx_gpio_regs,
 };
@@ -188,7 +185,6 @@ static struct __initdata resource omap16xx_gpio4_resources[] = {
 
 static struct __initdata omap_gpio_platform_data omap16xx_gpio4_config = {
 	.virtual_irq_start	= IH_GPIO_BASE + 48,
-	.bank_type		= METHOD_GPIO_1610,
 	.bank_width		= 16,
 	.regs                   = &omap16xx_gpio_regs,
 };
diff --git a/arch/arm/mach-omap1/gpio7xx.c b/arch/arm/mach-omap1/gpio7xx.c
index 6e439ff..91a7691 100644
--- a/arch/arm/mach-omap1/gpio7xx.c
+++ b/arch/arm/mach-omap1/gpio7xx.c
@@ -52,8 +52,8 @@ static struct omap_gpio_reg_offs omap7xx_mpuio_regs = {
 
 static struct __initdata omap_gpio_platform_data omap7xx_mpu_gpio_config = {
 	.virtual_irq_start	= IH_MPUIO_BASE,
-	.bank_type		= METHOD_MPUIO,
 	.bank_width		= 32,
+	.is_mpuio		= true,
 	.bank_stride		= 2,
 	.regs                   = &omap7xx_mpuio_regs,
 };
@@ -94,7 +94,6 @@ static struct omap_gpio_reg_offs omap7xx_gpio_regs = {
 
 static struct __initdata omap_gpio_platform_data omap7xx_gpio1_config = {
 	.virtual_irq_start	= IH_GPIO_BASE,
-	.bank_type		= METHOD_GPIO_7XX,
 	.bank_width		= 32,
 	.regs			= &omap7xx_gpio_regs,
 };
@@ -124,7 +123,6 @@ static struct __initdata resource omap7xx_gpio2_resources[] = {
 
 static struct __initdata omap_gpio_platform_data omap7xx_gpio2_config = {
 	.virtual_irq_start	= IH_GPIO_BASE + 32,
-	.bank_type		= METHOD_GPIO_7XX,
 	.bank_width		= 32,
 	.regs			= &omap7xx_gpio_regs,
 };
@@ -154,7 +152,6 @@ static struct __initdata resource omap7xx_gpio3_resources[] = {
 
 static struct __initdata omap_gpio_platform_data omap7xx_gpio3_config = {
 	.virtual_irq_start	= IH_GPIO_BASE + 64,
-	.bank_type		= METHOD_GPIO_7XX,
 	.bank_width		= 32,
 	.regs			= &omap7xx_gpio_regs,
 };
@@ -184,7 +181,6 @@ static struct __initdata resource omap7xx_gpio4_resources[] = {
 
 static struct __initdata omap_gpio_platform_data omap7xx_gpio4_config = {
 	.virtual_irq_start	= IH_GPIO_BASE + 96,
-	.bank_type		= METHOD_GPIO_7XX,
 	.bank_width		= 32,
 	.regs			= &omap7xx_gpio_regs,
 };
@@ -214,7 +210,6 @@ static struct __initdata resource omap7xx_gpio5_resources[] = {
 
 static struct __initdata omap_gpio_platform_data omap7xx_gpio5_config = {
 	.virtual_irq_start	= IH_GPIO_BASE + 128,
-	.bank_type		= METHOD_GPIO_7XX,
 	.bank_width		= 32,
 	.regs			= &omap7xx_gpio_regs,
 };
@@ -244,7 +239,6 @@ static struct __initdata resource omap7xx_gpio6_resources[] = {
 
 static struct __initdata omap_gpio_platform_data omap7xx_gpio6_config = {
 	.virtual_irq_start	= IH_GPIO_BASE + 160,
-	.bank_type		= METHOD_GPIO_7XX,
 	.bank_width		= 32,
 	.regs			= &omap7xx_gpio_regs,
 };
diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c
index c99eea4..1e72a56 100644
--- a/arch/arm/mach-omap2/gpio.c
+++ b/arch/arm/mach-omap2/gpio.c
@@ -97,7 +97,6 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
 		/* fall through */
 
 	case 1:
-		pdata->bank_type = METHOD_GPIO_24XX;
 		pdata->regs->revision = OMAP24XX_GPIO_REVISION;
 		pdata->regs->direction = OMAP24XX_GPIO_OE;
 		pdata->regs->datain = OMAP24XX_GPIO_DATAIN;
@@ -120,7 +119,6 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
 		pdata->regs->fallingdetect = OMAP24XX_GPIO_FALLINGDETECT;
 		break;
 	case 2:
-		pdata->bank_type = METHOD_GPIO_44XX;
 		pdata->regs->revision = OMAP4_GPIO_REVISION;
 		pdata->regs->direction = OMAP4_GPIO_OE;
 		pdata->regs->datain = OMAP4_GPIO_DATAIN;
diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h
index e1ef4e4..168b335 100644
--- a/arch/arm/plat-omap/include/plat/gpio.h
+++ b/arch/arm/plat-omap/include/plat/gpio.h
@@ -162,13 +162,6 @@
 				 IH_MPUIO_BASE + ((nr) & 0x0f) : \
 				 IH_GPIO_BASE + (nr))
 
-#define METHOD_MPUIO		0
-#define METHOD_GPIO_1510	1
-#define METHOD_GPIO_1610	2
-#define METHOD_GPIO_7XX		3
-#define METHOD_GPIO_24XX	5
-#define METHOD_GPIO_44XX	6
-
 struct omap_gpio_dev_attr {
 	int bank_width;		/* GPIO bank width */
 	bool dbck_flag;		/* dbck required or not - True for OMAP3&4 */
@@ -212,6 +205,7 @@ struct omap_gpio_platform_data {
 	int bank_stride;	/* Only needed for omap1 MPUIO */
 	bool dbck_flag;		/* dbck required or not - True for OMAP3&4 */
 	bool loses_context;	/* whether the bank would ever lose context */
+	bool is_mpuio;		/* whether the bank is of type MPUIO */
 	u32 non_wakeup_gpios;
 
 	struct omap_gpio_reg_offs *regs;
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 25675a6..f1e346b 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -49,7 +49,6 @@ struct gpio_bank {
 	void __iomem *base;
 	u16 irq;
 	u16 virtual_irq_start;
-	int method;
 	u32 suspend_wakeup;
 	u32 saved_wakeup;
 	u32 non_wakeup_gpios;
@@ -66,6 +65,7 @@ struct gpio_bank {
 	u32 mod_usage;
 	u32 dbck_enable_mask;
 	struct device *dev;
+	bool is_mpuio;
 	bool dbck_flag;
 	bool loses_context;
 	int stride;
@@ -685,8 +685,6 @@ static struct irq_chip gpio_irq_chip = {
 };
 
 /*---------------------------------------------------------------------*/
-#define bank_is_mpuio(bank)	((bank)->method == METHOD_MPUIO)
-
 static int omap_mpuio_suspend_noirq(struct device *dev)
 {
 	struct platform_device *pdev = to_platform_device(dev);
@@ -750,10 +748,6 @@ static inline void mpuio_init(struct gpio_bank *bank)
 
 /*---------------------------------------------------------------------*/
 
-/* REVISIT these are stupid implementations!  replace by ones that
- * don't switch on METHOD_* and which mostly avoid spinlocks
- */
-
 static int gpio_input(struct gpio_chip *chip, unsigned offset)
 {
 	struct gpio_bank *bank;
@@ -885,7 +879,7 @@ static struct lock_class_key gpio_lock_class;
 
 static void omap_gpio_mod_init(struct gpio_bank *bank)
 {
-	if (bank_is_mpuio(bank)) {
+	if (bank->is_mpuio) {
 		bank->do_raw_write(bank->base + bank->regs->irqenable, 1);
 		if (bank->regs->wkup_status)
 			mpuio_init(bank);
@@ -952,7 +946,7 @@ static void __devinit omap_gpio_chip_init(struct gpio_bank *bank)
 	bank->chip.set_debounce = gpio_debounce;
 	bank->chip.set = gpio_set;
 	bank->chip.to_irq = gpio_2irq;
-	if (bank_is_mpuio(bank)) {
+	if (bank->is_mpuio) {
 		bank->chip.label = "mpuio";
 		if (bank->regs->wkup_status)
 			bank->chip.dev = &omap_mpuio_device.dev;
@@ -970,7 +964,7 @@ static void __devinit omap_gpio_chip_init(struct gpio_bank *bank)
 		     j < bank->virtual_irq_start + bank->width; j++) {
 		irq_set_lockdep_class(j, &gpio_lock_class);
 		irq_set_chip_data(j, bank);
-		if (bank_is_mpuio(bank)) {
+		if (bank->is_mpuio) {
 			omap_mpuio_alloc_gc(bank, j, bank->width);
 		} else {
 			irq_set_chip(j, &gpio_irq_chip);
@@ -1014,11 +1008,11 @@ static int __devinit omap_gpio_probe(struct platform_device *pdev)
 
 	pdata = pdev->dev.platform_data;
 	bank->virtual_irq_start = pdata->virtual_irq_start;
-	bank->method = pdata->bank_type;
 	bank->dev = &pdev->dev;
 	bank->dbck_flag = pdata->dbck_flag;
 	bank->stride = pdata->bank_stride;
 	bank->width = pdata->bank_width;
+	bank->is_mpuio = pdata->is_mpuio;
 	bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
 	bank->loses_context = pdata->loses_context;
 	bank->get_context_loss_count = pdata->get_context_loss_count;
-- 
1.6.0.4

[PATCH v3 17/20] GPIO: OMAP: Fix bankwidth for OMAP7xx MPUIO

[Tarun Kanti DebBarma]

From: Charulatha V <charu@ti.com>

In all OMAP1 SoCs, the MPUIO bank width is 16 bits. But, in OMAP7xx,
it is wrongly initialised to 32. Fix this.

Signed-off-by: Charulatha V <charu@ti.com>
---
 arch/arm/mach-omap1/gpio7xx.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap1/gpio7xx.c b/arch/arm/mach-omap1/gpio7xx.c
index 91a7691..65949c8 100644
--- a/arch/arm/mach-omap1/gpio7xx.c
+++ b/arch/arm/mach-omap1/gpio7xx.c
@@ -52,8 +52,8 @@ static struct omap_gpio_reg_offs omap7xx_mpuio_regs = {
 
 static struct __initdata omap_gpio_platform_data omap7xx_mpu_gpio_config = {
 	.virtual_irq_start	= IH_MPUIO_BASE,
-	.bank_width		= 32,
 	.is_mpuio		= true,
+	.bank_width		= 16,
 	.bank_stride		= 2,
 	.regs                   = &omap7xx_mpuio_regs,
 };
-- 
1.6.0.4

[PATCH v3 18/20] GPIO: OMAP: Use PM runtime framework

[Tarun Kanti DebBarma]

From: Charulatha V <charu@ti.com>

Call runtime pm APIs pm_runtime_get_sync() and pm_runtime_put_sync()
for enabling/disabling clocks appropriately. Remove syscore_ops and
instead use dev_pm_ops now.

Signed-off-by: Charulatha V <charu@ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
---
 drivers/gpio/gpio-omap.c |   99 ++++++++++++++++++++++++++++++++++++----------
 1 files changed, 78 insertions(+), 21 deletions(-)

diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index f1e346b..66eff1d 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -80,6 +80,8 @@ struct gpio_bank {
 	struct omap_gpio_reg_offs *regs;
 };
 
+static void omap_gpio_mod_init(struct gpio_bank *bank);
+
 #define GPIO_INDEX(bank, gpio) (gpio % bank->width)
 #define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio))
 #define GPIO_MOD_CTRL_BIT	BIT(0)
@@ -475,6 +477,22 @@ static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
 	struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
 	unsigned long flags;
 
+	/*
+	 * If this is the first gpio_request for the bank,
+	 * enable the bank module.
+	 */
+	if (!bank->mod_usage) {
+		if (IS_ERR_VALUE(pm_runtime_get_sync(bank->dev) < 0)) {
+			dev_err(bank->dev, "%s: GPIO bank %d "
+					"pm_runtime_get_sync failed\n",
+					__func__, bank->id);
+			return -EINVAL;
+		}
+
+		/* Initialize the gpio bank registers to init time value */
+		omap_gpio_mod_init(bank);
+	}
+
 	spin_lock_irqsave(&bank->lock, flags);
 
 	/* Set trigger to none. You need to enable the desired trigger with
@@ -532,6 +550,18 @@ static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
 
 	_reset_gpio(bank, bank->chip.base + offset);
 	spin_unlock_irqrestore(&bank->lock, flags);
+
+	/*
+	 * If this is the last gpio to be freed in the bank,
+	 * disable the bank module.
+	 */
+	if (!bank->mod_usage) {
+		if (IS_ERR_VALUE(pm_runtime_put_sync(bank->dev) < 0)) {
+			dev_err(bank->dev, "%s: GPIO bank %d "
+					"pm_runtime_put_sync failed\n",
+					__func__, bank->id);
+		}
+	}
 }
 
 /*
@@ -556,6 +586,9 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 	chained_irq_enter(chip, desc);
 
 	bank = irq_get_handler_data(irq);
+
+	pm_runtime_get_sync(bank->dev);
+
 	isr_reg = bank->base + bank->regs->irqstatus;
 
 	if (WARN_ON(!isr_reg))
@@ -618,6 +651,8 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 exit:
 	if (!unmasked)
 		chained_irq_exit(chip, desc);
+
+	pm_runtime_put_sync(bank->dev);
 }
 
 static void gpio_irq_shutdown(struct irq_data *d)
@@ -1048,12 +1083,25 @@ static int __devinit omap_gpio_probe(struct platform_device *pdev)
 	}
 
 	pm_runtime_enable(bank->dev);
-	pm_runtime_get_sync(bank->dev);
+	pm_runtime_irq_safe(bank->dev);
+	if (IS_ERR_VALUE(pm_runtime_get_sync(bank->dev) < 0)) {
+		dev_err(bank->dev, "%s: GPIO bank %d pm_runtime_get_sync "
+				"failed\n", __func__, bank->id);
+		iounmap(bank->base);
+		return -EINVAL;
+	}
 
 	omap_gpio_mod_init(bank);
 	omap_gpio_chip_init(bank);
 	omap_gpio_show_rev(bank);
 
+	if (IS_ERR_VALUE(pm_runtime_put_sync(bank->dev) < 0)) {
+		dev_err(bank->dev, "%s: GPIO bank %d pm_runtime_put_sync "
+				"failed\n", __func__, bank->id);
+		iounmap(bank->base);
+		return -EINVAL;
+	}
+
 	list_add_tail(&bank->node, &omap_gpio_list);
 
 	return ret;
@@ -1064,10 +1112,12 @@ err_exit:
 	return ret;
 }
 
-static int omap_gpio_suspend(void)
+static int omap_gpio_suspend(struct device *dev)
 {
 	struct gpio_bank *bank;
 
+	pm_runtime_get_sync(dev);
+
 	list_for_each_entry(bank, &omap_gpio_list, node) {
 		void __iomem *base = bank->base;
 		void __iomem *wake_status;
@@ -1085,31 +1135,34 @@ static int omap_gpio_suspend(void)
 		spin_unlock_irqrestore(&bank->lock, flags);
 	}
 
+	pm_runtime_put_sync(dev);
+
 	return 0;
 }
 
-static void omap_gpio_resume(void)
+static int omap_gpio_resume(struct device *dev)
 {
 	struct gpio_bank *bank;
 
+	pm_runtime_get_sync(dev);
+
 	list_for_each_entry(bank, &omap_gpio_list, node) {
 		void __iomem *base = bank->base;
 		unsigned long flags;
 
 		if (!bank->regs->wkup_status)
-			return;
+			return 0;
 
 		spin_lock_irqsave(&bank->lock, flags);
 		MOD_REG_BIT(bank->regs->wkup_status, 0xffffffff, 0);
 		MOD_REG_BIT(bank->regs->wkup_status, bank->saved_wakeup, 1);
 		spin_unlock_irqrestore(&bank->lock, flags);
 	}
-}
 
-static struct syscore_ops omap_gpio_syscore_ops = {
-	.suspend	= omap_gpio_suspend,
-	.resume		= omap_gpio_resume,
-};
+	pm_runtime_put_sync(dev);
+
+	return 0;
+}
 
 #ifdef CONFIG_ARCH_OMAP2PLUS
 
@@ -1133,6 +1186,11 @@ void omap2_gpio_prepare_for_idle(int off_mode)
 		if (!off_mode)
 			continue;
 
+		if (IS_ERR_VALUE(pm_runtime_put_sync(bank->dev) < 0))
+			dev_err(bank->dev, "%s: GPIO bank %d "
+					"pm_runtime_put_sync failed\n",
+					__func__, bank->id);
+
 		/* If going to OFF, remove triggering for all
 		 * non-wakeup GPIOs.  Otherwise spurious IRQs will be
 		 * generated.  See OMAP2420 Errata item 1.101. */
@@ -1173,6 +1231,11 @@ void omap2_gpio_resume_after_idle(void)
 		if (!bank->loses_context)
 			continue;
 
+		if (IS_ERR_VALUE(pm_runtime_get_sync(bank->dev) < 0))
+			dev_err(bank->dev, "%s: GPIO bank %d "
+					"pm_runtime_get_sync failed\n",
+					__func__, bank->id);
+
 		for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
 			clk_enable(bank->dbck);
 
@@ -1288,10 +1351,16 @@ static void omap_gpio_restore_context(struct gpio_bank *bank)
 }
 #endif
 
+static const struct dev_pm_ops gpio_pm_ops = {
+	.suspend		= omap_gpio_suspend,
+	.resume			= omap_gpio_resume,
+};
+
 static struct platform_driver omap_gpio_driver = {
 	.probe		= omap_gpio_probe,
 	.driver		= {
 		.name	= "omap_gpio",
+		.pm	= &gpio_pm_ops,
 	},
 };
 
@@ -1306,15 +1375,3 @@ static int __init omap_gpio_drv_reg(void)
 }
 postcore_initcall(omap_gpio_drv_reg);
 
-static int __init omap_gpio_sysinit(void)
-{
-
-#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
-	if (cpu_is_omap16xx() || cpu_class_is_omap2())
-		register_syscore_ops(&omap_gpio_syscore_ops);
-#endif
-
-	return 0;
-}
-
-arch_initcall(omap_gpio_sysinit);
-- 
1.6.0.4

Re: [PATCH v3 18/20] GPIO: OMAP: Use PM runtime framework

[Roger Quadros]

Hi,

 From this patch it seems that the GPIO module is kept active as long as 
one of its GPIOs is requested. This is not optimal.

The GPIO needs to be active only when accessing its registers e.g. 
during gpio_get or gpio_set. The rest of the time it can be suspended.

cheers,
-roger

On 07/01/2011 12:47 PM, DebBarma, Tarun Kanti wrote:
> From: Charulatha V<charu@ti.com>
>
> Call runtime pm APIs pm_runtime_get_sync() and pm_runtime_put_sync()
> for enabling/disabling clocks appropriately. Remove syscore_ops and
> instead use dev_pm_ops now.
>
> Signed-off-by: Charulatha V<charu@ti.com>
> Signed-off-by: Tarun Kanti DebBarma<tarun.kanti@ti.com>
> ---
>   drivers/gpio/gpio-omap.c |   99 ++++++++++++++++++++++++++++++++++++----------
>   1 files changed, 78 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
> index f1e346b..66eff1d 100644
> --- a/drivers/gpio/gpio-omap.c
> +++ b/drivers/gpio/gpio-omap.c
> @@ -80,6 +80,8 @@ struct gpio_bank {
>   	struct omap_gpio_reg_offs *regs;
>   };
>
> +static void omap_gpio_mod_init(struct gpio_bank *bank);
> +
>   #define GPIO_INDEX(bank, gpio) (gpio % bank->width)
>   #define GPIO_BIT(bank, gpio) (1<<  GPIO_INDEX(bank, gpio))
>   #define GPIO_MOD_CTRL_BIT	BIT(0)
> @@ -475,6 +477,22 @@ static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
>   	struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
>   	unsigned long flags;
>
> +	/*
> +	 * If this is the first gpio_request for the bank,
> +	 * enable the bank module.
> +	 */
> +	if (!bank->mod_usage) {
> +		if (IS_ERR_VALUE(pm_runtime_get_sync(bank->dev)<  0)) {
> +			dev_err(bank->dev, "%s: GPIO bank %d "
> +					"pm_runtime_get_sync failed\n",
> +					__func__, bank->id);
> +			return -EINVAL;
> +		}
> +
> +		/* Initialize the gpio bank registers to init time value */
> +		omap_gpio_mod_init(bank);
> +	}
> +
>   	spin_lock_irqsave(&bank->lock, flags);
>
>   	/* Set trigger to none. You need to enable the desired trigger with
> @@ -532,6 +550,18 @@ static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
>
>   	_reset_gpio(bank, bank->chip.base + offset);
>   	spin_unlock_irqrestore(&bank->lock, flags);
> +
> +	/*
> +	 * If this is the last gpio to be freed in the bank,
> +	 * disable the bank module.
> +	 */
> +	if (!bank->mod_usage) {
> +		if (IS_ERR_VALUE(pm_runtime_put_sync(bank->dev)<  0)) {
> +			dev_err(bank->dev, "%s: GPIO bank %d "
> +					"pm_runtime_put_sync failed\n",
> +					__func__, bank->id);
> +		}
> +	}
>   }
>
>   /*
> @@ -556,6 +586,9 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
>   	chained_irq_enter(chip, desc);
>
>   	bank = irq_get_handler_data(irq);
> +
> +	pm_runtime_get_sync(bank->dev);
> +
>   	isr_reg = bank->base + bank->regs->irqstatus;
>
>   	if (WARN_ON(!isr_reg))
> @@ -618,6 +651,8 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
>   exit:
>   	if (!unmasked)
>   		chained_irq_exit(chip, desc);
> +
> +	pm_runtime_put_sync(bank->dev);
>   }
>
>   static void gpio_irq_shutdown(struct irq_data *d)
> @@ -1048,12 +1083,25 @@ static int __devinit omap_gpio_probe(struct platform_device *pdev)
>   	}
>
>   	pm_runtime_enable(bank->dev);
> -	pm_runtime_get_sync(bank->dev);
> +	pm_runtime_irq_safe(bank->dev);
> +	if (IS_ERR_VALUE(pm_runtime_get_sync(bank->dev)<  0)) {
> +		dev_err(bank->dev, "%s: GPIO bank %d pm_runtime_get_sync "
> +				"failed\n", __func__, bank->id);
> +		iounmap(bank->base);
> +		return -EINVAL;
> +	}
>
>   	omap_gpio_mod_init(bank);
>   	omap_gpio_chip_init(bank);
>   	omap_gpio_show_rev(bank);
>
> +	if (IS_ERR_VALUE(pm_runtime_put_sync(bank->dev)<  0)) {
> +		dev_err(bank->dev, "%s: GPIO bank %d pm_runtime_put_sync "
> +				"failed\n", __func__, bank->id);
> +		iounmap(bank->base);
> +		return -EINVAL;
> +	}
> +
>   	list_add_tail(&bank->node,&omap_gpio_list);
>
>   	return ret;
> @@ -1064,10 +1112,12 @@ err_exit:
>   	return ret;
>   }
>
> -static int omap_gpio_suspend(void)
> +static int omap_gpio_suspend(struct device *dev)
>   {
>   	struct gpio_bank *bank;
>
> +	pm_runtime_get_sync(dev);
> +
>   	list_for_each_entry(bank,&omap_gpio_list, node) {
>   		void __iomem *base = bank->base;
>   		void __iomem *wake_status;
> @@ -1085,31 +1135,34 @@ static int omap_gpio_suspend(void)
>   		spin_unlock_irqrestore(&bank->lock, flags);
>   	}
>
> +	pm_runtime_put_sync(dev);
> +
>   	return 0;
>   }
>
> -static void omap_gpio_resume(void)
> +static int omap_gpio_resume(struct device *dev)
>   {
>   	struct gpio_bank *bank;
>
> +	pm_runtime_get_sync(dev);
> +
>   	list_for_each_entry(bank,&omap_gpio_list, node) {
>   		void __iomem *base = bank->base;
>   		unsigned long flags;
>
>   		if (!bank->regs->wkup_status)
> -			return;
> +			return 0;
>
>   		spin_lock_irqsave(&bank->lock, flags);
>   		MOD_REG_BIT(bank->regs->wkup_status, 0xffffffff, 0);
>   		MOD_REG_BIT(bank->regs->wkup_status, bank->saved_wakeup, 1);
>   		spin_unlock_irqrestore(&bank->lock, flags);
>   	}
> -}
>
> -static struct syscore_ops omap_gpio_syscore_ops = {
> -	.suspend	= omap_gpio_suspend,
> -	.resume		= omap_gpio_resume,
> -};
> +	pm_runtime_put_sync(dev);
> +
> +	return 0;
> +}
>
>   #ifdef CONFIG_ARCH_OMAP2PLUS
>
> @@ -1133,6 +1186,11 @@ void omap2_gpio_prepare_for_idle(int off_mode)
>   		if (!off_mode)
>   			continue;
>
> +		if (IS_ERR_VALUE(pm_runtime_put_sync(bank->dev)<  0))
> +			dev_err(bank->dev, "%s: GPIO bank %d "
> +					"pm_runtime_put_sync failed\n",
> +					__func__, bank->id);
> +
>   		/* If going to OFF, remove triggering for all
>   		 * non-wakeup GPIOs.  Otherwise spurious IRQs will be
>   		 * generated.  See OMAP2420 Errata item 1.101. */
> @@ -1173,6 +1231,11 @@ void omap2_gpio_resume_after_idle(void)
>   		if (!bank->loses_context)
>   			continue;
>
> +		if (IS_ERR_VALUE(pm_runtime_get_sync(bank->dev)<  0))
> +			dev_err(bank->dev, "%s: GPIO bank %d "
> +					"pm_runtime_get_sync failed\n",
> +					__func__, bank->id);
> +
>   		for (j = 0; j<  hweight_long(bank->dbck_enable_mask); j++)
>   			clk_enable(bank->dbck);
>
> @@ -1288,10 +1351,16 @@ static void omap_gpio_restore_context(struct gpio_bank *bank)
>   }
>   #endif
>
> +static const struct dev_pm_ops gpio_pm_ops = {
> +	.suspend		= omap_gpio_suspend,
> +	.resume			= omap_gpio_resume,
> +};
> +
>   static struct platform_driver omap_gpio_driver = {
>   	.probe		= omap_gpio_probe,
>   	.driver		= {
>   		.name	= "omap_gpio",
> +		.pm	=&gpio_pm_ops,
>   	},
>   };
>
> @@ -1306,15 +1375,3 @@ static int __init omap_gpio_drv_reg(void)
>   }
>   postcore_initcall(omap_gpio_drv_reg);
>
> -static int __init omap_gpio_sysinit(void)
> -{
> -
> -#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
> -	if (cpu_is_omap16xx() || cpu_class_is_omap2())
> -		register_syscore_ops(&omap_gpio_syscore_ops);
> -#endif
> -
> -	return 0;
> -}
> -
> -arch_initcall(omap_gpio_sysinit);

RE: [PATCH v3 18/20] GPIO: OMAP: Use PM runtime framework

[DebBarma, Tarun Kanti]

[...]
>  From this patch it seems that the GPIO module is kept active as long as
> one of its GPIOs is requested. This is not optimal.
Yes, but...

> 
> The GPIO needs to be active only when accessing its registers e.g.
> during gpio_get or gpio_set. The rest of the time it can be suspended.
A GPIO module would typically be used by multiple client drivers.
However, the clock control is common for all GPIO pins within the module.
So clocks can't be turned-off/on without negatively impacting present users.
Instead, client drivers have to ensure that they free GPIO pin(s) after use.
This would make power savings optimal.
--
Tarun

> 
> cheers,
> -roger
[...]

Re: [PATCH v3 18/20] GPIO: OMAP: Use PM runtime framework

[Roger Quadros]

On 07/20/2011 12:28 PM, DebBarma, Tarun Kanti wrote:
> [...]
>>    From this patch it seems that the GPIO module is kept active as long as
>> one of its GPIOs is requested. This is not optimal.
> Yes, but...
>
>>
>> The GPIO needs to be active only when accessing its registers e.g.
>> during gpio_get or gpio_set. The rest of the time it can be suspended.
> A GPIO module would typically be used by multiple client drivers.
> However, the clock control is common for all GPIO pins within the module.
> So clocks can't be turned-off/on without negatively impacting present users.

Why not.

Let's say GPIO 1 and 2 belong to the same GPIO module.
Driver A uses GPIO 1 and driver B uses GPIO 2.
A is just blinking an LED every second whereas B uses GPIO 2 as input.

both drivers will keep the GPIOs requested as long as they are loaded.
Why can't you turn off the clocks when nobody is accessing GPIO registers?

In your current implementation, the GPIO module will never go idle.

cheers,
-roger

RE: [PATCH v3 18/20] GPIO: OMAP: Use PM runtime framework

[DebBarma, Tarun Kanti]

[...]
> Let's say GPIO 1 and 2 belong to the same GPIO module.
> Driver A uses GPIO 1 and driver B uses GPIO 2.
> A is just blinking an LED every second whereas B uses GPIO 2 as input.
> 
> both drivers will keep the GPIOs requested as long as they are loaded.
> Why can't you turn off the clocks when nobody is accessing GPIO registers?
Ok, I get your point. I will have patch for off/retention mode support.
--
Tarun
> 
> In your current implementation, the GPIO module will never go idle.
> 
> cheers,
> -roger

[PATCH v3 19/20] GPIO: OMAP: optimize suspend and resume functions

[Tarun Kanti DebBarma]

There is no need to operate on all the banks every time the function is called.
Just operate on the current bank passed by the framework.

Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
---
 drivers/gpio/gpio-omap.c |   56 ++++++++++++++++++++++-----------------------
 1 files changed, 27 insertions(+), 29 deletions(-)

diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 66eff1d..e9d2e1e 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -1082,6 +1082,8 @@ static int __devinit omap_gpio_probe(struct platform_device *pdev)
 		goto err_free;
 	}
 
+	platform_set_drvdata(pdev, bank);
+
 	pm_runtime_enable(bank->dev);
 	pm_runtime_irq_safe(bank->dev);
 	if (IS_ERR_VALUE(pm_runtime_get_sync(bank->dev) < 0)) {
@@ -1114,26 +1116,24 @@ err_exit:
 
 static int omap_gpio_suspend(struct device *dev)
 {
-	struct gpio_bank *bank;
-
-	pm_runtime_get_sync(dev);
+	struct platform_device *pdev = to_platform_device(dev);
+	struct gpio_bank *bank = platform_get_drvdata(pdev);
+	void __iomem *base = bank->base;
+	void __iomem *wake_status;
+	unsigned long flags;
 
-	list_for_each_entry(bank, &omap_gpio_list, node) {
-		void __iomem *base = bank->base;
-		void __iomem *wake_status;
-		unsigned long flags;
+	if (!bank->regs->wkup_status)
+		return 0;
 
-		if (!bank->regs->wkup_status)
-			return 0;
+	wake_status = bank->base + bank->regs->wkup_status;
 
-		wake_status = bank->base + bank->regs->wkup_status;
+	pm_runtime_get_sync(dev);
 
-		spin_lock_irqsave(&bank->lock, flags);
-		bank->saved_wakeup = __raw_readl(wake_status);
-		MOD_REG_BIT(bank->regs->wkup_status, 0xffffffff, 0);
-		MOD_REG_BIT(bank->regs->wkup_status, bank->suspend_wakeup, 1);
-		spin_unlock_irqrestore(&bank->lock, flags);
-	}
+	spin_lock_irqsave(&bank->lock, flags);
+	bank->saved_wakeup = __raw_readl(wake_status);
+	MOD_REG_BIT(bank->regs->wkup_status, 0xffffffff, 0);
+	MOD_REG_BIT(bank->regs->wkup_status, bank->suspend_wakeup, 1);
+	spin_unlock_irqrestore(&bank->lock, flags);
 
 	pm_runtime_put_sync(dev);
 
@@ -1142,22 +1142,20 @@ static int omap_gpio_suspend(struct device *dev)
 
 static int omap_gpio_resume(struct device *dev)
 {
-	struct gpio_bank *bank;
+	struct platform_device *pdev = to_platform_device(dev);
+	struct gpio_bank *bank = platform_get_drvdata(pdev);
+	void __iomem *base = bank->base;
+	unsigned long flags;
 
-	pm_runtime_get_sync(dev);
+	if (!bank->regs->wkup_status)
+		return 0;
 
-	list_for_each_entry(bank, &omap_gpio_list, node) {
-		void __iomem *base = bank->base;
-		unsigned long flags;
-
-		if (!bank->regs->wkup_status)
-			return 0;
+	pm_runtime_get_sync(dev);
 
-		spin_lock_irqsave(&bank->lock, flags);
-		MOD_REG_BIT(bank->regs->wkup_status, 0xffffffff, 0);
-		MOD_REG_BIT(bank->regs->wkup_status, bank->saved_wakeup, 1);
-		spin_unlock_irqrestore(&bank->lock, flags);
-	}
+	spin_lock_irqsave(&bank->lock, flags);
+	MOD_REG_BIT(bank->regs->wkup_status, 0xffffffff, 0);
+	MOD_REG_BIT(bank->regs->wkup_status, bank->saved_wakeup, 1);
+	spin_unlock_irqrestore(&bank->lock, flags);
 
 	pm_runtime_put_sync(dev);
 
-- 
1.6.0.4

Re: [PATCH v3 19/20] GPIO: OMAP: optimize suspend and resume functions

[Kevin Hilman]

Tarun Kanti DebBarma <tarun.kanti@ti.com> writes:

> There is no need to operate on all the banks every time the function is called.
> Just operate on the current bank passed by the framework.

That's a good change.

There is also no need to runtime suspend/resume the bank if
bank->suspend_wakeup == 0 during suspend (or bank->saved_wakeup == 0
during resume.)

IOW, banks with no wakeups enabled have an unnecessary runtime
resume/suspend in both the system suspend and resume path.

Kevin

RE: [PATCH v3 19/20] GPIO: OMAP: optimize suspend and resume functions

[DebBarma, Tarun Kanti]

> -----Original Message-----
> From: Hilman, Kevin
> Sent: Thursday, July 07, 2011 2:25 AM
> To: DebBarma, Tarun Kanti
> Cc: linux-omap@vger.kernel.org; Shilimkar, Santosh; tony@atomide.com
> Subject: Re: [PATCH v3 19/20] GPIO: OMAP: optimize suspend and resume
> functions
> 
> Tarun Kanti DebBarma <tarun.kanti@ti.com> writes:
> 
> > There is no need to operate on all the banks every time the function is
> called.
> > Just operate on the current bank passed by the framework.
> 
> That's a good change.
> 
> There is also no need to runtime suspend/resume the bank if
> bank->suspend_wakeup == 0 during suspend (or bank->saved_wakeup == 0
> during resume.)
> 
> IOW, banks with no wakeups enabled have an unnecessary runtime
> resume/suspend in both the system suspend and resume path.
Ok, I will incorporate the change.
--
Tarun

> 
> Kevin

[PATCH v3 20/20] GPIO: OMAP2+: Clean prepare_for_idle and resume_after_idle

[Tarun Kanti DebBarma]

Simplify  omap2_gpio_prepare_for_idle() and omap2_gpio_resume_after_idle()
by moving most of the stuff to *_pm_runtime_suspend() and *_pm_runtime_resume().
Also, omap_gpio_suspend() and omap_gpio_resume() optimized to operate per
GPIO bank instead of operating on entire list every time.

Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
Signed-off-by: Charulatha V <charu@ti.com>
---
 drivers/gpio/gpio-omap.c |  234 ++++++++++++++++++++++++---------------------
 1 files changed, 125 insertions(+), 109 deletions(-)

diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index e9d2e1e..b2c1892 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -1167,142 +1167,153 @@ static int omap_gpio_resume(struct device *dev)
 static void omap_gpio_save_context(struct gpio_bank *bank);
 static void omap_gpio_restore_context(struct gpio_bank *bank);
 
-void omap2_gpio_prepare_for_idle(int off_mode)
+static int omap_gpio_runtime_suspend(struct device *dev)
 {
-	struct gpio_bank *bank;
+	struct platform_device *pdev = to_platform_device(dev);
+	struct gpio_bank *bank = platform_get_drvdata(pdev);
+	u32 l1 = 0, l2 = 0;
+	int j;
 
-	list_for_each_entry(bank, &omap_gpio_list, node) {
-		u32 l1 = 0, l2 = 0;
-		int j;
+	for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
+		clk_disable(bank->dbck);
 
-		if (!bank->loses_context)
-			continue;
+	/* If going to OFF, remove triggering for all
+	 * non-wakeup GPIOs.  Otherwise spurious IRQs will be
+	 * generated.  See OMAP2420 Errata item 1.101. */
+	if (!(bank->enabled_non_wakeup_gpios))
+		goto save_gpio_ctx;
 
-		for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
-			clk_disable(bank->dbck);
+	bank->saved_datain = __raw_readl(bank->base +
+						bank->regs->datain);
+	l1 = __raw_readl(bank->base + bank->regs->fallingdetect);
+	l2 = __raw_readl(bank->base + bank->regs->risingdetect);
 
-		if (!off_mode)
-			continue;
+	bank->saved_fallingdetect = l1;
+	bank->saved_risingdetect = l2;
+	l1 &= ~bank->enabled_non_wakeup_gpios;
+	l2 &= ~bank->enabled_non_wakeup_gpios;
 
-		if (IS_ERR_VALUE(pm_runtime_put_sync(bank->dev) < 0))
-			dev_err(bank->dev, "%s: GPIO bank %d "
-					"pm_runtime_put_sync failed\n",
-					__func__, bank->id);
+	__raw_writel(l1, bank->base + bank->regs->fallingdetect);
+	__raw_writel(l2, bank->base + bank->regs->risingdetect);
+
+save_gpio_ctx:
+	if (bank->get_context_loss_count)
+		bank->ctx_loss_count = bank->get_context_loss_count(bank->dev);
+	omap_gpio_save_context(bank);
+
+	return 0;
+}
+
+static int omap_gpio_runtime_resume(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct gpio_bank *bank = platform_get_drvdata(pdev);
+	u32 ctx_lost_cnt_after;
+	u32 l = 0, gen, gen0, gen1;
+	int j;
+
+	for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
+		clk_enable(bank->dbck);
 
-		/* If going to OFF, remove triggering for all
-		 * non-wakeup GPIOs.  Otherwise spurious IRQs will be
-		 * generated.  See OMAP2420 Errata item 1.101. */
-		if (!(bank->enabled_non_wakeup_gpios))
-			goto save_gpio_ctx;
+	if (bank->get_context_loss_count) {
+		ctx_lost_cnt_after =
+			bank->get_context_loss_count(bank->dev);
+		if (ctx_lost_cnt_after != bank->ctx_loss_count)
+			omap_gpio_restore_context(bank);
+	}
 
-		bank->saved_datain = __raw_readl(bank->base +
-							bank->regs->datain);
-		l1 = __raw_readl(bank->base + bank->regs->fallingdetect);
-		l2 = __raw_readl(bank->base + bank->regs->risingdetect);
+	if (!(bank->enabled_non_wakeup_gpios))
+		return 0;
 
-		bank->saved_fallingdetect = l1;
-		bank->saved_risingdetect = l2;
-		l1 &= ~bank->enabled_non_wakeup_gpios;
-		l2 &= ~bank->enabled_non_wakeup_gpios;
+	__raw_writel(bank->saved_fallingdetect,
+			bank->base + bank->regs->fallingdetect);
+	__raw_writel(bank->saved_risingdetect,
+			bank->base + bank->regs->risingdetect);
+	l = __raw_readl(bank->base + bank->regs->datain);
 
-		__raw_writel(l1, bank->base + bank->regs->fallingdetect);
-		__raw_writel(l2, bank->base + bank->regs->risingdetect);
+	/* Check if any of the non-wakeup interrupt GPIOs have changed
+	 * state.  If so, generate an IRQ by software.  This is
+	 * horribly racy, but it's the best we can do to work around
+	 * this silicon bug. */
+	l ^= bank->saved_datain;
+	l &= bank->enabled_non_wakeup_gpios;
 
-save_gpio_ctx:
-		if (bank->get_context_loss_count)
-			bank->ctx_loss_count =
-				bank->get_context_loss_count(bank->dev);
+	/*
+	 * No need to generate IRQs for the rising edge for gpio IRQs
+	 * configured with falling edge only; and vice versa.
+	 */
+	gen0 = l & bank->saved_fallingdetect;
+	gen0 &= bank->saved_datain;
+	gen1 = l & bank->saved_risingdetect;
+	gen1 &= ~(bank->saved_datain);
+
+	/* FIXME: Consider GPIO IRQs with level detections properly! */
+	gen = l & (~(bank->saved_fallingdetect) &
+			~(bank->saved_risingdetect));
+	/* Consider all GPIO IRQs needed to be updated */
+	gen |= gen0 | gen1;
+
+	if (gen) {
+		u32 old0, old1;
+
+		old0 = __raw_readl(bank->base +
+					bank->regs->leveldetect0);
+		old1 = __raw_readl(bank->base +
+					bank->regs->leveldetect1);
+
+		__raw_writel(old0, bank->base +
+					bank->regs->leveldetect0);
+		__raw_writel(old1, bank->base +
+					bank->regs->leveldetect1);
+		if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
+			old0 |= gen;
+			old1 |= gen;
+		}
 
-		omap_gpio_save_context(bank);
+		if (cpu_is_omap44xx()) {
+			old0 |= l;
+			old1 |= l;
+		}
+		__raw_writel(old0, bank->base +
+					bank->regs->leveldetect0);
+		__raw_writel(old1, bank->base +
+					bank->regs->leveldetect1);
 	}
+
+	return 0;
 }
 
-void omap2_gpio_resume_after_idle(void)
+
+void omap2_gpio_prepare_for_idle(int off_mode)
 {
 	struct gpio_bank *bank;
 
-	list_for_each_entry(bank, &omap_gpio_list, node) {
-		u32 ctx_lost_cnt_after;
-		u32 l = 0, gen, gen0, gen1;
-		int j;
+	if (!off_mode)
+		return;
 
-		if (!bank->loses_context)
+	list_for_each_entry(bank, &omap_gpio_list, node) {
+		if (!bank->mod_usage || !bank->loses_context)
 			continue;
 
-		if (IS_ERR_VALUE(pm_runtime_get_sync(bank->dev) < 0))
+		if (IS_ERR_VALUE(pm_runtime_put_sync(bank->dev) < 0))
 			dev_err(bank->dev, "%s: GPIO bank %d "
-					"pm_runtime_get_sync failed\n",
+					"pm_runtime_put_sync failed\n",
 					__func__, bank->id);
+	}
+}
 
-		for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
-			clk_enable(bank->dbck);
-
-		if (bank->get_context_loss_count) {
-			ctx_lost_cnt_after =
-				bank->get_context_loss_count(bank->dev);
-			if (ctx_lost_cnt_after != bank->ctx_loss_count ||
-				!ctx_lost_cnt_after)
-				omap_gpio_restore_context(bank);
-		}
+void omap2_gpio_resume_after_idle(void)
+{
+	struct gpio_bank *bank;
 
-		if (!(bank->enabled_non_wakeup_gpios))
+	list_for_each_entry(bank, &omap_gpio_list, node) {
+		if (!bank->mod_usage || !bank->loses_context)
 			continue;
 
-		__raw_writel(bank->saved_fallingdetect,
-				bank->base + bank->regs->fallingdetect);
-		__raw_writel(bank->saved_risingdetect,
-				bank->base + bank->regs->risingdetect);
-		l = __raw_readl(bank->base + bank->regs->datain);
-
-		/* Check if any of the non-wakeup interrupt GPIOs have changed
-		 * state.  If so, generate an IRQ by software.  This is
-		 * horribly racy, but it's the best we can do to work around
-		 * this silicon bug. */
-		l ^= bank->saved_datain;
-		l &= bank->enabled_non_wakeup_gpios;
-
-		/*
-		 * No need to generate IRQs for the rising edge for gpio IRQs
-		 * configured with falling edge only; and vice versa.
-		 */
-		gen0 = l & bank->saved_fallingdetect;
-		gen0 &= bank->saved_datain;
-
-		gen1 = l & bank->saved_risingdetect;
-		gen1 &= ~(bank->saved_datain);
-
-		/* FIXME: Consider GPIO IRQs with level detections properly! */
-		gen = l & (~(bank->saved_fallingdetect) &
-				~(bank->saved_risingdetect));
-		/* Consider all GPIO IRQs needed to be updated */
-		gen |= gen0 | gen1;
-
-		if (gen) {
-			u32 old0, old1;
-
-			old0 = __raw_readl(bank->base +
-						bank->regs->leveldetect0);
-			old1 = __raw_readl(bank->base +
-						bank->regs->leveldetect1);
-
-			__raw_writel(old0, bank->base +
-						bank->regs->leveldetect0);
-			__raw_writel(old1, bank->base +
-						bank->regs->leveldetect1);
-			if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
-				old0 |= gen;
-				old1 |= gen;
-			}
-
-			if (cpu_is_omap44xx()) {
-				old0 |= l;
-				old1 |= l;
-			}
-			__raw_writel(old0, bank->base +
-						bank->regs->leveldetect0);
-			__raw_writel(old1, bank->base +
-						bank->regs->leveldetect1);
-		}
+		if (IS_ERR_VALUE(pm_runtime_get_sync(bank->dev) < 0))
+			dev_err(bank->dev, "%s: GPIO bank %d "
+					"pm_runtime_get_sync failed\n",
+					__func__, bank->id);
 	}
 }
 
@@ -1347,9 +1358,14 @@ static void omap_gpio_restore_context(struct gpio_bank *bank)
 				bank->base + bank->regs->fallingdetect);
 	__raw_writel(bank->context.dataout, bank->base + bank->regs->dataout);
 }
+#else
+#define omap_gpio_runtime_suspend NULL
+#define omap_gpio_runtime_resume NULL
 #endif
 
 static const struct dev_pm_ops gpio_pm_ops = {
+	.runtime_suspend	= omap_gpio_runtime_suspend,
+	.runtime_resume		= omap_gpio_runtime_resume,
 	.suspend		= omap_gpio_suspend,
 	.resume			= omap_gpio_resume,
 };
-- 
1.6.0.4

Re: [PATCH v3 00/20] GPIO: OMAP: driver cleanup and fixes

[Kevin Hilman]

Tarun Kanti DebBarma <tarun.kanti@ti.com> writes:

> This series is continuation of cleanup of OMAP GPIO driver and fixes.
> The cleanup include getting rid of cpu_is_* checks wherever possible,
> use of gpio_bank list instead of static array, use of unique platform
> specific value associated data member to OMAP platforms to avoid
> cpu_is_* checks. The series also include PM runtime support.
>
> Baseline: git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap-pm.git
> Branch: wip/gpio-cleanup

This fails to boot for me on 4430/Blaze and 3630/Zoom3.

In both cases, I have these boards setup for NFS root, and it appears
that the IRQ setup (specifically triggering) is failing during init, so
the result is no ethernet interface is detected in either case.

Here's the example error from 3630/Zoom3:

[    1.565338] smsc911x: Driver version 2008-10-21                          
[    1.570373] setting trigger mode 8 for irq 318 failed (gpio_irq_type+...)
[    1.577941] smsc911x: probe of smsc911x.0 failed with error -22              

and a similar thing happens on Blaze but with errors from the SPI NIC.

> Test Details:
> - Compile tested for omap1_defconfig and omap2plus_defconfig.
> - OMAP1710-H3: Bootup test.
> - OMAP2430-SDP, OMAP3430-SDP, OMAP4430-SDP: Functional testing. 

Looks like the functional tests need to be expanded to set different
triggering modes, since they're failing above.

> - PM Testing on OMAP3430-SDP: retention, off_mode, system_wide
>   suspend and gpio wakeup.
>
> Following patch is required for testing retention and off-mode:
> https://patchwork.kernel.org/patch/834372/
> OMAP: PM: omap_device: fix device power domain callbacks

FYI... for my testI applied your series on top of my
for_3.1/gpio-cleanups branch and then merged in my for_3.0/pm-fixes
branch (which includes the above fix/dependency).

Kevin

RE: [PATCH v3 00/20] GPIO: OMAP: driver cleanup and fixes

[DebBarma, Tarun Kanti]

[...]
> 
> > Test Details:
> > - Compile tested for omap1_defconfig and omap2plus_defconfig.
> > - OMAP1710-H3: Bootup test.
> > - OMAP2430-SDP, OMAP3430-SDP, OMAP4430-SDP: Functional testing.
> 
> Looks like the functional tests need to be expanded to set different
> triggering modes, since they're failing above.
I will include Zoom3 platform as well before sending out the v4.

> 
> > - PM Testing on OMAP3430-SDP: retention, off_mode, system_wide
> >   suspend and gpio wakeup.
> >
> > Following patch is required for testing retention and off-mode:
> > https://patchwork.kernel.org/patch/834372/
> > OMAP: PM: omap_device: fix device power domain callbacks
> 
> FYI... for my testI applied your series on top of my
> for_3.1/gpio-cleanups branch and then merged in my for_3.0/pm-fixes
> branch (which includes the above fix/dependency).
Ok, thanks.
--
Tarun
> 
> Kevin

Re: [PATCH v3 00/20] GPIO: OMAP: driver cleanup and fixes

[Kevin Hilman]

Tarun Kanti DebBarma <tarun.kanti@ti.com> writes:

> This series is continuation of cleanup of OMAP GPIO driver and fixes.

Please also Cc the linux-arm-kernel mailing list for OMAP patches
targetted for upstream.

Thanks,

Kevin

RE: [PATCH v3 00/20] GPIO: OMAP: driver cleanup and fixes

[DebBarma, Tarun Kanti]

> -----Original Message-----
> From: Hilman, Kevin
> Sent: Thursday, July 07, 2011 2:37 AM
> To: DebBarma, Tarun Kanti
> Cc: linux-omap@vger.kernel.org; Shilimkar, Santosh; tony@atomide.com
> Subject: Re: [PATCH v3 00/20] GPIO: OMAP: driver cleanup and fixes
> 
> Tarun Kanti DebBarma <tarun.kanti@ti.com> writes:
> 
> > This series is continuation of cleanup of OMAP GPIO driver and fixes.
> 
> Please also Cc the linux-arm-kernel mailing list for OMAP patches
> targetted for upstream.
Sure, in my v4 posting I will do that!
--
Tarun
> 
> Thanks,
> 
> Kevin

Re: [PATCH v3 00/20] GPIO: OMAP: driver cleanup and fixes

[Hilman, Kevin]

On Wed, Jul 6, 2011 at 9:16 PM, DebBarma, Tarun Kanti
<tarun.kanti@ti.com> wrote:
>> -----Original Message-----
>> From: Hilman, Kevin
>> Sent: Thursday, July 07, 2011 2:37 AM
>> To: DebBarma, Tarun Kanti
>> Cc: linux-omap@vger.kernel.org; Shilimkar, Santosh; tony@atomide.com
>> Subject: Re: [PATCH v3 00/20] GPIO: OMAP: driver cleanup and fixes
>>
>> Tarun Kanti DebBarma <tarun.kanti@ti.com> writes:
>>
>> > This series is continuation of cleanup of OMAP GPIO driver and fixes.
>>
>> Please also Cc the linux-arm-kernel mailing list for OMAP patches
>> targetted for upstream.
>
> Sure, in my v4 posting I will do that!
>

And also, change all subject prefixes to 'gpio/omap: ...' as requested
by GPIO maintainer.

Kevin

RE: [PATCH v3 00/20] GPIO: OMAP: driver cleanup and fixes

[DebBarma, Tarun Kanti]

[...]
> 
> And also, change all subject prefixes to 'gpio/omap: ...' as requested
> by GPIO maintainer.
Ok.
> 
> Kevin