* [PATCH 1/5] OMAP: DSS2: DISPC: Prepare dispc_dump_regs() for shortening
2011-08-05 7:42 [PATCH 0/5] OMAP: DSS2: Miscellaneous DISPC Patches Archit Taneja
@ 2011-08-05 7:42 ` Archit Taneja
2011-08-05 7:42 ` [PATCH 2/5] OMAP: DSS2: DISPC: Shorten dispc_dump_regs() Archit Taneja
` (3 subsequent siblings)
4 siblings, 0 replies; 10+ messages in thread
From: Archit Taneja @ 2011-08-05 7:42 UTC (permalink / raw)
To: tomi.valkeinen; +Cc: linux-omap, Archit Taneja
Prepare dispc_dump_regs() to iterate over manager and overlay id's. Doing this
requires modifications of the macro "DUMPREG" which currently needs us to specify
the manager/overlay name to get the correct result. For example, in order to
print the register DISPC_TIMING_H(OMAP_DSS_CHANNEL_LCD), we can't iterate over
a varaible i and get the desired result through DUMPREG(DISPC_TIMING_H(i)).
Split the registers into 3 sections, the first with no arguments(common
registers), the second with one argument(manager/overlay id), and the third with
two arguments(overlay id and coefficient index), redefine DUMPREG macros for
each of these.
Signed-off-by: Archit Taneja <archit@ti.com>
---
drivers/video/omap2/dss/dispc.c | 444 +++++++++++++++++++++------------------
1 files changed, 239 insertions(+), 205 deletions(-)
diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
index d849fa0..cdb53aa 100644
--- a/drivers/video/omap2/dss/dispc.c
+++ b/drivers/video/omap2/dss/dispc.c
@@ -2712,6 +2712,7 @@ void dispc_dump_regs(struct seq_file *s)
if (dispc_runtime_get())
return;
+ /* DISPC common registers */
DUMPREG(DISPC_REVISION);
DUMPREG(DISPC_SYSCONFIG);
DUMPREG(DISPC_SYSSTATUS);
@@ -2720,242 +2721,275 @@ void dispc_dump_regs(struct seq_file *s)
DUMPREG(DISPC_CONTROL);
DUMPREG(DISPC_CONFIG);
DUMPREG(DISPC_CAPABLE);
- DUMPREG(DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD));
- DUMPREG(DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_DIGIT));
- DUMPREG(DISPC_TRANS_COLOR(OMAP_DSS_CHANNEL_LCD));
- DUMPREG(DISPC_TRANS_COLOR(OMAP_DSS_CHANNEL_DIGIT));
DUMPREG(DISPC_LINE_STATUS);
DUMPREG(DISPC_LINE_NUMBER);
- DUMPREG(DISPC_TIMING_H(OMAP_DSS_CHANNEL_LCD));
- DUMPREG(DISPC_TIMING_V(OMAP_DSS_CHANNEL_LCD));
- DUMPREG(DISPC_POL_FREQ(OMAP_DSS_CHANNEL_LCD));
- DUMPREG(DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD));
if (dss_has_feature(FEAT_GLOBAL_ALPHA))
DUMPREG(DISPC_GLOBAL_ALPHA);
- DUMPREG(DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT));
- DUMPREG(DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_LCD));
if (dss_has_feature(FEAT_MGR_LCD2)) {
DUMPREG(DISPC_CONTROL2);
DUMPREG(DISPC_CONFIG2);
- DUMPREG(DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD2));
- DUMPREG(DISPC_TRANS_COLOR(OMAP_DSS_CHANNEL_LCD2));
- DUMPREG(DISPC_TIMING_H(OMAP_DSS_CHANNEL_LCD2));
- DUMPREG(DISPC_TIMING_V(OMAP_DSS_CHANNEL_LCD2));
- DUMPREG(DISPC_POL_FREQ(OMAP_DSS_CHANNEL_LCD2));
- DUMPREG(DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD2));
- DUMPREG(DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_LCD2));
- }
-
- DUMPREG(DISPC_OVL_BA0(OMAP_DSS_GFX));
- DUMPREG(DISPC_OVL_BA1(OMAP_DSS_GFX));
- DUMPREG(DISPC_OVL_POSITION(OMAP_DSS_GFX));
- DUMPREG(DISPC_OVL_SIZE(OMAP_DSS_GFX));
- DUMPREG(DISPC_OVL_ATTRIBUTES(OMAP_DSS_GFX));
- DUMPREG(DISPC_OVL_FIFO_THRESHOLD(OMAP_DSS_GFX));
- DUMPREG(DISPC_OVL_FIFO_SIZE_STATUS(OMAP_DSS_GFX));
- DUMPREG(DISPC_OVL_ROW_INC(OMAP_DSS_GFX));
- DUMPREG(DISPC_OVL_PIXEL_INC(OMAP_DSS_GFX));
- DUMPREG(DISPC_OVL_WINDOW_SKIP(OMAP_DSS_GFX));
- DUMPREG(DISPC_OVL_TABLE_BA(OMAP_DSS_GFX));
-
- DUMPREG(DISPC_DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD));
- DUMPREG(DISPC_DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD));
- DUMPREG(DISPC_DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD));
+ }
+
+#undef DUMPREG
+
+#define DISPC_REG(i, name) name(i)
+#define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, #i, \
+ 48 - strlen(#r) - strlen(#i), " ", \
+ dispc_read_reg(DISPC_REG(i, r)))
+
+ /* LCD registers */
+ DUMPREG(OMAP_DSS_CHANNEL_LCD, DISPC_DEFAULT_COLOR);
+ DUMPREG(OMAP_DSS_CHANNEL_LCD, DISPC_TRANS_COLOR);
+ DUMPREG(OMAP_DSS_CHANNEL_LCD, DISPC_TIMING_H);
+ DUMPREG(OMAP_DSS_CHANNEL_LCD, DISPC_TIMING_V);
+ DUMPREG(OMAP_DSS_CHANNEL_LCD, DISPC_POL_FREQ);
+ DUMPREG(OMAP_DSS_CHANNEL_LCD, DISPC_DIVISORo);
+ DUMPREG(OMAP_DSS_CHANNEL_LCD, DISPC_SIZE_MGR);
+
+ DUMPREG(OMAP_DSS_CHANNEL_LCD, DISPC_DATA_CYCLE1);
+ DUMPREG(OMAP_DSS_CHANNEL_LCD, DISPC_DATA_CYCLE2);
+ DUMPREG(OMAP_DSS_CHANNEL_LCD, DISPC_DATA_CYCLE3);
if (dss_has_feature(FEAT_CPR)) {
- DUMPREG(DISPC_CPR_COEF_R(OMAP_DSS_CHANNEL_LCD));
- DUMPREG(DISPC_CPR_COEF_G(OMAP_DSS_CHANNEL_LCD));
- DUMPREG(DISPC_CPR_COEF_B(OMAP_DSS_CHANNEL_LCD));
+ DUMPREG(OMAP_DSS_CHANNEL_LCD, DISPC_CPR_COEF_R);
+ DUMPREG(OMAP_DSS_CHANNEL_LCD, DISPC_CPR_COEF_G);
+ DUMPREG(OMAP_DSS_CHANNEL_LCD, DISPC_CPR_COEF_B);
}
+
+ /* DIGIT registers */
+ DUMPREG(OMAP_DSS_CHANNEL_DIGIT, DISPC_DEFAULT_COLOR);
+ DUMPREG(OMAP_DSS_CHANNEL_DIGIT, DISPC_TRANS_COLOR);
+ DUMPREG(OMAP_DSS_CHANNEL_DIGIT, DISPC_SIZE_MGR);
+
+ /* LCD2 registers */
if (dss_has_feature(FEAT_MGR_LCD2)) {
- DUMPREG(DISPC_DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD2));
- DUMPREG(DISPC_DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD2));
- DUMPREG(DISPC_DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD2));
+ DUMPREG(OMAP_DSS_CHANNEL_LCD2, DISPC_DEFAULT_COLOR);
+ DUMPREG(OMAP_DSS_CHANNEL_LCD2, DISPC_TRANS_COLOR);
+ DUMPREG(OMAP_DSS_CHANNEL_LCD2, DISPC_TIMING_H);
+ DUMPREG(OMAP_DSS_CHANNEL_LCD2, DISPC_TIMING_V);
+ DUMPREG(OMAP_DSS_CHANNEL_LCD2, DISPC_POL_FREQ);
+ DUMPREG(OMAP_DSS_CHANNEL_LCD2, DISPC_DIVISORo);
+ DUMPREG(OMAP_DSS_CHANNEL_LCD2, DISPC_SIZE_MGR);
+
+ DUMPREG(OMAP_DSS_CHANNEL_LCD2, DISPC_DATA_CYCLE1);
+ DUMPREG(OMAP_DSS_CHANNEL_LCD2, DISPC_DATA_CYCLE2);
+ DUMPREG(OMAP_DSS_CHANNEL_LCD2, DISPC_DATA_CYCLE3);
if (dss_has_feature(FEAT_CPR)) {
- DUMPREG(DISPC_CPR_COEF_R(OMAP_DSS_CHANNEL_LCD2));
- DUMPREG(DISPC_CPR_COEF_G(OMAP_DSS_CHANNEL_LCD2));
- DUMPREG(DISPC_CPR_COEF_B(OMAP_DSS_CHANNEL_LCD2));
+ DUMPREG(OMAP_DSS_CHANNEL_LCD2, DISPC_CPR_COEF_R);
+ DUMPREG(OMAP_DSS_CHANNEL_LCD2, DISPC_CPR_COEF_G);
+ DUMPREG(OMAP_DSS_CHANNEL_LCD2, DISPC_CPR_COEF_B);
}
}
+ /* GFX registers */
+ DUMPREG(OMAP_DSS_GFX, DISPC_OVL_BA0);
+ DUMPREG(OMAP_DSS_GFX, DISPC_OVL_BA1);
+ DUMPREG(OMAP_DSS_GFX, DISPC_OVL_POSITION);
+ DUMPREG(OMAP_DSS_GFX, DISPC_OVL_SIZE);
+ DUMPREG(OMAP_DSS_GFX, DISPC_OVL_ATTRIBUTES);
+ DUMPREG(OMAP_DSS_GFX, DISPC_OVL_FIFO_THRESHOLD);
+ DUMPREG(OMAP_DSS_GFX, DISPC_OVL_FIFO_SIZE_STATUS);
+ DUMPREG(OMAP_DSS_GFX, DISPC_OVL_ROW_INC);
+ DUMPREG(OMAP_DSS_GFX, DISPC_OVL_PIXEL_INC);
+ DUMPREG(OMAP_DSS_GFX, DISPC_OVL_WINDOW_SKIP);
+ DUMPREG(OMAP_DSS_GFX, DISPC_OVL_TABLE_BA);
if (dss_has_feature(FEAT_PRELOAD))
- DUMPREG(DISPC_OVL_PRELOAD(OMAP_DSS_GFX));
-
- DUMPREG(DISPC_OVL_BA0(OMAP_DSS_VIDEO1));
- DUMPREG(DISPC_OVL_BA1(OMAP_DSS_VIDEO1));
- DUMPREG(DISPC_OVL_POSITION(OMAP_DSS_VIDEO1));
- DUMPREG(DISPC_OVL_SIZE(OMAP_DSS_VIDEO1));
- DUMPREG(DISPC_OVL_ATTRIBUTES(OMAP_DSS_VIDEO1));
- DUMPREG(DISPC_OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO1));
- DUMPREG(DISPC_OVL_FIFO_SIZE_STATUS(OMAP_DSS_VIDEO1));
- DUMPREG(DISPC_OVL_ROW_INC(OMAP_DSS_VIDEO1));
- DUMPREG(DISPC_OVL_PIXEL_INC(OMAP_DSS_VIDEO1));
- DUMPREG(DISPC_OVL_FIR(OMAP_DSS_VIDEO1));
- DUMPREG(DISPC_OVL_PICTURE_SIZE(OMAP_DSS_VIDEO1));
- DUMPREG(DISPC_OVL_ACCU0(OMAP_DSS_VIDEO1));
- DUMPREG(DISPC_OVL_ACCU1(OMAP_DSS_VIDEO1));
-
- DUMPREG(DISPC_OVL_BA0(OMAP_DSS_VIDEO2));
- DUMPREG(DISPC_OVL_BA1(OMAP_DSS_VIDEO2));
- DUMPREG(DISPC_OVL_POSITION(OMAP_DSS_VIDEO2));
- DUMPREG(DISPC_OVL_SIZE(OMAP_DSS_VIDEO2));
- DUMPREG(DISPC_OVL_ATTRIBUTES(OMAP_DSS_VIDEO2));
- DUMPREG(DISPC_OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO2));
- DUMPREG(DISPC_OVL_FIFO_SIZE_STATUS(OMAP_DSS_VIDEO2));
- DUMPREG(DISPC_OVL_ROW_INC(OMAP_DSS_VIDEO2));
- DUMPREG(DISPC_OVL_PIXEL_INC(OMAP_DSS_VIDEO2));
- DUMPREG(DISPC_OVL_FIR(OMAP_DSS_VIDEO2));
- DUMPREG(DISPC_OVL_PICTURE_SIZE(OMAP_DSS_VIDEO2));
- DUMPREG(DISPC_OVL_ACCU0(OMAP_DSS_VIDEO2));
- DUMPREG(DISPC_OVL_ACCU1(OMAP_DSS_VIDEO2));
-
- DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 0));
- DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 1));
- DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 2));
- DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 3));
- DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 4));
- DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 5));
- DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 6));
- DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 7));
- DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 0));
- DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 1));
- DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 2));
- DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 3));
- DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 4));
- DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 5));
- DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 6));
- DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 7));
- DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 0));
- DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 1));
- DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 2));
- DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 3));
- DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 4));
- if (dss_has_feature(FEAT_FIR_COEF_V)) {
- DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 0));
- DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 1));
- DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 2));
- DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 3));
- DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 4));
- DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 5));
- DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 6));
- DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 7));
+ DUMPREG(OMAP_DSS_GFX, DISPC_OVL_PRELOAD);
+
+ /* VIDEO1 registers */
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_BA0);
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_BA1);
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_POSITION);
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_SIZE);
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_ATTRIBUTES);
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIFO_THRESHOLD);
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIFO_SIZE_STATUS);
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_ROW_INC);
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_PIXEL_INC);
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR);
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_PICTURE_SIZE);
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_ACCU0);
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_ACCU1);
+ if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_BA0_UV);
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_BA1_UV);
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR2);
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_ACCU2_0);
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_ACCU2_1);
}
-
+ if (dss_has_feature(FEAT_ATTR2))
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_ATTRIBUTES2);
+ if (dss_has_feature(FEAT_PRELOAD))
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_PRELOAD);
+
+ /* VIDEO2 registers */
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_BA0);
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_BA1);
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_POSITION);
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_SIZE);
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_ATTRIBUTES);
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIFO_THRESHOLD);
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIFO_SIZE_STATUS);
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_ROW_INC);
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_PIXEL_INC);
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR);
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_PICTURE_SIZE);
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_ACCU0);
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_ACCU1);
if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
- DUMPREG(DISPC_OVL_BA0_UV(OMAP_DSS_VIDEO1));
- DUMPREG(DISPC_OVL_BA1_UV(OMAP_DSS_VIDEO1));
- DUMPREG(DISPC_OVL_FIR2(OMAP_DSS_VIDEO1));
- DUMPREG(DISPC_OVL_ACCU2_0(OMAP_DSS_VIDEO1));
- DUMPREG(DISPC_OVL_ACCU2_1(OMAP_DSS_VIDEO1));
-
- DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 0));
- DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 1));
- DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 2));
- DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 3));
- DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 4));
- DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 5));
- DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 6));
- DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 7));
-
- DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 0));
- DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 1));
- DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 2));
- DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 3));
- DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 4));
- DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 5));
- DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 6));
- DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 7));
-
- DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 0));
- DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 1));
- DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 2));
- DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 3));
- DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 4));
- DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 5));
- DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 6));
- DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 7));
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_BA0_UV);
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_BA1_UV);
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR2);
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_ACCU2_0);
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_ACCU2_1);
}
if (dss_has_feature(FEAT_ATTR2))
- DUMPREG(DISPC_OVL_ATTRIBUTES2(OMAP_DSS_VIDEO1));
-
-
- DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 0));
- DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 1));
- DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 2));
- DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 3));
- DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 4));
- DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 5));
- DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 6));
- DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 7));
- DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 0));
- DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 1));
- DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 2));
- DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 3));
- DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 4));
- DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 5));
- DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 6));
- DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 7));
- DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 0));
- DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 1));
- DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 2));
- DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 3));
- DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 4));
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_ATTRIBUTES2);
+ if (dss_has_feature(FEAT_PRELOAD))
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_PRELOAD);
+
+#undef DISPC_REG
+#undef DUMPREG
+
+#define DISPC_REG(plane, name, i) name(plane, i)
+#define DUMPREG(plane, name, i) \
+ seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, #plane, \
+ 46 - strlen(#name) - strlen(#plane), " ", \
+ dispc_read_reg(DISPC_REG(plane, name, i)))
+
+ /* VIDEO1 coefficient registers */
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_H, 0);
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_H, 1);
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_H, 2);
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_H, 3);
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_H, 4);
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_H, 5);
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_H, 6);
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_H, 7);
+
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_HV, 0);
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_HV, 1);
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_HV, 2);
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_HV, 3);
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_HV, 4);
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_HV, 5);
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_HV, 6);
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_HV, 7);
+
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_CONV_COEF, 0);
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_CONV_COEF, 1);
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_CONV_COEF, 2);
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_CONV_COEF, 3);
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_CONV_COEF, 4);
if (dss_has_feature(FEAT_FIR_COEF_V)) {
- DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 0));
- DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 1));
- DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 2));
- DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 3));
- DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 4));
- DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 5));
- DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 6));
- DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 7));
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_V, 0);
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_V, 1);
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_V, 2);
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_V, 3);
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_V, 4);
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_V, 5);
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_V, 6);
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_V, 7);
}
if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
- DUMPREG(DISPC_OVL_BA0_UV(OMAP_DSS_VIDEO2));
- DUMPREG(DISPC_OVL_BA1_UV(OMAP_DSS_VIDEO2));
- DUMPREG(DISPC_OVL_FIR2(OMAP_DSS_VIDEO2));
- DUMPREG(DISPC_OVL_ACCU2_0(OMAP_DSS_VIDEO2));
- DUMPREG(DISPC_OVL_ACCU2_1(OMAP_DSS_VIDEO2));
-
- DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 0));
- DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 1));
- DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 2));
- DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 3));
- DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 4));
- DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 5));
- DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 6));
- DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 7));
-
- DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 0));
- DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 1));
- DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 2));
- DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 3));
- DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 4));
- DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 5));
- DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 6));
- DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 7));
-
- DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 0));
- DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 1));
- DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 2));
- DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 3));
- DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 4));
- DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 5));
- DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 6));
- DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 7));
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_H2, 0);
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_H2, 1);
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_H2, 2);
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_H2, 3);
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_H2, 4);
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_H2, 5);
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_H2, 6);
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_H2, 7);
+
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_HV2, 0);
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_HV2, 1);
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_HV2, 2);
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_HV2, 3);
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_HV2, 4);
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_HV2, 5);
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_HV2, 6);
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_HV2, 7);
+
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_V2, 0);
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_V2, 1);
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_V2, 2);
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_V2, 3);
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_V2, 4);
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_V2, 5);
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_V2, 6);
+ DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_V2, 7);
+ }
+
+ /* VIDEO2 coefficient registers */
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_H, 0);
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_H, 1);
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_H, 2);
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_H, 3);
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_H, 4);
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_H, 5);
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_H, 6);
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_H, 7);
+
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_HV, 0);
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_HV, 1);
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_HV, 2);
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_HV, 3);
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_HV, 4);
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_HV, 5);
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_HV, 6);
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_HV, 7);
+
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_CONV_COEF, 0);
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_CONV_COEF, 1);
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_CONV_COEF, 2);
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_CONV_COEF, 3);
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_CONV_COEF, 4);
+ if (dss_has_feature(FEAT_FIR_COEF_V)) {
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_V, 0);
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_V, 1);
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_V, 2);
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_V, 3);
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_V, 4);
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_V, 5);
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_V, 6);
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_V, 7);
}
- if (dss_has_feature(FEAT_ATTR2))
- DUMPREG(DISPC_OVL_ATTRIBUTES2(OMAP_DSS_VIDEO2));
- if (dss_has_feature(FEAT_PRELOAD)) {
- DUMPREG(DISPC_OVL_PRELOAD(OMAP_DSS_VIDEO1));
- DUMPREG(DISPC_OVL_PRELOAD(OMAP_DSS_VIDEO2));
+ if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_H2, 0);
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_H2, 1);
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_H2, 2);
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_H2, 3);
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_H2, 4);
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_H2, 5);
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_H2, 6);
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_H2, 7);
+
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_HV2, 0);
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_HV2, 1);
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_HV2, 2);
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_HV2, 3);
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_HV2, 4);
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_HV2, 5);
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_HV2, 6);
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_HV2, 7);
+
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_V2, 0);
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_V2, 1);
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_V2, 2);
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_V2, 3);
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_V2, 4);
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_V2, 5);
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_V2, 6);
+ DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_V2, 7);
}
dispc_runtime_put();
+
+#undef DISPC_REG
#undef DUMPREG
}
--
1.7.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH 2/5] OMAP: DSS2: DISPC: Shorten dispc_dump_regs()
2011-08-05 7:42 [PATCH 0/5] OMAP: DSS2: Miscellaneous DISPC Patches Archit Taneja
2011-08-05 7:42 ` [PATCH 1/5] OMAP: DSS2: DISPC: Prepare dispc_dump_regs() for shortening Archit Taneja
@ 2011-08-05 7:42 ` Archit Taneja
2011-08-05 7:42 ` [PATCH 3/5] OMAP: DSS2: DISPC: dispc_save_context() and dispc_restore_context() cleanup Archit Taneja
` (2 subsequent siblings)
4 siblings, 0 replies; 10+ messages in thread
From: Archit Taneja @ 2011-08-05 7:42 UTC (permalink / raw)
To: tomi.valkeinen; +Cc: linux-omap, Archit Taneja
Iterate over manager and overlay id's to shorten dispc_dump_regs().
Signed-off-by: Archit Taneja <archit@ti.com>
---
drivers/video/omap2/dss/dispc.c | 326 ++++++++++++---------------------------
1 files changed, 98 insertions(+), 228 deletions(-)
diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
index cdb53aa..bdd24a2 100644
--- a/drivers/video/omap2/dss/dispc.c
+++ b/drivers/video/omap2/dss/dispc.c
@@ -2707,6 +2707,19 @@ void dispc_dump_irqs(struct seq_file *s)
void dispc_dump_regs(struct seq_file *s)
{
+ int i, j;
+ const char *mgr_names[] = {
+ [OMAP_DSS_CHANNEL_LCD] = "LCD",
+ [OMAP_DSS_CHANNEL_DIGIT] = "TV",
+ [OMAP_DSS_CHANNEL_LCD2] = "LCD2",
+ };
+ const char *ovl_names[] = {
+ [OMAP_DSS_GFX] = "GFX",
+ [OMAP_DSS_VIDEO1] = "VID1",
+ [OMAP_DSS_VIDEO2] = "VID2",
+ };
+ const char **p_names;
+
#define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
if (dispc_runtime_get())
@@ -2733,258 +2746,115 @@ void dispc_dump_regs(struct seq_file *s)
#undef DUMPREG
#define DISPC_REG(i, name) name(i)
-#define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, #i, \
- 48 - strlen(#r) - strlen(#i), " ", \
+#define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
+ 48 - strlen(#r) - strlen(p_names[i]), " ", \
dispc_read_reg(DISPC_REG(i, r)))
- /* LCD registers */
- DUMPREG(OMAP_DSS_CHANNEL_LCD, DISPC_DEFAULT_COLOR);
- DUMPREG(OMAP_DSS_CHANNEL_LCD, DISPC_TRANS_COLOR);
- DUMPREG(OMAP_DSS_CHANNEL_LCD, DISPC_TIMING_H);
- DUMPREG(OMAP_DSS_CHANNEL_LCD, DISPC_TIMING_V);
- DUMPREG(OMAP_DSS_CHANNEL_LCD, DISPC_POL_FREQ);
- DUMPREG(OMAP_DSS_CHANNEL_LCD, DISPC_DIVISORo);
- DUMPREG(OMAP_DSS_CHANNEL_LCD, DISPC_SIZE_MGR);
+ p_names = mgr_names;
- DUMPREG(OMAP_DSS_CHANNEL_LCD, DISPC_DATA_CYCLE1);
- DUMPREG(OMAP_DSS_CHANNEL_LCD, DISPC_DATA_CYCLE2);
- DUMPREG(OMAP_DSS_CHANNEL_LCD, DISPC_DATA_CYCLE3);
+ /* DISPC channel specific registers */
+ for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
+ DUMPREG(i, DISPC_DEFAULT_COLOR);
+ DUMPREG(i, DISPC_TRANS_COLOR);
+ DUMPREG(i, DISPC_SIZE_MGR);
- if (dss_has_feature(FEAT_CPR)) {
- DUMPREG(OMAP_DSS_CHANNEL_LCD, DISPC_CPR_COEF_R);
- DUMPREG(OMAP_DSS_CHANNEL_LCD, DISPC_CPR_COEF_G);
- DUMPREG(OMAP_DSS_CHANNEL_LCD, DISPC_CPR_COEF_B);
- }
+ if (i == OMAP_DSS_CHANNEL_DIGIT)
+ continue;
- /* DIGIT registers */
- DUMPREG(OMAP_DSS_CHANNEL_DIGIT, DISPC_DEFAULT_COLOR);
- DUMPREG(OMAP_DSS_CHANNEL_DIGIT, DISPC_TRANS_COLOR);
- DUMPREG(OMAP_DSS_CHANNEL_DIGIT, DISPC_SIZE_MGR);
+ DUMPREG(i, DISPC_DEFAULT_COLOR);
+ DUMPREG(i, DISPC_TRANS_COLOR);
+ DUMPREG(i, DISPC_TIMING_H);
+ DUMPREG(i, DISPC_TIMING_V);
+ DUMPREG(i, DISPC_POL_FREQ);
+ DUMPREG(i, DISPC_DIVISORo);
+ DUMPREG(i, DISPC_SIZE_MGR);
- /* LCD2 registers */
- if (dss_has_feature(FEAT_MGR_LCD2)) {
- DUMPREG(OMAP_DSS_CHANNEL_LCD2, DISPC_DEFAULT_COLOR);
- DUMPREG(OMAP_DSS_CHANNEL_LCD2, DISPC_TRANS_COLOR);
- DUMPREG(OMAP_DSS_CHANNEL_LCD2, DISPC_TIMING_H);
- DUMPREG(OMAP_DSS_CHANNEL_LCD2, DISPC_TIMING_V);
- DUMPREG(OMAP_DSS_CHANNEL_LCD2, DISPC_POL_FREQ);
- DUMPREG(OMAP_DSS_CHANNEL_LCD2, DISPC_DIVISORo);
- DUMPREG(OMAP_DSS_CHANNEL_LCD2, DISPC_SIZE_MGR);
-
- DUMPREG(OMAP_DSS_CHANNEL_LCD2, DISPC_DATA_CYCLE1);
- DUMPREG(OMAP_DSS_CHANNEL_LCD2, DISPC_DATA_CYCLE2);
- DUMPREG(OMAP_DSS_CHANNEL_LCD2, DISPC_DATA_CYCLE3);
+ DUMPREG(i, DISPC_DATA_CYCLE1);
+ DUMPREG(i, DISPC_DATA_CYCLE2);
+ DUMPREG(i, DISPC_DATA_CYCLE3);
if (dss_has_feature(FEAT_CPR)) {
- DUMPREG(OMAP_DSS_CHANNEL_LCD2, DISPC_CPR_COEF_R);
- DUMPREG(OMAP_DSS_CHANNEL_LCD2, DISPC_CPR_COEF_G);
- DUMPREG(OMAP_DSS_CHANNEL_LCD2, DISPC_CPR_COEF_B);
+ DUMPREG(i, DISPC_CPR_COEF_R);
+ DUMPREG(i, DISPC_CPR_COEF_G);
+ DUMPREG(i, DISPC_CPR_COEF_B);
}
}
- /* GFX registers */
- DUMPREG(OMAP_DSS_GFX, DISPC_OVL_BA0);
- DUMPREG(OMAP_DSS_GFX, DISPC_OVL_BA1);
- DUMPREG(OMAP_DSS_GFX, DISPC_OVL_POSITION);
- DUMPREG(OMAP_DSS_GFX, DISPC_OVL_SIZE);
- DUMPREG(OMAP_DSS_GFX, DISPC_OVL_ATTRIBUTES);
- DUMPREG(OMAP_DSS_GFX, DISPC_OVL_FIFO_THRESHOLD);
- DUMPREG(OMAP_DSS_GFX, DISPC_OVL_FIFO_SIZE_STATUS);
- DUMPREG(OMAP_DSS_GFX, DISPC_OVL_ROW_INC);
- DUMPREG(OMAP_DSS_GFX, DISPC_OVL_PIXEL_INC);
- DUMPREG(OMAP_DSS_GFX, DISPC_OVL_WINDOW_SKIP);
- DUMPREG(OMAP_DSS_GFX, DISPC_OVL_TABLE_BA);
- if (dss_has_feature(FEAT_PRELOAD))
- DUMPREG(OMAP_DSS_GFX, DISPC_OVL_PRELOAD);
-
- /* VIDEO1 registers */
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_BA0);
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_BA1);
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_POSITION);
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_SIZE);
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_ATTRIBUTES);
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIFO_THRESHOLD);
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIFO_SIZE_STATUS);
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_ROW_INC);
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_PIXEL_INC);
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR);
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_PICTURE_SIZE);
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_ACCU0);
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_ACCU1);
- if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_BA0_UV);
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_BA1_UV);
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR2);
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_ACCU2_0);
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_ACCU2_1);
- }
- if (dss_has_feature(FEAT_ATTR2))
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_ATTRIBUTES2);
- if (dss_has_feature(FEAT_PRELOAD))
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_PRELOAD);
-
- /* VIDEO2 registers */
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_BA0);
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_BA1);
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_POSITION);
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_SIZE);
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_ATTRIBUTES);
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIFO_THRESHOLD);
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIFO_SIZE_STATUS);
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_ROW_INC);
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_PIXEL_INC);
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR);
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_PICTURE_SIZE);
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_ACCU0);
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_ACCU1);
- if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_BA0_UV);
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_BA1_UV);
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR2);
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_ACCU2_0);
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_ACCU2_1);
+ p_names = ovl_names;
+
+ for (i = 0; i < dss_feat_get_num_ovls(); i++) {
+ DUMPREG(i, DISPC_OVL_BA0);
+ DUMPREG(i, DISPC_OVL_BA1);
+ DUMPREG(i, DISPC_OVL_POSITION);
+ DUMPREG(i, DISPC_OVL_SIZE);
+ DUMPREG(i, DISPC_OVL_ATTRIBUTES);
+ DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
+ DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
+ DUMPREG(i, DISPC_OVL_ROW_INC);
+ DUMPREG(i, DISPC_OVL_PIXEL_INC);
+ if (dss_has_feature(FEAT_PRELOAD))
+ DUMPREG(i, DISPC_OVL_PRELOAD);
+
+ if (i == OMAP_DSS_GFX) {
+ DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
+ DUMPREG(i, DISPC_OVL_TABLE_BA);
+ continue;
+ }
+
+ DUMPREG(i, DISPC_OVL_FIR);
+ DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
+ DUMPREG(i, DISPC_OVL_ACCU0);
+ DUMPREG(i, DISPC_OVL_ACCU1);
+ if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
+ DUMPREG(i, DISPC_OVL_BA0_UV);
+ DUMPREG(i, DISPC_OVL_BA1_UV);
+ DUMPREG(i, DISPC_OVL_FIR2);
+ DUMPREG(i, DISPC_OVL_ACCU2_0);
+ DUMPREG(i, DISPC_OVL_ACCU2_1);
+ }
+ if (dss_has_feature(FEAT_ATTR2))
+ DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
+ if (dss_has_feature(FEAT_PRELOAD))
+ DUMPREG(i, DISPC_OVL_PRELOAD);
}
- if (dss_has_feature(FEAT_ATTR2))
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_ATTRIBUTES2);
- if (dss_has_feature(FEAT_PRELOAD))
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_PRELOAD);
#undef DISPC_REG
#undef DUMPREG
#define DISPC_REG(plane, name, i) name(plane, i)
#define DUMPREG(plane, name, i) \
- seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, #plane, \
- 46 - strlen(#name) - strlen(#plane), " ", \
+ seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
+ 46 - strlen(#name) - strlen(p_names[plane]), " ", \
dispc_read_reg(DISPC_REG(plane, name, i)))
- /* VIDEO1 coefficient registers */
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_H, 0);
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_H, 1);
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_H, 2);
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_H, 3);
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_H, 4);
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_H, 5);
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_H, 6);
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_H, 7);
-
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_HV, 0);
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_HV, 1);
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_HV, 2);
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_HV, 3);
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_HV, 4);
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_HV, 5);
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_HV, 6);
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_HV, 7);
-
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_CONV_COEF, 0);
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_CONV_COEF, 1);
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_CONV_COEF, 2);
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_CONV_COEF, 3);
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_CONV_COEF, 4);
+ /* Video pipeline coefficient registers */
- if (dss_has_feature(FEAT_FIR_COEF_V)) {
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_V, 0);
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_V, 1);
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_V, 2);
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_V, 3);
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_V, 4);
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_V, 5);
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_V, 6);
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_V, 7);
- }
+ /* start from OMAP_DSS_VIDEO1 */
+ for (i = 1; i < dss_feat_get_num_ovls(); i++) {
+ for (j = 0; j < 8; j++)
+ DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
- if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_H2, 0);
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_H2, 1);
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_H2, 2);
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_H2, 3);
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_H2, 4);
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_H2, 5);
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_H2, 6);
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_H2, 7);
-
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_HV2, 0);
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_HV2, 1);
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_HV2, 2);
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_HV2, 3);
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_HV2, 4);
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_HV2, 5);
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_HV2, 6);
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_HV2, 7);
-
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_V2, 0);
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_V2, 1);
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_V2, 2);
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_V2, 3);
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_V2, 4);
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_V2, 5);
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_V2, 6);
- DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_V2, 7);
- }
-
- /* VIDEO2 coefficient registers */
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_H, 0);
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_H, 1);
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_H, 2);
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_H, 3);
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_H, 4);
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_H, 5);
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_H, 6);
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_H, 7);
-
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_HV, 0);
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_HV, 1);
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_HV, 2);
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_HV, 3);
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_HV, 4);
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_HV, 5);
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_HV, 6);
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_HV, 7);
-
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_CONV_COEF, 0);
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_CONV_COEF, 1);
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_CONV_COEF, 2);
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_CONV_COEF, 3);
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_CONV_COEF, 4);
- if (dss_has_feature(FEAT_FIR_COEF_V)) {
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_V, 0);
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_V, 1);
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_V, 2);
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_V, 3);
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_V, 4);
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_V, 5);
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_V, 6);
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_V, 7);
- }
+ for (j = 0; j < 8; j++)
+ DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
- if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_H2, 0);
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_H2, 1);
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_H2, 2);
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_H2, 3);
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_H2, 4);
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_H2, 5);
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_H2, 6);
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_H2, 7);
-
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_HV2, 0);
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_HV2, 1);
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_HV2, 2);
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_HV2, 3);
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_HV2, 4);
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_HV2, 5);
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_HV2, 6);
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_HV2, 7);
-
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_V2, 0);
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_V2, 1);
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_V2, 2);
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_V2, 3);
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_V2, 4);
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_V2, 5);
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_V2, 6);
- DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_V2, 7);
+ for (j = 0; j < 5; j++)
+ DUMPREG(i, DISPC_OVL_CONV_COEF, j);
+
+ if (dss_has_feature(FEAT_FIR_COEF_V)) {
+ for (j = 0; j < 8; j++)
+ DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
+ }
+
+ if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
+ for (j = 0; j < 8; j++)
+ DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
+
+ for (j = 0; j < 8; j++)
+ DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
+
+ for (j = 0; j < 8; j++)
+ DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
+ }
}
dispc_runtime_put();
--
1.7.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH 3/5] OMAP: DSS2: DISPC: dispc_save_context() and dispc_restore_context() cleanup
2011-08-05 7:42 [PATCH 0/5] OMAP: DSS2: Miscellaneous DISPC Patches Archit Taneja
2011-08-05 7:42 ` [PATCH 1/5] OMAP: DSS2: DISPC: Prepare dispc_dump_regs() for shortening Archit Taneja
2011-08-05 7:42 ` [PATCH 2/5] OMAP: DSS2: DISPC: Shorten dispc_dump_regs() Archit Taneja
@ 2011-08-05 7:42 ` Archit Taneja
2011-08-05 7:42 ` [PATCH 4/5] OMAP: DSS2: DISPC: Shorten _dispc_set_color_conv_coef() Archit Taneja
2011-08-05 7:42 ` [PATCH 5/5] OMAP4: DSS2: VIDEO3 pipeline support Archit Taneja
4 siblings, 0 replies; 10+ messages in thread
From: Archit Taneja @ 2011-08-05 7:42 UTC (permalink / raw)
To: tomi.valkeinen; +Cc: linux-omap, Archit Taneja
Iterate over manager and overlay id's to shorten dispc_save_context() and
dispc_restore_context().
Signed-off-by: Archit Taneja <archit@ti.com>
---
drivers/video/omap2/dss/dispc.c | 408 ++++++++++++---------------------------
1 files changed, 128 insertions(+), 280 deletions(-)
diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
index bdd24a2..2fd16ac 100644
--- a/drivers/video/omap2/dss/dispc.c
+++ b/drivers/video/omap2/dss/dispc.c
@@ -171,172 +171,97 @@ static int dispc_get_ctx_loss_count(void)
static void dispc_save_context(void)
{
- int i;
+ int i, j;
DSSDBG("dispc_save_context\n");
SR(IRQENABLE);
SR(CONTROL);
SR(CONFIG);
- SR(DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD));
- SR(DEFAULT_COLOR(OMAP_DSS_CHANNEL_DIGIT));
- SR(TRANS_COLOR(OMAP_DSS_CHANNEL_LCD));
- SR(TRANS_COLOR(OMAP_DSS_CHANNEL_DIGIT));
SR(LINE_NUMBER);
- SR(TIMING_H(OMAP_DSS_CHANNEL_LCD));
- SR(TIMING_V(OMAP_DSS_CHANNEL_LCD));
- SR(POL_FREQ(OMAP_DSS_CHANNEL_LCD));
- SR(DIVISORo(OMAP_DSS_CHANNEL_LCD));
if (dss_has_feature(FEAT_GLOBAL_ALPHA))
SR(GLOBAL_ALPHA);
- SR(SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT));
- SR(SIZE_MGR(OMAP_DSS_CHANNEL_LCD));
if (dss_has_feature(FEAT_MGR_LCD2)) {
SR(CONTROL2);
- SR(DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD2));
- SR(TRANS_COLOR(OMAP_DSS_CHANNEL_LCD2));
- SR(SIZE_MGR(OMAP_DSS_CHANNEL_LCD2));
- SR(TIMING_H(OMAP_DSS_CHANNEL_LCD2));
- SR(TIMING_V(OMAP_DSS_CHANNEL_LCD2));
- SR(POL_FREQ(OMAP_DSS_CHANNEL_LCD2));
- SR(DIVISORo(OMAP_DSS_CHANNEL_LCD2));
SR(CONFIG2);
}
- SR(OVL_BA0(OMAP_DSS_GFX));
- SR(OVL_BA1(OMAP_DSS_GFX));
- SR(OVL_POSITION(OMAP_DSS_GFX));
- SR(OVL_SIZE(OMAP_DSS_GFX));
- SR(OVL_ATTRIBUTES(OMAP_DSS_GFX));
- SR(OVL_FIFO_THRESHOLD(OMAP_DSS_GFX));
- SR(OVL_ROW_INC(OMAP_DSS_GFX));
- SR(OVL_PIXEL_INC(OMAP_DSS_GFX));
- SR(OVL_WINDOW_SKIP(OMAP_DSS_GFX));
- SR(OVL_TABLE_BA(OMAP_DSS_GFX));
+ for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
+ SR(DEFAULT_COLOR(i));
+ SR(TRANS_COLOR(i));
+ SR(SIZE_MGR(i));
+ if (i == OMAP_DSS_CHANNEL_DIGIT)
+ continue;
+ SR(TIMING_H(i));
+ SR(TIMING_V(i));
+ SR(POL_FREQ(i));
+ SR(DIVISORo(i));
- SR(DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD));
- SR(DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD));
- SR(DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD));
+ SR(DATA_CYCLE1(i));
+ SR(DATA_CYCLE2(i));
+ SR(DATA_CYCLE3(i));
- if (dss_has_feature(FEAT_CPR)) {
- SR(CPR_COEF_R(OMAP_DSS_CHANNEL_LCD));
- SR(CPR_COEF_G(OMAP_DSS_CHANNEL_LCD));
- SR(CPR_COEF_B(OMAP_DSS_CHANNEL_LCD));
- }
- if (dss_has_feature(FEAT_MGR_LCD2)) {
if (dss_has_feature(FEAT_CPR)) {
- SR(CPR_COEF_B(OMAP_DSS_CHANNEL_LCD2));
- SR(CPR_COEF_G(OMAP_DSS_CHANNEL_LCD2));
- SR(CPR_COEF_R(OMAP_DSS_CHANNEL_LCD2));
+ SR(CPR_COEF_R(i));
+ SR(CPR_COEF_G(i));
+ SR(CPR_COEF_B(i));
}
-
- SR(DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD2));
- SR(DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD2));
- SR(DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD2));
}
- if (dss_has_feature(FEAT_PRELOAD))
- SR(OVL_PRELOAD(OMAP_DSS_GFX));
-
- /* VID1 */
- SR(OVL_BA0(OMAP_DSS_VIDEO1));
- SR(OVL_BA1(OMAP_DSS_VIDEO1));
- SR(OVL_POSITION(OMAP_DSS_VIDEO1));
- SR(OVL_SIZE(OMAP_DSS_VIDEO1));
- SR(OVL_ATTRIBUTES(OMAP_DSS_VIDEO1));
- SR(OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO1));
- SR(OVL_ROW_INC(OMAP_DSS_VIDEO1));
- SR(OVL_PIXEL_INC(OMAP_DSS_VIDEO1));
- SR(OVL_FIR(OMAP_DSS_VIDEO1));
- SR(OVL_PICTURE_SIZE(OMAP_DSS_VIDEO1));
- SR(OVL_ACCU0(OMAP_DSS_VIDEO1));
- SR(OVL_ACCU1(OMAP_DSS_VIDEO1));
-
- for (i = 0; i < 8; i++)
- SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, i));
-
- for (i = 0; i < 8; i++)
- SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, i));
-
- for (i = 0; i < 5; i++)
- SR(OVL_CONV_COEF(OMAP_DSS_VIDEO1, i));
-
- if (dss_has_feature(FEAT_FIR_COEF_V)) {
- for (i = 0; i < 8; i++)
- SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, i));
- }
-
- if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
- SR(OVL_BA0_UV(OMAP_DSS_VIDEO1));
- SR(OVL_BA1_UV(OMAP_DSS_VIDEO1));
- SR(OVL_FIR2(OMAP_DSS_VIDEO1));
- SR(OVL_ACCU2_0(OMAP_DSS_VIDEO1));
- SR(OVL_ACCU2_1(OMAP_DSS_VIDEO1));
-
- for (i = 0; i < 8; i++)
- SR(OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, i));
-
- for (i = 0; i < 8; i++)
- SR(OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, i));
-
- for (i = 0; i < 8; i++)
- SR(OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, i));
- }
- if (dss_has_feature(FEAT_ATTR2))
- SR(OVL_ATTRIBUTES2(OMAP_DSS_VIDEO1));
-
- if (dss_has_feature(FEAT_PRELOAD))
- SR(OVL_PRELOAD(OMAP_DSS_VIDEO1));
-
- /* VID2 */
- SR(OVL_BA0(OMAP_DSS_VIDEO2));
- SR(OVL_BA1(OMAP_DSS_VIDEO2));
- SR(OVL_POSITION(OMAP_DSS_VIDEO2));
- SR(OVL_SIZE(OMAP_DSS_VIDEO2));
- SR(OVL_ATTRIBUTES(OMAP_DSS_VIDEO2));
- SR(OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO2));
- SR(OVL_ROW_INC(OMAP_DSS_VIDEO2));
- SR(OVL_PIXEL_INC(OMAP_DSS_VIDEO2));
- SR(OVL_FIR(OMAP_DSS_VIDEO2));
- SR(OVL_PICTURE_SIZE(OMAP_DSS_VIDEO2));
- SR(OVL_ACCU0(OMAP_DSS_VIDEO2));
- SR(OVL_ACCU1(OMAP_DSS_VIDEO2));
+ for (i = 0; i < dss_feat_get_num_ovls(); i++) {
+ SR(OVL_BA0(i));
+ SR(OVL_BA1(i));
+ SR(OVL_POSITION(i));
+ SR(OVL_SIZE(i));
+ SR(OVL_ATTRIBUTES(i));
+ SR(OVL_FIFO_THRESHOLD(i));
+ SR(OVL_ROW_INC(i));
+ SR(OVL_PIXEL_INC(i));
+ if (dss_has_feature(FEAT_PRELOAD))
+ SR(OVL_PRELOAD(i));
+ if (i == OMAP_DSS_GFX) {
+ SR(OVL_WINDOW_SKIP(i));
+ SR(OVL_TABLE_BA(i));
+ continue;
+ }
+ SR(OVL_FIR(i));
+ SR(OVL_PICTURE_SIZE(i));
+ SR(OVL_ACCU0(i));
+ SR(OVL_ACCU1(i));
- for (i = 0; i < 8; i++)
- SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, i));
+ for (j = 0; j < 8; j++)
+ SR(OVL_FIR_COEF_H(i, j));
- for (i = 0; i < 8; i++)
- SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, i));
+ for (j = 0; j < 8; j++)
+ SR(OVL_FIR_COEF_HV(i, j));
- for (i = 0; i < 5; i++)
- SR(OVL_CONV_COEF(OMAP_DSS_VIDEO2, i));
+ for (j = 0; j < 5; j++)
+ SR(OVL_CONV_COEF(i, j));
- if (dss_has_feature(FEAT_FIR_COEF_V)) {
- for (i = 0; i < 8; i++)
- SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, i));
- }
+ if (dss_has_feature(FEAT_FIR_COEF_V)) {
+ for (j = 0; j < 8; j++)
+ SR(OVL_FIR_COEF_V(i, j));
+ }
- if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
- SR(OVL_BA0_UV(OMAP_DSS_VIDEO2));
- SR(OVL_BA1_UV(OMAP_DSS_VIDEO2));
- SR(OVL_FIR2(OMAP_DSS_VIDEO2));
- SR(OVL_ACCU2_0(OMAP_DSS_VIDEO2));
- SR(OVL_ACCU2_1(OMAP_DSS_VIDEO2));
+ if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
+ SR(OVL_BA0_UV(i));
+ SR(OVL_BA1_UV(i));
+ SR(OVL_FIR2(i));
+ SR(OVL_ACCU2_0(i));
+ SR(OVL_ACCU2_1(i));
- for (i = 0; i < 8; i++)
- SR(OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, i));
+ for (j = 0; j < 8; j++)
+ SR(OVL_FIR_COEF_H2(i, j));
- for (i = 0; i < 8; i++)
- SR(OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, i));
+ for (j = 0; j < 8; j++)
+ SR(OVL_FIR_COEF_HV2(i, j));
- for (i = 0; i < 8; i++)
- SR(OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, i));
+ for (j = 0; j < 8; j++)
+ SR(OVL_FIR_COEF_V2(i, j));
+ }
+ if (dss_has_feature(FEAT_ATTR2))
+ SR(OVL_ATTRIBUTES2(i));
}
- if (dss_has_feature(FEAT_ATTR2))
- SR(OVL_ATTRIBUTES2(OMAP_DSS_VIDEO2));
-
- if (dss_has_feature(FEAT_PRELOAD))
- SR(OVL_PRELOAD(OMAP_DSS_VIDEO2));
if (dss_has_feature(FEAT_CORE_CLK_DIV))
SR(DIVISOR);
@@ -349,7 +274,7 @@ static void dispc_save_context(void)
static void dispc_restore_context(void)
{
- int i, ctx;
+ int i, j, ctx;
DSSDBG("dispc_restore_context\n");
@@ -367,165 +292,88 @@ static void dispc_restore_context(void)
/*RR(IRQENABLE);*/
/*RR(CONTROL);*/
RR(CONFIG);
- RR(DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD));
- RR(DEFAULT_COLOR(OMAP_DSS_CHANNEL_DIGIT));
- RR(TRANS_COLOR(OMAP_DSS_CHANNEL_LCD));
- RR(TRANS_COLOR(OMAP_DSS_CHANNEL_DIGIT));
RR(LINE_NUMBER);
- RR(TIMING_H(OMAP_DSS_CHANNEL_LCD));
- RR(TIMING_V(OMAP_DSS_CHANNEL_LCD));
- RR(POL_FREQ(OMAP_DSS_CHANNEL_LCD));
- RR(DIVISORo(OMAP_DSS_CHANNEL_LCD));
if (dss_has_feature(FEAT_GLOBAL_ALPHA))
RR(GLOBAL_ALPHA);
- RR(SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT));
- RR(SIZE_MGR(OMAP_DSS_CHANNEL_LCD));
- if (dss_has_feature(FEAT_MGR_LCD2)) {
- RR(DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD2));
- RR(TRANS_COLOR(OMAP_DSS_CHANNEL_LCD2));
- RR(SIZE_MGR(OMAP_DSS_CHANNEL_LCD2));
- RR(TIMING_H(OMAP_DSS_CHANNEL_LCD2));
- RR(TIMING_V(OMAP_DSS_CHANNEL_LCD2));
- RR(POL_FREQ(OMAP_DSS_CHANNEL_LCD2));
- RR(DIVISORo(OMAP_DSS_CHANNEL_LCD2));
+ if (dss_has_feature(FEAT_MGR_LCD2))
RR(CONFIG2);
- }
-
- RR(OVL_BA0(OMAP_DSS_GFX));
- RR(OVL_BA1(OMAP_DSS_GFX));
- RR(OVL_POSITION(OMAP_DSS_GFX));
- RR(OVL_SIZE(OMAP_DSS_GFX));
- RR(OVL_ATTRIBUTES(OMAP_DSS_GFX));
- RR(OVL_FIFO_THRESHOLD(OMAP_DSS_GFX));
- RR(OVL_ROW_INC(OMAP_DSS_GFX));
- RR(OVL_PIXEL_INC(OMAP_DSS_GFX));
- RR(OVL_WINDOW_SKIP(OMAP_DSS_GFX));
- RR(OVL_TABLE_BA(OMAP_DSS_GFX));
+ for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
+ RR(DEFAULT_COLOR(i));
+ RR(TRANS_COLOR(i));
+ RR(SIZE_MGR(i));
+ if (i == OMAP_DSS_CHANNEL_DIGIT)
+ continue;
+ RR(TIMING_H(i));
+ RR(TIMING_V(i));
+ RR(POL_FREQ(i));
+ RR(DIVISORo(i));
- RR(DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD));
- RR(DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD));
- RR(DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD));
-
- if (dss_has_feature(FEAT_CPR)) {
- RR(CPR_COEF_R(OMAP_DSS_CHANNEL_LCD));
- RR(CPR_COEF_G(OMAP_DSS_CHANNEL_LCD));
- RR(CPR_COEF_B(OMAP_DSS_CHANNEL_LCD));
- }
- if (dss_has_feature(FEAT_MGR_LCD2)) {
- RR(DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD2));
- RR(DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD2));
- RR(DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD2));
+ RR(DATA_CYCLE1(i));
+ RR(DATA_CYCLE2(i));
+ RR(DATA_CYCLE3(i));
if (dss_has_feature(FEAT_CPR)) {
- RR(CPR_COEF_B(OMAP_DSS_CHANNEL_LCD2));
- RR(CPR_COEF_G(OMAP_DSS_CHANNEL_LCD2));
- RR(CPR_COEF_R(OMAP_DSS_CHANNEL_LCD2));
+ RR(CPR_COEF_R(i));
+ RR(CPR_COEF_G(i));
+ RR(CPR_COEF_B(i));
}
}
- if (dss_has_feature(FEAT_PRELOAD))
- RR(OVL_PRELOAD(OMAP_DSS_GFX));
-
- /* VID1 */
- RR(OVL_BA0(OMAP_DSS_VIDEO1));
- RR(OVL_BA1(OMAP_DSS_VIDEO1));
- RR(OVL_POSITION(OMAP_DSS_VIDEO1));
- RR(OVL_SIZE(OMAP_DSS_VIDEO1));
- RR(OVL_ATTRIBUTES(OMAP_DSS_VIDEO1));
- RR(OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO1));
- RR(OVL_ROW_INC(OMAP_DSS_VIDEO1));
- RR(OVL_PIXEL_INC(OMAP_DSS_VIDEO1));
- RR(OVL_FIR(OMAP_DSS_VIDEO1));
- RR(OVL_PICTURE_SIZE(OMAP_DSS_VIDEO1));
- RR(OVL_ACCU0(OMAP_DSS_VIDEO1));
- RR(OVL_ACCU1(OMAP_DSS_VIDEO1));
-
- for (i = 0; i < 8; i++)
- RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, i));
-
- for (i = 0; i < 8; i++)
- RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, i));
-
- for (i = 0; i < 5; i++)
- RR(OVL_CONV_COEF(OMAP_DSS_VIDEO1, i));
-
- if (dss_has_feature(FEAT_FIR_COEF_V)) {
- for (i = 0; i < 8; i++)
- RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, i));
- }
-
- if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
- RR(OVL_BA0_UV(OMAP_DSS_VIDEO1));
- RR(OVL_BA1_UV(OMAP_DSS_VIDEO1));
- RR(OVL_FIR2(OMAP_DSS_VIDEO1));
- RR(OVL_ACCU2_0(OMAP_DSS_VIDEO1));
- RR(OVL_ACCU2_1(OMAP_DSS_VIDEO1));
-
- for (i = 0; i < 8; i++)
- RR(OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, i));
-
- for (i = 0; i < 8; i++)
- RR(OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, i));
-
- for (i = 0; i < 8; i++)
- RR(OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, i));
- }
- if (dss_has_feature(FEAT_ATTR2))
- RR(OVL_ATTRIBUTES2(OMAP_DSS_VIDEO1));
-
- if (dss_has_feature(FEAT_PRELOAD))
- RR(OVL_PRELOAD(OMAP_DSS_VIDEO1));
-
- /* VID2 */
- RR(OVL_BA0(OMAP_DSS_VIDEO2));
- RR(OVL_BA1(OMAP_DSS_VIDEO2));
- RR(OVL_POSITION(OMAP_DSS_VIDEO2));
- RR(OVL_SIZE(OMAP_DSS_VIDEO2));
- RR(OVL_ATTRIBUTES(OMAP_DSS_VIDEO2));
- RR(OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO2));
- RR(OVL_ROW_INC(OMAP_DSS_VIDEO2));
- RR(OVL_PIXEL_INC(OMAP_DSS_VIDEO2));
- RR(OVL_FIR(OMAP_DSS_VIDEO2));
- RR(OVL_PICTURE_SIZE(OMAP_DSS_VIDEO2));
- RR(OVL_ACCU0(OMAP_DSS_VIDEO2));
- RR(OVL_ACCU1(OMAP_DSS_VIDEO2));
+ for (i = 0; i < dss_feat_get_num_ovls(); i++) {
+ RR(OVL_BA0(i));
+ RR(OVL_BA1(i));
+ RR(OVL_POSITION(i));
+ RR(OVL_SIZE(i));
+ RR(OVL_ATTRIBUTES(i));
+ RR(OVL_FIFO_THRESHOLD(i));
+ RR(OVL_ROW_INC(i));
+ RR(OVL_PIXEL_INC(i));
+ if (dss_has_feature(FEAT_PRELOAD))
+ RR(OVL_PRELOAD(i));
+ if (i == OMAP_DSS_GFX) {
+ RR(OVL_WINDOW_SKIP(i));
+ RR(OVL_TABLE_BA(i));
+ continue;
+ }
+ RR(OVL_FIR(i));
+ RR(OVL_PICTURE_SIZE(i));
+ RR(OVL_ACCU0(i));
+ RR(OVL_ACCU1(i));
- for (i = 0; i < 8; i++)
- RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, i));
+ for (j = 0; j < 8; j++)
+ RR(OVL_FIR_COEF_H(i, j));
- for (i = 0; i < 8; i++)
- RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, i));
+ for (j = 0; j < 8; j++)
+ RR(OVL_FIR_COEF_HV(i, j));
- for (i = 0; i < 5; i++)
- RR(OVL_CONV_COEF(OMAP_DSS_VIDEO2, i));
+ for (j = 0; j < 5; j++)
+ RR(OVL_CONV_COEF(i, j));
- if (dss_has_feature(FEAT_FIR_COEF_V)) {
- for (i = 0; i < 8; i++)
- RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, i));
- }
+ if (dss_has_feature(FEAT_FIR_COEF_V)) {
+ for (j = 0; j < 8; j++)
+ RR(OVL_FIR_COEF_V(i, j));
+ }
- if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
- RR(OVL_BA0_UV(OMAP_DSS_VIDEO2));
- RR(OVL_BA1_UV(OMAP_DSS_VIDEO2));
- RR(OVL_FIR2(OMAP_DSS_VIDEO2));
- RR(OVL_ACCU2_0(OMAP_DSS_VIDEO2));
- RR(OVL_ACCU2_1(OMAP_DSS_VIDEO2));
+ if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
+ RR(OVL_BA0_UV(i));
+ RR(OVL_BA1_UV(i));
+ RR(OVL_FIR2(i));
+ RR(OVL_ACCU2_0(i));
+ RR(OVL_ACCU2_1(i));
- for (i = 0; i < 8; i++)
- RR(OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, i));
+ for (j = 0; j < 8; j++)
+ RR(OVL_FIR_COEF_H2(i, j));
- for (i = 0; i < 8; i++)
- RR(OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, i));
+ for (j = 0; j < 8; j++)
+ RR(OVL_FIR_COEF_HV2(i, j));
- for (i = 0; i < 8; i++)
- RR(OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, i));
+ for (j = 0; j < 8; j++)
+ RR(OVL_FIR_COEF_V2(i, j));
+ }
+ if (dss_has_feature(FEAT_ATTR2))
+ RR(OVL_ATTRIBUTES2(i));
}
- if (dss_has_feature(FEAT_ATTR2))
- RR(OVL_ATTRIBUTES2(OMAP_DSS_VIDEO2));
-
- if (dss_has_feature(FEAT_PRELOAD))
- RR(OVL_PRELOAD(OMAP_DSS_VIDEO2));
if (dss_has_feature(FEAT_CORE_CLK_DIV))
RR(DIVISOR);
--
1.7.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH 4/5] OMAP: DSS2: DISPC: Shorten _dispc_set_color_conv_coef()
2011-08-05 7:42 [PATCH 0/5] OMAP: DSS2: Miscellaneous DISPC Patches Archit Taneja
` (2 preceding siblings ...)
2011-08-05 7:42 ` [PATCH 3/5] OMAP: DSS2: DISPC: dispc_save_context() and dispc_restore_context() cleanup Archit Taneja
@ 2011-08-05 7:42 ` Archit Taneja
2011-08-05 7:42 ` [PATCH 5/5] OMAP4: DSS2: VIDEO3 pipeline support Archit Taneja
4 siblings, 0 replies; 10+ messages in thread
From: Archit Taneja @ 2011-08-05 7:42 UTC (permalink / raw)
To: tomi.valkeinen; +Cc: linux-omap, Archit Taneja
Iterate over overlay id's to shorten _dispc_set_color_conv_coef()
Signed-off-by: Archit Taneja <archit@ti.com>
---
drivers/video/omap2/dss/dispc.c | 42 ++++++++++++++------------------------
1 files changed, 16 insertions(+), 26 deletions(-)
diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
index 2fd16ac..8cab996 100644
--- a/drivers/video/omap2/dss/dispc.c
+++ b/drivers/video/omap2/dss/dispc.c
@@ -641,6 +641,7 @@ static void _dispc_set_scale_coef(enum omap_plane plane, int hscaleup,
static void _dispc_setup_color_conv_coef(void)
{
+ int i;
const struct color_conv_coef {
int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
int full_range;
@@ -654,34 +655,23 @@ static void _dispc_setup_color_conv_coef(void)
ct = &ctbl_bt601_5;
- dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 0),
- CVAL(ct->rcr, ct->ry));
- dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 1),
- CVAL(ct->gy, ct->rcb));
- dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 2),
- CVAL(ct->gcb, ct->gcr));
- dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 3),
- CVAL(ct->bcr, ct->by));
- dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 4),
- CVAL(0, ct->bcb));
-
- dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 0),
- CVAL(ct->rcr, ct->ry));
- dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 1),
- CVAL(ct->gy, ct->rcb));
- dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 2),
- CVAL(ct->gcb, ct->gcr));
- dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 3),
- CVAL(ct->bcr, ct->by));
- dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 4),
- CVAL(0, ct->bcb));
+ for (i = 1; i < dss_feat_get_num_ovls(); i++) {
+ dispc_write_reg(DISPC_OVL_CONV_COEF(i, 0),
+ CVAL(ct->rcr, ct->ry));
+ dispc_write_reg(DISPC_OVL_CONV_COEF(i, 1),
+ CVAL(ct->gy, ct->rcb));
+ dispc_write_reg(DISPC_OVL_CONV_COEF(i, 2),
+ CVAL(ct->gcb, ct->gcr));
+ dispc_write_reg(DISPC_OVL_CONV_COEF(i, 3),
+ CVAL(ct->bcr, ct->by));
+ dispc_write_reg(DISPC_OVL_CONV_COEF(i, 4),
+ CVAL(0, ct->bcb));
-#undef CVAL
+ REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), ct->full_range,
+ 11, 11);
+ }
- REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(OMAP_DSS_VIDEO1),
- ct->full_range, 11, 11);
- REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(OMAP_DSS_VIDEO2),
- ct->full_range, 11, 11);
+#undef CVAL
}
--
1.7.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH 5/5] OMAP4: DSS2: VIDEO3 pipeline support
2011-08-05 7:42 [PATCH 0/5] OMAP: DSS2: Miscellaneous DISPC Patches Archit Taneja
` (3 preceding siblings ...)
2011-08-05 7:42 ` [PATCH 4/5] OMAP: DSS2: DISPC: Shorten _dispc_set_color_conv_coef() Archit Taneja
@ 2011-08-05 7:42 ` Archit Taneja
[not found] ` <CAB2ybb_fDM8bDr1CsFUHRhE9fNoSKvOoWTktQGzh+VV=efEMZw@mail.gmail.com>
4 siblings, 1 reply; 10+ messages in thread
From: Archit Taneja @ 2011-08-05 7:42 UTC (permalink / raw)
To: tomi.valkeinen; +Cc: linux-omap, Archit Taneja
Add support for VIDEO3 pipeline on OMAP4:
- Add VIDEO3 pipeline information in dss_features and omapdss.h
- Add VIDEO3 pipeline register coefficients in dispc.h
- Create a new overlay structure corresponding to VIDEO3.
Signed-off-by: Archit Taneja <archit@ti.com>
---
drivers/video/omap2/dss/dispc.c | 31 ++++++++++++++++-
drivers/video/omap2/dss/dispc.h | 57 ++++++++++++++++++++++++++++++++
drivers/video/omap2/dss/dss_features.c | 14 +++++++-
drivers/video/omap2/dss/dss_features.h | 2 +-
drivers/video/omap2/dss/overlay.c | 7 ++++
include/video/omapdss.h | 5 ++-
6 files changed, 110 insertions(+), 6 deletions(-)
diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
index 8cab996..202b8c7 100644
--- a/drivers/video/omap2/dss/dispc.c
+++ b/drivers/video/omap2/dss/dispc.c
@@ -106,7 +106,7 @@ static struct {
int irq;
struct clk *dss_clk;
- u32 fifo_size[3];
+ u32 fifo_size[MAX_DSS_OVERLAYS];
spinlock_t irq_lock;
u32 irq_error_mask;
@@ -748,6 +748,8 @@ static void _dispc_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 7, 0);
else if (plane == OMAP_DSS_VIDEO2)
REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 23, 16);
+ else if (plane == OMAP_DSS_VIDEO3)
+ REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 31, 24);
}
static void _dispc_set_pix_inc(enum omap_plane plane, s32 inc)
@@ -854,6 +856,7 @@ void dispc_set_channel_out(enum omap_plane plane,
break;
case OMAP_DSS_VIDEO1:
case OMAP_DSS_VIDEO2:
+ case OMAP_DSS_VIDEO3:
shift = 16;
break;
default:
@@ -899,6 +902,7 @@ static void dispc_set_burst_size(enum omap_plane plane,
break;
case OMAP_DSS_VIDEO1:
case OMAP_DSS_VIDEO2:
+ case OMAP_DSS_VIDEO3:
shift = 14;
break;
default:
@@ -1024,7 +1028,7 @@ static void dispc_read_plane_fifo_sizes(void)
dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
- for (plane = 0; plane < ARRAY_SIZE(dispc.fifo_size); ++plane) {
+ for (plane = 0; plane < dss_feat_get_num_ovls(); ++plane) {
size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(plane), start, end);
size *= unit;
dispc.fifo_size[plane] = size;
@@ -1987,6 +1991,8 @@ static void dispc_enable_digit_out(bool enable)
dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
if (dss_has_feature(FEAT_MGR_LCD2))
dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
+ if (dss_feat_get_num_ovls() > 3)
+ dispc.irq_error_mask |= DISPC_IRQ_VID3_FIFO_UNDERFLOW;
dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
_omap_dispc_set_irqs();
spin_unlock_irqrestore(&dispc.irq_lock, flags);
@@ -2555,6 +2561,7 @@ void dispc_dump_regs(struct seq_file *s)
[OMAP_DSS_GFX] = "GFX",
[OMAP_DSS_VIDEO1] = "VID1",
[OMAP_DSS_VIDEO2] = "VID2",
+ [OMAP_DSS_VIDEO3] = "VID3",
};
const char **p_names;
@@ -3102,6 +3109,24 @@ static void dispc_error_worker(struct work_struct *work)
}
}
+ if (errors & DISPC_IRQ_VID3_FIFO_UNDERFLOW) {
+ DSSERR("VID3_FIFO_UNDERFLOW, disabling VID3\n");
+ for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
+ struct omap_overlay *ovl;
+ ovl = omap_dss_get_overlay(i);
+
+ if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
+ continue;
+
+ if (ovl->id == 3) {
+ dispc_enable_plane(ovl->id, 0);
+ dispc_go(ovl->manager->id);
+ mdelay(50);
+ break;
+ }
+ }
+ }
+
if (errors & DISPC_IRQ_SYNC_LOST) {
struct omap_overlay_manager *manager = NULL;
bool enable = false;
@@ -3328,6 +3353,8 @@ static void _omap_dispc_initialize_irq(void)
dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
if (dss_has_feature(FEAT_MGR_LCD2))
dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
+ if (dss_feat_get_num_ovls() > 3)
+ dispc.irq_error_mask |= DISPC_IRQ_VID3_FIFO_UNDERFLOW;
/* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
* so clear it */
diff --git a/drivers/video/omap2/dss/dispc.h b/drivers/video/omap2/dss/dispc.h
index 6c9ee0a..b0c2aed 100644
--- a/drivers/video/omap2/dss/dispc.h
+++ b/drivers/video/omap2/dss/dispc.h
@@ -291,6 +291,8 @@ static inline u16 DISPC_OVL_BASE(enum omap_plane plane)
return 0x00BC;
case OMAP_DSS_VIDEO2:
return 0x014C;
+ case OMAP_DSS_VIDEO3:
+ return 0x0300;
default:
BUG();
}
@@ -304,6 +306,8 @@ static inline u16 DISPC_BA0_OFFSET(enum omap_plane plane)
case OMAP_DSS_VIDEO1:
case OMAP_DSS_VIDEO2:
return 0x0000;
+ case OMAP_DSS_VIDEO3:
+ return 0x0008;
default:
BUG();
}
@@ -316,6 +320,8 @@ static inline u16 DISPC_BA1_OFFSET(enum omap_plane plane)
case OMAP_DSS_VIDEO1:
case OMAP_DSS_VIDEO2:
return 0x0004;
+ case OMAP_DSS_VIDEO3:
+ return 0x000C;
default:
BUG();
}
@@ -330,6 +336,8 @@ static inline u16 DISPC_BA0_UV_OFFSET(enum omap_plane plane)
return 0x0544;
case OMAP_DSS_VIDEO2:
return 0x04BC;
+ case OMAP_DSS_VIDEO3:
+ return 0x0310;
default:
BUG();
}
@@ -344,6 +352,8 @@ static inline u16 DISPC_BA1_UV_OFFSET(enum omap_plane plane)
return 0x0548;
case OMAP_DSS_VIDEO2:
return 0x04C0;
+ case OMAP_DSS_VIDEO3:
+ return 0x0314;
default:
BUG();
}
@@ -356,6 +366,8 @@ static inline u16 DISPC_POS_OFFSET(enum omap_plane plane)
case OMAP_DSS_VIDEO1:
case OMAP_DSS_VIDEO2:
return 0x0008;
+ case OMAP_DSS_VIDEO3:
+ return 0x009C;
default:
BUG();
}
@@ -368,6 +380,8 @@ static inline u16 DISPC_SIZE_OFFSET(enum omap_plane plane)
case OMAP_DSS_VIDEO1:
case OMAP_DSS_VIDEO2:
return 0x000C;
+ case OMAP_DSS_VIDEO3:
+ return 0x00A8;
default:
BUG();
}
@@ -381,6 +395,8 @@ static inline u16 DISPC_ATTR_OFFSET(enum omap_plane plane)
case OMAP_DSS_VIDEO1:
case OMAP_DSS_VIDEO2:
return 0x0010;
+ case OMAP_DSS_VIDEO3:
+ return 0x0070;
default:
BUG();
}
@@ -395,6 +411,8 @@ static inline u16 DISPC_ATTR2_OFFSET(enum omap_plane plane)
return 0x0568;
case OMAP_DSS_VIDEO2:
return 0x04DC;
+ case OMAP_DSS_VIDEO3:
+ return 0x032C;
default:
BUG();
}
@@ -408,6 +426,8 @@ static inline u16 DISPC_FIFO_THRESH_OFFSET(enum omap_plane plane)
case OMAP_DSS_VIDEO1:
case OMAP_DSS_VIDEO2:
return 0x0014;
+ case OMAP_DSS_VIDEO3:
+ return 0x008C;
default:
BUG();
}
@@ -421,6 +441,8 @@ static inline u16 DISPC_FIFO_SIZE_STATUS_OFFSET(enum omap_plane plane)
case OMAP_DSS_VIDEO1:
case OMAP_DSS_VIDEO2:
return 0x0018;
+ case OMAP_DSS_VIDEO3:
+ return 0x0088;
default:
BUG();
}
@@ -434,6 +456,8 @@ static inline u16 DISPC_ROW_INC_OFFSET(enum omap_plane plane)
case OMAP_DSS_VIDEO1:
case OMAP_DSS_VIDEO2:
return 0x001C;
+ case OMAP_DSS_VIDEO3:
+ return 0x00A4;
default:
BUG();
}
@@ -447,6 +471,8 @@ static inline u16 DISPC_PIX_INC_OFFSET(enum omap_plane plane)
case OMAP_DSS_VIDEO1:
case OMAP_DSS_VIDEO2:
return 0x0020;
+ case OMAP_DSS_VIDEO3:
+ return 0x0098;
default:
BUG();
}
@@ -459,6 +485,7 @@ static inline u16 DISPC_WINDOW_SKIP_OFFSET(enum omap_plane plane)
return 0x0034;
case OMAP_DSS_VIDEO1:
case OMAP_DSS_VIDEO2:
+ case OMAP_DSS_VIDEO3:
BUG();
default:
BUG();
@@ -472,6 +499,7 @@ static inline u16 DISPC_TABLE_BA_OFFSET(enum omap_plane plane)
return 0x0038;
case OMAP_DSS_VIDEO1:
case OMAP_DSS_VIDEO2:
+ case OMAP_DSS_VIDEO3:
BUG();
default:
BUG();
@@ -486,6 +514,8 @@ static inline u16 DISPC_FIR_OFFSET(enum omap_plane plane)
case OMAP_DSS_VIDEO1:
case OMAP_DSS_VIDEO2:
return 0x0024;
+ case OMAP_DSS_VIDEO3:
+ return 0x0090;
default:
BUG();
}
@@ -500,6 +530,8 @@ static inline u16 DISPC_FIR2_OFFSET(enum omap_plane plane)
return 0x0580;
case OMAP_DSS_VIDEO2:
return 0x055C;
+ case OMAP_DSS_VIDEO3:
+ return 0x0424;
default:
BUG();
}
@@ -513,6 +545,8 @@ static inline u16 DISPC_PIC_SIZE_OFFSET(enum omap_plane plane)
case OMAP_DSS_VIDEO1:
case OMAP_DSS_VIDEO2:
return 0x0028;
+ case OMAP_DSS_VIDEO3:
+ return 0x0094;
default:
BUG();
}
@@ -527,6 +561,8 @@ static inline u16 DISPC_ACCU0_OFFSET(enum omap_plane plane)
case OMAP_DSS_VIDEO1:
case OMAP_DSS_VIDEO2:
return 0x002C;
+ case OMAP_DSS_VIDEO3:
+ return 0x0000;
default:
BUG();
}
@@ -541,6 +577,8 @@ static inline u16 DISPC_ACCU2_0_OFFSET(enum omap_plane plane)
return 0x0584;
case OMAP_DSS_VIDEO2:
return 0x0560;
+ case OMAP_DSS_VIDEO3:
+ return 0x0428;
default:
BUG();
}
@@ -554,6 +592,8 @@ static inline u16 DISPC_ACCU1_OFFSET(enum omap_plane plane)
case OMAP_DSS_VIDEO1:
case OMAP_DSS_VIDEO2:
return 0x0030;
+ case OMAP_DSS_VIDEO3:
+ return 0x0004;
default:
BUG();
}
@@ -568,6 +608,8 @@ static inline u16 DISPC_ACCU2_1_OFFSET(enum omap_plane plane)
return 0x0588;
case OMAP_DSS_VIDEO2:
return 0x0564;
+ case OMAP_DSS_VIDEO3:
+ return 0x042C;
default:
BUG();
}
@@ -582,6 +624,8 @@ static inline u16 DISPC_FIR_COEF_H_OFFSET(enum omap_plane plane, u16 i)
case OMAP_DSS_VIDEO1:
case OMAP_DSS_VIDEO2:
return 0x0034 + i * 0x8;
+ case OMAP_DSS_VIDEO3:
+ return 0x0010 + i * 0x8;
default:
BUG();
}
@@ -597,6 +641,8 @@ static inline u16 DISPC_FIR_COEF_H2_OFFSET(enum omap_plane plane, u16 i)
return 0x058C + i * 0x8;
case OMAP_DSS_VIDEO2:
return 0x0568 + i * 0x8;
+ case OMAP_DSS_VIDEO3:
+ return 0x0430 + i * 0x8;
default:
BUG();
}
@@ -611,6 +657,8 @@ static inline u16 DISPC_FIR_COEF_HV_OFFSET(enum omap_plane plane, u16 i)
case OMAP_DSS_VIDEO1:
case OMAP_DSS_VIDEO2:
return 0x0038 + i * 0x8;
+ case OMAP_DSS_VIDEO3:
+ return 0x0014 + i * 0x8;
default:
BUG();
}
@@ -626,6 +674,8 @@ static inline u16 DISPC_FIR_COEF_HV2_OFFSET(enum omap_plane plane, u16 i)
return 0x0590 + i * 8;
case OMAP_DSS_VIDEO2:
return 0x056C + i * 0x8;
+ case OMAP_DSS_VIDEO3:
+ return 0x0434 + i * 0x8;
default:
BUG();
}
@@ -639,6 +689,7 @@ static inline u16 DISPC_CONV_COEF_OFFSET(enum omap_plane plane, u16 i)
BUG();
case OMAP_DSS_VIDEO1:
case OMAP_DSS_VIDEO2:
+ case OMAP_DSS_VIDEO3:
return 0x0074 + i * 0x4;
default:
BUG();
@@ -655,6 +706,8 @@ static inline u16 DISPC_FIR_COEF_V_OFFSET(enum omap_plane plane, u16 i)
return 0x0124 + i * 0x4;
case OMAP_DSS_VIDEO2:
return 0x00B4 + i * 0x4;
+ case OMAP_DSS_VIDEO3:
+ return 0x0050 + i * 0x8;
default:
BUG();
}
@@ -670,6 +723,8 @@ static inline u16 DISPC_FIR_COEF_V2_OFFSET(enum omap_plane plane, u16 i)
return 0x05CC + i * 0x4;
case OMAP_DSS_VIDEO2:
return 0x05A8 + i * 0x4;
+ case OMAP_DSS_VIDEO3:
+ return 0x0470 + i * 0x8;
default:
BUG();
}
@@ -684,6 +739,8 @@ static inline u16 DISPC_PRELOAD_OFFSET(enum omap_plane plane)
return 0x0174;
case OMAP_DSS_VIDEO2:
return 0x00E8;
+ case OMAP_DSS_VIDEO3:
+ return 0x00A0;
default:
BUG();
}
diff --git a/drivers/video/omap2/dss/dss_features.c b/drivers/video/omap2/dss/dss_features.c
index b415c4e..fb9641b 100644
--- a/drivers/video/omap2/dss/dss_features.c
+++ b/drivers/video/omap2/dss/dss_features.c
@@ -209,6 +209,16 @@ static const enum omap_color_mode omap4_dss_supported_color_modes[] = {
OMAP_DSS_COLOR_ARGB16 | OMAP_DSS_COLOR_XRGB16_1555 |
OMAP_DSS_COLOR_ARGB32 | OMAP_DSS_COLOR_RGBX16 |
OMAP_DSS_COLOR_RGBX32,
+
+ /* OMAP_DSS_VIDEO3 */
+ OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB12U |
+ OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_ARGB16_1555 |
+ OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_NV12 |
+ OMAP_DSS_COLOR_RGBA16 | OMAP_DSS_COLOR_RGB24U |
+ OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_UYVY |
+ OMAP_DSS_COLOR_ARGB16 | OMAP_DSS_COLOR_XRGB16_1555 |
+ OMAP_DSS_COLOR_ARGB32 | OMAP_DSS_COLOR_RGBX16 |
+ OMAP_DSS_COLOR_RGBX32,
};
static const char * const omap2_dss_clk_source_names[] = {
@@ -343,7 +353,7 @@ static const struct omap_dss_features omap4430_es1_0_dss_features = {
FEAT_CPR | FEAT_PRELOAD | FEAT_FIR_COEF_V,
.num_mgrs = 3,
- .num_ovls = 3,
+ .num_ovls = 4,
.supported_displays = omap4_dss_supported_displays,
.supported_color_modes = omap4_dss_supported_color_modes,
.clksrc_names = omap4_dss_clk_source_names,
@@ -367,7 +377,7 @@ static const struct omap_dss_features omap4_dss_features = {
FEAT_PRELOAD | FEAT_FIR_COEF_V,
.num_mgrs = 3,
- .num_ovls = 3,
+ .num_ovls = 4,
.supported_displays = omap4_dss_supported_displays,
.supported_color_modes = omap4_dss_supported_color_modes,
.clksrc_names = omap4_dss_clk_source_names,
diff --git a/drivers/video/omap2/dss/dss_features.h b/drivers/video/omap2/dss/dss_features.h
index b7398cb..ff11c6f 100644
--- a/drivers/video/omap2/dss/dss_features.h
+++ b/drivers/video/omap2/dss/dss_features.h
@@ -21,7 +21,7 @@
#define __OMAP2_DSS_FEATURES_H
#define MAX_DSS_MANAGERS 3
-#define MAX_DSS_OVERLAYS 3
+#define MAX_DSS_OVERLAYS 4
#define MAX_DSS_LCD_MANAGERS 2
#define MAX_NUM_DSI 2
diff --git a/drivers/video/omap2/dss/overlay.c b/drivers/video/omap2/dss/overlay.c
index c84380c..b05f77d 100644
--- a/drivers/video/omap2/dss/overlay.c
+++ b/drivers/video/omap2/dss/overlay.c
@@ -635,6 +635,13 @@ void dss_init_overlays(struct platform_device *pdev)
OMAP_DSS_OVL_CAP_DISPC;
ovl->info.global_alpha = 255;
break;
+ case 3:
+ ovl->name = "vid3";
+ ovl->id = OMAP_DSS_VIDEO3;
+ ovl->caps = OMAP_DSS_OVL_CAP_SCALE |
+ OMAP_DSS_OVL_CAP_DISPC;
+ ovl->info.global_alpha = 255;
+ break;
}
ovl->set_manager = &omap_dss_set_manager;
diff --git a/include/video/omapdss.h b/include/video/omapdss.h
index dd6a580..028c37d 100644
--- a/include/video/omapdss.h
+++ b/include/video/omapdss.h
@@ -41,6 +41,8 @@
#define DISPC_IRQ_WAKEUP (1 << 16)
#define DISPC_IRQ_SYNC_LOST2 (1 << 17)
#define DISPC_IRQ_VSYNC2 (1 << 18)
+#define DISPC_IRQ_VID3_END_WIN (1 << 19)
+#define DISPC_IRQ_VID3_FIFO_UNDERFLOW (1 << 20)
#define DISPC_IRQ_ACBIAS_COUNT_STAT2 (1 << 21)
#define DISPC_IRQ_FRAMEDONE2 (1 << 22)
@@ -60,7 +62,8 @@ enum omap_display_type {
enum omap_plane {
OMAP_DSS_GFX = 0,
OMAP_DSS_VIDEO1 = 1,
- OMAP_DSS_VIDEO2 = 2
+ OMAP_DSS_VIDEO2 = 2,
+ OMAP_DSS_VIDEO3 = 3,
};
enum omap_channel {
--
1.7.1
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