[PATCH 1/4] OMAP2xxx: HWMOD: fix DSS opt clocks

[PATCH 1/4] OMAP2xxx: HWMOD: fix DSS opt clocks

[Tomi Valkeinen]

Set HWMOD_CONTROL_OPT_CLKS_IN_RESET for dss_core to allow DSS reset
properly.

Add missing ick opt-clock for rfbi. Rfbi uses the ick to calculate
timings.

Fix the venc iclk and fclk.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
---
 arch/arm/mach-omap2/omap_hwmod_2420_data.c |   15 +++++++++++++--
 arch/arm/mach-omap2/omap_hwmod_2430_data.c |   15 +++++++++++++--
 2 files changed, 26 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index a015c69..09d9395 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -874,12 +874,17 @@ static struct omap_hwmod_ocp_if *omap2420_dss_slaves[] = {
 };
 
 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
+	/*
+	 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
+	 * driver does not use these clocks.
+	 */
 	{ .role = "tv_clk", .clk = "dss_54m_fck" },
 	{ .role = "sys_clk", .clk = "dss2_fck" },
 };
 
 static struct omap_hwmod omap2420_dss_core_hwmod = {
 	.name		= "dss_core",
+	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 	.class		= &omap2_dss_hwmod_class,
 	.main_clk	= "dss1_fck", /* instead of dss_fck */
 	.sdma_reqs	= omap2xxx_dss_sdma_chs,
@@ -962,6 +967,10 @@ static struct omap_hwmod_ocp_if *omap2420_dss_rfbi_slaves[] = {
 	&omap2420_l4_core__dss_rfbi,
 };
 
+static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
+	{ .role = "ick", .clk = "dss_ick" },
+};
+
 static struct omap_hwmod omap2420_dss_rfbi_hwmod = {
 	.name		= "dss_rfbi",
 	.class		= &omap2_rfbi_hwmod_class,
@@ -973,6 +982,8 @@ static struct omap_hwmod omap2420_dss_rfbi_hwmod = {
 			.module_offs = CORE_MOD,
 		},
 	},
+	.opt_clks	= dss_rfbi_opt_clks,
+	.opt_clks_cnt	= ARRAY_SIZE(dss_rfbi_opt_clks),
 	.slaves		= omap2420_dss_rfbi_slaves,
 	.slaves_cnt	= ARRAY_SIZE(omap2420_dss_rfbi_slaves),
 	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
@@ -983,7 +994,7 @@ static struct omap_hwmod omap2420_dss_rfbi_hwmod = {
 static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = {
 	.master		= &omap2420_l4_core_hwmod,
 	.slave		= &omap2420_dss_venc_hwmod,
-	.clk		= "dss_54m_fck",
+	.clk		= "dss_ick",
 	.addr		= omap2_dss_venc_addrs,
 	.fw = {
 		.omap2 = {
@@ -1003,7 +1014,7 @@ static struct omap_hwmod_ocp_if *omap2420_dss_venc_slaves[] = {
 static struct omap_hwmod omap2420_dss_venc_hwmod = {
 	.name		= "dss_venc",
 	.class		= &omap2_venc_hwmod_class,
-	.main_clk	= "dss1_fck",
+	.main_clk	= "dss_54m_fck",
 	.prcm		= {
 		.omap2 = {
 			.prcm_reg_id = 1,
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 16743c7..67aff19 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -940,12 +940,17 @@ static struct omap_hwmod_ocp_if *omap2430_dss_slaves[] = {
 };
 
 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
+	/*
+	 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
+	 * driver does not use these clocks.
+	 */
 	{ .role = "tv_clk", .clk = "dss_54m_fck" },
 	{ .role = "sys_clk", .clk = "dss2_fck" },
 };
 
 static struct omap_hwmod omap2430_dss_core_hwmod = {
 	.name		= "dss_core",
+	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 	.class		= &omap2_dss_hwmod_class,
 	.main_clk	= "dss1_fck", /* instead of dss_fck */
 	.sdma_reqs	= omap2xxx_dss_sdma_chs,
@@ -1016,6 +1021,10 @@ static struct omap_hwmod_ocp_if *omap2430_dss_rfbi_slaves[] = {
 	&omap2430_l4_core__dss_rfbi,
 };
 
+static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
+	{ .role = "ick", .clk = "dss_ick" },
+};
+
 static struct omap_hwmod omap2430_dss_rfbi_hwmod = {
 	.name		= "dss_rfbi",
 	.class		= &omap2_rfbi_hwmod_class,
@@ -1027,6 +1036,8 @@ static struct omap_hwmod omap2430_dss_rfbi_hwmod = {
 			.module_offs = CORE_MOD,
 		},
 	},
+	.opt_clks	= dss_rfbi_opt_clks,
+	.opt_clks_cnt	= ARRAY_SIZE(dss_rfbi_opt_clks),
 	.slaves		= omap2430_dss_rfbi_slaves,
 	.slaves_cnt	= ARRAY_SIZE(omap2430_dss_rfbi_slaves),
 	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
@@ -1037,7 +1048,7 @@ static struct omap_hwmod omap2430_dss_rfbi_hwmod = {
 static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = {
 	.master		= &omap2430_l4_core_hwmod,
 	.slave		= &omap2430_dss_venc_hwmod,
-	.clk		= "dss_54m_fck",
+	.clk		= "dss_ick",
 	.addr		= omap2_dss_venc_addrs,
 	.flags		= OCPIF_SWSUP_IDLE,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
@@ -1051,7 +1062,7 @@ static struct omap_hwmod_ocp_if *omap2430_dss_venc_slaves[] = {
 static struct omap_hwmod omap2430_dss_venc_hwmod = {
 	.name		= "dss_venc",
 	.class		= &omap2_venc_hwmod_class,
-	.main_clk	= "dss1_fck",
+	.main_clk	= "dss_54m_fck",
 	.prcm		= {
 		.omap2 = {
 			.prcm_reg_id = 1,
-- 
1.7.4.1

[PATCH 2/4] OMAP3: HWMOD: fix DSS opt clocks

[Tomi Valkeinen]

Set HWMOD_CONTROL_OPT_CLKS_IN_RESET for dss_core to allow DSS reset
properly.

Add missing dss_96m_fck, which is used by venc on OMAP3430.

Add missing ick and sys_clk for dsi.

Add missing ick for rfbi.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
---
 arch/arm/mach-omap2/omap_hwmod_3xxx_data.c |   35 ++++++++++++++++++++++++---
 1 files changed, 31 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 25bf43b..4a02cc3 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -1365,13 +1365,19 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = {
 };
 
 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
-	{ .role = "tv_clk", .clk = "dss_tv_fck" },
-	{ .role = "video_clk", .clk = "dss_96m_fck" },
+	/*
+	 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
+	 * driver does not use these clocks.
+	 */
 	{ .role = "sys_clk", .clk = "dss2_alwon_fck" },
+	{ .role = "tv_clk", .clk = "dss_tv_fck" },
+	/* required only on OMAP3430 */
+	{ .role = "tv_dac_clk", .clk = "dss_96m_fck" },
 };
 
 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
 	.name		= "dss_core",
+	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 	.class		= &omap2_dss_hwmod_class,
 	.main_clk	= "dss1_alwon_fck", /* instead of dss_fck */
 	.sdma_reqs	= omap3xxx_dss_sdma_chs,
@@ -1396,6 +1402,7 @@ static struct omap_hwmod omap3430es1_dss_core_hwmod = {
 
 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
 	.name		= "dss_core",
+	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 	.class		= &omap2_dss_hwmod_class,
 	.main_clk	= "dss1_alwon_fck", /* instead of dss_fck */
 	.sdma_reqs	= omap3xxx_dss_sdma_chs,
@@ -1488,6 +1495,7 @@ static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
 	.master		= &omap3xxx_l4_core_hwmod,
 	.slave		= &omap3xxx_dss_dsi1_hwmod,
+	.clk		= "dss_ick",
 	.addr		= omap3xxx_dss_dsi1_addrs,
 	.fw = {
 		.omap2 = {
@@ -1504,6 +1512,10 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = {
 	&omap3xxx_l4_core__dss_dsi1,
 };
 
+static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
+	{ .role = "sys_clk", .clk = "dss2_alwon_fck" },
+};
+
 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
 	.name		= "dss_dsi1",
 	.class		= &omap3xxx_dsi_hwmod_class,
@@ -1516,6 +1528,8 @@ static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
 			.module_offs = OMAP3430_DSS_MOD,
 		},
 	},
+	.opt_clks	= dss_dsi1_opt_clks,
+	.opt_clks_cnt	= ARRAY_SIZE(dss_dsi1_opt_clks),
 	.slaves		= omap3xxx_dss_dsi1_slaves,
 	.slaves_cnt	= ARRAY_SIZE(omap3xxx_dss_dsi1_slaves),
 	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
@@ -1545,6 +1559,10 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = {
 	&omap3xxx_l4_core__dss_rfbi,
 };
 
+static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
+	{ .role = "ick", .clk = "dss_ick" },
+};
+
 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
 	.name		= "dss_rfbi",
 	.class		= &omap2_rfbi_hwmod_class,
@@ -1556,6 +1574,8 @@ static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
 			.module_offs = OMAP3430_DSS_MOD,
 		},
 	},
+	.opt_clks	= dss_rfbi_opt_clks,
+	.opt_clks_cnt	= ARRAY_SIZE(dss_rfbi_opt_clks),
 	.slaves		= omap3xxx_dss_rfbi_slaves,
 	.slaves_cnt	= ARRAY_SIZE(omap3xxx_dss_rfbi_slaves),
 	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
@@ -1568,7 +1588,7 @@ static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
 	.master		= &omap3xxx_l4_core_hwmod,
 	.slave		= &omap3xxx_dss_venc_hwmod,
-	.clk		= "dss_tv_fck",
+	.clk		= "dss_ick",
 	.addr		= omap2_dss_venc_addrs,
 	.fw = {
 		.omap2 = {
@@ -1586,10 +1606,15 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = {
 	&omap3xxx_l4_core__dss_venc,
 };
 
+static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
+	/* required only on OMAP3430 */
+	{ .role = "tv_dac_clk", .clk = "dss_96m_fck" },
+};
+
 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
 	.name		= "dss_venc",
 	.class		= &omap2_venc_hwmod_class,
-	.main_clk	= "dss1_alwon_fck",
+	.main_clk	= "dss_tv_fck",
 	.prcm		= {
 		.omap2 = {
 			.prcm_reg_id = 1,
@@ -1597,6 +1622,8 @@ static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
 			.module_offs = OMAP3430_DSS_MOD,
 		},
 	},
+	.opt_clks	= dss_venc_opt_clks,
+	.opt_clks_cnt	= ARRAY_SIZE(dss_venc_opt_clks),
 	.slaves		= omap3xxx_dss_venc_slaves,
 	.slaves_cnt	= ARRAY_SIZE(omap3xxx_dss_venc_slaves),
 	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
-- 
1.7.4.1

[PATCH 3/4] OMAP4: HWMOD: fix DSS opt clocks

[Tomi Valkeinen]

Remove the opt clocks for dss and dispc, as they are not needed.

Change the main_clk for hdmi and venc to dss_48mhz_clk and dss_tv_clk,
respectively.

Cc: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
---
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c |   21 ++-------------------
 1 files changed, 2 insertions(+), 19 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 6201422..21f03d4 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -1254,13 +1254,6 @@ static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = {
 	&omap44xx_l4_per__dss,
 };
 
-static struct omap_hwmod_opt_clk dss_opt_clks[] = {
-	{ .role = "sys_clk", .clk = "dss_sys_clk" },
-	{ .role = "tv_clk", .clk = "dss_tv_clk" },
-	{ .role = "dss_clk", .clk = "dss_dss_clk" },
-	{ .role = "video_clk", .clk = "dss_48mhz_clk" },
-};
-
 static struct omap_hwmod omap44xx_dss_hwmod = {
 	.name		= "dss_core",
 	.class		= &omap44xx_dss_hwmod_class,
@@ -1272,8 +1265,6 @@ static struct omap_hwmod omap44xx_dss_hwmod = {
 			.context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 		},
 	},
-	.opt_clks	= dss_opt_clks,
-	.opt_clks_cnt	= ARRAY_SIZE(dss_opt_clks),
 	.slaves		= omap44xx_dss_slaves,
 	.slaves_cnt	= ARRAY_SIZE(omap44xx_dss_slaves),
 	.masters	= omap44xx_dss_masters,
@@ -1358,12 +1349,6 @@ static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = {
 	&omap44xx_l4_per__dss_dispc,
 };
 
-static struct omap_hwmod_opt_clk dss_dispc_opt_clks[] = {
-	{ .role = "sys_clk", .clk = "dss_sys_clk" },
-	{ .role = "tv_clk", .clk = "dss_tv_clk" },
-	{ .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
-};
-
 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
 	.name		= "dss_dispc",
 	.class		= &omap44xx_dispc_hwmod_class,
@@ -1377,8 +1362,6 @@ static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
 			.context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 		},
 	},
-	.opt_clks	= dss_dispc_opt_clks,
-	.opt_clks_cnt	= ARRAY_SIZE(dss_dispc_opt_clks),
 	.slaves		= omap44xx_dss_dispc_slaves,
 	.slaves_cnt	= ARRAY_SIZE(omap44xx_dss_dispc_slaves),
 	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
@@ -1645,7 +1628,7 @@ static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
 	.clkdm_name	= "l3_dss_clkdm",
 	.mpu_irqs	= omap44xx_dss_hdmi_irqs,
 	.sdma_reqs	= omap44xx_dss_hdmi_sdma_reqs,
-	.main_clk	= "dss_dss_clk",
+	.main_clk	= "dss_48mhz_clk",
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
@@ -1808,7 +1791,7 @@ static struct omap_hwmod omap44xx_dss_venc_hwmod = {
 	.name		= "dss_venc",
 	.class		= &omap44xx_venc_hwmod_class,
 	.clkdm_name	= "l3_dss_clkdm",
-	.main_clk	= "dss_dss_clk",
+	.main_clk	= "dss_tv_clk",
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
-- 
1.7.4.1

Re: [PATCH 3/4] OMAP4: HWMOD: fix DSS opt clocks

[Cousson, Benoit]

On 8/2/2011 12:33 PM, Valkeinen, Tomi wrote:
> Remove the opt clocks for dss and dispc, as they are not needed.
>
> Change the main_clk for hdmi and venc to dss_48mhz_clk and dss_tv_clk,
> respectively.
>
> Cc: Benoit Cousson<b-cousson@ti.com>
> Signed-off-by: Tomi Valkeinen<tomi.valkeinen@ti.com>

That one alone is OK, but associated with the next one, it is weird.

Benoit

> ---
>   arch/arm/mach-omap2/omap_hwmod_44xx_data.c |   21 ++-------------------
>   1 files changed, 2 insertions(+), 19 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
> index 6201422..21f03d4 100644
> --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
> +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
> @@ -1254,13 +1254,6 @@ static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = {
>   	&omap44xx_l4_per__dss,
>   };
>
> -static struct omap_hwmod_opt_clk dss_opt_clks[] = {
> -	{ .role = "sys_clk", .clk = "dss_sys_clk" },
> -	{ .role = "tv_clk", .clk = "dss_tv_clk" },
> -	{ .role = "dss_clk", .clk = "dss_dss_clk" },
> -	{ .role = "video_clk", .clk = "dss_48mhz_clk" },
> -};
> -
>   static struct omap_hwmod omap44xx_dss_hwmod = {
>   	.name		= "dss_core",
>   	.class		=&omap44xx_dss_hwmod_class,
> @@ -1272,8 +1265,6 @@ static struct omap_hwmod omap44xx_dss_hwmod = {
>   			.context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
>   		},
>   	},
> -	.opt_clks	= dss_opt_clks,
> -	.opt_clks_cnt	= ARRAY_SIZE(dss_opt_clks),
>   	.slaves		= omap44xx_dss_slaves,
>   	.slaves_cnt	= ARRAY_SIZE(omap44xx_dss_slaves),
>   	.masters	= omap44xx_dss_masters,
> @@ -1358,12 +1349,6 @@ static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = {
>   	&omap44xx_l4_per__dss_dispc,
>   };
>
> -static struct omap_hwmod_opt_clk dss_dispc_opt_clks[] = {
> -	{ .role = "sys_clk", .clk = "dss_sys_clk" },
> -	{ .role = "tv_clk", .clk = "dss_tv_clk" },
> -	{ .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
> -};
> -
>   static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
>   	.name		= "dss_dispc",
>   	.class		=&omap44xx_dispc_hwmod_class,
> @@ -1377,8 +1362,6 @@ static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
>   			.context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
>   		},
>   	},
> -	.opt_clks	= dss_dispc_opt_clks,
> -	.opt_clks_cnt	= ARRAY_SIZE(dss_dispc_opt_clks),
>   	.slaves		= omap44xx_dss_dispc_slaves,
>   	.slaves_cnt	= ARRAY_SIZE(omap44xx_dss_dispc_slaves),
>   	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
> @@ -1645,7 +1628,7 @@ static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
>   	.clkdm_name	= "l3_dss_clkdm",
>   	.mpu_irqs	= omap44xx_dss_hdmi_irqs,
>   	.sdma_reqs	= omap44xx_dss_hdmi_sdma_reqs,
> -	.main_clk	= "dss_dss_clk",
> +	.main_clk	= "dss_48mhz_clk",
>   	.prcm = {
>   		.omap4 = {
>   			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
> @@ -1808,7 +1791,7 @@ static struct omap_hwmod omap44xx_dss_venc_hwmod = {
>   	.name		= "dss_venc",
>   	.class		=&omap44xx_venc_hwmod_class,
>   	.clkdm_name	= "l3_dss_clkdm",
> -	.main_clk	= "dss_dss_clk",
> +	.main_clk	= "dss_tv_clk",
>   	.prcm = {
>   		.omap4 = {
>   			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,

[PATCH 4/4] OMAP4: HWMOD: fix DSS reset

[Tomi Valkeinen]

The HWMOD code currently fails to reset dispc and rfbi modules.

This patch adds all DSS clocks as opt clocks for dispc, and sets
HWMOD_CONTROL_OPT_CLKS_IN_RESET. This seems to fix the issue, although
this feels like a hack.

The reason why this patch fixes the reset issue is probably because
dispc is the first DSS module being reset, and by enabling all the
clocks during dispc's reset we also allow the other DSS modules to
finish their reset as a side effect.

Cc: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
---
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c |    9 +++++++++
 1 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 21f03d4..4731f6b 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -1349,8 +1349,15 @@ static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = {
 	&omap44xx_l4_per__dss_dispc,
 };
 
+static struct omap_hwmod_opt_clk dss_dispc_opt_clks[] = {
+	{ .role = "sys_clk", .clk = "dss_sys_clk" },
+	{ .role = "tv_clk", .clk = "dss_tv_clk" },
+	{ .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
+};
+
 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
 	.name		= "dss_dispc",
+	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 	.class		= &omap44xx_dispc_hwmod_class,
 	.clkdm_name	= "l3_dss_clkdm",
 	.mpu_irqs	= omap44xx_dss_dispc_irqs,
@@ -1362,6 +1369,8 @@ static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
 			.context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 		},
 	},
+	.opt_clks	= dss_dispc_opt_clks,
+	.opt_clks_cnt	= ARRAY_SIZE(dss_dispc_opt_clks),
 	.slaves		= omap44xx_dss_dispc_slaves,
 	.slaves_cnt	= ARRAY_SIZE(omap44xx_dss_dispc_slaves),
 	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
-- 
1.7.4.1

Re: [PATCH 4/4] OMAP4: HWMOD: fix DSS reset

[Cousson, Benoit]

Hi Tomi,

On 8/2/2011 12:33 PM, Valkeinen, Tomi wrote:
> The HWMOD code currently fails to reset dispc and rfbi modules.
>
> This patch adds all DSS clocks as opt clocks for dispc, and sets
> HWMOD_CONTROL_OPT_CLKS_IN_RESET. This seems to fix the issue, although
> this feels like a hack.

Enabling the opt clock for a proper reset seems to be a feature in 
several IPs. GPIO does require the same kind of trick.

> The reason why this patch fixes the reset issue is probably because
> dispc is the first DSS module being reset, and by enabling all the
> clocks during dispc's reset we also allow the other DSS modules to
> finish their reset as a side effect.

That part is a little bit unclear. Did you check that assumption with 
the HW architect?

> Cc: Benoit Cousson<b-cousson@ti.com>
> Signed-off-by: Tomi Valkeinen<tomi.valkeinen@ti.com>
> ---
>   arch/arm/mach-omap2/omap_hwmod_44xx_data.c |    9 +++++++++
>   1 files changed, 9 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
> index 21f03d4..4731f6b 100644
> --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
> +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
> @@ -1349,8 +1349,15 @@ static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = {
>   	&omap44xx_l4_per__dss_dispc,
>   };
>
> +static struct omap_hwmod_opt_clk dss_dispc_opt_clks[] = {
> +	{ .role = "sys_clk", .clk = "dss_sys_clk" },
> +	{ .role = "tv_clk", .clk = "dss_tv_clk" },
> +	{ .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
> +};
> +

It seems that your are adding back the optional clocks your remove the 
patch before. Is it done on purpose?

Benoit

>   static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
>   	.name		= "dss_dispc",
> +	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
>   	.class		=&omap44xx_dispc_hwmod_class,
>   	.clkdm_name	= "l3_dss_clkdm",
>   	.mpu_irqs	= omap44xx_dss_dispc_irqs,
> @@ -1362,6 +1369,8 @@ static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
>   			.context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
>   		},
>   	},
> +	.opt_clks	= dss_dispc_opt_clks,
> +	.opt_clks_cnt	= ARRAY_SIZE(dss_dispc_opt_clks),
>   	.slaves		= omap44xx_dss_dispc_slaves,
>   	.slaves_cnt	= ARRAY_SIZE(omap44xx_dss_dispc_slaves),
>   	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),

Re: [PATCH 4/4] OMAP4: HWMOD: fix DSS reset

[Tomi Valkeinen]

On Fri, 2011-08-05 at 16:56 +0200, Cousson, Benoit wrote:
> Hi Tomi,
> 
> On 8/2/2011 12:33 PM, Valkeinen, Tomi wrote:
> > The HWMOD code currently fails to reset dispc and rfbi modules.
> >
> > This patch adds all DSS clocks as opt clocks for dispc, and sets
> > HWMOD_CONTROL_OPT_CLKS_IN_RESET. This seems to fix the issue, although
> > this feels like a hack.
> 
> Enabling the opt clock for a proper reset seems to be a feature in 
> several IPs. GPIO does require the same kind of trick.
> 
> > The reason why this patch fixes the reset issue is probably because 
> > dispc is the first DSS module being reset, and by enabling all the
> > clocks during dispc's reset we also allow the other DSS modules to
> > finish their reset as a side effect.
> 
> That part is a little bit unclear. Did you check that assumption with 
> the HW architect?

No. Do you know a contact we could ask this?

There's more tuning we need to do to DSS reset at some point, and while
we can discuss that later, during testing the custom DSS reset I noticed
that having a custom reset function for dss_core, which enables and
disables all the DSS clocks, the resets of dispc and rfbi go also
through fine.

So that also makes my theory sound true: there's a DSS HW reset at
power-on, but it's just "started", and doesn't proceed without the DSS
clocks. And the reset doesn't totally finish before all the DSS clocks
have been on.

So if we enable the hwmods individually one by one, we never get all the
clocks enabled at the same time, but the DSS reset has probably finished
after enabling/disabling all the hwmods as all clocks have been turned
on at some point. But, for example, dispc is being reset first, and at
that point only the ick and the main fck have been turned on, and the
DSS is still in some kind of "not-quite-reseted" state, causing dispc
reset fail.

> > Cc: Benoit Cousson<b-cousson@ti.com>
> > Signed-off-by: Tomi Valkeinen<tomi.valkeinen@ti.com>
> > ---
> >   arch/arm/mach-omap2/omap_hwmod_44xx_data.c |    9 +++++++++
> >   1 files changed, 9 insertions(+), 0 deletions(-)
> >
> > diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
> > index 21f03d4..4731f6b 100644
> > --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
> > +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
> > @@ -1349,8 +1349,15 @@ static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = {
> >   	&omap44xx_l4_per__dss_dispc,
> >   };
> >
> > +static struct omap_hwmod_opt_clk dss_dispc_opt_clks[] = {
> > +	{ .role = "sys_clk", .clk = "dss_sys_clk" },
> > +	{ .role = "tv_clk", .clk = "dss_tv_clk" },
> > +	{ .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
> > +};
> > +
> 
> It seems that your are adding back the optional clocks your remove the 
> patch before. Is it done on purpose?

Yes. It's an extra remove/add, true, but I wanted to make the patches
independent. The previous patch removes the opt-clocks, because they are
extra in a sense that the driver doesn't use them. Then we are left with
the reset problem. This patch tries to fix the reset problem by adding
these opt-clocks back and setting the flag.

So my point was mainly to make this fourth patch easily changeable to
something else, if this approach is not good.

And I've been thinking that perhaps a simple custom reset function for
dss_core would be cleaner here. We would add the opt-clocks to dss_core
(instead of dss_dispc), and the custom reset function would enable all
DSS clocks, check the DSS reset status, and disable the clocks. Then it
would be somewhat similar than OMAP2/3. Or can the HWMOD fmwk do that
already? Is it possible to have a reset which only enables the clocks
and checks the reset status?

I can try that out and send a patch, if it sounds ok to you.

 Tomi

Re: [PATCH 4/4] OMAP4: HWMOD: fix DSS reset

[Cousson, Benoit]

On 8/5/2011 5:48 PM, Valkeinen, Tomi wrote:
> On Fri, 2011-08-05 at 16:56 +0200, Cousson, Benoit wrote:
>> Hi Tomi,
>>
>> On 8/2/2011 12:33 PM, Valkeinen, Tomi wrote:
>>> The HWMOD code currently fails to reset dispc and rfbi modules.
>>>
>>> This patch adds all DSS clocks as opt clocks for dispc, and sets
>>> HWMOD_CONTROL_OPT_CLKS_IN_RESET. This seems to fix the issue, although
>>> this feels like a hack.
>>
>> Enabling the opt clock for a proper reset seems to be a feature in
>> several IPs. GPIO does require the same kind of trick.
>>
>>> The reason why this patch fixes the reset issue is probably because
>>> dispc is the first DSS module being reset, and by enabling all the
>>> clocks during dispc's reset we also allow the other DSS modules to
>>> finish their reset as a side effect.
>>
>> That part is a little bit unclear. Did you check that assumption with
>> the HW architect?
>
> No. Do you know a contact we could ask this?
>
> There's more tuning we need to do to DSS reset at some point, and while
> we can discuss that later, during testing the custom DSS reset I noticed
> that having a custom reset function for dss_core, which enables and
> disables all the DSS clocks, the resets of dispc and rfbi go also
> through fine.
>
> So that also makes my theory sound true: there's a DSS HW reset at
> power-on, but it's just "started", and doesn't proceed without the DSS
> clocks. And the reset doesn't totally finish before all the DSS clocks
> have been on.
>
> So if we enable the hwmods individually one by one, we never get all the
> clocks enabled at the same time, but the DSS reset has probably finished
> after enabling/disabling all the hwmods as all clocks have been turned
> on at some point. But, for example, dispc is being reset first, and at
> that point only the ick and the main fck have been turned on, and the
> DSS is still in some kind of "not-quite-reseted" state, causing dispc
> reset fail.
>
>>> Cc: Benoit Cousson<b-cousson@ti.com>
>>> Signed-off-by: Tomi Valkeinen<tomi.valkeinen@ti.com>
>>> ---
>>>    arch/arm/mach-omap2/omap_hwmod_44xx_data.c |    9 +++++++++
>>>    1 files changed, 9 insertions(+), 0 deletions(-)
>>>
>>> diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
>>> index 21f03d4..4731f6b 100644
>>> --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
>>> +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
>>> @@ -1349,8 +1349,15 @@ static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = {
>>>    	&omap44xx_l4_per__dss_dispc,
>>>    };
>>>
>>> +static struct omap_hwmod_opt_clk dss_dispc_opt_clks[] = {
>>> +	{ .role = "sys_clk", .clk = "dss_sys_clk" },
>>> +	{ .role = "tv_clk", .clk = "dss_tv_clk" },
>>> +	{ .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
>>> +};
>>> +
>>
>> It seems that your are adding back the optional clocks your remove the
>> patch before. Is it done on purpose?
>
> Yes. It's an extra remove/add, true, but I wanted to make the patches
> independent. The previous patch removes the opt-clocks, because they are
> extra in a sense that the driver doesn't use them. Then we are left with
> the reset problem. This patch tries to fix the reset problem by adding
> these opt-clocks back and setting the flag.
>
> So my point was mainly to make this fourth patch easily changeable to
> something else, if this approach is not good.
>
> And I've been thinking that perhaps a simple custom reset function for
> dss_core would be cleaner here. We would add the opt-clocks to dss_core
> (instead of dss_dispc), and the custom reset function would enable all
> DSS clocks, check the DSS reset status, and disable the clocks. Then it
> would be somewhat similar than OMAP2/3. Or can the HWMOD fmwk do that
> already? Is it possible to have a reset which only enables the clocks
> and checks the reset status?

The issue is still the same wrt hwmod, the DSS hierarchy is not encoded, 
so the DSS does not have a clue about its children.
This is the next hwmod fix that should be done for 3.2.

> I can try that out and send a patch, if it sounds ok to you.

That sounds to be the best way for the moment.

Thanks,
Benoit