[PATCH v3 3/6] OMAP3+: use DPLL's round_rate when setting rate

[PATCH v3 3/6] OMAP3+: use DPLL's round_rate when setting rate

[Jon Hunter]

From: Mike Turquette <mturquette@ti.com>

omap3_noncore_dpll_set_rate uses omap2_dpll_round_rate explicitly.  Instead
use the struct clk pointer's round_rate function to allow for DPLL's with
special needs.

Also the rounded rate can differ from target rate, so to better reflect
reality set clk->rate equal to the rounded rate when setting DPLL frequency.
This avoids issues where the DPLL frequency is slightly different than what
debugfs clock tree reports using the old target rate.

An example of both of these needs is DPLL_ABE on OMAP4 which can have a 4x
multiplier on top of the usual MN dividers depending on register settings.
This requires a special round_rate function that might yield a rate
different from the initial target.

Signed-off-by: Mike Turquette <mturquette@ti.com>
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
---
 arch/arm/mach-omap2/dpll3xxx.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index f77022b..73a1595 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -455,7 +455,7 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
 			new_parent = dd->clk_bypass;
 	} else {
 		if (dd->last_rounded_rate != rate)
-			omap2_dpll_round_rate(clk, rate);
+			rate = clk->round_rate(clk, rate);
 
 		if (dd->last_rounded_rate == 0)
 			return -EINVAL;
-- 
1.7.4.1

Re: [PATCH v3 3/6] OMAP3+: use DPLL's round_rate when setting rate

[Paul Walmsley]

Hi,

On Fri, 16 Sep 2011, Jon Hunter wrote:

> From: Mike Turquette <mturquette@ti.com>
> 
> omap3_noncore_dpll_set_rate uses omap2_dpll_round_rate explicitly.  Instead
> use the struct clk pointer's round_rate function to allow for DPLL's with
> special needs.
> 
> Also the rounded rate can differ from target rate, so to better reflect
> reality set clk->rate equal to the rounded rate when setting DPLL frequency.
> This avoids issues where the DPLL frequency is slightly different than what
> debugfs clock tree reports using the old target rate.
> 
> An example of both of these needs is DPLL_ABE on OMAP4 which can have a 4x
> multiplier on top of the usual MN dividers depending on register settings.
> This requires a special round_rate function that might yield a rate
> different from the initial target.
> 
> Signed-off-by: Mike Turquette <mturquette@ti.com>
> Signed-off-by: Jon Hunter <jon-hunter@ti.com>

The two separate changes in this patch have been separated out into two 
patches - both included below.  Please let me know if you have any 
comments; otherwise, I'll queue for 3.2.


- Paul

From: Mike Turquette <mturquette@ti.com>
Date: Wed, 28 Sep 2011 00:00:32 -0600
Subject: [PATCH] ARM: OMAP3+: dpll: use DPLL's round_rate when setting rate

omap3_noncore_dpll_set_rate uses omap2_dpll_round_rate explicitly.  Instead
use the struct clk pointer's round_rate function to allow for DPLL's with
special needs.

An example of a clock that requires this is DPLL_ABE on OMAP4 which
can have a 4x multiplier on top of the usual MN dividers depending on
register settings.  This requires a special round_rate function that
might yield a rate different from the initial target.

Signed-off-by: Mike Turquette <mturquette@ti.com>
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
[paul@pwsan.com: split rate assignment portion into a separate patch]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
 arch/arm/mach-omap2/dpll3xxx.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index f77022b..6b0fa37 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -455,7 +455,7 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
 			new_parent = dd->clk_bypass;
 	} else {
 		if (dd->last_rounded_rate != rate)
-			omap2_dpll_round_rate(clk, rate);
+			clk->round_rate(clk, rate);
 
 		if (dd->last_rounded_rate == 0)
 			return -EINVAL;
-- 
1.7.6.3


--------------------

From: Mike Turquette <mturquette@ti.com>
Date: Wed, 28 Sep 2011 00:00:32 -0600
Subject: [PATCH] ARM: OMAP3+: dpll: assign clk rate from rounded rate during
 rate set

The rounded rate can differ from target rate, so to better reflect
reality set clk->rate equal to the rounded rate when setting DPLL frequency.
This avoids issues where the DPLL frequency is slightly different than what
debugfs clock tree reports using the old target rate.

An example of a clock that requires this is DPLL_ABE on OMAP4 which
can have a 4x multiplier on top of the usual MN dividers depending on
register settings.  This requires a special round_rate function that
might yield a rate different from the initial target.

Signed-off-by: Mike Turquette <mturquette@ti.com>
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
 arch/arm/mach-omap2/dpll3xxx.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index 6b0fa37..73a1595 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -455,7 +455,7 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
 			new_parent = dd->clk_bypass;
 	} else {
 		if (dd->last_rounded_rate != rate)
-			clk->round_rate(clk, rate);
+			rate = clk->round_rate(clk, rate);
 
 		if (dd->last_rounded_rate == 0)
 			return -EINVAL;
-- 
1.7.6.3

Re: [PATCH v3 3/6] OMAP3+: use DPLL's round_rate when setting rate

[Jon Hunter]

Hi Paul,

On 9/28/2011 2:02, Paul Walmsley wrote:
> Hi,
>
> On Fri, 16 Sep 2011, Jon Hunter wrote:
>
>> From: Mike Turquette<mturquette@ti.com>
>>
>> omap3_noncore_dpll_set_rate uses omap2_dpll_round_rate explicitly.  Instead
>> use the struct clk pointer's round_rate function to allow for DPLL's with
>> special needs.
>>
>> Also the rounded rate can differ from target rate, so to better reflect
>> reality set clk->rate equal to the rounded rate when setting DPLL frequency.
>> This avoids issues where the DPLL frequency is slightly different than what
>> debugfs clock tree reports using the old target rate.
>>
>> An example of both of these needs is DPLL_ABE on OMAP4 which can have a 4x
>> multiplier on top of the usual MN dividers depending on register settings.
>> This requires a special round_rate function that might yield a rate
>> different from the initial target.
>>
>> Signed-off-by: Mike Turquette<mturquette@ti.com>
>> Signed-off-by: Jon Hunter<jon-hunter@ti.com>
>
> The two separate changes in this patch have been separated out into two
> patches - both included below.  Please let me know if you have any
> comments; otherwise, I'll queue for 3.2.

Yes, looks good to me. Thanks. Jon

Re: [PATCH v3 3/6] OMAP3+: use DPLL's round_rate when setting rate

[Turquette, Mike]

On Wed, Sep 28, 2011 at 12:02 AM, Paul Walmsley <paul@pwsan.com> wrote:
> Hi,
>
> On Fri, 16 Sep 2011, Jon Hunter wrote:
>
>> From: Mike Turquette <mturquette@ti.com>
>>
>> omap3_noncore_dpll_set_rate uses omap2_dpll_round_rate explicitly.  Instead
>> use the struct clk pointer's round_rate function to allow for DPLL's with
>> special needs.
>>
>> Also the rounded rate can differ from target rate, so to better reflect
>> reality set clk->rate equal to the rounded rate when setting DPLL frequency.
>> This avoids issues where the DPLL frequency is slightly different than what
>> debugfs clock tree reports using the old target rate.
>>
>> An example of both of these needs is DPLL_ABE on OMAP4 which can have a 4x
>> multiplier on top of the usual MN dividers depending on register settings.
>> This requires a special round_rate function that might yield a rate
>> different from the initial target.
>>
>> Signed-off-by: Mike Turquette <mturquette@ti.com>
>> Signed-off-by: Jon Hunter <jon-hunter@ti.com>
>
> The two separate changes in this patch have been separated out into two
> patches - both included below.  Please let me know if you have any
> comments; otherwise, I'll queue for 3.2.

The split patches look good to me.  I have another patch which does a
similar thing (converts omap2_get_dpll_rate use to clk->recalc) which
fixes yet more bugs that plague DPLL_ABE.  Will send across shortly;
hopefully can make it into 3.2?

Regards,
Mike
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[PATCH] OMAP2+: clock: use clock's recalc in DPLL handling

[Mike Turquette]

Not all DPLLs are identical; some require special consideration such as
OMAP4's ABE DPLL, which can have an additional 4x multiplier added to
it's clock rate based on programming the REGM4XEN bit in it's CLKMODE
register.

Unfortunately the clock framework makes a few assumptions that all DPLLs
can have their rates calculated the same way which has led to incorrect
rates for OMAP4's DPLL_ABE in some cases.  This patch fixes the same by
replacing explicit calls to omap2_dpll_get_rate with clk->recalc if
.recalc is populated for a clock.  If .recalc is NULL then fall back to
omap2_dpll_get_rate.

Reported-by: Misael Lopez Cruz <misael.lopez@ti.com>
Signed-off-by: Mike Turquette <mturquette@ti.com>
---
 arch/arm/mach-omap2/dpll3xxx.c |    6 ++++--
 1 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index f77022b..193868d 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -390,7 +390,8 @@ int omap3_noncore_dpll_enable(struct clk *clk)
 	 * propagating?
 	 */
 	if (!r)
-		clk->rate = omap2_get_dpll_rate(clk);
+		clk->rate = (clk->recalc) ? clk->recalc(clk) :
+			omap2_get_dpll_rate(clk);
 
 	return r;
 }
@@ -435,7 +436,8 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
 	if (!dd)
 		return -EINVAL;
 
-	if (rate == omap2_get_dpll_rate(clk))
+	if (rate == ((clk->recalc) ? clk->recalc(clk) :
+				omap2_get_dpll_rate(clk)))
 		return 0;
 
 	/*
-- 
1.7.4.1

Re: [PATCH] OMAP2+: clock: use clock's recalc in DPLL handling

[Paul Walmsley]

Hi

On Thu, 29 Sep 2011, Mike Turquette wrote:

> Not all DPLLs are identical; some require special consideration such as
> OMAP4's ABE DPLL, which can have an additional 4x multiplier added to
> it's clock rate based on programming the REGM4XEN bit in it's CLKMODE
> register.
> 
> Unfortunately the clock framework makes a few assumptions that all DPLLs
> can have their rates calculated the same way which has led to incorrect
> rates for OMAP4's DPLL_ABE in some cases.  This patch fixes the same by
> replacing explicit calls to omap2_dpll_get_rate with clk->recalc if
> .recalc is populated for a clock.  If .recalc is NULL then fall back to
> omap2_dpll_get_rate.
> 
> Reported-by: Misael Lopez Cruz <misael.lopez@ti.com>
> Signed-off-by: Mike Turquette <mturquette@ti.com>

The conditional in the second hunk of this patch has been simplified for 
readability.  Updated patch below.  Please let me know if I screwed 
something up.  Otherwise, queued for 3.2 fixes.

thanks


- Paul

From: Mike Turquette <mturquette@ti.com>
Date: Thu, 29 Sep 2011 17:51:28 -0700
Subject: [PATCH] ARM: OMAP2+: clock: use clock's recalc in DPLL handling

Not all DPLLs are identical; some require special consideration such as
OMAP4's ABE DPLL, which can have an additional 4x multiplier added to
it's clock rate based on programming the REGM4XEN bit in it's CLKMODE
register.

Unfortunately the clock framework makes a few assumptions that all DPLLs
can have their rates calculated the same way which has led to incorrect
rates for OMAP4's DPLL_ABE in some cases.  This patch fixes the same by
replacing explicit calls to omap2_dpll_get_rate with clk->recalc if
.recalc is populated for a clock.  If .recalc is NULL then fall back to
omap2_dpll_get_rate.

Reported-by: Misael Lopez Cruz <misael.lopez@ti.com>
Signed-off-by: Mike Turquette <mturquette@ti.com>
[paul@pwsan.com: simplified conditional]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
 arch/arm/mach-omap2/dpll3xxx.c |    7 +++++--
 1 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index f77022b..fe4533f 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -390,7 +390,8 @@ int omap3_noncore_dpll_enable(struct clk *clk)
 	 * propagating?
 	 */
 	if (!r)
-		clk->rate = omap2_get_dpll_rate(clk);
+		clk->rate = (clk->recalc) ? clk->recalc(clk) :
+			omap2_get_dpll_rate(clk);
 
 	return r;
 }
@@ -425,6 +426,7 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
 {
 	struct clk *new_parent = NULL;
 	u16 freqsel = 0;
+	unsigned long hw_rate;
 	struct dpll_data *dd;
 	int ret;
 
@@ -435,7 +437,8 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
 	if (!dd)
 		return -EINVAL;
 
-	if (rate == omap2_get_dpll_rate(clk))
+	hw_rate = (clk->recalc) ? clk->recalc(clk) : omap2_get_dpll_rate(clk);
+	if (rate == hw_rate)
 		return 0;
 
 	/*
-- 
1.7.6.3

Re: [PATCH] OMAP2+: clock: use clock's recalc in DPLL handling

[Turquette, Mike]

On Thu, Sep 29, 2011 at 6:26 PM, Paul Walmsley <paul@pwsan.com> wrote:
> Hi
>
> On Thu, 29 Sep 2011, Mike Turquette wrote:
>
>> Not all DPLLs are identical; some require special consideration such as
>> OMAP4's ABE DPLL, which can have an additional 4x multiplier added to
>> it's clock rate based on programming the REGM4XEN bit in it's CLKMODE
>> register.
>>
>> Unfortunately the clock framework makes a few assumptions that all DPLLs
>> can have their rates calculated the same way which has led to incorrect
>> rates for OMAP4's DPLL_ABE in some cases.  This patch fixes the same by
>> replacing explicit calls to omap2_dpll_get_rate with clk->recalc if
>> .recalc is populated for a clock.  If .recalc is NULL then fall back to
>> omap2_dpll_get_rate.
>>
>> Reported-by: Misael Lopez Cruz <misael.lopez@ti.com>
>> Signed-off-by: Mike Turquette <mturquette@ti.com>
>
> The conditional in the second hunk of this patch has been simplified for
> readability.  Updated patch below.  Please let me know if I screwed
> something up.  Otherwise, queued for 3.2 fixes.

Looks good to me.

Regards,
Mike

> thanks
>
>
> - Paul
>
> From: Mike Turquette <mturquette@ti.com>
> Date: Thu, 29 Sep 2011 17:51:28 -0700
> Subject: [PATCH] ARM: OMAP2+: clock: use clock's recalc in DPLL handling
>
> Not all DPLLs are identical; some require special consideration such as
> OMAP4's ABE DPLL, which can have an additional 4x multiplier added to
> it's clock rate based on programming the REGM4XEN bit in it's CLKMODE
> register.
>
> Unfortunately the clock framework makes a few assumptions that all DPLLs
> can have their rates calculated the same way which has led to incorrect
> rates for OMAP4's DPLL_ABE in some cases.  This patch fixes the same by
> replacing explicit calls to omap2_dpll_get_rate with clk->recalc if
> .recalc is populated for a clock.  If .recalc is NULL then fall back to
> omap2_dpll_get_rate.
>
> Reported-by: Misael Lopez Cruz <misael.lopez@ti.com>
> Signed-off-by: Mike Turquette <mturquette@ti.com>
> [paul@pwsan.com: simplified conditional]
> Signed-off-by: Paul Walmsley <paul@pwsan.com>
> ---
>  arch/arm/mach-omap2/dpll3xxx.c |    7 +++++--
>  1 files changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
> index f77022b..fe4533f 100644
> --- a/arch/arm/mach-omap2/dpll3xxx.c
> +++ b/arch/arm/mach-omap2/dpll3xxx.c
> @@ -390,7 +390,8 @@ int omap3_noncore_dpll_enable(struct clk *clk)
>         * propagating?
>         */
>        if (!r)
> -               clk->rate = omap2_get_dpll_rate(clk);
> +               clk->rate = (clk->recalc) ? clk->recalc(clk) :
> +                       omap2_get_dpll_rate(clk);
>
>        return r;
>  }
> @@ -425,6 +426,7 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
>  {
>        struct clk *new_parent = NULL;
>        u16 freqsel = 0;
> +       unsigned long hw_rate;
>        struct dpll_data *dd;
>        int ret;
>
> @@ -435,7 +437,8 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
>        if (!dd)
>                return -EINVAL;
>
> -       if (rate == omap2_get_dpll_rate(clk))
> +       hw_rate = (clk->recalc) ? clk->recalc(clk) : omap2_get_dpll_rate(clk);
> +       if (rate == hw_rate)
>                return 0;
>
>        /*
> --
> 1.7.6.3
>
>
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Re: [PATCH] OMAP2+: clock: use clock's recalc in DPLL handling

[Paul Walmsley]

On Thu, 29 Sep 2011, Mike Turquette wrote:

> Not all DPLLs are identical; some require special consideration such as
> OMAP4's ABE DPLL, which can have an additional 4x multiplier added to
> it's clock rate based on programming the REGM4XEN bit in it's CLKMODE
> register.
> 
> Unfortunately the clock framework makes a few assumptions that all DPLLs
> can have their rates calculated the same way which has led to incorrect
> rates for OMAP4's DPLL_ABE in some cases.  This patch fixes the same by
> replacing explicit calls to omap2_dpll_get_rate with clk->recalc if
> .recalc is populated for a clock.  If .recalc is NULL then fall back to
> omap2_dpll_get_rate.
> 
> Reported-by: Misael Lopez Cruz <misael.lopez@ti.com>
> Signed-off-by: Mike Turquette <mturquette@ti.com>

I've merged this patch with Jon's "ARM: OMAP3+: dpll: use DPLLs recalc 
function instead of omap2_get_dpll_rate" patch, which does almost exactly 
the same thing, just without the conditionals on clk->recalc.  Updated 
patch below.  Please let me know if you think I should change anything 
about the changelog.


- Paul

From: Jon Hunter <jon-hunter@ti.com>
Date: Fri, 7 Oct 2011 00:53:01 -0600
Subject: [PATCH] ARM: OMAP3+: dpll: use DPLLs recalc function instead of
 omap2_get_dpll_rate

This is a continuation of Mike Turquette's patch "OMAP3+: use
DPLL's round_rate when setting rate".

omap3_noncore_dpll_set_rate() and omap3_noncore_dpll_enable() call
omap2_get_dpll_rate() explicitly. It may be necessary for some
DPLLs to use a different function and so use the DPLLs recalc()
function pointer instead.

An example is the DPLL_ABE on OMAP4 which can have a 4X multiplier
in addition to the usual MN multipler and dividers and therefore
uses a different round_rate and recalc function.

Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Cc: Mike Turquette <mturquette@ti.com>
Cc: Misael Lopez Cruz <misael.lopez@ti.com>
[paul@pwsan.com: merged this patch with Mike's "use clock's recalc in DPLL
 handling" patch; also reported by Misael]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
 arch/arm/mach-omap2/dpll3xxx.c |    7 +++++--
 1 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index 73a1595..fc56745 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -390,7 +390,8 @@ int omap3_noncore_dpll_enable(struct clk *clk)
 	 * propagating?
 	 */
 	if (!r)
-		clk->rate = omap2_get_dpll_rate(clk);
+		clk->rate = (clk->recalc) ? clk->recalc(clk) :
+			omap2_get_dpll_rate(clk);
 
 	return r;
 }
@@ -424,6 +425,7 @@ void omap3_noncore_dpll_disable(struct clk *clk)
 int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
 {
 	struct clk *new_parent = NULL;
+	unsigned long hw_rate;
 	u16 freqsel = 0;
 	struct dpll_data *dd;
 	int ret;
@@ -435,7 +437,8 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
 	if (!dd)
 		return -EINVAL;
 
-	if (rate == omap2_get_dpll_rate(clk))
+	hw_rate = (clk->recalc) ? clk->recalc(clk) : omap2_get_dpll_rate(clk);
+	if (rate == hw_rate)
 		return 0;
 
 	/*
-- 
1.7.6.3

Re: [PATCH] OMAP2+: clock: use clock's recalc in DPLL handling

[Turquette, Mike]

On Fri, Oct 7, 2011 at 12:07 AM, Paul Walmsley <paul@pwsan.com> wrote:
> On Thu, 29 Sep 2011, Mike Turquette wrote:
>
>> Not all DPLLs are identical; some require special consideration such as
>> OMAP4's ABE DPLL, which can have an additional 4x multiplier added to
>> it's clock rate based on programming the REGM4XEN bit in it's CLKMODE
>> register.
>>
>> Unfortunately the clock framework makes a few assumptions that all DPLLs
>> can have their rates calculated the same way which has led to incorrect
>> rates for OMAP4's DPLL_ABE in some cases.  This patch fixes the same by
>> replacing explicit calls to omap2_dpll_get_rate with clk->recalc if
>> .recalc is populated for a clock.  If .recalc is NULL then fall back to
>> omap2_dpll_get_rate.
>>
>> Reported-by: Misael Lopez Cruz <misael.lopez@ti.com>
>> Signed-off-by: Mike Turquette <mturquette@ti.com>
>
> I've merged this patch with Jon's "ARM: OMAP3+: dpll: use DPLLs recalc
> function instead of omap2_get_dpll_rate" patch, which does almost exactly
> the same thing, just without the conditionals on clk->recalc.  Updated
> patch below.  Please let me know if you think I should change anything
> about the changelog.

Heh, I hadn't realized we had overlapping patches like that.  Looks fine to me.

Regards,
Mike

> - Paul
>
> From: Jon Hunter <jon-hunter@ti.com>
> Date: Fri, 7 Oct 2011 00:53:01 -0600
> Subject: [PATCH] ARM: OMAP3+: dpll: use DPLLs recalc function instead of
>  omap2_get_dpll_rate
>
> This is a continuation of Mike Turquette's patch "OMAP3+: use
> DPLL's round_rate when setting rate".
>
> omap3_noncore_dpll_set_rate() and omap3_noncore_dpll_enable() call
> omap2_get_dpll_rate() explicitly. It may be necessary for some
> DPLLs to use a different function and so use the DPLLs recalc()
> function pointer instead.
>
> An example is the DPLL_ABE on OMAP4 which can have a 4X multiplier
> in addition to the usual MN multipler and dividers and therefore
> uses a different round_rate and recalc function.
>
> Signed-off-by: Jon Hunter <jon-hunter@ti.com>
> Cc: Mike Turquette <mturquette@ti.com>
> Cc: Misael Lopez Cruz <misael.lopez@ti.com>
> [paul@pwsan.com: merged this patch with Mike's "use clock's recalc in DPLL
>  handling" patch; also reported by Misael]
> Signed-off-by: Paul Walmsley <paul@pwsan.com>
> ---
>  arch/arm/mach-omap2/dpll3xxx.c |    7 +++++--
>  1 files changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
> index 73a1595..fc56745 100644
> --- a/arch/arm/mach-omap2/dpll3xxx.c
> +++ b/arch/arm/mach-omap2/dpll3xxx.c
> @@ -390,7 +390,8 @@ int omap3_noncore_dpll_enable(struct clk *clk)
>         * propagating?
>         */
>        if (!r)
> -               clk->rate = omap2_get_dpll_rate(clk);
> +               clk->rate = (clk->recalc) ? clk->recalc(clk) :
> +                       omap2_get_dpll_rate(clk);
>
>        return r;
>  }
> @@ -424,6 +425,7 @@ void omap3_noncore_dpll_disable(struct clk *clk)
>  int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
>  {
>        struct clk *new_parent = NULL;
> +       unsigned long hw_rate;
>        u16 freqsel = 0;
>        struct dpll_data *dd;
>        int ret;
> @@ -435,7 +437,8 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
>        if (!dd)
>                return -EINVAL;
>
> -       if (rate == omap2_get_dpll_rate(clk))
> +       hw_rate = (clk->recalc) ? clk->recalc(clk) : omap2_get_dpll_rate(clk);
> +       if (rate == hw_rate)
>                return 0;
>
>        /*
> --
> 1.7.6.3
>
>
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