* [PATCH 0/5] ARM: OMAP: Few device tree patches for 3.7
@ 2012-08-13 11:00 Santosh Shilimkar
2012-08-13 11:00 ` [PATCH 1/5] dt: device tree bindings for LPDDR2 memories Santosh Shilimkar
` (5 more replies)
0 siblings, 6 replies; 18+ messages in thread
From: Santosh Shilimkar @ 2012-08-13 11:00 UTC (permalink / raw)
To: linux-omap; +Cc: linux-arm-kernel, tony, Santosh Shilimkar
These are the few device tree related patches which has been posted and
reviewed on the list. They are intended for 3.7 merge window but I am
posting them early enough to get into linux-next and linux-omap for testing.
The following changes since commit 0d7614f09c1ebdbaa1599a5aba7593f147bf96ee:
Linux 3.6-rc1 (2012-08-02 16:38:10 -0700)
are available in the git repository at:
git://github.com/SantoshShilimkar/linux.git for_3.7/omap_dt
for you to fetch changes up to bedee5fcb18062dfc933e0971e67fd6889c6446d:
ARM: OMAP4: Add local timer support for Device Tree (2012-08-13 11:59:26 +0530)
----------------------------------------------------------------
Aneesh V (3):
dt: device tree bindings for LPDDR2 memories
dt: emif: device tree bindings for TI's EMIF sdram controller
ARM: dts: EMIF and LPDDR2 device tree data for OMAP4 boards
Santosh Shilimkar (2):
ARM: OMAP4: Add L2 Cache Controller in Device Tree
ARM: OMAP4: Add local timer support for Device Tree
.../devicetree/bindings/lpddr2/lpddr2-timings.txt | 52 ++++++++++
.../devicetree/bindings/lpddr2/lpddr2.txt | 102 ++++++++++++++++++++
.../bindings/memory-controllers/ti/emif.txt | 55 +++++++++++
arch/arm/boot/dts/elpida_ecb240abacn.dtsi | 67 +++++++++++++
arch/arm/boot/dts/omap4-panda.dts | 13 +++
arch/arm/boot/dts/omap4-sdp.dts | 13 +++
arch/arm/boot/dts/omap4.dtsi | 31 ++++++
arch/arm/mach-omap2/omap4-common.c | 6 +-
arch/arm/mach-omap2/timer.c | 6 ++
9 files changed, 344 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/lpddr2/lpddr2-timings.txt
create mode 100644 Documentation/devicetree/bindings/lpddr2/lpddr2.txt
create mode 100644 Documentation/devicetree/bindings/memory-controllers/ti/emif.txt
create mode 100644 arch/arm/boot/dts/elpida_ecb240abacn.dtsi
Aneesh V (3):
dt: device tree bindings for LPDDR2 memories
dt: emif: device tree bindings for TI's EMIF sdram controller
ARM: dts: EMIF and LPDDR2 device tree data for OMAP4 boards
Santosh Shilimkar (2):
ARM: OMAP4: Add L2 Cache Controller in Device Tree
ARM: OMAP4: Add local timer support for Device Tree
.../devicetree/bindings/lpddr2/lpddr2-timings.txt | 52 ++++++++++
.../devicetree/bindings/lpddr2/lpddr2.txt | 102 ++++++++++++++++++++
.../bindings/memory-controllers/ti/emif.txt | 55 +++++++++++
arch/arm/boot/dts/elpida_ecb240abacn.dtsi | 67 +++++++++++++
arch/arm/boot/dts/omap4-panda.dts | 13 +++
arch/arm/boot/dts/omap4-sdp.dts | 13 +++
arch/arm/boot/dts/omap4.dtsi | 31 ++++++
arch/arm/mach-omap2/omap4-common.c | 6 +-
arch/arm/mach-omap2/timer.c | 6 ++
9 files changed, 344 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/lpddr2/lpddr2-timings.txt
create mode 100644 Documentation/devicetree/bindings/lpddr2/lpddr2.txt
create mode 100644 Documentation/devicetree/bindings/memory-controllers/ti/emif.txt
create mode 100644 arch/arm/boot/dts/elpida_ecb240abacn.dtsi
--
1.7.9.5
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 1/5] dt: device tree bindings for LPDDR2 memories
2012-08-13 11:00 [PATCH 0/5] ARM: OMAP: Few device tree patches for 3.7 Santosh Shilimkar
@ 2012-08-13 11:00 ` Santosh Shilimkar
2012-08-13 11:00 ` [PATCH 2/5] dt: emif: device tree bindings for TI's EMIF sdram controller Santosh Shilimkar
` (4 subsequent siblings)
5 siblings, 0 replies; 18+ messages in thread
From: Santosh Shilimkar @ 2012-08-13 11:00 UTC (permalink / raw)
To: linux-omap; +Cc: linux-arm-kernel, tony, Aneesh V, Santosh Shilimkar
From: Aneesh V <aneesh@ti.com>
device tree bindings for LPDDR2 SDRAM memories compliant
to JESD209-2 standard.
The 'lpddr2' binding in-turn uses another binding 'lpddr2-timings'
for specifying the AC timing parameters of the memory device at
different speed-bins.
Reviewed-by: Benoit Cousson <b-cousson@ti.com>
Reviewed-by: Grant Likely <grant.likely@secretlab.ca>
Tested-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Aneesh V <aneesh@ti.com>
[santosh.shilimkar@ti.com: Rebased against 3.6-rc]
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
.../devicetree/bindings/lpddr2/lpddr2-timings.txt | 52 ++++++++++
.../devicetree/bindings/lpddr2/lpddr2.txt | 102 ++++++++++++++++++++
2 files changed, 154 insertions(+)
create mode 100644 Documentation/devicetree/bindings/lpddr2/lpddr2-timings.txt
create mode 100644 Documentation/devicetree/bindings/lpddr2/lpddr2.txt
diff --git a/Documentation/devicetree/bindings/lpddr2/lpddr2-timings.txt b/Documentation/devicetree/bindings/lpddr2/lpddr2-timings.txt
new file mode 100644
index 0000000..9ceb19e
--- /dev/null
+++ b/Documentation/devicetree/bindings/lpddr2/lpddr2-timings.txt
@@ -0,0 +1,52 @@
+* AC timing parameters of LPDDR2(JESD209-2) memories for a given speed-bin
+
+Required properties:
+- compatible : Should be "jedec,lpddr2-timings"
+- min-freq : minimum DDR clock frequency for the speed-bin. Type is <u32>
+- max-freq : maximum DDR clock frequency for the speed-bin. Type is <u32>
+
+Optional properties:
+
+The following properties represent AC timing parameters from the memory
+data-sheet of the device for a given speed-bin. All these properties are
+of type <u32> and the default unit is ps (pico seconds). Parameters with
+a different unit have a suffix indicating the unit such as 'tRAS-max-ns'
+- tRCD
+- tWR
+- tRAS-min
+- tRRD
+- tWTR
+- tXP
+- tRTP
+- tDQSCK-max
+- tFAW
+- tZQCS
+- tZQinit
+- tRPab
+- tZQCL
+- tCKESR
+- tRAS-max-ns
+- tDQSCK-max-derated
+
+Example:
+
+timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 {
+ compatible = "jedec,lpddr2-timings";
+ min-freq = <10000000>;
+ max-freq = <400000000>;
+ tRPab = <21000>;
+ tRCD = <18000>;
+ tWR = <15000>;
+ tRAS-min = <42000>;
+ tRRD = <10000>;
+ tWTR = <7500>;
+ tXP = <7500>;
+ tRTP = <7500>;
+ tCKESR = <15000>;
+ tDQSCK-max = <5500>;
+ tFAW = <50000>;
+ tZQCS = <90000>;
+ tZQCL = <360000>;
+ tZQinit = <1000000>;
+ tRAS-max-ns = <70000>;
+};
diff --git a/Documentation/devicetree/bindings/lpddr2/lpddr2.txt b/Documentation/devicetree/bindings/lpddr2/lpddr2.txt
new file mode 100644
index 0000000..58354a0
--- /dev/null
+++ b/Documentation/devicetree/bindings/lpddr2/lpddr2.txt
@@ -0,0 +1,102 @@
+* LPDDR2 SDRAM memories compliant to JEDEC JESD209-2
+
+Required properties:
+- compatible : Should be one of - "jedec,lpddr2-nvm", "jedec,lpddr2-s2",
+ "jedec,lpddr2-s4"
+
+ "ti,jedec-lpddr2-s2" should be listed if the memory part is LPDDR2-S2 type
+
+ "ti,jedec-lpddr2-s4" should be listed if the memory part is LPDDR2-S4 type
+
+ "ti,jedec-lpddr2-nvm" should be listed if the memory part is LPDDR2-NVM type
+
+- density : <u32> representing density in Mb (Mega bits)
+
+- io-width : <u32> representing bus width. Possible values are 8, 16, and 32
+
+Optional properties:
+
+The following optional properties represent the minimum value of some AC
+timing parameters of the DDR device in terms of number of clock cycles.
+These values shall be obtained from the device data-sheet.
+- tRRD-min-tck
+- tWTR-min-tck
+- tXP-min-tck
+- tRTP-min-tck
+- tCKE-min-tck
+- tRPab-min-tck
+- tRCD-min-tck
+- tWR-min-tck
+- tRASmin-min-tck
+- tCKESR-min-tck
+- tFAW-min-tck
+
+Child nodes:
+- The lpddr2 node may have one or more child nodes of type "lpddr2-timings".
+ "lpddr2-timings" provides AC timing parameters of the device for
+ a given speed-bin. The user may provide the timings for as many
+ speed-bins as is required. Please see Documentation/devicetree/
+ bindings/lpddr2/lpddr2-timings.txt for more information on "lpddr2-timings"
+
+Example:
+
+elpida_ECB240ABACN : lpddr2 {
+ compatible = "Elpida,ECB240ABACN","jedec,lpddr2-s4";
+ density = <2048>;
+ io-width = <32>;
+
+ tRPab-min-tck = <3>;
+ tRCD-min-tck = <3>;
+ tWR-min-tck = <3>;
+ tRASmin-min-tck = <3>;
+ tRRD-min-tck = <2>;
+ tWTR-min-tck = <2>;
+ tXP-min-tck = <2>;
+ tRTP-min-tck = <2>;
+ tCKE-min-tck = <3>;
+ tCKESR-min-tck = <3>;
+ tFAW-min-tck = <8>;
+
+ timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 {
+ compatible = "jedec,lpddr2-timings";
+ min-freq = <10000000>;
+ max-freq = <400000000>;
+ tRPab = <21000>;
+ tRCD = <18000>;
+ tWR = <15000>;
+ tRAS-min = <42000>;
+ tRRD = <10000>;
+ tWTR = <7500>;
+ tXP = <7500>;
+ tRTP = <7500>;
+ tCKESR = <15000>;
+ tDQSCK-max = <5500>;
+ tFAW = <50000>;
+ tZQCS = <90000>;
+ tZQCL = <360000>;
+ tZQinit = <1000000>;
+ tRAS-max-ns = <70000>;
+ };
+
+ timings_elpida_ECB240ABACN_200mhz: lpddr2-timings@1 {
+ compatible = "jedec,lpddr2-timings";
+ min-freq = <10000000>;
+ max-freq = <200000000>;
+ tRPab = <21000>;
+ tRCD = <18000>;
+ tWR = <15000>;
+ tRAS-min = <42000>;
+ tRRD = <10000>;
+ tWTR = <10000>;
+ tXP = <7500>;
+ tRTP = <7500>;
+ tCKESR = <15000>;
+ tDQSCK-max = <5500>;
+ tFAW = <50000>;
+ tZQCS = <90000>;
+ tZQCL = <360000>;
+ tZQinit = <1000000>;
+ tRAS-max-ns = <70000>;
+ };
+
+}
--
1.7.9.5
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 2/5] dt: emif: device tree bindings for TI's EMIF sdram controller
2012-08-13 11:00 [PATCH 0/5] ARM: OMAP: Few device tree patches for 3.7 Santosh Shilimkar
2012-08-13 11:00 ` [PATCH 1/5] dt: device tree bindings for LPDDR2 memories Santosh Shilimkar
@ 2012-08-13 11:00 ` Santosh Shilimkar
2012-08-13 11:00 ` [PATCH 3/5] ARM: dts: EMIF and LPDDR2 device tree data for OMAP4 boards Santosh Shilimkar
` (3 subsequent siblings)
5 siblings, 0 replies; 18+ messages in thread
From: Santosh Shilimkar @ 2012-08-13 11:00 UTC (permalink / raw)
To: linux-omap; +Cc: linux-arm-kernel, tony, Aneesh V, Santosh Shilimkar
From: Aneesh V <aneesh@ti.com>
EMIF - External Memory Interface - is an SDRAM controller used in
TI SoCs. EMIF supports, based on the IP revision, one or more of
DDR2/DDR3/LPDDR2 protocols. This binding describes a given instance
of the EMIF IP and memory parts attached to it.
Reviewed-by: Benoit Cousson <b-cousson@ti.com>
Reviewed-by: Grant Likely <grant.likely@secretlab.ca>
Tested-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Aneesh V <aneesh@ti.com>
[santosh.shilimkar@ti.com: Rebased against 3.6-rc]
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
.../bindings/memory-controllers/ti/emif.txt | 55 ++++++++++++++++++++
1 file changed, 55 insertions(+)
create mode 100644 Documentation/devicetree/bindings/memory-controllers/ti/emif.txt
diff --git a/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt b/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt
new file mode 100644
index 0000000..938f8e1
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt
@@ -0,0 +1,55 @@
+* EMIF family of TI SDRAM controllers
+
+EMIF - External Memory Interface - is an SDRAM controller used in
+TI SoCs. EMIF supports, based on the IP revision, one or more of
+DDR2/DDR3/LPDDR2 protocols. This binding describes a given instance
+of the EMIF IP and memory parts attached to it.
+
+Required properties:
+- compatible : Should be of the form "ti,emif-<ip-rev>" where <ip-rev>
+ is the IP revision of the specific EMIF instance.
+
+- phy-type : <u32> indicating the DDR phy type. Following are the
+ allowed values
+ <1> : Attila PHY
+ <2> : Intelli PHY
+
+- device-handle : phandle to a "lpddr2" node representing the memory part
+
+- ti,hwmods : For TI hwmods processing and omap device creation
+ the value shall be "emif<n>" where <n> is the number of the EMIF
+ instance with base 1.
+
+Optional properties:
+- cs1-used : Have this property if CS1 of this EMIF
+ instance has a memory part attached to it. If there is a memory
+ part attached to CS1, it should be the same type as the one on CS0,
+ so there is no need to give the details of this memory part.
+
+- cal-resistor-per-cs : Have this property if the board has one
+ calibration resistor per chip-select.
+
+- hw-caps-read-idle-ctrl: Have this property if the controller
+ supports read idle window programming
+
+- hw-caps-dll-calib-ctrl: Have this property if the controller
+ supports dll calibration control
+
+- hw-caps-ll-interface : Have this property if the controller
+ has a low latency interface and corresponding interrupt events
+
+- hw-caps-temp-alert : Have this property if the controller
+ has capability for generating SDRAM temperature alerts
+
+Example:
+
+emif1: emif@0x4c000000 {
+ compatible = "ti,emif-4d";
+ ti,hwmods = "emif2";
+ phy-type = <1>;
+ device-handle = <&elpida_ECB240ABACN>;
+ cs1-used;
+ hw-caps-read-idle-ctrl;
+ hw-caps-ll-interface;
+ hw-caps-temp-alert;
+};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 3/5] ARM: dts: EMIF and LPDDR2 device tree data for OMAP4 boards
2012-08-13 11:00 [PATCH 0/5] ARM: OMAP: Few device tree patches for 3.7 Santosh Shilimkar
2012-08-13 11:00 ` [PATCH 1/5] dt: device tree bindings for LPDDR2 memories Santosh Shilimkar
2012-08-13 11:00 ` [PATCH 2/5] dt: emif: device tree bindings for TI's EMIF sdram controller Santosh Shilimkar
@ 2012-08-13 11:00 ` Santosh Shilimkar
2012-08-13 11:00 ` [PATCH 4/5] ARM: OMAP4: Add L2 Cache Controller in Device Tree Santosh Shilimkar
` (2 subsequent siblings)
5 siblings, 0 replies; 18+ messages in thread
From: Santosh Shilimkar @ 2012-08-13 11:00 UTC (permalink / raw)
To: linux-omap; +Cc: linux-arm-kernel, tony, Aneesh V, Santosh Shilimkar
From: Aneesh V <aneesh@ti.com>
Device tree data for the EMIF sdram controllers in OMAP4
and LPDDR2 memory devices attached to OMAP4 boards.
Reviewed-by: Benoit Cousson <b-cousson@ti.com>
Reviewed-by: Grant Likely <grant.likely@secretlab.ca>
Tested-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Aneesh V <aneesh@ti.com>
[santosh.shilimkar@ti.com: Rebased against 3.6-rc]
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
arch/arm/boot/dts/elpida_ecb240abacn.dtsi | 67 +++++++++++++++++++++++++++++
arch/arm/boot/dts/omap4-panda.dts | 13 ++++++
arch/arm/boot/dts/omap4-sdp.dts | 13 ++++++
arch/arm/boot/dts/omap4.dtsi | 18 ++++++++
4 files changed, 111 insertions(+)
create mode 100644 arch/arm/boot/dts/elpida_ecb240abacn.dtsi
diff --git a/arch/arm/boot/dts/elpida_ecb240abacn.dtsi b/arch/arm/boot/dts/elpida_ecb240abacn.dtsi
new file mode 100644
index 0000000..f97f70f
--- /dev/null
+++ b/arch/arm/boot/dts/elpida_ecb240abacn.dtsi
@@ -0,0 +1,67 @@
+/*
+ * Common devices used in different OMAP boards
+ */
+
+/ {
+ elpida_ECB240ABACN: lpddr2 {
+ compatible = "Elpida,ECB240ABACN","jedec,lpddr2-s4";
+ density = <2048>;
+ io-width = <32>;
+
+ tRPab-min-tck = <3>;
+ tRCD-min-tck = <3>;
+ tWR-min-tck = <3>;
+ tRASmin-min-tck = <3>;
+ tRRD-min-tck = <2>;
+ tWTR-min-tck = <2>;
+ tXP-min-tck = <2>;
+ tRTP-min-tck = <2>;
+ tCKE-min-tck = <3>;
+ tCKESR-min-tck = <3>;
+ tFAW-min-tck = <8>;
+
+ timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 {
+ compatible = "jedec,lpddr2-timings";
+ min-freq = <10000000>;
+ max-freq = <400000000>;
+ tRPab = <21000>;
+ tRCD = <18000>;
+ tWR = <15000>;
+ tRAS-min = <42000>;
+ tRRD = <10000>;
+ tWTR = <7500>;
+ tXP = <7500>;
+ tRTP = <7500>;
+ tCKESR = <15000>;
+ tDQSCK-max = <5500>;
+ tFAW = <50000>;
+ tZQCS = <90000>;
+ tZQCL = <360000>;
+ tZQinit = <1000000>;
+ tRAS-max-ns = <70000>;
+ tDQSCK-max-derated = <6000>;
+ };
+
+ timings_elpida_ECB240ABACN_200mhz: lpddr2-timings@1 {
+ compatible = "jedec,lpddr2-timings";
+ min-freq = <10000000>;
+ max-freq = <200000000>;
+ tRPab = <21000>;
+ tRCD = <18000>;
+ tWR = <15000>;
+ tRAS-min = <42000>;
+ tRRD = <10000>;
+ tWTR = <10000>;
+ tXP = <7500>;
+ tRTP = <7500>;
+ tCKESR = <15000>;
+ tDQSCK-max = <5500>;
+ tFAW = <50000>;
+ tZQCS = <90000>;
+ tZQCL = <360000>;
+ tZQinit = <1000000>;
+ tRAS-max-ns = <70000>;
+ tDQSCK-max-derated = <6000>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/omap4-panda.dts b/arch/arm/boot/dts/omap4-panda.dts
index 9880c12..80cd6cb 100644
--- a/arch/arm/boot/dts/omap4-panda.dts
+++ b/arch/arm/boot/dts/omap4-panda.dts
@@ -8,6 +8,7 @@
/dts-v1/;
/include/ "omap4.dtsi"
+/include/ "elpida_ecb240abacn.dtsi"
/ {
model = "TI OMAP4 PandaBoard";
@@ -56,6 +57,18 @@
"AFML", "Line In",
"AFMR", "Line In";
};
+
+ ocp {
+ emif1: emif@0x4c000000 {
+ cs1-used;
+ device-handle = <&elpida_ECB240ABACN>;
+ };
+
+ emif2: emif@0x4d000000 {
+ cs1-used;
+ device-handle = <&elpida_ECB240ABACN>;
+ };
+ };
};
&i2c1 {
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index 72216e9..b6f8ec2 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -8,6 +8,7 @@
/dts-v1/;
/include/ "omap4.dtsi"
+/include/ "elpida_ecb240abacn.dtsi"
/ {
model = "TI OMAP4 SDP board";
@@ -113,6 +114,18 @@
"DMic", "Digital Mic",
"Digital Mic", "Digital Mic1 Bias";
};
+
+ ocp {
+ emif1: emif@0x4c000000 {
+ cs1-used;
+ device-handle = <&elpida_ECB240ABACN>;
+ };
+
+ emif2: emif@0x4d000000 {
+ cs1-used;
+ device-handle = <&elpida_ECB240ABACN>;
+ };
+ };
};
&i2c1 {
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 04cbbcb..6717c71 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -295,5 +295,23 @@
interrupt-parent = <&gic>;
ti,hwmods = "dmic";
};
+
+ emif1: emif@0x4c000000 {
+ compatible = "ti,emif-4d";
+ ti,hwmods = "emif1";
+ phy-type = <1>;
+ hw-caps-read-idle-ctrl;
+ hw-caps-ll-interface;
+ hw-caps-temp-alert;
+ };
+
+ emif2: emif@0x4d000000 {
+ compatible = "ti,emif-4d";
+ ti,hwmods = "emif2";
+ phy-type = <1>;
+ hw-caps-read-idle-ctrl;
+ hw-caps-ll-interface;
+ hw-caps-temp-alert;
+ };
};
};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 4/5] ARM: OMAP4: Add L2 Cache Controller in Device Tree
2012-08-13 11:00 [PATCH 0/5] ARM: OMAP: Few device tree patches for 3.7 Santosh Shilimkar
` (2 preceding siblings ...)
2012-08-13 11:00 ` [PATCH 3/5] ARM: dts: EMIF and LPDDR2 device tree data for OMAP4 boards Santosh Shilimkar
@ 2012-08-13 11:00 ` Santosh Shilimkar
2012-08-20 13:51 ` Benoit Cousson
2012-08-13 11:00 ` [PATCH 5/5] ARM: OMAP4: Add local timer support for " Santosh Shilimkar
2012-08-23 7:32 ` [PATCH 0/5] ARM: OMAP: Few device tree patches for 3.7 Santosh Shilimkar
5 siblings, 1 reply; 18+ messages in thread
From: Santosh Shilimkar @ 2012-08-13 11:00 UTC (permalink / raw)
To: linux-omap; +Cc: linux-arm-kernel, tony, Santosh Shilimkar, Benoit Cousson
This provides PL310 Level 2 Cache Controller Device Tree
support for OMAP4 based devices.
Cc: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
arch/arm/boot/dts/omap4.dtsi | 7 +++++++
arch/arm/mach-omap2/omap4-common.c | 6 +++++-
2 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 6717c71..cf1efb6 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -36,6 +36,13 @@
};
};
+ L2: l2-cache-controller {
+ compatible = "arm,pl310-cache";
+ reg = <0x48242000 0x1000>;
+ cache-unified;
+ cache-level = <2>;
+ };
+
/*
* The soc node represents the soc top level view. It is uses for IPs
* that are not memory mapped in the MPU view or for the MPU itself.
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index c29dee9..6f95992 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -16,6 +16,7 @@
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/memblock.h>
+#include <linux/of.h>
#include <asm/hardware/gic.h>
#include <asm/hardware/cache-l2x0.h>
@@ -171,7 +172,10 @@ static int __init omap_l2_cache_init(void)
/* Enable PL310 L2 Cache controller */
omap_smc1(0x102, 0x1);
- l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK);
+ if (of_have_populated_dt())
+ l2x0_of_init(aux_ctrl, L2X0_AUX_CTRL_MASK);
+ else
+ l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK);
/*
* Override default outer_cache.disable with a OMAP4
--
1.7.9.5
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 5/5] ARM: OMAP4: Add local timer support for Device Tree
2012-08-13 11:00 [PATCH 0/5] ARM: OMAP: Few device tree patches for 3.7 Santosh Shilimkar
` (3 preceding siblings ...)
2012-08-13 11:00 ` [PATCH 4/5] ARM: OMAP4: Add L2 Cache Controller in Device Tree Santosh Shilimkar
@ 2012-08-13 11:00 ` Santosh Shilimkar
2012-08-23 7:32 ` [PATCH 0/5] ARM: OMAP: Few device tree patches for 3.7 Santosh Shilimkar
5 siblings, 0 replies; 18+ messages in thread
From: Santosh Shilimkar @ 2012-08-13 11:00 UTC (permalink / raw)
To: linux-omap; +Cc: linux-arm-kernel, tony, Santosh Shilimkar, Benoit Cousson
Add cortex-a9 local timer support for all OMAP4 based
SOCs using DT.
Cc: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
arch/arm/boot/dts/omap4.dtsi | 6 ++++++
arch/arm/mach-omap2/timer.c | 6 ++++++
2 files changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index cf1efb6..640d807 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -43,6 +43,12 @@
cache-level = <2>;
};
+ local-timer {
+ compatible = "arm,cortex-a9-twd-timer";
+ reg = <0x48240600 0x20>;
+ interrupts = <1 13 0x304>;
+ };
+
/*
* The soc node represents the soc top level view. It is uses for IPs
* that are not memory mapped in the MPU view or for the MPU itself.
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 2ff6d41..31f9c93 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -36,6 +36,7 @@
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/slab.h>
+#include <linux/of.h>
#include <asm/mach/time.h>
#include <plat/dmtimer.h>
@@ -386,6 +387,11 @@ static void __init omap4_timer_init(void)
if (omap_rev() != OMAP4430_REV_ES1_0) {
int err;
+ if (of_have_populated_dt()) {
+ twd_local_timer_of_register();
+ return;
+ }
+
err = twd_local_timer_register(&twd_local_timer);
if (err)
pr_err("twd_local_timer_register failed %d\n", err);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH 4/5] ARM: OMAP4: Add L2 Cache Controller in Device Tree
2012-08-13 11:00 ` [PATCH 4/5] ARM: OMAP4: Add L2 Cache Controller in Device Tree Santosh Shilimkar
@ 2012-08-20 13:51 ` Benoit Cousson
2012-08-20 15:51 ` Shilimkar, Santosh
2012-08-20 15:59 ` Felipe Balbi
0 siblings, 2 replies; 18+ messages in thread
From: Benoit Cousson @ 2012-08-20 13:51 UTC (permalink / raw)
To: Santosh Shilimkar; +Cc: linux-omap, linux-arm-kernel, tony
Hi Santosh,
On 08/13/2012 01:00 PM, Santosh Shilimkar wrote:
> This provides PL310 Level 2 Cache Controller Device Tree
> support for OMAP4 based devices.
>
> Cc: Benoit Cousson <b-cousson@ti.com>
> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> ---
> arch/arm/boot/dts/omap4.dtsi | 7 +++++++
> arch/arm/mach-omap2/omap4-common.c | 6 +++++-
> 2 files changed, 12 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
> index 6717c71..cf1efb6 100644
> --- a/arch/arm/boot/dts/omap4.dtsi
> +++ b/arch/arm/boot/dts/omap4.dtsi
> @@ -36,6 +36,13 @@
> };
> };
>
> + L2: l2-cache-controller {
The reg offset is missing: l2-cache-controller@48242000
> + compatible = "arm,pl310-cache";
> + reg = <0x48242000 0x1000>;
> + cache-unified;
> + cache-level = <2>;
> + };
> +
In theory, the L2 cache should be referenced from the CPUs.
Here is the way it is done for mpc8541cdc.dts for example:
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,8541@0 {
device_type = "cpu";
reg = <0x0>;
d-cache-line-size = <32>; // 32 bytes
i-cache-line-size = <32>; // 32 bytes
d-cache-size = <0x8000>; // L1, 32K
i-cache-size = <0x8000>; // L1, 32K
timebase-frequency = <0>; // 33 MHz, from uboot
bus-frequency = <0>; // 166 MHz
clock-frequency = <0>; // 825 MHz, from uboot
next-level-cache = <&L2>;
};
};
...
L2: l2-cache-controller@20000 {
compatible = "fsl,mpc8541-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <32>; // 32 bytes
cache-size = <0x40000>; // L2, 256K
interrupt-parent = <&mpic>;
interrupts = <16 2>;
};
Regards,
Benoit
> /*
> * The soc node represents the soc top level view. It is uses for IPs
> * that are not memory mapped in the MPU view or for the MPU itself.
> diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
> index c29dee9..6f95992 100644
> --- a/arch/arm/mach-omap2/omap4-common.c
> +++ b/arch/arm/mach-omap2/omap4-common.c
> @@ -16,6 +16,7 @@
> #include <linux/io.h>
> #include <linux/platform_device.h>
> #include <linux/memblock.h>
> +#include <linux/of.h>
>
> #include <asm/hardware/gic.h>
> #include <asm/hardware/cache-l2x0.h>
> @@ -171,7 +172,10 @@ static int __init omap_l2_cache_init(void)
> /* Enable PL310 L2 Cache controller */
> omap_smc1(0x102, 0x1);
>
> - l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK);
> + if (of_have_populated_dt())
> + l2x0_of_init(aux_ctrl, L2X0_AUX_CTRL_MASK);
> + else
> + l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK);
>
> /*
> * Override default outer_cache.disable with a OMAP4
>
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 4/5] ARM: OMAP4: Add L2 Cache Controller in Device Tree
2012-08-20 13:51 ` Benoit Cousson
@ 2012-08-20 15:51 ` Shilimkar, Santosh
2012-08-21 9:41 ` Shilimkar, Santosh
2012-08-20 15:59 ` Felipe Balbi
1 sibling, 1 reply; 18+ messages in thread
From: Shilimkar, Santosh @ 2012-08-20 15:51 UTC (permalink / raw)
To: Benoit Cousson; +Cc: linux-omap, linux-arm-kernel, tony
On Mon, Aug 20, 2012 at 7:21 PM, Benoit Cousson <b-cousson@ti.com> wrote:
> Hi Santosh,
>
> On 08/13/2012 01:00 PM, Santosh Shilimkar wrote:
>> This provides PL310 Level 2 Cache Controller Device Tree
>> support for OMAP4 based devices.
>>
>> Cc: Benoit Cousson <b-cousson@ti.com>
>> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
>> ---
>> arch/arm/boot/dts/omap4.dtsi | 7 +++++++
>> arch/arm/mach-omap2/omap4-common.c | 6 +++++-
>> 2 files changed, 12 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
>> index 6717c71..cf1efb6 100644
>> --- a/arch/arm/boot/dts/omap4.dtsi
>> +++ b/arch/arm/boot/dts/omap4.dtsi
>> @@ -36,6 +36,13 @@
>> };
>> };
>>
>
>> + L2: l2-cache-controller {
>
> The reg offset is missing: l2-cache-controller@48242000
>
>> + compatible = "arm,pl310-cache";
>> + reg = <0x48242000 0x1000>;
>> + cache-unified;
>> + cache-level = <2>;
>> + };
>> +
>
> In theory, the L2 cache should be referenced from the CPUs.
>
Agree.
> Here is the way it is done for mpc8541cdc.dts for example:
>
I will move it under CPU. Thanks
regards
Santosh
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 4/5] ARM: OMAP4: Add L2 Cache Controller in Device Tree
2012-08-20 13:51 ` Benoit Cousson
2012-08-20 15:51 ` Shilimkar, Santosh
@ 2012-08-20 15:59 ` Felipe Balbi
1 sibling, 0 replies; 18+ messages in thread
From: Felipe Balbi @ 2012-08-20 15:59 UTC (permalink / raw)
To: Benoit Cousson; +Cc: Santosh Shilimkar, linux-omap, linux-arm-kernel, tony
[-- Attachment #1: Type: text/plain, Size: 1196 bytes --]
On Mon, Aug 20, 2012 at 03:51:43PM +0200, Benoit Cousson wrote:
> > + compatible = "arm,pl310-cache";
> > + reg = <0x48242000 0x1000>;
> > + cache-unified;
> > + cache-level = <2>;
> > + };
> > +
>
> In theory, the L2 cache should be referenced from the CPUs.
>
> Here is the way it is done for mpc8541cdc.dts for example:
>
> cpus {
> #address-cells = <1>;
> #size-cells = <0>;
>
> PowerPC,8541@0 {
> device_type = "cpu";
> reg = <0x0>;
> d-cache-line-size = <32>; // 32 bytes
> i-cache-line-size = <32>; // 32 bytes
> d-cache-size = <0x8000>; // L1, 32K
> i-cache-size = <0x8000>; // L1, 32K
> timebase-frequency = <0>; // 33 MHz, from uboot
> bus-frequency = <0>; // 166 MHz
> clock-frequency = <0>; // 825 MHz, from uboot
> next-level-cache = <&L2>;
> };
> };
>
> ...
>
> L2: l2-cache-controller@20000 {
> compatible = "fsl,mpc8541-l2-cache-controller";
> reg = <0x20000 0x1000>;
> cache-line-size = <32>; // 32 bytes
> cache-size = <0x40000>; // L2, 256K
> interrupt-parent = <&mpic>;
> interrupts = <16 2>;
> };
that's actually outside of the cpus {} block.
--
balbi
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^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 4/5] ARM: OMAP4: Add L2 Cache Controller in Device Tree
2012-08-20 15:51 ` Shilimkar, Santosh
@ 2012-08-21 9:41 ` Shilimkar, Santosh
2012-08-21 10:24 ` Felipe Balbi
0 siblings, 1 reply; 18+ messages in thread
From: Shilimkar, Santosh @ 2012-08-21 9:41 UTC (permalink / raw)
To: Benoit Cousson; +Cc: linux-omap, linux-arm-kernel, tony
On Mon, Aug 20, 2012 at 9:21 PM, Shilimkar, Santosh
<santosh.shilimkar@ti.com> wrote:
> On Mon, Aug 20, 2012 at 7:21 PM, Benoit Cousson <b-cousson@ti.com> wrote:
>> Hi Santosh,
>>
>> On 08/13/2012 01:00 PM, Santosh Shilimkar wrote:
>>> This provides PL310 Level 2 Cache Controller Device Tree
>>> support for OMAP4 based devices.
>>>
>>> Cc: Benoit Cousson <b-cousson@ti.com>
>>> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
>>> ---
>>> arch/arm/boot/dts/omap4.dtsi | 7 +++++++
>>> arch/arm/mach-omap2/omap4-common.c | 6 +++++-
>>> 2 files changed, 12 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
>>> index 6717c71..cf1efb6 100644
>>> --- a/arch/arm/boot/dts/omap4.dtsi
>>> +++ b/arch/arm/boot/dts/omap4.dtsi
>>> @@ -36,6 +36,13 @@
>>> };
>>> };
>>>
>>
>>> + L2: l2-cache-controller {
>>
>> The reg offset is missing: l2-cache-controller@48242000
>>
>>> + compatible = "arm,pl310-cache";
>>> + reg = <0x48242000 0x1000>;
>>> + cache-unified;
>>> + cache-level = <2>;
>>> + };
>>> +
>>
>> In theory, the L2 cache should be referenced from the CPUs.
>>
> Agree.
>
I have added the reference for the L2 controller in CPUs.
Other information like L1 cache size etc can be added in cpu
DT node with another patch.
Updated patch below. Have also updated git branch
accordingly.
Regards
Santosh
>From 91d6cb4f999061c8cfc844a3916ee3384f2e488a Mon Sep 17 00:00:00 2001
From: Santosh Shilimkar <santosh.shilimkar@ti.com>
Date: Wed, 4 Jul 2012 17:57:34 +0530
Subject: [PATCH 1/2 v2] ARM: OMAP4: Add L2 Cache Controller in Device Tree
This provides PL310 Level 2 Cache Controller Device Tree
support for OMAP4 based devices.
Cc: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
arch/arm/boot/dts/omap4.dtsi | 9 +++++++++
arch/arm/mach-omap2/omap4-common.c | 6 +++++-
2 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 6717c71..0229dd2 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -30,12 +30,21 @@
cpus {
cpu@0 {
compatible = "arm,cortex-a9";
+ next-level-cache = <&L2>;
};
cpu@1 {
compatible = "arm,cortex-a9";
+ next-level-cache = <&L2>;
};
};
+ L2: l2-cache-controller@48242000 {
+ compatible = "arm,pl310-cache";
+ reg = <0x48242000 0x1000>;
+ cache-unified;
+ cache-level = <2>;
+ };
+
/*
* The soc node represents the soc top level view. It is uses for IPs
* that are not memory mapped in the MPU view or for the MPU itself.
diff --git a/arch/arm/mach-omap2/omap4-common.c
b/arch/arm/mach-omap2/omap4-common.c
index c29dee9..6f95992 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -16,6 +16,7 @@
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/memblock.h>
+#include <linux/of.h>
#include <asm/hardware/gic.h>
#include <asm/hardware/cache-l2x0.h>
@@ -171,7 +172,10 @@ static int __init omap_l2_cache_init(void)
/* Enable PL310 L2 Cache controller */
omap_smc1(0x102, 0x1);
- l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK);
+ if (of_have_populated_dt())
+ l2x0_of_init(aux_ctrl, L2X0_AUX_CTRL_MASK);
+ else
+ l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK);
/*
* Override default outer_cache.disable with a OMAP4
--
1.7.9.5
^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH 4/5] ARM: OMAP4: Add L2 Cache Controller in Device Tree
2012-08-21 9:41 ` Shilimkar, Santosh
@ 2012-08-21 10:24 ` Felipe Balbi
2012-08-21 10:32 ` Shilimkar, Santosh
0 siblings, 1 reply; 18+ messages in thread
From: Felipe Balbi @ 2012-08-21 10:24 UTC (permalink / raw)
To: Shilimkar, Santosh; +Cc: Benoit Cousson, linux-omap, linux-arm-kernel, tony
[-- Attachment #1: Type: text/plain, Size: 4314 bytes --]
On Tue, Aug 21, 2012 at 03:11:51PM +0530, Shilimkar, Santosh wrote:
> On Mon, Aug 20, 2012 at 9:21 PM, Shilimkar, Santosh
> <santosh.shilimkar@ti.com> wrote:
> > On Mon, Aug 20, 2012 at 7:21 PM, Benoit Cousson <b-cousson@ti.com> wrote:
> >> Hi Santosh,
> >>
> >> On 08/13/2012 01:00 PM, Santosh Shilimkar wrote:
> >>> This provides PL310 Level 2 Cache Controller Device Tree
> >>> support for OMAP4 based devices.
> >>>
> >>> Cc: Benoit Cousson <b-cousson@ti.com>
> >>> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> >>> ---
> >>> arch/arm/boot/dts/omap4.dtsi | 7 +++++++
> >>> arch/arm/mach-omap2/omap4-common.c | 6 +++++-
> >>> 2 files changed, 12 insertions(+), 1 deletion(-)
> >>>
> >>> diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
> >>> index 6717c71..cf1efb6 100644
> >>> --- a/arch/arm/boot/dts/omap4.dtsi
> >>> +++ b/arch/arm/boot/dts/omap4.dtsi
> >>> @@ -36,6 +36,13 @@
> >>> };
> >>> };
> >>>
> >>
> >>> + L2: l2-cache-controller {
> >>
> >> The reg offset is missing: l2-cache-controller@48242000
> >>
> >>> + compatible = "arm,pl310-cache";
> >>> + reg = <0x48242000 0x1000>;
> >>> + cache-unified;
> >>> + cache-level = <2>;
> >>> + };
> >>> +
> >>
> >> In theory, the L2 cache should be referenced from the CPUs.
> >>
> > Agree.
> >
> I have added the reference for the L2 controller in CPUs.
> Other information like L1 cache size etc can be added in cpu
> DT node with another patch.
>
> Updated patch below. Have also updated git branch
> accordingly.
>
> Regards
> Santosh
>
> From 91d6cb4f999061c8cfc844a3916ee3384f2e488a Mon Sep 17 00:00:00 2001
> From: Santosh Shilimkar <santosh.shilimkar@ti.com>
> Date: Wed, 4 Jul 2012 17:57:34 +0530
> Subject: [PATCH 1/2 v2] ARM: OMAP4: Add L2 Cache Controller in Device Tree
>
> This provides PL310 Level 2 Cache Controller Device Tree
> support for OMAP4 based devices.
>
> Cc: Benoit Cousson <b-cousson@ti.com>
> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
nice work :-)
FWIW this looks good to me:
Acked-by: Felipe Balbi <balbi@ti.com>
just one thing, will a similar patch for omap3 be sent ?
cheers
> ---
> arch/arm/boot/dts/omap4.dtsi | 9 +++++++++
> arch/arm/mach-omap2/omap4-common.c | 6 +++++-
> 2 files changed, 14 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
> index 6717c71..0229dd2 100644
> --- a/arch/arm/boot/dts/omap4.dtsi
> +++ b/arch/arm/boot/dts/omap4.dtsi
> @@ -30,12 +30,21 @@
> cpus {
> cpu@0 {
> compatible = "arm,cortex-a9";
> + next-level-cache = <&L2>;
> };
> cpu@1 {
> compatible = "arm,cortex-a9";
> + next-level-cache = <&L2>;
> };
> };
>
> + L2: l2-cache-controller@48242000 {
> + compatible = "arm,pl310-cache";
> + reg = <0x48242000 0x1000>;
> + cache-unified;
> + cache-level = <2>;
> + };
> +
> /*
> * The soc node represents the soc top level view. It is uses for IPs
> * that are not memory mapped in the MPU view or for the MPU itself.
> diff --git a/arch/arm/mach-omap2/omap4-common.c
> b/arch/arm/mach-omap2/omap4-common.c
> index c29dee9..6f95992 100644
> --- a/arch/arm/mach-omap2/omap4-common.c
> +++ b/arch/arm/mach-omap2/omap4-common.c
> @@ -16,6 +16,7 @@
> #include <linux/io.h>
> #include <linux/platform_device.h>
> #include <linux/memblock.h>
> +#include <linux/of.h>
>
> #include <asm/hardware/gic.h>
> #include <asm/hardware/cache-l2x0.h>
> @@ -171,7 +172,10 @@ static int __init omap_l2_cache_init(void)
> /* Enable PL310 L2 Cache controller */
> omap_smc1(0x102, 0x1);
>
> - l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK);
> + if (of_have_populated_dt())
> + l2x0_of_init(aux_ctrl, L2X0_AUX_CTRL_MASK);
> + else
> + l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK);
>
> /*
> * Override default outer_cache.disable with a OMAP4
> --
> 1.7.9.5
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
--
balbi
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^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 4/5] ARM: OMAP4: Add L2 Cache Controller in Device Tree
2012-08-21 10:32 ` Shilimkar, Santosh
@ 2012-08-21 10:29 ` Felipe Balbi
2012-08-21 10:44 ` Benoit Cousson
1 sibling, 0 replies; 18+ messages in thread
From: Felipe Balbi @ 2012-08-21 10:29 UTC (permalink / raw)
To: Shilimkar, Santosh
Cc: balbi, Benoit Cousson, linux-omap, linux-arm-kernel, tony
[-- Attachment #1: Type: text/plain, Size: 2895 bytes --]
On Tue, Aug 21, 2012 at 04:02:38PM +0530, Shilimkar, Santosh wrote:
> On Tue, Aug 21, 2012 at 3:54 PM, Felipe Balbi <balbi@ti.com> wrote:
> > On Tue, Aug 21, 2012 at 03:11:51PM +0530, Shilimkar, Santosh wrote:
> >> On Mon, Aug 20, 2012 at 9:21 PM, Shilimkar, Santosh
> >> <santosh.shilimkar@ti.com> wrote:
> >> > On Mon, Aug 20, 2012 at 7:21 PM, Benoit Cousson <b-cousson@ti.com> wrote:
> >> >> Hi Santosh,
> >> >>
> >> >> On 08/13/2012 01:00 PM, Santosh Shilimkar wrote:
> >> >>> This provides PL310 Level 2 Cache Controller Device Tree
> >> >>> support for OMAP4 based devices.
> >> >>>
> >> >>> Cc: Benoit Cousson <b-cousson@ti.com>
> >> >>> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> >> >>> ---
> >> >>> arch/arm/boot/dts/omap4.dtsi | 7 +++++++
> >> >>> arch/arm/mach-omap2/omap4-common.c | 6 +++++-
> >> >>> 2 files changed, 12 insertions(+), 1 deletion(-)
> >> >>>
> >> >>> diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
> >> >>> index 6717c71..cf1efb6 100644
> >> >>> --- a/arch/arm/boot/dts/omap4.dtsi
> >> >>> +++ b/arch/arm/boot/dts/omap4.dtsi
> >> >>> @@ -36,6 +36,13 @@
> >> >>> };
> >> >>> };
> >> >>>
> >> >>
> >> >>> + L2: l2-cache-controller {
> >> >>
> >> >> The reg offset is missing: l2-cache-controller@48242000
> >> >>
> >> >>> + compatible = "arm,pl310-cache";
> >> >>> + reg = <0x48242000 0x1000>;
> >> >>> + cache-unified;
> >> >>> + cache-level = <2>;
> >> >>> + };
> >> >>> +
> >> >>
> >> >> In theory, the L2 cache should be referenced from the CPUs.
> >> >>
> >> > Agree.
> >> >
> >> I have added the reference for the L2 controller in CPUs.
> >> Other information like L1 cache size etc can be added in cpu
> >> DT node with another patch.
> >>
> >> Updated patch below. Have also updated git branch
> >> accordingly.
> >>
> >> Regards
> >> Santosh
> >>
> >> From 91d6cb4f999061c8cfc844a3916ee3384f2e488a Mon Sep 17 00:00:00 2001
> >> From: Santosh Shilimkar <santosh.shilimkar@ti.com>
> >> Date: Wed, 4 Jul 2012 17:57:34 +0530
> >> Subject: [PATCH 1/2 v2] ARM: OMAP4: Add L2 Cache Controller in Device Tree
> >>
> >> This provides PL310 Level 2 Cache Controller Device Tree
> >> support for OMAP4 based devices.
> >>
> >> Cc: Benoit Cousson <b-cousson@ti.com>
> >> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> >
> > nice work :-)
> >
> > FWIW this looks good to me:
> >
> > Acked-by: Felipe Balbi <balbi@ti.com>
> >
> Thanks.
>
> > just one thing, will a similar patch for omap3 be sent ?
> >
> OMAP3 has an integrated L2 cache controller so there
> won't any additional DT node for L2.
>
> OMAP3 CPU DT node can be updated with l1/l2 cache
> size etc related information though.
fair enough, thanks for the info.
--
balbi
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^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 4/5] ARM: OMAP4: Add L2 Cache Controller in Device Tree
2012-08-21 10:24 ` Felipe Balbi
@ 2012-08-21 10:32 ` Shilimkar, Santosh
2012-08-21 10:29 ` Felipe Balbi
2012-08-21 10:44 ` Benoit Cousson
0 siblings, 2 replies; 18+ messages in thread
From: Shilimkar, Santosh @ 2012-08-21 10:32 UTC (permalink / raw)
To: balbi; +Cc: Benoit Cousson, linux-omap, linux-arm-kernel, tony
On Tue, Aug 21, 2012 at 3:54 PM, Felipe Balbi <balbi@ti.com> wrote:
> On Tue, Aug 21, 2012 at 03:11:51PM +0530, Shilimkar, Santosh wrote:
>> On Mon, Aug 20, 2012 at 9:21 PM, Shilimkar, Santosh
>> <santosh.shilimkar@ti.com> wrote:
>> > On Mon, Aug 20, 2012 at 7:21 PM, Benoit Cousson <b-cousson@ti.com> wrote:
>> >> Hi Santosh,
>> >>
>> >> On 08/13/2012 01:00 PM, Santosh Shilimkar wrote:
>> >>> This provides PL310 Level 2 Cache Controller Device Tree
>> >>> support for OMAP4 based devices.
>> >>>
>> >>> Cc: Benoit Cousson <b-cousson@ti.com>
>> >>> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
>> >>> ---
>> >>> arch/arm/boot/dts/omap4.dtsi | 7 +++++++
>> >>> arch/arm/mach-omap2/omap4-common.c | 6 +++++-
>> >>> 2 files changed, 12 insertions(+), 1 deletion(-)
>> >>>
>> >>> diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
>> >>> index 6717c71..cf1efb6 100644
>> >>> --- a/arch/arm/boot/dts/omap4.dtsi
>> >>> +++ b/arch/arm/boot/dts/omap4.dtsi
>> >>> @@ -36,6 +36,13 @@
>> >>> };
>> >>> };
>> >>>
>> >>
>> >>> + L2: l2-cache-controller {
>> >>
>> >> The reg offset is missing: l2-cache-controller@48242000
>> >>
>> >>> + compatible = "arm,pl310-cache";
>> >>> + reg = <0x48242000 0x1000>;
>> >>> + cache-unified;
>> >>> + cache-level = <2>;
>> >>> + };
>> >>> +
>> >>
>> >> In theory, the L2 cache should be referenced from the CPUs.
>> >>
>> > Agree.
>> >
>> I have added the reference for the L2 controller in CPUs.
>> Other information like L1 cache size etc can be added in cpu
>> DT node with another patch.
>>
>> Updated patch below. Have also updated git branch
>> accordingly.
>>
>> Regards
>> Santosh
>>
>> From 91d6cb4f999061c8cfc844a3916ee3384f2e488a Mon Sep 17 00:00:00 2001
>> From: Santosh Shilimkar <santosh.shilimkar@ti.com>
>> Date: Wed, 4 Jul 2012 17:57:34 +0530
>> Subject: [PATCH 1/2 v2] ARM: OMAP4: Add L2 Cache Controller in Device Tree
>>
>> This provides PL310 Level 2 Cache Controller Device Tree
>> support for OMAP4 based devices.
>>
>> Cc: Benoit Cousson <b-cousson@ti.com>
>> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
>
> nice work :-)
>
> FWIW this looks good to me:
>
> Acked-by: Felipe Balbi <balbi@ti.com>
>
Thanks.
> just one thing, will a similar patch for omap3 be sent ?
>
OMAP3 has an integrated L2 cache controller so there
won't any additional DT node for L2.
OMAP3 CPU DT node can be updated with l1/l2 cache
size etc related information though.
Regards
Santosh
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 4/5] ARM: OMAP4: Add L2 Cache Controller in Device Tree
2012-08-21 10:32 ` Shilimkar, Santosh
2012-08-21 10:29 ` Felipe Balbi
@ 2012-08-21 10:44 ` Benoit Cousson
2012-08-21 10:46 ` Shilimkar, Santosh
1 sibling, 1 reply; 18+ messages in thread
From: Benoit Cousson @ 2012-08-21 10:44 UTC (permalink / raw)
To: Shilimkar, Santosh; +Cc: balbi, linux-omap, linux-arm-kernel, tony
Hi Santosh,
On 08/21/2012 12:32 PM, Shilimkar, Santosh wrote:
> On Tue, Aug 21, 2012 at 3:54 PM, Felipe Balbi <balbi@ti.com> wrote:
>> On Tue, Aug 21, 2012 at 03:11:51PM +0530, Shilimkar, Santosh wrote:
>>> On Mon, Aug 20, 2012 at 9:21 PM, Shilimkar, Santosh
>>> <santosh.shilimkar@ti.com> wrote:
>>>> On Mon, Aug 20, 2012 at 7:21 PM, Benoit Cousson <b-cousson@ti.com> wrote:
>>>>> Hi Santosh,
>>>>>
>>>>> On 08/13/2012 01:00 PM, Santosh Shilimkar wrote:
>>>>>> This provides PL310 Level 2 Cache Controller Device Tree
>>>>>> support for OMAP4 based devices.
>>>>>>
>>>>>> Cc: Benoit Cousson <b-cousson@ti.com>
>>>>>> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
>>>>>> ---
>>>>>> arch/arm/boot/dts/omap4.dtsi | 7 +++++++
>>>>>> arch/arm/mach-omap2/omap4-common.c | 6 +++++-
>>>>>> 2 files changed, 12 insertions(+), 1 deletion(-)
>>>>>>
>>>>>> diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
>>>>>> index 6717c71..cf1efb6 100644
>>>>>> --- a/arch/arm/boot/dts/omap4.dtsi
>>>>>> +++ b/arch/arm/boot/dts/omap4.dtsi
>>>>>> @@ -36,6 +36,13 @@
>>>>>> };
>>>>>> };
>>>>>>
>>>>>
>>>>>> + L2: l2-cache-controller {
>>>>>
>>>>> The reg offset is missing: l2-cache-controller@48242000
>>>>>
>>>>>> + compatible = "arm,pl310-cache";
>>>>>> + reg = <0x48242000 0x1000>;
>>>>>> + cache-unified;
>>>>>> + cache-level = <2>;
>>>>>> + };
>>>>>> +
>>>>>
>>>>> In theory, the L2 cache should be referenced from the CPUs.
>>>>>
>>>> Agree.
>>>>
>>> I have added the reference for the L2 controller in CPUs.
>>> Other information like L1 cache size etc can be added in cpu
>>> DT node with another patch.
>>>
>>> Updated patch below. Have also updated git branch
>>> accordingly.
>>>
>>> Regards
>>> Santosh
>>>
>>> From 91d6cb4f999061c8cfc844a3916ee3384f2e488a Mon Sep 17 00:00:00 2001
>>> From: Santosh Shilimkar <santosh.shilimkar@ti.com>
>>> Date: Wed, 4 Jul 2012 17:57:34 +0530
>>> Subject: [PATCH 1/2 v2] ARM: OMAP4: Add L2 Cache Controller in Device Tree
>>>
>>> This provides PL310 Level 2 Cache Controller Device Tree
>>> support for OMAP4 based devices.
>>>
>>> Cc: Benoit Cousson <b-cousson@ti.com>
>>> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
>>
>> nice work :-)
>>
>> FWIW this looks good to me:
>>
>> Acked-by: Felipe Balbi <balbi@ti.com>
>>
> Thanks.
>
>> just one thing, will a similar patch for omap3 be sent ?
>>
> OMAP3 has an integrated L2 cache controller so there
> won't any additional DT node for L2.
>
> OMAP3 CPU DT node can be updated with l1/l2 cache
> size etc related information though.
That's not needed if the information is available from the HW.
DT is only there to provide information that cannot be extracted from HW.
If CP15 registers already contains the details about caches, then there
is no need to add them in the DT file.
Regards,
Benoit
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 4/5] ARM: OMAP4: Add L2 Cache Controller in Device Tree
2012-08-21 10:44 ` Benoit Cousson
@ 2012-08-21 10:46 ` Shilimkar, Santosh
0 siblings, 0 replies; 18+ messages in thread
From: Shilimkar, Santosh @ 2012-08-21 10:46 UTC (permalink / raw)
To: Benoit Cousson; +Cc: balbi, linux-omap, linux-arm-kernel, tony
On Tue, Aug 21, 2012 at 4:14 PM, Benoit Cousson <b-cousson@ti.com> wrote:
> Hi Santosh,
>
[...]
>>>> From 91d6cb4f999061c8cfc844a3916ee3384f2e488a Mon Sep 17 00:00:00 2001
>>>> From: Santosh Shilimkar <santosh.shilimkar@ti.com>
>>>> Date: Wed, 4 Jul 2012 17:57:34 +0530
>>>> Subject: [PATCH 1/2 v2] ARM: OMAP4: Add L2 Cache Controller in Device Tree
>>>>
>>>> This provides PL310 Level 2 Cache Controller Device Tree
>>>> support for OMAP4 based devices.
>>>>
>>>> Cc: Benoit Cousson <b-cousson@ti.com>
>>>> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
>>>
>>> nice work :-)
>>>
>>> FWIW this looks good to me:
>>>
>>> Acked-by: Felipe Balbi <balbi@ti.com>
>>>
>> Thanks.
>>
>>> just one thing, will a similar patch for omap3 be sent ?
>>>
>> OMAP3 has an integrated L2 cache controller so there
>> won't any additional DT node for L2.
>>
>> OMAP3 CPU DT node can be updated with l1/l2 cache
>> size etc related information though.
>
> That's not needed if the information is available from the HW.
> DT is only there to provide information that cannot be extracted from HW.
>
Good to know.
> If CP15 registers already contains the details about caches, then there
> is no need to add them in the DT file.
>
True. In that case as you said, there is no need to add that information
in DT.
Regards
Santosh
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 0/5] ARM: OMAP: Few device tree patches for 3.7
2012-08-13 11:00 [PATCH 0/5] ARM: OMAP: Few device tree patches for 3.7 Santosh Shilimkar
` (4 preceding siblings ...)
2012-08-13 11:00 ` [PATCH 5/5] ARM: OMAP4: Add local timer support for " Santosh Shilimkar
@ 2012-08-23 7:32 ` Santosh Shilimkar
2012-09-03 15:04 ` Benoit Cousson
5 siblings, 1 reply; 18+ messages in thread
From: Santosh Shilimkar @ 2012-08-23 7:32 UTC (permalink / raw)
To: Benoit Cousson; +Cc: linux-omap, linux-arm-kernel, tony
Benoit,
On Monday 13 August 2012 04:30 PM, Santosh Shilimkar wrote:
> These are the few device tree related patches which has been posted and
> reviewed on the list. They are intended for 3.7 merge window but I am
> posting them early enough to get into linux-next and linux-omap for testing.
>
> The following changes since commit 0d7614f09c1ebdbaa1599a5aba7593f147bf96ee:
>
> Linux 3.6-rc1 (2012-08-02 16:38:10 -0700)
>
> are available in the git repository at:
>
> git://github.com/SantoshShilimkar/linux.git for_3.7/omap_dt
>
> for you to fetch changes up to bedee5fcb18062dfc933e0971e67fd6889c6446d:
>
> ARM: OMAP4: Add local timer support for Device Tree (2012-08-13 11:59:26 +0530)
>
> ----------------------------------------------------------------
> Aneesh V (3):
> dt: device tree bindings for LPDDR2 memories
> dt: emif: device tree bindings for TI's EMIF sdram controller
> ARM: dts: EMIF and LPDDR2 device tree data for OMAP4 boards
>
> Santosh Shilimkar (2):
> ARM: OMAP4: Add L2 Cache Controller in Device Tree
> ARM: OMAP4: Add local timer support for Device Tree
>
Will you pull this series from above git url or do you want me to send
a separate git pull request email ?
Regards
santosh
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 0/5] ARM: OMAP: Few device tree patches for 3.7
2012-08-23 7:32 ` [PATCH 0/5] ARM: OMAP: Few device tree patches for 3.7 Santosh Shilimkar
@ 2012-09-03 15:04 ` Benoit Cousson
2012-09-04 5:24 ` Shilimkar, Santosh
0 siblings, 1 reply; 18+ messages in thread
From: Benoit Cousson @ 2012-09-03 15:04 UTC (permalink / raw)
To: Santosh Shilimkar; +Cc: linux-omap, linux-arm-kernel, tony
Hi Santosh,
Sorry for the delay, I missed that email :-(
On 08/23/2012 09:32 AM, Santosh Shilimkar wrote:
> Benoit,
>
> On Monday 13 August 2012 04:30 PM, Santosh Shilimkar wrote:
>> These are the few device tree related patches which has been posted and
>> reviewed on the list. They are intended for 3.7 merge window but I am
>> posting them early enough to get into linux-next and linux-omap for
>> testing.
>>
>> The following changes since commit
>> 0d7614f09c1ebdbaa1599a5aba7593f147bf96ee:
>>
>> Linux 3.6-rc1 (2012-08-02 16:38:10 -0700)
>>
>> are available in the git repository at:
>>
>> git://github.com/SantoshShilimkar/linux.git for_3.7/omap_dt
>>
>> for you to fetch changes up to bedee5fcb18062dfc933e0971e67fd6889c6446d:
>>
>> ARM: OMAP4: Add local timer support for Device Tree (2012-08-13
>> 11:59:26 +0530)
>>
>> ----------------------------------------------------------------
>> Aneesh V (3):
>> dt: device tree bindings for LPDDR2 memories
>> dt: emif: device tree bindings for TI's EMIF sdram controller
>> ARM: dts: EMIF and LPDDR2 device tree data for OMAP4 boards
>>
>> Santosh Shilimkar (2):
>> ARM: OMAP4: Add L2 Cache Controller in Device Tree
>> ARM: OMAP4: Add local timer support for Device Tree
>>
>
> Will you pull this series from above git url or do you want me to send
> a separate git pull request email ?
I'll merge that branch on top of Sourav's and Peter's series and send
the pull request to Tony.
Regards,
Benoit
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 0/5] ARM: OMAP: Few device tree patches for 3.7
2012-09-03 15:04 ` Benoit Cousson
@ 2012-09-04 5:24 ` Shilimkar, Santosh
0 siblings, 0 replies; 18+ messages in thread
From: Shilimkar, Santosh @ 2012-09-04 5:24 UTC (permalink / raw)
To: Benoit Cousson; +Cc: linux-omap, linux-arm-kernel, tony
On Mon, Sep 3, 2012 at 8:04 AM, Benoit Cousson <b-cousson@ti.com> wrote:
>
> Hi Santosh,
>
> Sorry for the delay, I missed that email :-(
>
> On 08/23/2012 09:32 AM, Santosh Shilimkar wrote:
> > Benoit,
> >
> > On Monday 13 August 2012 04:30 PM, Santosh Shilimkar wrote:
> >> These are the few device tree related patches which has been posted and
> >> reviewed on the list. They are intended for 3.7 merge window but I am
> >> posting them early enough to get into linux-next and linux-omap for
> >> testing.
> >>
> >> The following changes since commit
> >> 0d7614f09c1ebdbaa1599a5aba7593f147bf96ee:
> >>
> >> Linux 3.6-rc1 (2012-08-02 16:38:10 -0700)
> >>
> >> are available in the git repository at:
> >>
> >> git://github.com/SantoshShilimkar/linux.git for_3.7/omap_dt
> >>
> >> for you to fetch changes up to
> >> bedee5fcb18062dfc933e0971e67fd6889c6446d:
> >>
> >> ARM: OMAP4: Add local timer support for Device Tree (2012-08-13
> >> 11:59:26 +0530)
> >>
> >> ----------------------------------------------------------------
> >> Aneesh V (3):
> >> dt: device tree bindings for LPDDR2 memories
> >> dt: emif: device tree bindings for TI's EMIF sdram controller
> >> ARM: dts: EMIF and LPDDR2 device tree data for OMAP4 boards
> >>
> >> Santosh Shilimkar (2):
> >> ARM: OMAP4: Add L2 Cache Controller in Device Tree
> >> ARM: OMAP4: Add local timer support for Device Tree
> >>
> >
> > Will you pull this series from above git url or do you want me to send
> > a separate git pull request email ?
>
> I'll merge that branch on top of Sourav's and Peter's series and send
> the pull request to Tony.
>
Thanks Benoit.
Regards
Santosh
^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2012-09-04 5:24 UTC | newest]
Thread overview: 18+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2012-08-13 11:00 [PATCH 0/5] ARM: OMAP: Few device tree patches for 3.7 Santosh Shilimkar
2012-08-13 11:00 ` [PATCH 1/5] dt: device tree bindings for LPDDR2 memories Santosh Shilimkar
2012-08-13 11:00 ` [PATCH 2/5] dt: emif: device tree bindings for TI's EMIF sdram controller Santosh Shilimkar
2012-08-13 11:00 ` [PATCH 3/5] ARM: dts: EMIF and LPDDR2 device tree data for OMAP4 boards Santosh Shilimkar
2012-08-13 11:00 ` [PATCH 4/5] ARM: OMAP4: Add L2 Cache Controller in Device Tree Santosh Shilimkar
2012-08-20 13:51 ` Benoit Cousson
2012-08-20 15:51 ` Shilimkar, Santosh
2012-08-21 9:41 ` Shilimkar, Santosh
2012-08-21 10:24 ` Felipe Balbi
2012-08-21 10:32 ` Shilimkar, Santosh
2012-08-21 10:29 ` Felipe Balbi
2012-08-21 10:44 ` Benoit Cousson
2012-08-21 10:46 ` Shilimkar, Santosh
2012-08-20 15:59 ` Felipe Balbi
2012-08-13 11:00 ` [PATCH 5/5] ARM: OMAP4: Add local timer support for " Santosh Shilimkar
2012-08-23 7:32 ` [PATCH 0/5] ARM: OMAP: Few device tree patches for 3.7 Santosh Shilimkar
2012-09-03 15:04 ` Benoit Cousson
2012-09-04 5:24 ` Shilimkar, Santosh
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