Re: omap4 ehci sporadic resume issue

[Michael Trimarchi <michael-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>]

Hi

On 07/02/2013 05:03 PM, Roger Quadros wrote:
> 
> On 07/02/2013 05:49 PM, Michael Trimarchi wrote:
>> Hi Roger
>>
>> On 07/02/2013 04:42 PM, Roger Quadros wrote:
>>> On 06/28/2013 07:47 PM, Michael Trimarchi wrote:
>>>> Hi
>>>>
> 
>>>>>
>>>>> When you said earlier that the problem doesn't happen when one of the ULPIs is used
>>>>> did you try both of them individually. e.g. case 1: port 1 only enabled,
>>>>> case 2: port 2 only enabled.
>>>>>
>>>>> Did it work in both the cases?
>>>>
>>>> Yes, so I don't think could be a problem of ulpi pins and why this happen
>>>> on both at the same time? Seems more connected to somenthing else.
>>>>
>>>
>>> Right. Seems to be related to two things. OFF Mode and 2 ports being used simultaneously.
>>>
>>> I'm not sure how to go about fixing this. How important is OFF Mode for your application.
>>> Can you keep it always disabled?
>>>
> 
> 
>>
>> Right now I delivery without off mode. I will try to fix in long run the usb and I think that it could be a good platform to test omap4 mainline.
>>
> 
> Yes, our aim is to get it working with mainline as well.
> 
>> Last question:
>> If one domain is in RET mode and not OFF mode what happen during SAR restore in OFF mode?
>>
> 
> SAR restore will only happen when the Device enters OFF mode.
> 
> Device OFF mode can only be reached when all voltage domains are switched OFF and that would depend
> if all power domains entered OFF or not. Just a simplistic explanation. You can refer to chapter
> "3.9.3 Device OFF State Management" in the TRM.

What happen if we ask to go in off mode for all domains but one doesn't go in off mode so the device
will not go in off mode and the sar will not be used? How can work the restore?

> 

I have added a check of CM_RESTORE_ST. This register need to be clear before
going in OFF mode and then show if the status of phase1 2a and 2b is completed.
So before proceed with system resume and after resetting OFF_MODE bit I have tried to wait on this register,
but without success.

Michael

> cheers,
> -roger
> 


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