* [PATCH v2 0/8] DRA7xx core support
@ 2013-07-30 11:25 Rajendra Nayak
2013-07-30 11:25 ` [PATCH v2 1/8] ARM: DRA7: id: Add cpu detection support for DRA7xx based SoCs' Rajendra Nayak
` (8 more replies)
0 siblings, 9 replies; 41+ messages in thread
From: Rajendra Nayak @ 2013-07-30 11:25 UTC (permalink / raw)
To: linux-omap, linux-arm-kernel
Cc: tony, paul, khilman, benoit.cousson, r.sricharan, ambresh,
sourav.poddar, Rajendra Nayak
Changes in v2:
-1- Fixed minor changelog details
-2- Dropped the SRAM support patch since we need to move to drivers/misc/sram.c
-3- Added DTS update patches to this series which were earlier posted as
part of the data series (Since they don't have much objections as against the
other in-kernel data files)
-4- Updated the EVM dts file with pin config details for uart/mcspi and i2c
DRA7xx based SoCs' are high-performance, infotainment application devices,
based on enhanced OMAP architecture integrated on a 28nm
technology.
The DRA7xx family is composed of DRA75x and DRA74x devices.
The current device for which the patches add support is the
DRA752 SoC.
Most of the core IPs are similar to those found on the OMAP5
devices, including the dual cortex-A15 based MPU subsystem,
which has helped quite some reuse from existing OMAP5 support.
This series contains only core support patches and none of
the PRCM and hwmod data needed for the device to boot.
The bootloader support for the platform is already available
in mainline u-boot.
The patches posted in this series are available at:
git://github.com/rrnayak/linux.git for-3.12/dra-core-v2
The patches (including the ones for in-kernel data) which boot
on dra7xx evm are available at:
t://github.com/rrnayak/linux.git out-of-tree/dra-integrated-v2
R Sricharan (7):
ARM: DRA7: id: Add cpu detection support for DRA7xx based SoCs'
ARM: DRA7: Reuse all of PRCM and MPUSS SMP infra
ARM: DRA7: Reuse io tables and add a new .init_early
ARM: DRA7: Resue the clocksource, clockevent support
ARM: DRA7: board-generic: Add basic DT support
ARM: DRA7: Kconfig: Make ARCH_NR_GPIO default to 512
ARM: DRA7: dts: Add the dts files for dra7 SoC and dra7-evm board
Rajendra Nayak (1):
ARM: DRA7: hwmod: Reuse the soc_ops used for OMAP4/5
.../devicetree/bindings/arm/omap/omap.txt | 3 +
arch/arm/Kconfig | 2 +-
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/dra7-evm.dts | 163 +++++++
arch/arm/boot/dts/dra7.dtsi | 488 ++++++++++++++++++++
arch/arm/mach-omap1/include/mach/soc.h | 1 +
arch/arm/mach-omap2/Kconfig | 2 +-
arch/arm/mach-omap2/Makefile | 8 +
arch/arm/mach-omap2/board-generic.c | 18 +
arch/arm/mach-omap2/common.h | 1 +
arch/arm/mach-omap2/id.c | 30 +-
arch/arm/mach-omap2/io.c | 22 +-
arch/arm/mach-omap2/omap54xx.h | 4 +
arch/arm/mach-omap2/omap_hwmod.c | 2 +-
arch/arm/mach-omap2/soc.h | 39 ++
arch/arm/mach-omap2/timer.c | 3 +-
16 files changed, 780 insertions(+), 9 deletions(-)
create mode 100644 arch/arm/boot/dts/dra7-evm.dts
create mode 100644 arch/arm/boot/dts/dra7.dtsi
--
1.7.9.5
^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH v2 1/8] ARM: DRA7: id: Add cpu detection support for DRA7xx based SoCs'
2013-07-30 11:25 [PATCH v2 0/8] DRA7xx core support Rajendra Nayak
@ 2013-07-30 11:25 ` Rajendra Nayak
2013-07-30 13:10 ` Felipe Balbi
2013-07-30 11:25 ` [PATCH v2 2/8] ARM: DRA7: hwmod: Reuse the soc_ops used for OMAP4/5 Rajendra Nayak
` (7 subsequent siblings)
8 siblings, 1 reply; 41+ messages in thread
From: Rajendra Nayak @ 2013-07-30 11:25 UTC (permalink / raw)
To: linux-omap, linux-arm-kernel
Cc: tony, paul, khilman, benoit.cousson, r.sricharan, ambresh,
sourav.poddar, Rajendra Nayak
From: R Sricharan <r.sricharan@ti.com>
The DRA7xx is a high-performance, infotainment application device,
based on enhanced OMAP architecture integrated on a 28-nm technology.
DRA7xx family is composed of DRA75x and DRA74x devices.
Adding the DRA752 ES1.0 cpu revision detection support.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
---
arch/arm/mach-omap1/include/mach/soc.h | 1 +
arch/arm/mach-omap2/id.c | 30 ++++++++++++++++++++++--
arch/arm/mach-omap2/soc.h | 39 ++++++++++++++++++++++++++++++++
3 files changed, 68 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap1/include/mach/soc.h b/arch/arm/mach-omap1/include/mach/soc.h
index 6cf9c1c..612bd1c 100644
--- a/arch/arm/mach-omap1/include/mach/soc.h
+++ b/arch/arm/mach-omap1/include/mach/soc.h
@@ -195,6 +195,7 @@ IS_OMAP_TYPE(1710, 0x1710)
#define cpu_is_omap34xx() 0
#define cpu_is_omap44xx() 0
#define soc_is_omap54xx() 0
+#define soc_is_dra7xx() 0
#define soc_is_am33xx() 0
#define cpu_class_is_omap1() 1
#define cpu_class_is_omap2() 0
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 2dc62a2..332ae95 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -61,7 +61,7 @@ int omap_type(void)
val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
} else if (cpu_is_omap44xx()) {
val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS);
- } else if (soc_is_omap54xx()) {
+ } else if (soc_is_omap54xx() || soc_is_dra7xx()) {
val = omap_ctrl_readl(OMAP5XXX_CONTROL_STATUS);
val &= OMAP5_DEVICETYPE_MASK;
val >>= 6;
@@ -116,7 +116,7 @@ static u16 tap_prod_id;
void omap_get_die_id(struct omap_die_id *odi)
{
- if (cpu_is_omap44xx() || soc_is_omap54xx()) {
+ if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) {
odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0);
odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_1);
odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_2);
@@ -606,6 +606,32 @@ void __init omap5xxx_check_revision(void)
pr_info("%s %s\n", soc_name, soc_rev);
}
+void __init dra7xx_check_revision(void)
+{
+ u32 idcode;
+ u16 hawkeye;
+ u8 rev;
+
+ idcode = read_tap_reg(OMAP_TAP_IDCODE);
+ hawkeye = (idcode >> 12) & 0xffff;
+ rev = (idcode >> 28) & 0xff;
+ switch (hawkeye) {
+ case 0xb990:
+ switch (rev) {
+ case 0:
+ default:
+ omap_revision = DRA752_REV_ES1_0;
+ }
+ break;
+ default:
+ /* Unknown. Default to latest silicon revision */
+ omap_revision = DRA752_REV_ES1_0;
+ }
+
+ pr_info("DRA%03x ES%d.%d\n", omap_rev() >> 16,
+ ((omap_rev() >> 12) & 0xf), ((omap_rev() >> 8) & 0xf));
+}
+
/*
* Set up things for map_io and processor detection later on. Gets called
* pretty much first thing from board init. For multi-omap, this gets
diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h
index 8c616e4..0d242f1 100644
--- a/arch/arm/mach-omap2/soc.h
+++ b/arch/arm/mach-omap2/soc.h
@@ -8,6 +8,7 @@
* Written by Tony Lindgren <tony.lindgren@nokia.com>
*
* Added OMAP4/5 specific defines - Santosh Shilimkar<santosh.shilimkar@ti.com>
+ * Added DRA7xxx specific defines - Sricharan R<r.sricharan@ti.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -105,6 +106,15 @@
# endif
#endif
+#ifdef CONFIG_SOC_DRA7XX
+# ifdef OMAP_NAME
+# undef MULTI_OMAP2
+# define MULTI_OMAP2
+# else
+# define OMAP_NAME DRA7XX
+# endif
+#endif
+
/*
* Omap device type i.e. EMU/HS/TST/GP/BAD
*/
@@ -145,6 +155,7 @@ static inline int soc_is_omap(void)
* cpu_is_omap446x(): True for OMAP4460
* cpu_is_omap447x(): True for OMAP4470
* soc_is_omap543x(): True for OMAP5430, OMAP5432
+ * soc_is_dra75x(): True for DRA752, DRA754, DRA756
*/
#define GET_OMAP_CLASS (omap_rev() & 0xff)
@@ -170,6 +181,12 @@ static inline int is_ti ##class (void) \
return (GET_TI_CLASS == (id)) ? 1 : 0; \
}
+#define IS_DRA_CLASS(class, id) \
+static inline int is_dra ##class(void) \
+{ \
+ return (GET_OMAP_CLASS == (id)) ? 1 : 0; \
+}
+
#define GET_OMAP_SUBCLASS ((omap_rev() >> 20) & 0x0fff)
#define IS_OMAP_SUBCLASS(subclass, id) \
@@ -190,6 +207,12 @@ static inline int is_am ##subclass (void) \
return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \
}
+#define IS_DRA_SUBCLASS(subclass, id) \
+static inline int is_dra ##subclass(void) \
+{ \
+ return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \
+}
+
IS_OMAP_CLASS(24xx, 0x24)
IS_OMAP_CLASS(34xx, 0x34)
IS_OMAP_CLASS(44xx, 0x44)
@@ -197,6 +220,7 @@ IS_AM_CLASS(35xx, 0x35)
IS_OMAP_CLASS(54xx, 0x54)
IS_AM_CLASS(33xx, 0x33)
IS_AM_CLASS(43xx, 0x43)
+IS_DRA_CLASS(7xx, 0x7)
IS_TI_CLASS(81xx, 0x81)
@@ -213,6 +237,8 @@ IS_TI_SUBCLASS(816x, 0x816)
IS_TI_SUBCLASS(814x, 0x814)
IS_AM_SUBCLASS(335x, 0x335)
IS_AM_SUBCLASS(437x, 0x437)
+IS_DRA_SUBCLASS(75x, 0x75)
+IS_DRA_SUBCLASS(74x, 0x74)
#define cpu_is_omap24xx() 0
#define cpu_is_omap242x() 0
@@ -233,6 +259,8 @@ IS_AM_SUBCLASS(437x, 0x437)
#define cpu_is_omap447x() 0
#define soc_is_omap54xx() 0
#define soc_is_omap543x() 0
+#define soc_is_dra7xx() 0
+#define soc_is_dra75x() 0
#if defined(MULTI_OMAP2)
# if defined(CONFIG_ARCH_OMAP2)
@@ -379,6 +407,13 @@ IS_OMAP_TYPE(3430, 0x3430)
# define soc_is_omap543x() is_omap543x()
#endif
+# if defined(CONFIG_SOC_DRA7XX)
+# undef soc_is_dra7xx
+# undef soc_is_dra75x
+# define soc_is_dra7xx() is_dra7xx()
+# define soc_is_dra75x() is_dra75x()
+#endif
+
/* Various silicon revisions for omap2 */
#define OMAP242X_CLASS 0x24200024
#define OMAP2420_REV_ES1_0 OMAP242X_CLASS
@@ -443,6 +478,9 @@ IS_OMAP_TYPE(3430, 0x3430)
#define OMAP5432_REV_ES1_0 (OMAP54XX_CLASS | (0x32 << 16) | (0x10 << 8))
#define OMAP5432_REV_ES2_0 (OMAP54XX_CLASS | (0x32 << 16) | (0x20 << 8))
+#define DRA7XX_CLASS 0x07000007
+#define DRA752_REV_ES1_0 (DRA7XX_CLASS | (0x52 << 16) | (0x10 << 8))
+
void omap2xxx_check_revision(void);
void omap3xxx_check_revision(void);
void omap4xxx_check_revision(void);
@@ -451,6 +489,7 @@ void omap3xxx_check_features(void);
void ti81xx_check_features(void);
void am33xx_check_features(void);
void omap4xxx_check_features(void);
+void dra7xx_check_revision(void);
/*
* Runtime detection of OMAP3 features
--
1.7.9.5
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v2 2/8] ARM: DRA7: hwmod: Reuse the soc_ops used for OMAP4/5
2013-07-30 11:25 [PATCH v2 0/8] DRA7xx core support Rajendra Nayak
2013-07-30 11:25 ` [PATCH v2 1/8] ARM: DRA7: id: Add cpu detection support for DRA7xx based SoCs' Rajendra Nayak
@ 2013-07-30 11:25 ` Rajendra Nayak
2013-07-30 11:25 ` [PATCH v2 3/8] ARM: DRA7: Reuse all of PRCM and MPUSS SMP infra Rajendra Nayak
` (6 subsequent siblings)
8 siblings, 0 replies; 41+ messages in thread
From: Rajendra Nayak @ 2013-07-30 11:25 UTC (permalink / raw)
To: linux-omap, linux-arm-kernel
Cc: tony, paul, khilman, benoit.cousson, r.sricharan, ambresh,
sourav.poddar, Rajendra Nayak
The soc_ops for dra7xx devices can be completed reused
from the ones used for omap4 and omap5 devices.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
---
arch/arm/mach-omap2/omap_hwmod.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 7341eff..f6eb29b 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -4113,7 +4113,7 @@ void __init omap_hwmod_init(void)
soc_ops.assert_hardreset = _omap2_assert_hardreset;
soc_ops.deassert_hardreset = _omap2_deassert_hardreset;
soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted;
- } else if (cpu_is_omap44xx() || soc_is_omap54xx()) {
+ } else if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) {
soc_ops.enable_module = _omap4_enable_module;
soc_ops.disable_module = _omap4_disable_module;
soc_ops.wait_target_ready = _omap4_wait_target_ready;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v2 3/8] ARM: DRA7: Reuse all of PRCM and MPUSS SMP infra
2013-07-30 11:25 [PATCH v2 0/8] DRA7xx core support Rajendra Nayak
2013-07-30 11:25 ` [PATCH v2 1/8] ARM: DRA7: id: Add cpu detection support for DRA7xx based SoCs' Rajendra Nayak
2013-07-30 11:25 ` [PATCH v2 2/8] ARM: DRA7: hwmod: Reuse the soc_ops used for OMAP4/5 Rajendra Nayak
@ 2013-07-30 11:25 ` Rajendra Nayak
2013-07-30 12:26 ` Nishanth Menon
2013-07-30 11:25 ` [PATCH v2 4/8] ARM: DRA7: Reuse io tables and add a new .init_early Rajendra Nayak
` (5 subsequent siblings)
8 siblings, 1 reply; 41+ messages in thread
From: Rajendra Nayak @ 2013-07-30 11:25 UTC (permalink / raw)
To: linux-omap, linux-arm-kernel
Cc: tony, paul, khilman, benoit.cousson, r.sricharan, ambresh,
sourav.poddar, Rajendra Nayak
From: R Sricharan <r.sricharan@ti.com>
The PRCM and MPUSS parts of DRA7 devices are quite identical
to OMAP5 so as to reuse all the existing infrastructure around it.
Makefile updates to do just that.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
---
arch/arm/mach-omap2/Makefile | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index d4f6715..17fb8b7 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -23,6 +23,7 @@ obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common)
obj-$(CONFIG_SOC_AM33XX) += irq.o $(hwmod-common)
obj-$(CONFIG_SOC_OMAP5) += prm44xx.o $(hwmod-common) $(secure-common)
obj-$(CONFIG_SOC_AM43XX) += $(hwmod-common) $(secure-common)
+obj-$(CONFIG_SOC_DRA7XX) += prm44xx.o $(hwmod-common) $(secure-common)
ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),)
obj-y += mcbsp.o
@@ -39,6 +40,7 @@ omap-4-5-common = omap4-common.o omap-wakeupgen.o
obj-$(CONFIG_ARCH_OMAP4) += $(omap-4-5-common) $(smp-y) sleep44xx.o
obj-$(CONFIG_SOC_OMAP5) += $(omap-4-5-common) $(smp-y) sleep44xx.o
obj-$(CONFIG_SOC_AM43XX) += $(omap-4-5-common)
+obj-$(CONFIG_SOC_DRA7XX) += $(omap-4-5-common) $(smp-y)
plus_sec := $(call as-instr,.arch_extension sec,+sec)
AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a$(plus_sec)
@@ -87,6 +89,7 @@ obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o
obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o
obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o omap-mpuss-lowpower.o
obj-$(CONFIG_SOC_OMAP5) += omap-mpuss-lowpower.o
+obj-$(CONFIG_SOC_DRA7XX) += omap-mpuss-lowpower.o
obj-$(CONFIG_PM_DEBUG) += pm-debug.o
obj-$(CONFIG_POWER_AVS_OMAP) += sr_device.o
@@ -114,6 +117,7 @@ omap-prcm-4-5-common = cminst44xx.o cm44xx.o prm44xx.o \
vc44xx_data.o vp44xx_data.o
obj-$(CONFIG_ARCH_OMAP4) += $(omap-prcm-4-5-common)
obj-$(CONFIG_SOC_OMAP5) += $(omap-prcm-4-5-common)
+obj-$(CONFIG_SOC_DRA7XX) += $(omap-prcm-4-5-common)
# OMAP voltage domains
voltagedomain-common := voltage.o vc.o vp.o
@@ -143,6 +147,7 @@ obj-$(CONFIG_SOC_AM33XX) += powerdomains33xx_data.o
obj-$(CONFIG_SOC_AM43XX) += $(powerdomain-common)
obj-$(CONFIG_SOC_OMAP5) += $(powerdomain-common)
obj-$(CONFIG_SOC_OMAP5) += powerdomains54xx_data.o
+obj-$(CONFIG_SOC_DRA7XX) += $(powerdomain-common)
# PRCM clockdomain control
clockdomain-common += clockdomain.o
@@ -160,6 +165,7 @@ obj-$(CONFIG_SOC_AM33XX) += clockdomains33xx_data.o
obj-$(CONFIG_SOC_AM43XX) += $(clockdomain-common)
obj-$(CONFIG_SOC_OMAP5) += $(clockdomain-common)
obj-$(CONFIG_SOC_OMAP5) += clockdomains54xx_data.o
+obj-$(CONFIG_SOC_DRA7XX) += $(clockdomain-common)
# Clock framework
obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o
@@ -181,6 +187,8 @@ obj-$(CONFIG_SOC_AM33XX) += $(clock-common) dpll3xxx.o
obj-$(CONFIG_SOC_AM33XX) += cclock33xx_data.o
obj-$(CONFIG_SOC_OMAP5) += $(clock-common)
obj-$(CONFIG_SOC_OMAP5) += dpll3xxx.o dpll44xx.o
+obj-$(CONFIG_SOC_DRA7XX) += $(clock-common)
+obj-$(CONFIG_SOC_DRA7XX) += dpll3xxx.o dpll44xx.o
# OMAP2 clock rate set data (old "OPP" data)
obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o
--
1.7.9.5
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v2 4/8] ARM: DRA7: Reuse io tables and add a new .init_early
2013-07-30 11:25 [PATCH v2 0/8] DRA7xx core support Rajendra Nayak
` (2 preceding siblings ...)
2013-07-30 11:25 ` [PATCH v2 3/8] ARM: DRA7: Reuse all of PRCM and MPUSS SMP infra Rajendra Nayak
@ 2013-07-30 11:25 ` Rajendra Nayak
2013-07-30 11:25 ` [PATCH v2 5/8] ARM: DRA7: Resue the clocksource, clockevent support Rajendra Nayak
` (4 subsequent siblings)
8 siblings, 0 replies; 41+ messages in thread
From: Rajendra Nayak @ 2013-07-30 11:25 UTC (permalink / raw)
To: linux-omap, linux-arm-kernel
Cc: tony, paul, khilman, benoit.cousson, r.sricharan, ambresh,
sourav.poddar, Rajendra Nayak
From: R Sricharan <r.sricharan@ti.com>
The IO descriptor tables for DRA7 are a complete reuse from OMAP5.
A new dra7xx_init_early() does the base address inits.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
---
arch/arm/mach-omap2/common.h | 1 +
arch/arm/mach-omap2/io.c | 22 ++++++++++++++++++++--
arch/arm/mach-omap2/omap54xx.h | 4 ++++
3 files changed, 25 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index dfcc182..4a5684b 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -110,6 +110,7 @@ void omap3630_init_late(void);
void am35xx_init_late(void);
void ti81xx_init_late(void);
int omap2_common_pm_late_init(void);
+void dra7xx_init_early(void);
#ifdef CONFIG_SOC_BUS
void omap_soc_device_init(void);
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 4a3f06f..44aa4f0 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -251,7 +251,7 @@ static struct map_desc omap44xx_io_desc[] __initdata = {
};
#endif
-#ifdef CONFIG_SOC_OMAP5
+#if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
static struct map_desc omap54xx_io_desc[] __initdata = {
{
.virtual = L3_54XX_VIRT,
@@ -333,7 +333,7 @@ void __init omap4_map_io(void)
}
#endif
-#ifdef CONFIG_SOC_OMAP5
+#if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
void __init omap5_map_io(void)
{
iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
@@ -653,6 +653,24 @@ void __init omap5_init_early(void)
}
#endif
+#ifdef CONFIG_SOC_DRA7XX
+void __init dra7xx_init_early(void)
+{
+ omap2_set_globals_tap(DRA7XX_CLASS,
+ OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE));
+ omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
+ OMAP2_L4_IO_ADDRESS(DRA7XX_CTRL_BASE));
+ omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE));
+ omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_AON_BASE),
+ OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE));
+ omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
+ omap_prm_base_init();
+ omap_cm_base_init();
+ dra7xx_check_revision();
+}
+#endif
+
+
void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
struct omap_sdrc_params *sdrc_cs1)
{
diff --git a/arch/arm/mach-omap2/omap54xx.h b/arch/arm/mach-omap2/omap54xx.h
index a086ba1..2d35c57 100644
--- a/arch/arm/mach-omap2/omap54xx.h
+++ b/arch/arm/mach-omap2/omap54xx.h
@@ -30,4 +30,8 @@
#define OMAP54XX_CTRL_BASE 0x4a002800
#define OMAP54XX_SAR_RAM_BASE 0x4ae26000
+#define DRA7XX_CM_CORE_AON_BASE 0x4a005000
+#define DRA7XX_CTRL_BASE 0x4a003400
+#define DRA7XX_TAP_BASE 0x4ae0c000
+
#endif /* __ASM_SOC_OMAP555554XX_H */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v2 5/8] ARM: DRA7: Resue the clocksource, clockevent support
2013-07-30 11:25 [PATCH v2 0/8] DRA7xx core support Rajendra Nayak
` (3 preceding siblings ...)
2013-07-30 11:25 ` [PATCH v2 4/8] ARM: DRA7: Reuse io tables and add a new .init_early Rajendra Nayak
@ 2013-07-30 11:25 ` Rajendra Nayak
2013-07-30 11:25 ` [PATCH v2 6/8] ARM: DRA7: board-generic: Add basic DT support Rajendra Nayak
` (3 subsequent siblings)
8 siblings, 0 replies; 41+ messages in thread
From: Rajendra Nayak @ 2013-07-30 11:25 UTC (permalink / raw)
To: linux-omap, linux-arm-kernel
Cc: tony, paul, khilman, benoit.cousson, r.sricharan, ambresh,
sourav.poddar, Rajendra Nayak
From: R Sricharan <r.sricharan@ti.com>
All of OMAP5 timer support for clocksource and clockevent is completely
reused across DRA7.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
---
arch/arm/mach-omap2/Kconfig | 2 +-
arch/arm/mach-omap2/timer.c | 3 ++-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 3eed000..fc6ec23 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -132,7 +132,7 @@ config SOC_HAS_OMAP2_SDRC
config SOC_HAS_REALTIME_COUNTER
bool "Real time free running counter"
- depends on SOC_OMAP5
+ depends on SOC_OMAP5 || SOC_DRA7XX
default y
comment "OMAP Core Type"
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index b37e1fc..1e77f11 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -594,7 +594,8 @@ OMAP_SYS_GP_TIMER_INIT(3, 2, "timer_sys_ck", NULL,
1, "timer_sys_ck", "ti,timer-alwon");
#endif
-#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5)
+#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
+ defined(CONFIG_SOC_DRA7XX)
static OMAP_SYS_32K_TIMER_INIT(4, 1, "timer_32k_ck", "ti,timer-alwon",
2, "sys_clkin_ck", NULL);
#endif
--
1.7.9.5
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v2 6/8] ARM: DRA7: board-generic: Add basic DT support
2013-07-30 11:25 [PATCH v2 0/8] DRA7xx core support Rajendra Nayak
` (4 preceding siblings ...)
2013-07-30 11:25 ` [PATCH v2 5/8] ARM: DRA7: Resue the clocksource, clockevent support Rajendra Nayak
@ 2013-07-30 11:25 ` Rajendra Nayak
2013-07-30 11:25 ` [PATCH v2 7/8] ARM: DRA7: Kconfig: Make ARCH_NR_GPIO default to 512 Rajendra Nayak
` (2 subsequent siblings)
8 siblings, 0 replies; 41+ messages in thread
From: Rajendra Nayak @ 2013-07-30 11:25 UTC (permalink / raw)
To: linux-omap, linux-arm-kernel
Cc: tony, paul, khilman, benoit.cousson, r.sricharan, ambresh,
sourav.poddar, Rajendra Nayak
From: R Sricharan <r.sricharan@ti.com>
Describe minimal DT boot machine details for DRA7xx based SoC's. DRA7xx
family is based on dual core ARM CORTEX A15 using GIC as the interrupt controller.
The PRCM and timer infrastructure is reused from OMAP5 and so are the io
descriptor tables.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
---
.../devicetree/bindings/arm/omap/omap.txt | 3 +++
arch/arm/mach-omap2/board-generic.c | 18 ++++++++++++++++++
2 files changed, 21 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/omap/omap.txt b/Documentation/devicetree/bindings/arm/omap/omap.txt
index 6d498c7..91b7049 100644
--- a/Documentation/devicetree/bindings/arm/omap/omap.txt
+++ b/Documentation/devicetree/bindings/arm/omap/omap.txt
@@ -59,3 +59,6 @@ Boards:
- AM43x EPOS EVM
compatible = "ti,am43x-epos-evm", "ti,am4372", "ti,am43"
+
+- DRA7 EVM: Software Developement Board for DRA7XX
+ compatible = "ti,dra7-evm", "ti,dra7"
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index be5d005..b89e55b 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -222,3 +222,21 @@ DT_MACHINE_START(AM43_DT, "Generic AM43 (Flattened Device Tree)")
.dt_compat = am43_boards_compat,
MACHINE_END
#endif
+
+#ifdef CONFIG_SOC_DRA7XX
+static const char *dra7xx_boards_compat[] __initdata = {
+ "ti,dra7",
+ NULL,
+};
+
+DT_MACHINE_START(DRA7XX_DT, "Generic DRA7XX (Flattened Device Tree)")
+ .reserve = omap_reserve,
+ .smp = smp_ops(omap4_smp_ops),
+ .map_io = omap5_map_io,
+ .init_early = dra7xx_init_early,
+ .init_irq = omap_gic_of_init,
+ .init_machine = omap_generic_init,
+ .init_time = omap5_realtime_timer_init,
+ .dt_compat = dra7xx_boards_compat,
+MACHINE_END
+#endif
--
1.7.9.5
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v2 7/8] ARM: DRA7: Kconfig: Make ARCH_NR_GPIO default to 512
2013-07-30 11:25 [PATCH v2 0/8] DRA7xx core support Rajendra Nayak
` (5 preceding siblings ...)
2013-07-30 11:25 ` [PATCH v2 6/8] ARM: DRA7: board-generic: Add basic DT support Rajendra Nayak
@ 2013-07-30 11:25 ` Rajendra Nayak
2013-07-30 11:25 ` [PATCH v2 8/8] ARM: DRA7: dts: Add the dts files for dra7 SoC and dra7-evm board Rajendra Nayak
2013-08-02 22:28 ` [PATCH v2 0/8] DRA7xx core support Santosh Shilimkar
8 siblings, 0 replies; 41+ messages in thread
From: Rajendra Nayak @ 2013-07-30 11:25 UTC (permalink / raw)
To: linux-omap, linux-arm-kernel
Cc: tony, paul, khilman, benoit.cousson, r.sricharan, ambresh,
sourav.poddar, Rajendra Nayak
From: R Sricharan <r.sricharan@ti.com>
DRA7xx has 8 GPIO banks so that there are 32x8 = 256 GPIOs.
In order for the gpiolib to detect and initialize these
and other TWL GPIOs, ARCH_NR_GPIO is set to 512 using the
kconfig default for DRA7.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
---
arch/arm/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 37c0f4e..b9e64f2 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1600,7 +1600,7 @@ config LOCAL_TIMERS
config ARCH_NR_GPIO
int
default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
- default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5
+ default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX
default 392 if ARCH_U8500
default 352 if ARCH_VT8500
default 288 if ARCH_SUNXI
--
1.7.9.5
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v2 8/8] ARM: DRA7: dts: Add the dts files for dra7 SoC and dra7-evm board
2013-07-30 11:25 [PATCH v2 0/8] DRA7xx core support Rajendra Nayak
` (6 preceding siblings ...)
2013-07-30 11:25 ` [PATCH v2 7/8] ARM: DRA7: Kconfig: Make ARCH_NR_GPIO default to 512 Rajendra Nayak
@ 2013-07-30 11:25 ` Rajendra Nayak
2013-07-30 12:30 ` Nishanth Menon
2013-08-12 11:44 ` Mark Rutland
2013-08-02 22:28 ` [PATCH v2 0/8] DRA7xx core support Santosh Shilimkar
8 siblings, 2 replies; 41+ messages in thread
From: Rajendra Nayak @ 2013-07-30 11:25 UTC (permalink / raw)
To: linux-omap, linux-arm-kernel
Cc: tony, paul, khilman, benoit.cousson, r.sricharan, ambresh,
sourav.poddar, Rajendra Nayak
From: R Sricharan <r.sricharan@ti.com>
Add minimal device tree source needed for DRA7 based SoCs.
Also add a board dts file for the dra7-evm (based on dra752)
which contains 1.5G of memory with 1G interleaved and 512MB
non-interleaved. Also added in the board file are pin configuration
details for i2c, mcspi and uart devices on board.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
---
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/dra7-evm.dts | 163 ++++++++++++++
arch/arm/boot/dts/dra7.dtsi | 488 ++++++++++++++++++++++++++++++++++++++++
3 files changed, 653 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/dra7-evm.dts
create mode 100644 arch/arm/boot/dts/dra7.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 641b3c9..e2f8566 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -173,7 +173,8 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
am335x-bone.dtb \
am3517-evm.dtb \
am3517_mt_ventoux.dtb \
- am43x-epos-evm.dtb
+ am43x-epos-evm.dtb \
+ dra7-evm.dtb
dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb
dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
dtb-$(CONFIG_ARCH_U8500) += snowball.dtb \
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
new file mode 100644
index 0000000..7b0b563
--- /dev/null
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -0,0 +1,163 @@
+/*
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+/include/ "dra7.dtsi"
+
+/ {
+ model = "TI DRA7";
+ compatible = "ti,dra7-evm", "ti,dra7";
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x60000000>; /* 1536 MB */
+ };
+};
+
+&dra7_pmx_core {
+ i2c1_pins: pinmux_i2c1_pins {
+ pinctrl-single,pins = <
+ 0x400 0x60000 /* i2c1_sda */
+ 0x404 0x60000 /* i2c1_scl */
+ >;
+ };
+
+ i2c2_pins: pinmux_i2c2_pins {
+ pinctrl-single,pins = <
+ 0x408 0x60000 /* i2c2_sda */
+ 0x40c 0x60000 /* i2c2_scl */
+ >;
+ };
+
+ i2c3_pins: pinmux_i2c3_pins {
+ pinctrl-single,pins = <
+ 0x410 0x60000 /* i2c3_sda */
+ 0x414 0x60000 /* i2c3_scl */
+ >;
+ };
+
+ mcspi1_pins: pinmux_mcspi1_pins {
+ pinctrl-single,pins = <
+ 0x3a4 0x40000 /* spi2_clk */
+ 0x3a8 0x40000 /* spi2_d1 */
+ 0x3ac 0x40000 /* spi2_d0 */
+ 0x3b0 0xc0000 /* spi2_cs0 */
+ 0x3b4 0xc0000 /* spi2_cs1 */
+ 0x3b8 0xe0006 /* spi2_cs2 */
+ 0x3bc 0xe0006 /* spi2_cs3 */
+ >;
+ };
+
+ mcspi2_pins: pinmux_mcspi2_pins {
+ pinctrl-single,pins = <
+ 0x3c0 0x40000 /* spi2_sclk */
+ 0x3c4 0xc0000 /* spi2_d1 */
+ 0x3c8 0xc0000 /* spi2_d1 */
+ 0x3cc 0xe0000 /* spi2_cs0 */
+ >;
+ };
+
+ uart1_pins: pinmux_uart1_pins {
+ pinctrl-single,pins = <
+ 0x3e0 0xe0000 /* uart1_rxd */
+ 0x3e4 0xe0000 /* uart1_txd */
+ 0x3e8 0x60003 /* uart1_ctsn */
+ 0x3ec 0x60003 /* uart1_rtsn */
+ >;
+ };
+
+ uart2_pins: pinmux_uart2_pins {
+ pinctrl-single,pins = <
+ 0x3f0 0x60000 /* uart2_rxd */
+ 0x3f4 0x60000 /* uart2_txd */
+ 0x3f8 0x60000 /* uart2_ctsn */
+ 0x3fc 0x60000 /* uart2_rtsn */
+ >;
+ };
+
+ uart3_pins: pinmux_uart3_pins {
+ pinctrl-single,pins = <
+ 0x248 0xc0000 /* uart3_rxd */
+ 0x24c 0xc0000 /* uart3_txd */
+ >;
+ };
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+
+ clock-frequency = <400000>;
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins>;
+
+ clock-frequency = <400000>;
+};
+
+&i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3_pins>;
+
+ clock-frequency = <3400000>;
+};
+
+&i2c4 {
+ status = "disabled";
+};
+
+&i2c5 {
+ status = "disabled";
+};
+
+&mcspi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcspi1_pins>;
+};
+
+&mcspi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcspi2_pins>;
+};
+
+&mcspi3 {
+ status = "disabled";
+};
+
+&mcspi4 {
+ status = "disabled";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>;
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pins>;
+};
+
+&uart4 {
+ status = "disabled";
+};
+
+&uart5 {
+ status = "disabled";
+};
+
+&uart6 {
+ status = "disabled";
+};
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
new file mode 100644
index 0000000..8a0c08e
--- /dev/null
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -0,0 +1,488 @@
+/*
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ * Based on "omap4.dtsi"
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+ compatible = "ti,dra7xx";
+ interrupt-parent = <&gic>;
+
+ aliases {
+ serial0 = &uart1;
+ serial1 = &uart2;
+ serial2 = &uart3;
+ serial3 = &uart4;
+ serial4 = &uart5;
+ serial5 = &uart6;
+ };
+
+ cpus {
+ cpu@0 {
+ compatible = "arm,cortex-a15";
+ timer {
+ compatible = "arm,armv7-timer";
+ /*
+ * PPI secure/nonsecure IRQ,
+ * active low level-sensitive
+ */
+ interrupts = <1 13 0x308>,
+ <1 14 0x308>;
+ clock-frequency = <6144000>;
+ };
+ };
+ cpu@1 {
+ compatible = "arm,cortex-a15";
+ timer {
+ compatible = "arm,armv7-timer";
+ /*
+ * PPI secure/nonsecure IRQ,
+ * active low level-sensitive
+ */
+ interrupts = <1 13 0x308>,
+ <1 14 0x308>;
+ clock-frequency = <6144000>;
+ };
+ };
+ };
+
+ gic: interrupt-controller@48211000 {
+ compatible = "arm,cortex-a15-gic";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ reg = <0x48211000 0x1000>,
+ <0x48212000 0x1000>;
+ };
+
+ /*
+ * The soc node represents the soc top level view. It is uses for IPs
+ * that are not memory mapped in the MPU view or for the MPU itself.
+ */
+ soc {
+ compatible = "ti,omap-infra";
+ mpu {
+ compatible = "ti,omap5-mpu";
+ ti,hwmods = "mpu";
+ };
+ };
+
+ /*
+ * XXX: Use a flat representation of the SOC interconnect.
+ * The real OMAP interconnect network is quite complex.
+ * Since that will not bring real advantage to represent that in DT for
+ * the moment, just use a fake OCP bus entry to represent the whole bus
+ * hierarchy.
+ */
+ ocp {
+ compatible = "ti,omap4-l3-noc", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ ti,hwmods = "l3_main_1", "l3_main_2";
+
+ counter32k: counter@4ae04000 {
+ compatible = "ti,omap-counter32k";
+ reg = <0x4ae04000 0x40>;
+ ti,hwmods = "counter_32k";
+ };
+
+ dra7_pmx_core: pinmux@4a003400 {
+ compatible = "pinctrl-single";
+ reg = <0x4a003400 0x0464>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x3fffffff>;
+ };
+
+ sdma: dma-controller@4a056000 {
+ compatible = "ti,omap4430-sdma";
+ reg = <0x4a056000 0x1000>;
+ interrupts = <0 12 0x4>,
+ <0 13 0x4>,
+ <0 14 0x4>,
+ <0 15 0x4>;
+ #dma-cells = <1>;
+ #dma-channels = <32>;
+ #dma-requests = <127>;
+ };
+
+ gpio1: gpio@4ae10000 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x4ae10000 0x200>;
+ interrupts = <0 29 0x4>;
+ ti,hwmods = "gpio1";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ gpio2: gpio@48055000 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x48055000 0x200>;
+ interrupts = <0 30 0x4>;
+ ti,hwmods = "gpio2";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ gpio3: gpio@48057000 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x48057000 0x200>;
+ interrupts = <0 31 0x4>;
+ ti,hwmods = "gpio3";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ gpio4: gpio@48059000 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x48059000 0x200>;
+ interrupts = <0 32 0x4>;
+ ti,hwmods = "gpio4";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ gpio5: gpio@4805b000 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x4805b000 0x200>;
+ interrupts = <0 33 0x4>;
+ ti,hwmods = "gpio5";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ gpio6: gpio@4805d000 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x4805d000 0x200>;
+ interrupts = <0 34 0x4>;
+ ti,hwmods = "gpio6";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ gpio7: gpio@48051000 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x48051000 0x200>;
+ interrupts = <0 35 0x4>;
+ ti,hwmods = "gpio7";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ gpio8: gpio@48053000 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x48053000 0x200>;
+ interrupts = <0 121 0x4>;
+ ti,hwmods = "gpio8";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ uart1: serial@4806a000 {
+ compatible = "ti,omap4-uart";
+ reg = <0x4806a000 0x100>;
+ interrupts = <0 72 0x4>;
+ ti,hwmods = "uart1";
+ clock-frequency = <48000000>;
+ };
+
+ uart2: serial@4806c000 {
+ compatible = "ti,omap4-uart";
+ reg = <0x4806c000 0x100>;
+ interrupts = <0 73 0x4>;
+ ti,hwmods = "uart2";
+ clock-frequency = <48000000>;
+ };
+
+ uart3: serial@48020000 {
+ compatible = "ti,omap4-uart";
+ reg = <0x48020000 0x100>;
+ interrupts = <0 74 0x4>;
+ ti,hwmods = "uart3";
+ clock-frequency = <48000000>;
+ };
+
+ uart4: serial@4806e000 {
+ compatible = "ti,omap4-uart";
+ reg = <0x4806e000 0x100>;
+ interrupts = <0 70 0x4>;
+ ti,hwmods = "uart4";
+ clock-frequency = <48000000>;
+ };
+
+ uart5: serial@48066000 {
+ compatible = "ti,omap4-uart";
+ reg = <0x48066000 0x100>;
+ interrupts = <0 105 0x4>;
+ ti,hwmods = "uart5";
+ clock-frequency = <48000000>;
+ };
+
+ uart6: serial@48068000 {
+ compatible = "ti,omap4-uart";
+ reg = <0x48068000 0x100>;
+ interrupts = <0 106 0x4>;
+ ti,hwmods = "uart6";
+ clock-frequency = <48000000>;
+ };
+
+ timer1: timer@4ae18000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x4ae18000 0x80>;
+ interrupts = <0 37 0x4>;
+ ti,hwmods = "timer1";
+ ti,timer-alwon;
+ };
+
+ timer2: timer@48032000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x48032000 0x80>;
+ interrupts = <0 38 0x4>;
+ ti,hwmods = "timer2";
+ };
+
+ timer3: timer@48034000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x48034000 0x80>;
+ interrupts = <0 39 0x4>;
+ ti,hwmods = "timer3";
+ };
+
+ timer4: timer@48036000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x48036000 0x80>;
+ interrupts = <0 40 0x4>;
+ ti,hwmods = "timer4";
+ };
+
+ timer5: timer@48820000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x48820000 0x80>;
+ interrupts = <0 41 0x4>;
+ ti,hwmods = "timer5";
+ ti,timer-dsp;
+ };
+
+ timer6: timer@48822000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x48822000 0x80>;
+ interrupts = <0 42 0x4>;
+ ti,hwmods = "timer6";
+ ti,timer-dsp;
+ ti,timer-pwm;
+ };
+
+ timer7: timer@48824000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x48824000 0x80>;
+ interrupts = <0 43 0x4>;
+ ti,hwmods = "timer7";
+ ti,timer-dsp;
+ };
+
+ timer8: timer@48826000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x48826000 0x80>;
+ interrupts = <0 44 0x4>;
+ ti,hwmods = "timer8";
+ ti,timer-dsp;
+ ti,timer-pwm;
+ };
+
+ timer9: timer@4803e000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x4803e000 0x80>;
+ interrupts = <0 45 0x4>;
+ ti,hwmods = "timer9";
+ };
+
+ timer10: timer@48086000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x48086000 0x80>;
+ interrupts = <0 46 0x4>;
+ ti,hwmods = "timer10";
+ };
+
+ timer11: timer@48088000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x48088000 0x80>;
+ interrupts = <0 47 0x4>;
+ ti,hwmods = "timer11";
+ ti,timer-pwm;
+ };
+
+ wdt2: wdt@4ae14000 {
+ compatible = "ti,omap4-wdt";
+ reg = <0x4ae14000 0x80>;
+ interrupts = <0 80 0x4>;
+ ti,hwmods = "wd_timer2";
+ };
+
+ i2c1: i2c@48070000 {
+ compatible = "ti,omap4-i2c";
+ reg = <0x48070000 0x100>;
+ interrupts = <0 56 0x4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "i2c1";
+ };
+
+ i2c2: i2c@48072000 {
+ compatible = "ti,omap4-i2c";
+ reg = <0x48072000 0x100>;
+ interrupts = <0 57 0x4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "i2c2";
+ };
+
+ i2c3: i2c@48060000 {
+ compatible = "ti,omap4-i2c";
+ reg = <0x48060000 0x100>;
+ interrupts = <0 61 0x4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "i2c3";
+ };
+
+ i2c4: i2c@4807a000 {
+ compatible = "ti,omap4-i2c";
+ reg = <0x4807a000 0x100>;
+ interrupts = <0 62 0x4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "i2c4";
+ };
+
+ i2c5: i2c@4807c000 {
+ compatible = "ti,omap4-i2c";
+ reg = <0x4807c000 0x100>;
+ interrupts = <0 60 0x4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "i2c5";
+ };
+
+ mmc1: mmc@4809c000 {
+ compatible = "ti,omap4-hsmmc";
+ reg = <0x4809c000 0x400>;
+ interrupts = <0 83 0x4>;
+ ti,hwmods = "mmc1";
+ ti,dual-volt;
+ ti,needs-special-reset;
+ dmas = <&sdma 61>, <&sdma 62>;
+ dma-names = "tx", "rx";
+ };
+
+ mmc2: mmc@480b4000 {
+ compatible = "ti,omap4-hsmmc";
+ reg = <0x480b4000 0x400>;
+ interrupts = <0 86 0x4>;
+ ti,hwmods = "mmc2";
+ ti,needs-special-reset;
+ dmas = <&sdma 47>, <&sdma 48>;
+ dma-names = "tx", "rx";
+ };
+
+ mmc3: mmc@480ad000 {
+ compatible = "ti,omap4-hsmmc";
+ reg = <0x480ad000 0x400>;
+ interrupts = <0 94 0x4>;
+ ti,hwmods = "mmc3";
+ ti,needs-special-reset;
+ dmas = <&sdma 77>, <&sdma 78>;
+ dma-names = "tx", "rx";
+ };
+
+ mmc4: mmc@480d1000 {
+ compatible = "ti,omap4-hsmmc";
+ reg = <0x480d1000 0x400>;
+ interrupts = <0 96 0x4>;
+ ti,hwmods = "mmc4";
+ ti,needs-special-reset;
+ dmas = <&sdma 57>, <&sdma 58>;
+ dma-names = "tx", "rx";
+ };
+
+ mcspi1: spi@48098000 {
+ compatible = "ti,omap4-mcspi";
+ reg = <0x48098000 0x200>;
+ interrupts = <0 65 0x4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "mcspi1";
+ ti,spi-num-cs = <4>;
+ dmas = <&sdma 35>,
+ <&sdma 36>,
+ <&sdma 37>,
+ <&sdma 38>,
+ <&sdma 39>,
+ <&sdma 40>,
+ <&sdma 41>,
+ <&sdma 42>;
+ dma-names = "tx0", "rx0", "tx1", "rx1",
+ "tx2", "rx2", "tx3", "rx3";
+ };
+
+ mcspi2: spi@4809a000 {
+ compatible = "ti,omap4-mcspi";
+ reg = <0x4809a000 0x200>;
+ interrupts = <0 66 0x4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "mcspi2";
+ ti,spi-num-cs = <2>;
+ dmas = <&sdma 43>,
+ <&sdma 44>,
+ <&sdma 45>,
+ <&sdma 46>;
+ dma-names = "tx0", "rx0", "tx1", "rx1";
+ };
+
+ mcspi3: spi@480b8000 {
+ compatible = "ti,omap4-mcspi";
+ reg = <0x480b8000 0x200>;
+ interrupts = <0 91 0x4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "mcspi3";
+ ti,spi-num-cs = <2>;
+ dmas = <&sdma 15>, <&sdma 16>;
+ dma-names = "tx0", "rx0";
+ };
+
+ mcspi4: spi@480ba000 {
+ compatible = "ti,omap4-mcspi";
+ reg = <0x480ba000 0x200>;
+ interrupts = <0 48 0x4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "mcspi4";
+ ti,spi-num-cs = <1>;
+ dmas = <&sdma 70>, <&sdma 71>;
+ dma-names = "tx0", "rx0";
+ };
+ };
+};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 41+ messages in thread
* Re: [PATCH v2 3/8] ARM: DRA7: Reuse all of PRCM and MPUSS SMP infra
2013-07-30 11:25 ` [PATCH v2 3/8] ARM: DRA7: Reuse all of PRCM and MPUSS SMP infra Rajendra Nayak
@ 2013-07-30 12:26 ` Nishanth Menon
2013-07-30 12:38 ` Rajendra Nayak
0 siblings, 1 reply; 41+ messages in thread
From: Nishanth Menon @ 2013-07-30 12:26 UTC (permalink / raw)
To: Rajendra Nayak
Cc: linux-omap, linux-arm-kernel, tony, paul, khilman, benoit.cousson,
r.sricharan, ambresh, sourav.poddar
On 07/30/2013 06:25 AM, Rajendra Nayak wrote:
> From: R Sricharan <r.sricharan@ti.com>
[...]
> # Clock framework
> obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o
> @@ -181,6 +187,8 @@ obj-$(CONFIG_SOC_AM33XX) += $(clock-common) dpll3xxx.o
> obj-$(CONFIG_SOC_AM33XX) += cclock33xx_data.o
> obj-$(CONFIG_SOC_OMAP5) += $(clock-common)
> obj-$(CONFIG_SOC_OMAP5) += dpll3xxx.o dpll44xx.o
> +obj-$(CONFIG_SOC_DRA7XX) += $(clock-common)
> +obj-$(CONFIG_SOC_DRA7XX) += dpll3xxx.o dpll44xx.o
>
are these in sync with DRA7 support being introduced for clock data in [1]?
[1] http://marc.info/?l=linux-omap&m=137456411706971&w=2
--
Regards,
Nishanth Menon
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v2 8/8] ARM: DRA7: dts: Add the dts files for dra7 SoC and dra7-evm board
2013-07-30 11:25 ` [PATCH v2 8/8] ARM: DRA7: dts: Add the dts files for dra7 SoC and dra7-evm board Rajendra Nayak
@ 2013-07-30 12:30 ` Nishanth Menon
2013-07-30 12:41 ` Rajendra Nayak
2013-08-12 11:44 ` Mark Rutland
1 sibling, 1 reply; 41+ messages in thread
From: Nishanth Menon @ 2013-07-30 12:30 UTC (permalink / raw)
To: Rajendra Nayak
Cc: linux-omap, linux-arm-kernel, tony, paul, khilman, benoit.cousson,
r.sricharan, ambresh, sourav.poddar
On 07/30/2013 06:25 AM, Rajendra Nayak wrote:
> From: R Sricharan <r.sricharan@ti.com>
>
> Add minimal device tree source needed for DRA7 based SoCs.
> Also add a board dts file for the dra7-evm (based on dra752)
> which contains 1.5G of memory with 1G interleaved and 512MB
> non-interleaved. Also added in the board file are pin configuration
> details for i2c, mcspi and uart devices on board.
>
> Signed-off-by: R Sricharan <r.sricharan@ti.com>
> Signed-off-by: Rajendra Nayak <rnayak@ti.com>
> Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
> ---
> arch/arm/boot/dts/Makefile | 3 +-
> arch/arm/boot/dts/dra7-evm.dts | 163 ++++++++++++++
> arch/arm/boot/dts/dra7.dtsi | 488 ++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 653 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/boot/dts/dra7-evm.dts
> create mode 100644 arch/arm/boot/dts/dra7.dtsi
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 641b3c9..e2f8566 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -173,7 +173,8 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
> am335x-bone.dtb \
> am3517-evm.dtb \
> am3517_mt_ventoux.dtb \
> - am43x-epos-evm.dtb
> + am43x-epos-evm.dtb \
> + dra7-evm.dtb
> dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb
> dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
> dtb-$(CONFIG_ARCH_U8500) += snowball.dtb \
> diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
> new file mode 100644
> index 0000000..7b0b563
> --- /dev/null
> +++ b/arch/arm/boot/dts/dra7-evm.dts
> @@ -0,0 +1,163 @@
> +/*
> + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +/dts-v1/;
> +
> +/include/ "dra7.dtsi"
> +
> +/ {
> + model = "TI DRA7";
> + compatible = "ti,dra7-evm", "ti,dra7";
> +
> + memory {
> + device_type = "memory";
> + reg = <0x80000000 0x60000000>; /* 1536 MB */
> + };
> +};
> +
> +&dra7_pmx_core {
> + i2c1_pins: pinmux_i2c1_pins {
> + pinctrl-single,pins = <
> + 0x400 0x60000 /* i2c1_sda */
> + 0x404 0x60000 /* i2c1_scl */
> + >;
> + };
> +
> + i2c2_pins: pinmux_i2c2_pins {
> + pinctrl-single,pins = <
> + 0x408 0x60000 /* i2c2_sda */
> + 0x40c 0x60000 /* i2c2_scl */
> + >;
> + };
> +
> + i2c3_pins: pinmux_i2c3_pins {
> + pinctrl-single,pins = <
> + 0x410 0x60000 /* i2c3_sda */
> + 0x414 0x60000 /* i2c3_scl */
> + >;
> + };
> +
> + mcspi1_pins: pinmux_mcspi1_pins {
> + pinctrl-single,pins = <
> + 0x3a4 0x40000 /* spi2_clk */
> + 0x3a8 0x40000 /* spi2_d1 */
> + 0x3ac 0x40000 /* spi2_d0 */
> + 0x3b0 0xc0000 /* spi2_cs0 */
> + 0x3b4 0xc0000 /* spi2_cs1 */
> + 0x3b8 0xe0006 /* spi2_cs2 */
> + 0x3bc 0xe0006 /* spi2_cs3 */
> + >;
> + };
> +
> + mcspi2_pins: pinmux_mcspi2_pins {
> + pinctrl-single,pins = <
> + 0x3c0 0x40000 /* spi2_sclk */
> + 0x3c4 0xc0000 /* spi2_d1 */
> + 0x3c8 0xc0000 /* spi2_d1 */
> + 0x3cc 0xe0000 /* spi2_cs0 */
> + >;
> + };
> +
> + uart1_pins: pinmux_uart1_pins {
> + pinctrl-single,pins = <
> + 0x3e0 0xe0000 /* uart1_rxd */
> + 0x3e4 0xe0000 /* uart1_txd */
> + 0x3e8 0x60003 /* uart1_ctsn */
> + 0x3ec 0x60003 /* uart1_rtsn */
> + >;
> + };
> +
> + uart2_pins: pinmux_uart2_pins {
> + pinctrl-single,pins = <
> + 0x3f0 0x60000 /* uart2_rxd */
> + 0x3f4 0x60000 /* uart2_txd */
> + 0x3f8 0x60000 /* uart2_ctsn */
> + 0x3fc 0x60000 /* uart2_rtsn */
> + >;
> + };
> +
> + uart3_pins: pinmux_uart3_pins {
> + pinctrl-single,pins = <
> + 0x248 0xc0000 /* uart3_rxd */
> + 0x24c 0xc0000 /* uart3_txd */
> + >;
> + };
> +};
> +
> +&i2c1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c1_pins>;
> +
> + clock-frequency = <400000>;
> +};
> +
> +&i2c2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c2_pins>;
> +
> + clock-frequency = <400000>;
> +};
> +
> +&i2c3 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c3_pins>;
> +
> + clock-frequency = <3400000>;
> +};
> +
> +&i2c4 {
> + status = "disabled";
> +};
> +
> +&i2c5 {
> + status = "disabled";
> +};
> +
> +&mcspi1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&mcspi1_pins>;
> +};
> +
> +&mcspi2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&mcspi2_pins>;
> +};
> +
> +&mcspi3 {
> + status = "disabled";
> +};
> +
> +&mcspi4 {
> + status = "disabled";
> +};
> +
> +&uart1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart1_pins>;
> +};
> +
> +&uart2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart2_pins>;
> +};
> +
> +&uart3 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart3_pins>;
> +};
> +
> +&uart4 {
> + status = "disabled";
> +};
> +
> +&uart5 {
> + status = "disabled";
> +};
> +
> +&uart6 {
> + status = "disabled";
> +};
> diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
> new file mode 100644
> index 0000000..8a0c08e
> --- /dev/null
> +++ b/arch/arm/boot/dts/dra7.dtsi
> @@ -0,0 +1,488 @@
> +/*
> + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + * Based on "omap4.dtsi"
> + */
> +
> +/include/ "skeleton.dtsi"
> +
> +/ {
> + compatible = "ti,dra7xx";
> + interrupt-parent = <&gic>;
> +
> + aliases {
> + serial0 = &uart1;
> + serial1 = &uart2;
> + serial2 = &uart3;
> + serial3 = &uart4;
> + serial4 = &uart5;
> + serial5 = &uart6;
> + };
> +
> + cpus {
> + cpu@0 {
> + compatible = "arm,cortex-a15";
> + timer {
> + compatible = "arm,armv7-timer";
> + /*
> + * PPI secure/nonsecure IRQ,
> + * active low level-sensitive
> + */
> + interrupts = <1 13 0x308>,
> + <1 14 0x308>;
> + clock-frequency = <6144000>;
> + };
> + };
> + cpu@1 {
> + compatible = "arm,cortex-a15";
> + timer {
> + compatible = "arm,armv7-timer";
> + /*
> + * PPI secure/nonsecure IRQ,
> + * active low level-sensitive
> + */
> + interrupts = <1 13 0x308>,
> + <1 14 0x308>;
> + clock-frequency = <6144000>;
> + };
> + };
> + };
> +
> + gic: interrupt-controller@48211000 {
> + compatible = "arm,cortex-a15-gic";
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + reg = <0x48211000 0x1000>,
> + <0x48212000 0x1000>;
> + };
> +
> + /*
> + * The soc node represents the soc top level view. It is uses for IPs
> + * that are not memory mapped in the MPU view or for the MPU itself.
> + */
> + soc {
> + compatible = "ti,omap-infra";
> + mpu {
> + compatible = "ti,omap5-mpu";
> + ti,hwmods = "mpu";
> + };
> + };
> +
> + /*
> + * XXX: Use a flat representation of the SOC interconnect.
> + * The real OMAP interconnect network is quite complex.
> + * Since that will not bring real advantage to represent that in DT for
> + * the moment, just use a fake OCP bus entry to represent the whole bus
> + * hierarchy.
> + */
> + ocp {
> + compatible = "ti,omap4-l3-noc", "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> + ti,hwmods = "l3_main_1", "l3_main_2";
> +
> + counter32k: counter@4ae04000 {
> + compatible = "ti,omap-counter32k";
> + reg = <0x4ae04000 0x40>;
> + ti,hwmods = "counter_32k";
> + };
> +
> + dra7_pmx_core: pinmux@4a003400 {
> + compatible = "pinctrl-single";
> + reg = <0x4a003400 0x0464>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pinctrl-single,register-width = <32>;
> + pinctrl-single,function-mask = <0x3fffffff>;
> + };
> +
> + sdma: dma-controller@4a056000 {
> + compatible = "ti,omap4430-sdma";
> + reg = <0x4a056000 0x1000>;
> + interrupts = <0 12 0x4>,
> + <0 13 0x4>,
> + <0 14 0x4>,
> + <0 15 0x4>;
> + #dma-cells = <1>;
> + #dma-channels = <32>;
> + #dma-requests = <127>;
> + };
> +
> + gpio1: gpio@4ae10000 {
> + compatible = "ti,omap4-gpio";
> + reg = <0x4ae10000 0x200>;
> + interrupts = <0 29 0x4>;
> + ti,hwmods = "gpio1";
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> +
> + gpio2: gpio@48055000 {
> + compatible = "ti,omap4-gpio";
> + reg = <0x48055000 0x200>;
> + interrupts = <0 30 0x4>;
> + ti,hwmods = "gpio2";
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> +
> + gpio3: gpio@48057000 {
> + compatible = "ti,omap4-gpio";
> + reg = <0x48057000 0x200>;
> + interrupts = <0 31 0x4>;
> + ti,hwmods = "gpio3";
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> +
> + gpio4: gpio@48059000 {
> + compatible = "ti,omap4-gpio";
> + reg = <0x48059000 0x200>;
> + interrupts = <0 32 0x4>;
> + ti,hwmods = "gpio4";
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> +
> + gpio5: gpio@4805b000 {
> + compatible = "ti,omap4-gpio";
> + reg = <0x4805b000 0x200>;
> + interrupts = <0 33 0x4>;
> + ti,hwmods = "gpio5";
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> +
> + gpio6: gpio@4805d000 {
> + compatible = "ti,omap4-gpio";
> + reg = <0x4805d000 0x200>;
> + interrupts = <0 34 0x4>;
> + ti,hwmods = "gpio6";
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> +
> + gpio7: gpio@48051000 {
> + compatible = "ti,omap4-gpio";
> + reg = <0x48051000 0x200>;
> + interrupts = <0 35 0x4>;
> + ti,hwmods = "gpio7";
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> +
> + gpio8: gpio@48053000 {
> + compatible = "ti,omap4-gpio";
> + reg = <0x48053000 0x200>;
> + interrupts = <0 121 0x4>;
> + ti,hwmods = "gpio8";
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> +
> + uart1: serial@4806a000 {
> + compatible = "ti,omap4-uart";
> + reg = <0x4806a000 0x100>;
> + interrupts = <0 72 0x4>;
> + ti,hwmods = "uart1";
> + clock-frequency = <48000000>;
> + };
> +
> + uart2: serial@4806c000 {
> + compatible = "ti,omap4-uart";
> + reg = <0x4806c000 0x100>;
> + interrupts = <0 73 0x4>;
> + ti,hwmods = "uart2";
> + clock-frequency = <48000000>;
> + };
> +
> + uart3: serial@48020000 {
> + compatible = "ti,omap4-uart";
> + reg = <0x48020000 0x100>;
> + interrupts = <0 74 0x4>;
> + ti,hwmods = "uart3";
> + clock-frequency = <48000000>;
> + };
> +
> + uart4: serial@4806e000 {
> + compatible = "ti,omap4-uart";
> + reg = <0x4806e000 0x100>;
> + interrupts = <0 70 0x4>;
> + ti,hwmods = "uart4";
> + clock-frequency = <48000000>;
> + };
> +
> + uart5: serial@48066000 {
> + compatible = "ti,omap4-uart";
> + reg = <0x48066000 0x100>;
> + interrupts = <0 105 0x4>;
> + ti,hwmods = "uart5";
> + clock-frequency = <48000000>;
> + };
> +
> + uart6: serial@48068000 {
> + compatible = "ti,omap4-uart";
> + reg = <0x48068000 0x100>;
> + interrupts = <0 106 0x4>;
> + ti,hwmods = "uart6";
> + clock-frequency = <48000000>;
> + };
> +
> + timer1: timer@4ae18000 {
> + compatible = "ti,omap5430-timer";
> + reg = <0x4ae18000 0x80>;
> + interrupts = <0 37 0x4>;
> + ti,hwmods = "timer1";
> + ti,timer-alwon;
> + };
> +
> + timer2: timer@48032000 {
> + compatible = "ti,omap5430-timer";
> + reg = <0x48032000 0x80>;
> + interrupts = <0 38 0x4>;
> + ti,hwmods = "timer2";
> + };
> +
> + timer3: timer@48034000 {
> + compatible = "ti,omap5430-timer";
> + reg = <0x48034000 0x80>;
> + interrupts = <0 39 0x4>;
> + ti,hwmods = "timer3";
> + };
> +
> + timer4: timer@48036000 {
> + compatible = "ti,omap5430-timer";
> + reg = <0x48036000 0x80>;
> + interrupts = <0 40 0x4>;
> + ti,hwmods = "timer4";
> + };
> +
> + timer5: timer@48820000 {
> + compatible = "ti,omap5430-timer";
> + reg = <0x48820000 0x80>;
> + interrupts = <0 41 0x4>;
> + ti,hwmods = "timer5";
> + ti,timer-dsp;
> + };
> +
> + timer6: timer@48822000 {
> + compatible = "ti,omap5430-timer";
> + reg = <0x48822000 0x80>;
> + interrupts = <0 42 0x4>;
> + ti,hwmods = "timer6";
> + ti,timer-dsp;
> + ti,timer-pwm;
> + };
> +
> + timer7: timer@48824000 {
> + compatible = "ti,omap5430-timer";
> + reg = <0x48824000 0x80>;
> + interrupts = <0 43 0x4>;
> + ti,hwmods = "timer7";
> + ti,timer-dsp;
> + };
> +
> + timer8: timer@48826000 {
> + compatible = "ti,omap5430-timer";
> + reg = <0x48826000 0x80>;
> + interrupts = <0 44 0x4>;
> + ti,hwmods = "timer8";
> + ti,timer-dsp;
> + ti,timer-pwm;
> + };
> +
> + timer9: timer@4803e000 {
> + compatible = "ti,omap5430-timer";
> + reg = <0x4803e000 0x80>;
> + interrupts = <0 45 0x4>;
> + ti,hwmods = "timer9";
> + };
> +
> + timer10: timer@48086000 {
> + compatible = "ti,omap5430-timer";
> + reg = <0x48086000 0x80>;
> + interrupts = <0 46 0x4>;
> + ti,hwmods = "timer10";
> + };
> +
> + timer11: timer@48088000 {
> + compatible = "ti,omap5430-timer";
> + reg = <0x48088000 0x80>;
> + interrupts = <0 47 0x4>;
> + ti,hwmods = "timer11";
> + ti,timer-pwm;
> + };
> +
> + wdt2: wdt@4ae14000 {
> + compatible = "ti,omap4-wdt";
> + reg = <0x4ae14000 0x80>;
> + interrupts = <0 80 0x4>;
> + ti,hwmods = "wd_timer2";
> + };
> +
> + i2c1: i2c@48070000 {
> + compatible = "ti,omap4-i2c";
> + reg = <0x48070000 0x100>;
> + interrupts = <0 56 0x4>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + ti,hwmods = "i2c1";
> + };
> +
> + i2c2: i2c@48072000 {
> + compatible = "ti,omap4-i2c";
> + reg = <0x48072000 0x100>;
> + interrupts = <0 57 0x4>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + ti,hwmods = "i2c2";
> + };
> +
> + i2c3: i2c@48060000 {
> + compatible = "ti,omap4-i2c";
> + reg = <0x48060000 0x100>;
> + interrupts = <0 61 0x4>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + ti,hwmods = "i2c3";
> + };
> +
> + i2c4: i2c@4807a000 {
> + compatible = "ti,omap4-i2c";
> + reg = <0x4807a000 0x100>;
> + interrupts = <0 62 0x4>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + ti,hwmods = "i2c4";
> + };
> +
> + i2c5: i2c@4807c000 {
> + compatible = "ti,omap4-i2c";
> + reg = <0x4807c000 0x100>;
> + interrupts = <0 60 0x4>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + ti,hwmods = "i2c5";
> + };
> +
> + mmc1: mmc@4809c000 {
> + compatible = "ti,omap4-hsmmc";
> + reg = <0x4809c000 0x400>;
> + interrupts = <0 83 0x4>;
> + ti,hwmods = "mmc1";
> + ti,dual-volt;
> + ti,needs-special-reset;
> + dmas = <&sdma 61>, <&sdma 62>;
> + dma-names = "tx", "rx";
> + };
> +
> + mmc2: mmc@480b4000 {
> + compatible = "ti,omap4-hsmmc";
> + reg = <0x480b4000 0x400>;
> + interrupts = <0 86 0x4>;
> + ti,hwmods = "mmc2";
> + ti,needs-special-reset;
> + dmas = <&sdma 47>, <&sdma 48>;
> + dma-names = "tx", "rx";
> + };
> +
> + mmc3: mmc@480ad000 {
> + compatible = "ti,omap4-hsmmc";
> + reg = <0x480ad000 0x400>;
> + interrupts = <0 94 0x4>;
> + ti,hwmods = "mmc3";
> + ti,needs-special-reset;
> + dmas = <&sdma 77>, <&sdma 78>;
> + dma-names = "tx", "rx";
> + };
> +
> + mmc4: mmc@480d1000 {
> + compatible = "ti,omap4-hsmmc";
> + reg = <0x480d1000 0x400>;
> + interrupts = <0 96 0x4>;
> + ti,hwmods = "mmc4";
> + ti,needs-special-reset;
> + dmas = <&sdma 57>, <&sdma 58>;
> + dma-names = "tx", "rx";
> + };
> +
> + mcspi1: spi@48098000 {
> + compatible = "ti,omap4-mcspi";
> + reg = <0x48098000 0x200>;
> + interrupts = <0 65 0x4>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + ti,hwmods = "mcspi1";
> + ti,spi-num-cs = <4>;
> + dmas = <&sdma 35>,
> + <&sdma 36>,
> + <&sdma 37>,
> + <&sdma 38>,
> + <&sdma 39>,
> + <&sdma 40>,
> + <&sdma 41>,
> + <&sdma 42>;
> + dma-names = "tx0", "rx0", "tx1", "rx1",
> + "tx2", "rx2", "tx3", "rx3";
> + };
> +
> + mcspi2: spi@4809a000 {
> + compatible = "ti,omap4-mcspi";
> + reg = <0x4809a000 0x200>;
> + interrupts = <0 66 0x4>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + ti,hwmods = "mcspi2";
> + ti,spi-num-cs = <2>;
> + dmas = <&sdma 43>,
> + <&sdma 44>,
> + <&sdma 45>,
> + <&sdma 46>;
> + dma-names = "tx0", "rx0", "tx1", "rx1";
> + };
> +
> + mcspi3: spi@480b8000 {
> + compatible = "ti,omap4-mcspi";
> + reg = <0x480b8000 0x200>;
> + interrupts = <0 91 0x4>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + ti,hwmods = "mcspi3";
> + ti,spi-num-cs = <2>;
> + dmas = <&sdma 15>, <&sdma 16>;
> + dma-names = "tx0", "rx0";
> + };
> +
> + mcspi4: spi@480ba000 {
> + compatible = "ti,omap4-mcspi";
> + reg = <0x480ba000 0x200>;
> + interrupts = <0 48 0x4>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + ti,hwmods = "mcspi4";
> + ti,spi-num-cs = <1>;
> + dmas = <&sdma 70>, <&sdma 71>;
> + dma-names = "tx0", "rx0";
> + };
> + };
> +};
>
ref: [1], we discussed that we should now be able to introduce all
instances of h/w blocks into the dra7.dts. Further, considering [2]
would you not want to follow "status = disabled" for all modules by
default and enable required modules in board file, so that we dont have
to respin this yet again?
[1] http://marc.info/?t=137416599400001&r=1&w=2
[2] http://marc.info/?l=linux-omap&m=137510358229479&w=2
--
Regards,
Nishanth Menon
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v2 3/8] ARM: DRA7: Reuse all of PRCM and MPUSS SMP infra
2013-07-30 12:26 ` Nishanth Menon
@ 2013-07-30 12:38 ` Rajendra Nayak
2013-07-30 12:41 ` Nishanth Menon
0 siblings, 1 reply; 41+ messages in thread
From: Rajendra Nayak @ 2013-07-30 12:38 UTC (permalink / raw)
To: Nishanth Menon
Cc: linux-omap, linux-arm-kernel, tony, paul, khilman, benoit.cousson,
r.sricharan, ambresh, sourav.poddar
On Tuesday 30 July 2013 05:56 PM, Nishanth Menon wrote:
> On 07/30/2013 06:25 AM, Rajendra Nayak wrote:
>> From: R Sricharan <r.sricharan@ti.com>
> [...]
>> # Clock framework
>> obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o
>> @@ -181,6 +187,8 @@ obj-$(CONFIG_SOC_AM33XX) += $(clock-common) dpll3xxx.o
>> obj-$(CONFIG_SOC_AM33XX) += cclock33xx_data.o
>> obj-$(CONFIG_SOC_OMAP5) += $(clock-common)
>> obj-$(CONFIG_SOC_OMAP5) += dpll3xxx.o dpll44xx.o
>> +obj-$(CONFIG_SOC_DRA7XX) += $(clock-common)
>> +obj-$(CONFIG_SOC_DRA7XX) += dpll3xxx.o dpll44xx.o
>>
>
> are these in sync with DRA7 support being introduced for clock data in [1]?
I don't want to have a dependency on those patches since I am not sure of them
making it into 3.12.
>
>
> [1] http://marc.info/?l=linux-omap&m=137456411706971&w=2
>
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v2 8/8] ARM: DRA7: dts: Add the dts files for dra7 SoC and dra7-evm board
2013-07-30 12:30 ` Nishanth Menon
@ 2013-07-30 12:41 ` Rajendra Nayak
2013-07-30 12:46 ` Nishanth Menon
0 siblings, 1 reply; 41+ messages in thread
From: Rajendra Nayak @ 2013-07-30 12:41 UTC (permalink / raw)
To: Nishanth Menon
Cc: paul, khilman, tony, benoit.cousson, r.sricharan, ambresh,
sourav.poddar, linux-omap, linux-arm-kernel
On Tuesday 30 July 2013 06:00 PM, Nishanth Menon wrote:
> On 07/30/2013 06:25 AM, Rajendra Nayak wrote:
>> From: R Sricharan <r.sricharan@ti.com>
>>
>> Add minimal device tree source needed for DRA7 based SoCs.
>> Also add a board dts file for the dra7-evm (based on dra752)
>> which contains 1.5G of memory with 1G interleaved and 512MB
>> non-interleaved. Also added in the board file are pin configuration
>> details for i2c, mcspi and uart devices on board.
>>
>> Signed-off-by: R Sricharan <r.sricharan@ti.com>
>> Signed-off-by: Rajendra Nayak <rnayak@ti.com>
>> Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
>> ---
>> arch/arm/boot/dts/Makefile | 3 +-
>> arch/arm/boot/dts/dra7-evm.dts | 163 ++++++++++++++
>> arch/arm/boot/dts/dra7.dtsi | 488 ++++++++++++++++++++++++++++++++++++++++
>> 3 files changed, 653 insertions(+), 1 deletion(-)
>> create mode 100644 arch/arm/boot/dts/dra7-evm.dts
>> create mode 100644 arch/arm/boot/dts/dra7.dtsi
>>
>> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
>> index 641b3c9..e2f8566 100644
>> --- a/arch/arm/boot/dts/Makefile
>> +++ b/arch/arm/boot/dts/Makefile
>> @@ -173,7 +173,8 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
>> am335x-bone.dtb \
>> am3517-evm.dtb \
>> am3517_mt_ventoux.dtb \
>> - am43x-epos-evm.dtb
>> + am43x-epos-evm.dtb \
>> + dra7-evm.dtb
>> dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb
>> dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
>> dtb-$(CONFIG_ARCH_U8500) += snowball.dtb \
>> diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
>> new file mode 100644
>> index 0000000..7b0b563
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/dra7-evm.dts
>> @@ -0,0 +1,163 @@
>> +/*
>> + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + */
>> +/dts-v1/;
>> +
>> +/include/ "dra7.dtsi"
>> +
>> +/ {
>> + model = "TI DRA7";
>> + compatible = "ti,dra7-evm", "ti,dra7";
>> +
>> + memory {
>> + device_type = "memory";
>> + reg = <0x80000000 0x60000000>; /* 1536 MB */
>> + };
>> +};
>> +
>> +&dra7_pmx_core {
>> + i2c1_pins: pinmux_i2c1_pins {
>> + pinctrl-single,pins = <
>> + 0x400 0x60000 /* i2c1_sda */
>> + 0x404 0x60000 /* i2c1_scl */
>> + >;
>> + };
>> +
>> + i2c2_pins: pinmux_i2c2_pins {
>> + pinctrl-single,pins = <
>> + 0x408 0x60000 /* i2c2_sda */
>> + 0x40c 0x60000 /* i2c2_scl */
>> + >;
>> + };
>> +
>> + i2c3_pins: pinmux_i2c3_pins {
>> + pinctrl-single,pins = <
>> + 0x410 0x60000 /* i2c3_sda */
>> + 0x414 0x60000 /* i2c3_scl */
>> + >;
>> + };
>> +
>> + mcspi1_pins: pinmux_mcspi1_pins {
>> + pinctrl-single,pins = <
>> + 0x3a4 0x40000 /* spi2_clk */
>> + 0x3a8 0x40000 /* spi2_d1 */
>> + 0x3ac 0x40000 /* spi2_d0 */
>> + 0x3b0 0xc0000 /* spi2_cs0 */
>> + 0x3b4 0xc0000 /* spi2_cs1 */
>> + 0x3b8 0xe0006 /* spi2_cs2 */
>> + 0x3bc 0xe0006 /* spi2_cs3 */
>> + >;
>> + };
>> +
>> + mcspi2_pins: pinmux_mcspi2_pins {
>> + pinctrl-single,pins = <
>> + 0x3c0 0x40000 /* spi2_sclk */
>> + 0x3c4 0xc0000 /* spi2_d1 */
>> + 0x3c8 0xc0000 /* spi2_d1 */
>> + 0x3cc 0xe0000 /* spi2_cs0 */
>> + >;
>> + };
>> +
>> + uart1_pins: pinmux_uart1_pins {
>> + pinctrl-single,pins = <
>> + 0x3e0 0xe0000 /* uart1_rxd */
>> + 0x3e4 0xe0000 /* uart1_txd */
>> + 0x3e8 0x60003 /* uart1_ctsn */
>> + 0x3ec 0x60003 /* uart1_rtsn */
>> + >;
>> + };
>> +
>> + uart2_pins: pinmux_uart2_pins {
>> + pinctrl-single,pins = <
>> + 0x3f0 0x60000 /* uart2_rxd */
>> + 0x3f4 0x60000 /* uart2_txd */
>> + 0x3f8 0x60000 /* uart2_ctsn */
>> + 0x3fc 0x60000 /* uart2_rtsn */
>> + >;
>> + };
>> +
>> + uart3_pins: pinmux_uart3_pins {
>> + pinctrl-single,pins = <
>> + 0x248 0xc0000 /* uart3_rxd */
>> + 0x24c 0xc0000 /* uart3_txd */
>> + >;
>> + };
>> +};
>> +
>> +&i2c1 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&i2c1_pins>;
>> +
>> + clock-frequency = <400000>;
>> +};
>> +
>> +&i2c2 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&i2c2_pins>;
>> +
>> + clock-frequency = <400000>;
>> +};
>> +
>> +&i2c3 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&i2c3_pins>;
>> +
>> + clock-frequency = <3400000>;
>> +};
>> +
>> +&i2c4 {
>> + status = "disabled";
>> +};
>> +
>> +&i2c5 {
>> + status = "disabled";
>> +};
>> +
>> +&mcspi1 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&mcspi1_pins>;
>> +};
>> +
>> +&mcspi2 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&mcspi2_pins>;
>> +};
>> +
>> +&mcspi3 {
>> + status = "disabled";
>> +};
>> +
>> +&mcspi4 {
>> + status = "disabled";
>> +};
>> +
>> +&uart1 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&uart1_pins>;
>> +};
>> +
>> +&uart2 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&uart2_pins>;
>> +};
>> +
>> +&uart3 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&uart3_pins>;
>> +};
>> +
>> +&uart4 {
>> + status = "disabled";
>> +};
>> +
>> +&uart5 {
>> + status = "disabled";
>> +};
>> +
>> +&uart6 {
>> + status = "disabled";
>> +};
>> diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
>> new file mode 100644
>> index 0000000..8a0c08e
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/dra7.dtsi
>> @@ -0,0 +1,488 @@
>> +/*
>> + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + * Based on "omap4.dtsi"
>> + */
>> +
>> +/include/ "skeleton.dtsi"
>> +
>> +/ {
>> + compatible = "ti,dra7xx";
>> + interrupt-parent = <&gic>;
>> +
>> + aliases {
>> + serial0 = &uart1;
>> + serial1 = &uart2;
>> + serial2 = &uart3;
>> + serial3 = &uart4;
>> + serial4 = &uart5;
>> + serial5 = &uart6;
>> + };
>> +
>> + cpus {
>> + cpu@0 {
>> + compatible = "arm,cortex-a15";
>> + timer {
>> + compatible = "arm,armv7-timer";
>> + /*
>> + * PPI secure/nonsecure IRQ,
>> + * active low level-sensitive
>> + */
>> + interrupts = <1 13 0x308>,
>> + <1 14 0x308>;
>> + clock-frequency = <6144000>;
>> + };
>> + };
>> + cpu@1 {
>> + compatible = "arm,cortex-a15";
>> + timer {
>> + compatible = "arm,armv7-timer";
>> + /*
>> + * PPI secure/nonsecure IRQ,
>> + * active low level-sensitive
>> + */
>> + interrupts = <1 13 0x308>,
>> + <1 14 0x308>;
>> + clock-frequency = <6144000>;
>> + };
>> + };
>> + };
>> +
>> + gic: interrupt-controller@48211000 {
>> + compatible = "arm,cortex-a15-gic";
>> + interrupt-controller;
>> + #interrupt-cells = <3>;
>> + reg = <0x48211000 0x1000>,
>> + <0x48212000 0x1000>;
>> + };
>> +
>> + /*
>> + * The soc node represents the soc top level view. It is uses for IPs
>> + * that are not memory mapped in the MPU view or for the MPU itself.
>> + */
>> + soc {
>> + compatible = "ti,omap-infra";
>> + mpu {
>> + compatible = "ti,omap5-mpu";
>> + ti,hwmods = "mpu";
>> + };
>> + };
>> +
>> + /*
>> + * XXX: Use a flat representation of the SOC interconnect.
>> + * The real OMAP interconnect network is quite complex.
>> + * Since that will not bring real advantage to represent that in DT for
>> + * the moment, just use a fake OCP bus entry to represent the whole bus
>> + * hierarchy.
>> + */
>> + ocp {
>> + compatible = "ti,omap4-l3-noc", "simple-bus";
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
>> + ti,hwmods = "l3_main_1", "l3_main_2";
>> +
>> + counter32k: counter@4ae04000 {
>> + compatible = "ti,omap-counter32k";
>> + reg = <0x4ae04000 0x40>;
>> + ti,hwmods = "counter_32k";
>> + };
>> +
>> + dra7_pmx_core: pinmux@4a003400 {
>> + compatible = "pinctrl-single";
>> + reg = <0x4a003400 0x0464>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + pinctrl-single,register-width = <32>;
>> + pinctrl-single,function-mask = <0x3fffffff>;
>> + };
>> +
>> + sdma: dma-controller@4a056000 {
>> + compatible = "ti,omap4430-sdma";
>> + reg = <0x4a056000 0x1000>;
>> + interrupts = <0 12 0x4>,
>> + <0 13 0x4>,
>> + <0 14 0x4>,
>> + <0 15 0x4>;
>> + #dma-cells = <1>;
>> + #dma-channels = <32>;
>> + #dma-requests = <127>;
>> + };
>> +
>> + gpio1: gpio@4ae10000 {
>> + compatible = "ti,omap4-gpio";
>> + reg = <0x4ae10000 0x200>;
>> + interrupts = <0 29 0x4>;
>> + ti,hwmods = "gpio1";
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> + interrupt-controller;
>> + #interrupt-cells = <1>;
>> + };
>> +
>> + gpio2: gpio@48055000 {
>> + compatible = "ti,omap4-gpio";
>> + reg = <0x48055000 0x200>;
>> + interrupts = <0 30 0x4>;
>> + ti,hwmods = "gpio2";
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> + interrupt-controller;
>> + #interrupt-cells = <1>;
>> + };
>> +
>> + gpio3: gpio@48057000 {
>> + compatible = "ti,omap4-gpio";
>> + reg = <0x48057000 0x200>;
>> + interrupts = <0 31 0x4>;
>> + ti,hwmods = "gpio3";
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> + interrupt-controller;
>> + #interrupt-cells = <1>;
>> + };
>> +
>> + gpio4: gpio@48059000 {
>> + compatible = "ti,omap4-gpio";
>> + reg = <0x48059000 0x200>;
>> + interrupts = <0 32 0x4>;
>> + ti,hwmods = "gpio4";
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> + interrupt-controller;
>> + #interrupt-cells = <1>;
>> + };
>> +
>> + gpio5: gpio@4805b000 {
>> + compatible = "ti,omap4-gpio";
>> + reg = <0x4805b000 0x200>;
>> + interrupts = <0 33 0x4>;
>> + ti,hwmods = "gpio5";
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> + interrupt-controller;
>> + #interrupt-cells = <1>;
>> + };
>> +
>> + gpio6: gpio@4805d000 {
>> + compatible = "ti,omap4-gpio";
>> + reg = <0x4805d000 0x200>;
>> + interrupts = <0 34 0x4>;
>> + ti,hwmods = "gpio6";
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> + interrupt-controller;
>> + #interrupt-cells = <1>;
>> + };
>> +
>> + gpio7: gpio@48051000 {
>> + compatible = "ti,omap4-gpio";
>> + reg = <0x48051000 0x200>;
>> + interrupts = <0 35 0x4>;
>> + ti,hwmods = "gpio7";
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> + interrupt-controller;
>> + #interrupt-cells = <1>;
>> + };
>> +
>> + gpio8: gpio@48053000 {
>> + compatible = "ti,omap4-gpio";
>> + reg = <0x48053000 0x200>;
>> + interrupts = <0 121 0x4>;
>> + ti,hwmods = "gpio8";
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> + interrupt-controller;
>> + #interrupt-cells = <1>;
>> + };
>> +
>> + uart1: serial@4806a000 {
>> + compatible = "ti,omap4-uart";
>> + reg = <0x4806a000 0x100>;
>> + interrupts = <0 72 0x4>;
>> + ti,hwmods = "uart1";
>> + clock-frequency = <48000000>;
>> + };
>> +
>> + uart2: serial@4806c000 {
>> + compatible = "ti,omap4-uart";
>> + reg = <0x4806c000 0x100>;
>> + interrupts = <0 73 0x4>;
>> + ti,hwmods = "uart2";
>> + clock-frequency = <48000000>;
>> + };
>> +
>> + uart3: serial@48020000 {
>> + compatible = "ti,omap4-uart";
>> + reg = <0x48020000 0x100>;
>> + interrupts = <0 74 0x4>;
>> + ti,hwmods = "uart3";
>> + clock-frequency = <48000000>;
>> + };
>> +
>> + uart4: serial@4806e000 {
>> + compatible = "ti,omap4-uart";
>> + reg = <0x4806e000 0x100>;
>> + interrupts = <0 70 0x4>;
>> + ti,hwmods = "uart4";
>> + clock-frequency = <48000000>;
>> + };
>> +
>> + uart5: serial@48066000 {
>> + compatible = "ti,omap4-uart";
>> + reg = <0x48066000 0x100>;
>> + interrupts = <0 105 0x4>;
>> + ti,hwmods = "uart5";
>> + clock-frequency = <48000000>;
>> + };
>> +
>> + uart6: serial@48068000 {
>> + compatible = "ti,omap4-uart";
>> + reg = <0x48068000 0x100>;
>> + interrupts = <0 106 0x4>;
>> + ti,hwmods = "uart6";
>> + clock-frequency = <48000000>;
>> + };
>> +
>> + timer1: timer@4ae18000 {
>> + compatible = "ti,omap5430-timer";
>> + reg = <0x4ae18000 0x80>;
>> + interrupts = <0 37 0x4>;
>> + ti,hwmods = "timer1";
>> + ti,timer-alwon;
>> + };
>> +
>> + timer2: timer@48032000 {
>> + compatible = "ti,omap5430-timer";
>> + reg = <0x48032000 0x80>;
>> + interrupts = <0 38 0x4>;
>> + ti,hwmods = "timer2";
>> + };
>> +
>> + timer3: timer@48034000 {
>> + compatible = "ti,omap5430-timer";
>> + reg = <0x48034000 0x80>;
>> + interrupts = <0 39 0x4>;
>> + ti,hwmods = "timer3";
>> + };
>> +
>> + timer4: timer@48036000 {
>> + compatible = "ti,omap5430-timer";
>> + reg = <0x48036000 0x80>;
>> + interrupts = <0 40 0x4>;
>> + ti,hwmods = "timer4";
>> + };
>> +
>> + timer5: timer@48820000 {
>> + compatible = "ti,omap5430-timer";
>> + reg = <0x48820000 0x80>;
>> + interrupts = <0 41 0x4>;
>> + ti,hwmods = "timer5";
>> + ti,timer-dsp;
>> + };
>> +
>> + timer6: timer@48822000 {
>> + compatible = "ti,omap5430-timer";
>> + reg = <0x48822000 0x80>;
>> + interrupts = <0 42 0x4>;
>> + ti,hwmods = "timer6";
>> + ti,timer-dsp;
>> + ti,timer-pwm;
>> + };
>> +
>> + timer7: timer@48824000 {
>> + compatible = "ti,omap5430-timer";
>> + reg = <0x48824000 0x80>;
>> + interrupts = <0 43 0x4>;
>> + ti,hwmods = "timer7";
>> + ti,timer-dsp;
>> + };
>> +
>> + timer8: timer@48826000 {
>> + compatible = "ti,omap5430-timer";
>> + reg = <0x48826000 0x80>;
>> + interrupts = <0 44 0x4>;
>> + ti,hwmods = "timer8";
>> + ti,timer-dsp;
>> + ti,timer-pwm;
>> + };
>> +
>> + timer9: timer@4803e000 {
>> + compatible = "ti,omap5430-timer";
>> + reg = <0x4803e000 0x80>;
>> + interrupts = <0 45 0x4>;
>> + ti,hwmods = "timer9";
>> + };
>> +
>> + timer10: timer@48086000 {
>> + compatible = "ti,omap5430-timer";
>> + reg = <0x48086000 0x80>;
>> + interrupts = <0 46 0x4>;
>> + ti,hwmods = "timer10";
>> + };
>> +
>> + timer11: timer@48088000 {
>> + compatible = "ti,omap5430-timer";
>> + reg = <0x48088000 0x80>;
>> + interrupts = <0 47 0x4>;
>> + ti,hwmods = "timer11";
>> + ti,timer-pwm;
>> + };
>> +
>> + wdt2: wdt@4ae14000 {
>> + compatible = "ti,omap4-wdt";
>> + reg = <0x4ae14000 0x80>;
>> + interrupts = <0 80 0x4>;
>> + ti,hwmods = "wd_timer2";
>> + };
>> +
>> + i2c1: i2c@48070000 {
>> + compatible = "ti,omap4-i2c";
>> + reg = <0x48070000 0x100>;
>> + interrupts = <0 56 0x4>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + ti,hwmods = "i2c1";
>> + };
>> +
>> + i2c2: i2c@48072000 {
>> + compatible = "ti,omap4-i2c";
>> + reg = <0x48072000 0x100>;
>> + interrupts = <0 57 0x4>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + ti,hwmods = "i2c2";
>> + };
>> +
>> + i2c3: i2c@48060000 {
>> + compatible = "ti,omap4-i2c";
>> + reg = <0x48060000 0x100>;
>> + interrupts = <0 61 0x4>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + ti,hwmods = "i2c3";
>> + };
>> +
>> + i2c4: i2c@4807a000 {
>> + compatible = "ti,omap4-i2c";
>> + reg = <0x4807a000 0x100>;
>> + interrupts = <0 62 0x4>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + ti,hwmods = "i2c4";
>> + };
>> +
>> + i2c5: i2c@4807c000 {
>> + compatible = "ti,omap4-i2c";
>> + reg = <0x4807c000 0x100>;
>> + interrupts = <0 60 0x4>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + ti,hwmods = "i2c5";
>> + };
>> +
>> + mmc1: mmc@4809c000 {
>> + compatible = "ti,omap4-hsmmc";
>> + reg = <0x4809c000 0x400>;
>> + interrupts = <0 83 0x4>;
>> + ti,hwmods = "mmc1";
>> + ti,dual-volt;
>> + ti,needs-special-reset;
>> + dmas = <&sdma 61>, <&sdma 62>;
>> + dma-names = "tx", "rx";
>> + };
>> +
>> + mmc2: mmc@480b4000 {
>> + compatible = "ti,omap4-hsmmc";
>> + reg = <0x480b4000 0x400>;
>> + interrupts = <0 86 0x4>;
>> + ti,hwmods = "mmc2";
>> + ti,needs-special-reset;
>> + dmas = <&sdma 47>, <&sdma 48>;
>> + dma-names = "tx", "rx";
>> + };
>> +
>> + mmc3: mmc@480ad000 {
>> + compatible = "ti,omap4-hsmmc";
>> + reg = <0x480ad000 0x400>;
>> + interrupts = <0 94 0x4>;
>> + ti,hwmods = "mmc3";
>> + ti,needs-special-reset;
>> + dmas = <&sdma 77>, <&sdma 78>;
>> + dma-names = "tx", "rx";
>> + };
>> +
>> + mmc4: mmc@480d1000 {
>> + compatible = "ti,omap4-hsmmc";
>> + reg = <0x480d1000 0x400>;
>> + interrupts = <0 96 0x4>;
>> + ti,hwmods = "mmc4";
>> + ti,needs-special-reset;
>> + dmas = <&sdma 57>, <&sdma 58>;
>> + dma-names = "tx", "rx";
>> + };
>> +
>> + mcspi1: spi@48098000 {
>> + compatible = "ti,omap4-mcspi";
>> + reg = <0x48098000 0x200>;
>> + interrupts = <0 65 0x4>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + ti,hwmods = "mcspi1";
>> + ti,spi-num-cs = <4>;
>> + dmas = <&sdma 35>,
>> + <&sdma 36>,
>> + <&sdma 37>,
>> + <&sdma 38>,
>> + <&sdma 39>,
>> + <&sdma 40>,
>> + <&sdma 41>,
>> + <&sdma 42>;
>> + dma-names = "tx0", "rx0", "tx1", "rx1",
>> + "tx2", "rx2", "tx3", "rx3";
>> + };
>> +
>> + mcspi2: spi@4809a000 {
>> + compatible = "ti,omap4-mcspi";
>> + reg = <0x4809a000 0x200>;
>> + interrupts = <0 66 0x4>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + ti,hwmods = "mcspi2";
>> + ti,spi-num-cs = <2>;
>> + dmas = <&sdma 43>,
>> + <&sdma 44>,
>> + <&sdma 45>,
>> + <&sdma 46>;
>> + dma-names = "tx0", "rx0", "tx1", "rx1";
>> + };
>> +
>> + mcspi3: spi@480b8000 {
>> + compatible = "ti,omap4-mcspi";
>> + reg = <0x480b8000 0x200>;
>> + interrupts = <0 91 0x4>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + ti,hwmods = "mcspi3";
>> + ti,spi-num-cs = <2>;
>> + dmas = <&sdma 15>, <&sdma 16>;
>> + dma-names = "tx0", "rx0";
>> + };
>> +
>> + mcspi4: spi@480ba000 {
>> + compatible = "ti,omap4-mcspi";
>> + reg = <0x480ba000 0x200>;
>> + interrupts = <0 48 0x4>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + ti,hwmods = "mcspi4";
>> + ti,spi-num-cs = <1>;
>> + dmas = <&sdma 70>, <&sdma 71>;
>> + dma-names = "tx0", "rx0";
>> + };
>> + };
>> +};
>>
> ref: [1], we discussed that we should now be able to introduce all instances of h/w blocks into the dra7.dts. Further, considering [2]
hmm, thats a long discussion on crossbar driver that [1] points to. Do you want to summarize what you mean by 'introduce all instances of h/w blocks'
> would you not want to follow "status = disabled" for all modules by default and enable required modules in board file, so that we dont have to respin this yet again?
Well, I was just following the convention of whats already followed on existing OMAPs. See [3] for some views on these.
>
>
> [1] http://marc.info/?t=137416599400001&r=1&w=2
> [2] http://marc.info/?l=linux-omap&m=137510358229479&w=2
[3] http://lists.infradead.org/pipermail/linux-arm-kernel/2012-February/086297.html
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v2 3/8] ARM: DRA7: Reuse all of PRCM and MPUSS SMP infra
2013-07-30 12:38 ` Rajendra Nayak
@ 2013-07-30 12:41 ` Nishanth Menon
2013-07-30 12:48 ` Rajendra Nayak
0 siblings, 1 reply; 41+ messages in thread
From: Nishanth Menon @ 2013-07-30 12:41 UTC (permalink / raw)
To: Rajendra Nayak
Cc: linux-omap, linux-arm-kernel, tony, paul, khilman, benoit.cousson,
r.sricharan, ambresh, sourav.poddar
On 07/30/2013 07:38 AM, Rajendra Nayak wrote:
> On Tuesday 30 July 2013 05:56 PM, Nishanth Menon wrote:
>> On 07/30/2013 06:25 AM, Rajendra Nayak wrote:
>>> From: R Sricharan <r.sricharan@ti.com>
>> [...]
>>> # Clock framework
>>> obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o
>>> @@ -181,6 +187,8 @@ obj-$(CONFIG_SOC_AM33XX) += $(clock-common) dpll3xxx.o
>>> obj-$(CONFIG_SOC_AM33XX) += cclock33xx_data.o
>>> obj-$(CONFIG_SOC_OMAP5) += $(clock-common)
>>> obj-$(CONFIG_SOC_OMAP5) += dpll3xxx.o dpll44xx.o
>>> +obj-$(CONFIG_SOC_DRA7XX) += $(clock-common)
>>> +obj-$(CONFIG_SOC_DRA7XX) += dpll3xxx.o dpll44xx.o
>>>
>>
>> are these in sync with DRA7 support being introduced for clock data in [1]?
>
> I don't want to have a dependency on those patches since I am not sure of them
> making it into 3.12.
Then we have to undo these changes again in clock data support. the chip
wont bootup anyways without clock data information, so why not try and
keep the changes that Tero is doing independent of these changes?
>
>>
>>
>> [1] http://marc.info/?l=linux-omap&m=137456411706971&w=2
>>
>
--
Regards,
Nishanth Menon
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v2 8/8] ARM: DRA7: dts: Add the dts files for dra7 SoC and dra7-evm board
2013-07-30 12:41 ` Rajendra Nayak
@ 2013-07-30 12:46 ` Nishanth Menon
2013-07-30 12:56 ` Rajendra Nayak
0 siblings, 1 reply; 41+ messages in thread
From: Nishanth Menon @ 2013-07-30 12:46 UTC (permalink / raw)
To: Rajendra Nayak
Cc: linux-omap, linux-arm-kernel, tony, paul, khilman, benoit.cousson,
r.sricharan, ambresh, sourav.poddar
On 07/30/2013 07:41 AM, Rajendra Nayak wrote:
> On Tuesday 30 July 2013 06:00 PM, Nishanth Menon wrote:
>> On 07/30/2013 06:25 AM, Rajendra Nayak wrote:
>>> From: R Sricharan <r.sricharan@ti.com>
[...]
>>> + mcspi4: spi@480ba000 {
>>> + compatible = "ti,omap4-mcspi";
>>> + reg = <0x480ba000 0x200>;
>>> + interrupts = <0 48 0x4>;
>>> + #address-cells = <1>;
>>> + #size-cells = <0>;
>>> + ti,hwmods = "mcspi4";
>>> + ti,spi-num-cs = <1>;
>>> + dmas = <&sdma 70>, <&sdma 71>;
>>> + dma-names = "tx0", "rx0";
>>> + };
>>> + };
>>> +};
>>>
>> ref: [1], we discussed that we should now be able to introduce all instances of h/w blocks into the dra7.dts. Further, considering [2]
>
> hmm, thats a long discussion on crossbar driver that [1] points to. Do you want to summarize what you mean by 'introduce all instances of h/w blocks'
I recommend reading the last few emails on the thread about how we could
do this with pinctrl. unfortunately, this patch is not informative
enough to indicate that not all instances of the potential IP blocks are
listed here.
>
>> would you not want to follow "status = disabled" for all modules by default and enable required modules in board file, so that we dont have to respin this yet again?
>
> Well, I was just following the convention of whats already followed on existing OMAPs. See [3] for some views on these.
DRA7 case, I would not think it makes sense due to the number of product
variants being done, not all will use the same set. Further, rationale
for DRA7 and my suggestion for Grant's option (1) is mainly because the
product variants will require more dtsis rather than board files using
the product variants use just the necessary modules from a common dtsi.
Makes support of variants like OMAP57xx etc trivial and constrainted to
board file usage, rather than spinning off new dtsis.
>
>>
>>
>> [1] http://marc.info/?t=137416599400001&r=1&w=2
>> [2] http://marc.info/?l=linux-omap&m=137510358229479&w=2
> [3] http://lists.infradead.org/pipermail/linux-arm-kernel/2012-February/086297.html
>
--
Regards,
Nishanth Menon
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v2 3/8] ARM: DRA7: Reuse all of PRCM and MPUSS SMP infra
2013-07-30 12:41 ` Nishanth Menon
@ 2013-07-30 12:48 ` Rajendra Nayak
2013-07-30 12:57 ` Nishanth Menon
0 siblings, 1 reply; 41+ messages in thread
From: Rajendra Nayak @ 2013-07-30 12:48 UTC (permalink / raw)
To: Nishanth Menon
Cc: paul, khilman, tony, benoit.cousson, r.sricharan, ambresh,
sourav.poddar, linux-omap, linux-arm-kernel
On Tuesday 30 July 2013 06:11 PM, Nishanth Menon wrote:
> On 07/30/2013 07:38 AM, Rajendra Nayak wrote:
>> On Tuesday 30 July 2013 05:56 PM, Nishanth Menon wrote:
>>> On 07/30/2013 06:25 AM, Rajendra Nayak wrote:
>>>> From: R Sricharan <r.sricharan@ti.com>
>>> [...]
>>>> # Clock framework
>>>> obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o
>>>> @@ -181,6 +187,8 @@ obj-$(CONFIG_SOC_AM33XX) += $(clock-common) dpll3xxx.o
>>>> obj-$(CONFIG_SOC_AM33XX) += cclock33xx_data.o
>>>> obj-$(CONFIG_SOC_OMAP5) += $(clock-common)
>>>> obj-$(CONFIG_SOC_OMAP5) += dpll3xxx.o dpll44xx.o
>>>> +obj-$(CONFIG_SOC_DRA7XX) += $(clock-common)
>>>> +obj-$(CONFIG_SOC_DRA7XX) += dpll3xxx.o dpll44xx.o
>>>>
>>>
>>> are these in sync with DRA7 support being introduced for clock data in [1]?
>>
>> I don't want to have a dependency on those patches since I am not sure of them
>> making it into 3.12.
>
> Then we have to undo these changes again in clock data support. the chip wont bootup anyways without clock data information, so why not try and keep the changes that Tero is doing independent of these changes?
I still have something with clock data information which boots which I am maintaining out of tree till the clock movement to DT is sorted out.
Maybe what you are suggesting is quite trivial and I am unable to understand. Are you suggesting we do no compile $(clock-common) and the
dpll files for DRA7? Is that what you are worried we might have to revert?
>
>>
>>>
>>>
>>> [1] http://marc.info/?l=linux-omap&m=137456411706971&w=2
>>>
>>
>
>
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v2 8/8] ARM: DRA7: dts: Add the dts files for dra7 SoC and dra7-evm board
2013-07-30 12:46 ` Nishanth Menon
@ 2013-07-30 12:56 ` Rajendra Nayak
2013-07-30 12:59 ` Nishanth Menon
0 siblings, 1 reply; 41+ messages in thread
From: Rajendra Nayak @ 2013-07-30 12:56 UTC (permalink / raw)
To: Nishanth Menon
Cc: linux-omap, linux-arm-kernel, tony, paul, khilman, benoit.cousson,
r.sricharan, ambresh, sourav.poddar
On Tuesday 30 July 2013 06:16 PM, Nishanth Menon wrote:
> On 07/30/2013 07:41 AM, Rajendra Nayak wrote:
>> On Tuesday 30 July 2013 06:00 PM, Nishanth Menon wrote:
>>> On 07/30/2013 06:25 AM, Rajendra Nayak wrote:
>>>> From: R Sricharan <r.sricharan@ti.com>
> [...]
>>>> + mcspi4: spi@480ba000 {
>>>> + compatible = "ti,omap4-mcspi";
>>>> + reg = <0x480ba000 0x200>;
>>>> + interrupts = <0 48 0x4>;
>>>> + #address-cells = <1>;
>>>> + #size-cells = <0>;
>>>> + ti,hwmods = "mcspi4";
>>>> + ti,spi-num-cs = <1>;
>>>> + dmas = <&sdma 70>, <&sdma 71>;
>>>> + dma-names = "tx0", "rx0";
>>>> + };
>>>> + };
>>>> +};
>>>>
>>> ref: [1], we discussed that we should now be able to introduce all instances of h/w blocks into the dra7.dts. Further, considering [2]
>>
>> hmm, thats a long discussion on crossbar driver that [1] points to. Do you want to summarize what you mean by 'introduce all instances of h/w blocks'
>
> I recommend reading the last few emails on the thread about how we could do this with pinctrl. unfortunately, this patch is not informative enough to indicate that not all instances of the potential IP blocks are listed here.
>
>>
>>> would you not want to follow "status = disabled" for all modules by default and enable required modules in board file, so that we dont have to respin this yet again?
>>
>> Well, I was just following the convention of whats already followed on existing OMAPs. See [3] for some views on these.
>
> DRA7 case, I would not think it makes sense due to the number of product variants being done, not all will use the same set. Further, rationale for DRA7 and my suggestion for Grant's option (1) is mainly because the product variants will require more dtsis rather than board files using the product variants use just the necessary modules from a common dtsi. Makes support of variants like OMAP57xx etc trivial and constrainted to board file usage, rather than spinning off new dtsis.
Makes sense with the different product variants for DRA7, AM335x already does it this way, but the rest of OMAP3/4/5 are doing it the other way.
I think its just too confusing to follow different conventions for different SoCs. We should stick to just one, either this way or that.
>
>>
>>>
>>>
>>> [1] http://marc.info/?t=137416599400001&r=1&w=2
>>> [2] http://marc.info/?l=linux-omap&m=137510358229479&w=2
>> [3] http://lists.infradead.org/pipermail/linux-arm-kernel/2012-February/086297.html
>>
>
>
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v2 3/8] ARM: DRA7: Reuse all of PRCM and MPUSS SMP infra
2013-07-30 12:48 ` Rajendra Nayak
@ 2013-07-30 12:57 ` Nishanth Menon
2013-07-30 12:59 ` Rajendra Nayak
0 siblings, 1 reply; 41+ messages in thread
From: Nishanth Menon @ 2013-07-30 12:57 UTC (permalink / raw)
To: Rajendra Nayak
Cc: linux-omap, linux-arm-kernel, tony, paul, khilman, benoit.cousson,
r.sricharan, ambresh, sourav.poddar
On 07/30/2013 07:48 AM, Rajendra Nayak wrote:
> On Tuesday 30 July 2013 06:11 PM, Nishanth Menon wrote:
>> On 07/30/2013 07:38 AM, Rajendra Nayak wrote:
>>> On Tuesday 30 July 2013 05:56 PM, Nishanth Menon wrote:
>>>> On 07/30/2013 06:25 AM, Rajendra Nayak wrote:
>>>>> From: R Sricharan <r.sricharan@ti.com>
>>>> [...]
>>>>> # Clock framework
>>>>> obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o
>>>>> @@ -181,6 +187,8 @@ obj-$(CONFIG_SOC_AM33XX) += $(clock-common) dpll3xxx.o
>>>>> obj-$(CONFIG_SOC_AM33XX) += cclock33xx_data.o
>>>>> obj-$(CONFIG_SOC_OMAP5) += $(clock-common)
>>>>> obj-$(CONFIG_SOC_OMAP5) += dpll3xxx.o dpll44xx.o
>>>>> +obj-$(CONFIG_SOC_DRA7XX) += $(clock-common)
>>>>> +obj-$(CONFIG_SOC_DRA7XX) += dpll3xxx.o dpll44xx.o
>>>>>
>>>>
>>>> are these in sync with DRA7 support being introduced for clock data in [1]?
>>>
>>> I don't want to have a dependency on those patches since I am not sure of them
>>> making it into 3.12.
>>
>> Then we have to undo these changes again in clock data support. the chip wont bootup anyways without clock data information, so why not try and keep the changes that Tero is doing independent of these changes?
>
> I still have something with clock data information which boots which I am maintaining out of tree till the clock movement to DT is sorted out.
> Maybe what you are suggesting is quite trivial and I am unable to understand. Are you suggesting we do no compile $(clock-common) and the
> dpll files for DRA7? Is that what you are worried we might have to revert?
yes - lets just drop that change. that allows what ever alignment we
have for clock data/driver to handle it appropriately. IMHO, could also
keeps your series independent from Tero's series.
>>
>>>
>>>>
>>>>
>>>> [1] http://marc.info/?l=linux-omap&m=137456411706971&w=2
>>>>
>>>
>>
>>
>
--
Regards,
Nishanth Menon
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v2 3/8] ARM: DRA7: Reuse all of PRCM and MPUSS SMP infra
2013-07-30 12:57 ` Nishanth Menon
@ 2013-07-30 12:59 ` Rajendra Nayak
0 siblings, 0 replies; 41+ messages in thread
From: Rajendra Nayak @ 2013-07-30 12:59 UTC (permalink / raw)
To: Nishanth Menon
Cc: linux-omap, linux-arm-kernel, tony, paul, khilman, benoit.cousson,
r.sricharan, ambresh, sourav.poddar
On Tuesday 30 July 2013 06:27 PM, Nishanth Menon wrote:
> On 07/30/2013 07:48 AM, Rajendra Nayak wrote:
>> On Tuesday 30 July 2013 06:11 PM, Nishanth Menon wrote:
>>> On 07/30/2013 07:38 AM, Rajendra Nayak wrote:
>>>> On Tuesday 30 July 2013 05:56 PM, Nishanth Menon wrote:
>>>>> On 07/30/2013 06:25 AM, Rajendra Nayak wrote:
>>>>>> From: R Sricharan <r.sricharan@ti.com>
>>>>> [...]
>>>>>> # Clock framework
>>>>>> obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o
>>>>>> @@ -181,6 +187,8 @@ obj-$(CONFIG_SOC_AM33XX) += $(clock-common) dpll3xxx.o
>>>>>> obj-$(CONFIG_SOC_AM33XX) += cclock33xx_data.o
>>>>>> obj-$(CONFIG_SOC_OMAP5) += $(clock-common)
>>>>>> obj-$(CONFIG_SOC_OMAP5) += dpll3xxx.o dpll44xx.o
>>>>>> +obj-$(CONFIG_SOC_DRA7XX) += $(clock-common)
>>>>>> +obj-$(CONFIG_SOC_DRA7XX) += dpll3xxx.o dpll44xx.o
>>>>>>
>>>>>
>>>>> are these in sync with DRA7 support being introduced for clock data in [1]?
>>>>
>>>> I don't want to have a dependency on those patches since I am not sure of them
>>>> making it into 3.12.
>>>
>>> Then we have to undo these changes again in clock data support. the chip wont bootup anyways without clock data information, so why not try and keep the changes that Tero is doing independent of these changes?
>>
>> I still have something with clock data information which boots which I am maintaining out of tree till the clock movement to DT is sorted out.
>> Maybe what you are suggesting is quite trivial and I am unable to understand. Are you suggesting we do no compile $(clock-common) and the
>> dpll files for DRA7? Is that what you are worried we might have to revert?
>
> yes - lets just drop that change. that allows what ever alignment we have for clock data/driver to handle it appropriately. IMHO, could also keeps your series independent from Tero's series.
I can drop those. no issues.
>
>>>
>>>>
>>>>>
>>>>>
>>>>> [1] http://marc.info/?l=linux-omap&m=137456411706971&w=2
>>>>>
>>>>
>>>
>>>
>>
>
>
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v2 8/8] ARM: DRA7: dts: Add the dts files for dra7 SoC and dra7-evm board
2013-07-30 12:56 ` Rajendra Nayak
@ 2013-07-30 12:59 ` Nishanth Menon
2013-07-30 13:01 ` Rajendra Nayak
0 siblings, 1 reply; 41+ messages in thread
From: Nishanth Menon @ 2013-07-30 12:59 UTC (permalink / raw)
To: Rajendra Nayak
Cc: linux-omap, linux-arm-kernel, tony, paul, khilman, benoit.cousson,
r.sricharan, ambresh, sourav.poddar
On 07/30/2013 07:56 AM, Rajendra Nayak wrote:
> On Tuesday 30 July 2013 06:16 PM, Nishanth Menon wrote:
>> On 07/30/2013 07:41 AM, Rajendra Nayak wrote:
>>> On Tuesday 30 July 2013 06:00 PM, Nishanth Menon wrote:
>>>> On 07/30/2013 06:25 AM, Rajendra Nayak wrote:
>>>>> From: R Sricharan <r.sricharan@ti.com>
>> [...]
>>>>> + mcspi4: spi@480ba000 {
>>>>> + compatible = "ti,omap4-mcspi";
>>>>> + reg = <0x480ba000 0x200>;
>>>>> + interrupts = <0 48 0x4>;
>>>>> + #address-cells = <1>;
>>>>> + #size-cells = <0>;
>>>>> + ti,hwmods = "mcspi4";
>>>>> + ti,spi-num-cs = <1>;
>>>>> + dmas = <&sdma 70>, <&sdma 71>;
>>>>> + dma-names = "tx0", "rx0";
>>>>> + };
>>>>> + };
>>>>> +};
>>>>>
>>>> ref: [1], we discussed that we should now be able to introduce all instances of h/w blocks into the dra7.dts. Further, considering [2]
>>>
>>> hmm, thats a long discussion on crossbar driver that [1] points to. Do you want to summarize what you mean by 'introduce all instances of h/w blocks'
>>
>> I recommend reading the last few emails on the thread about how we could do this with pinctrl. unfortunately, this patch is not informative enough to indicate that not all instances of the potential IP blocks are listed here.
>>
>>>
>>>> would you not want to follow "status = disabled" for all modules by default and enable required modules in board file, so that we dont have to respin this yet again?
>>>
>>> Well, I was just following the convention of whats already followed on existing OMAPs. See [3] for some views on these.
>>
>> DRA7 case, I would not think it makes sense due to the number of product variants being done, not all will use the same set. Further, rationale for DRA7 and my suggestion for Grant's option (1) is mainly because the product variants will require more dtsis rather than board files using the product variants use just the necessary modules from a common dtsi. Makes support of variants like OMAP57xx etc trivial and constrainted to board file usage, rather than spinning off new dtsis.
>
> Makes sense with the different product variants for DRA7, AM335x already does it this way, but the rest of OMAP3/4/5 are doing it the other way.
> I think its just too confusing to follow different conventions for different SoCs. We should stick to just one, either this way or that.
>
I think bucketing DRA7(with multitude of SoC variants) with OMAP
family(usually with <5 variants) will be a wrong approach. we should
choose the approach appropriate for the SoC. hence, OMAPx having all
default enabled makes sense (as the delta is usually trivial), but on
DRA7, the variants are larger :(
just my 2 cents.
>>
>>>
>>>>
>>>>
>>>> [1] http://marc.info/?t=137416599400001&r=1&w=2
>>>> [2] http://marc.info/?l=linux-omap&m=137510358229479&w=2
>>> [3] http://lists.infradead.org/pipermail/linux-arm-kernel/2012-February/086297.html
>>>
>>
>>
>
--
Regards,
Nishanth Menon
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v2 8/8] ARM: DRA7: dts: Add the dts files for dra7 SoC and dra7-evm board
2013-07-30 12:59 ` Nishanth Menon
@ 2013-07-30 13:01 ` Rajendra Nayak
2013-08-12 13:46 ` Benoit Cousson
0 siblings, 1 reply; 41+ messages in thread
From: Rajendra Nayak @ 2013-07-30 13:01 UTC (permalink / raw)
To: Nishanth Menon
Cc: linux-omap, linux-arm-kernel, tony, paul, khilman, benoit.cousson,
r.sricharan, ambresh, sourav.poddar
On Tuesday 30 July 2013 06:29 PM, Nishanth Menon wrote:
> On 07/30/2013 07:56 AM, Rajendra Nayak wrote:
>> On Tuesday 30 July 2013 06:16 PM, Nishanth Menon wrote:
>>> On 07/30/2013 07:41 AM, Rajendra Nayak wrote:
>>>> On Tuesday 30 July 2013 06:00 PM, Nishanth Menon wrote:
>>>>> On 07/30/2013 06:25 AM, Rajendra Nayak wrote:
>>>>>> From: R Sricharan <r.sricharan@ti.com>
>>> [...]
>>>>>> + mcspi4: spi@480ba000 {
>>>>>> + compatible = "ti,omap4-mcspi";
>>>>>> + reg = <0x480ba000 0x200>;
>>>>>> + interrupts = <0 48 0x4>;
>>>>>> + #address-cells = <1>;
>>>>>> + #size-cells = <0>;
>>>>>> + ti,hwmods = "mcspi4";
>>>>>> + ti,spi-num-cs = <1>;
>>>>>> + dmas = <&sdma 70>, <&sdma 71>;
>>>>>> + dma-names = "tx0", "rx0";
>>>>>> + };
>>>>>> + };
>>>>>> +};
>>>>>>
>>>>> ref: [1], we discussed that we should now be able to introduce all instances of h/w blocks into the dra7.dts. Further, considering [2]
>>>>
>>>> hmm, thats a long discussion on crossbar driver that [1] points to. Do you want to summarize what you mean by 'introduce all instances of h/w blocks'
>>>
>>> I recommend reading the last few emails on the thread about how we could do this with pinctrl. unfortunately, this patch is not informative enough to indicate that not all instances of the potential IP blocks are listed here.
>>>
>>>>
>>>>> would you not want to follow "status = disabled" for all modules by default and enable required modules in board file, so that we dont have to respin this yet again?
>>>>
>>>> Well, I was just following the convention of whats already followed on existing OMAPs. See [3] for some views on these.
>>>
>>> DRA7 case, I would not think it makes sense due to the number of product variants being done, not all will use the same set. Further, rationale for DRA7 and my suggestion for Grant's option (1) is mainly because the product variants will require more dtsis rather than board files using the product variants use just the necessary modules from a common dtsi. Makes support of variants like OMAP57xx etc trivial and constrainted to board file usage, rather than spinning off new dtsis.
>>
>> Makes sense with the different product variants for DRA7, AM335x already does it this way, but the rest of OMAP3/4/5 are doing it the other way.
>> I think its just too confusing to follow different conventions for different SoCs. We should stick to just one, either this way or that.
>>
>
> I think bucketing DRA7(with multitude of SoC variants) with OMAP family(usually with <5 variants) will be a wrong approach. we should choose the approach appropriate for the SoC. hence, OMAPx having all default enabled makes sense (as the delta is usually trivial), but on DRA7, the variants are larger :(
>
> just my 2 cents.
I can respin with the changes, but before I do so, Benoit do you agree with the rationale for these and fine with the approach?
>
>>>
>>>>
>>>>>
>>>>>
>>>>> [1] http://marc.info/?t=137416599400001&r=1&w=2
>>>>> [2] http://marc.info/?l=linux-omap&m=137510358229479&w=2
>>>> [3] http://lists.infradead.org/pipermail/linux-arm-kernel/2012-February/086297.html
>>>>
>>>
>>>
>>
>
>
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v2 1/8] ARM: DRA7: id: Add cpu detection support for DRA7xx based SoCs'
2013-07-30 11:25 ` [PATCH v2 1/8] ARM: DRA7: id: Add cpu detection support for DRA7xx based SoCs' Rajendra Nayak
@ 2013-07-30 13:10 ` Felipe Balbi
2013-07-30 13:18 ` Felipe Balbi
2013-07-30 14:18 ` Sricharan R
0 siblings, 2 replies; 41+ messages in thread
From: Felipe Balbi @ 2013-07-30 13:10 UTC (permalink / raw)
To: Rajendra Nayak
Cc: linux-omap, linux-arm-kernel, tony, paul, khilman, benoit.cousson,
r.sricharan, ambresh, sourav.poddar
[-- Attachment #1: Type: text/plain, Size: 5639 bytes --]
Hi,
On Tue, Jul 30, 2013 at 04:55:39PM +0530, Rajendra Nayak wrote:
> @@ -379,6 +407,13 @@ IS_OMAP_TYPE(3430, 0x3430)
> # define soc_is_omap543x() is_omap543x()
> #endif
>
> +# if defined(CONFIG_SOC_DRA7XX)
> +# undef soc_is_dra7xx
> +# undef soc_is_dra75x
> +# define soc_is_dra7xx() is_dra7xx()
> +# define soc_is_dra75x() is_dra75x()
since this platform is DT-only, couldn't we just believe DT-data to be
correct of_machine_is_compatible() ? 2/3 of this patch would be removed.
I patched this for OMAP5 (compile-tested only, no boards available) and
came out with the patch below (still needs to be split):
diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts
index 08b7267..b3136e5 100644
--- a/arch/arm/boot/dts/omap5-uevm.dts
+++ b/arch/arm/boot/dts/omap5-uevm.dts
@@ -13,7 +13,7 @@
/ {
model = "TI OMAP5 uEVM board";
- compatible = "ti,omap5-uevm", "ti,omap5";
+ compatible = "ti,omap5-uevm", "ti,omap5432-es2.0", "ti,omap5";
memory {
device_type = "memory";
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 07be2cd..a7bc906 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -17,7 +17,7 @@
#address-cells = <1>;
#size-cells = <1>;
- compatible = "ti,omap5";
+ compatible = "ti,omap5432-es2.0", "ti,omap5430-es2.0", "ti,omap5";
interrupt-parent = <&gic>;
aliases {
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 2dc62a2..ee94309 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -563,49 +563,6 @@ void __init omap4xxx_check_revision(void)
pr_info("%s %s\n", soc_name, soc_rev);
}
-void __init omap5xxx_check_revision(void)
-{
- u32 idcode;
- u16 hawkeye;
- u8 rev;
-
- idcode = read_tap_reg(OMAP_TAP_IDCODE);
- hawkeye = (idcode >> 12) & 0xffff;
- rev = (idcode >> 28) & 0xff;
- switch (hawkeye) {
- case 0xb942:
- switch (rev) {
- case 0:
- omap_revision = OMAP5430_REV_ES1_0;
- break;
- case 1:
- default:
- omap_revision = OMAP5430_REV_ES2_0;
- }
- break;
-
- case 0xb998:
- switch (rev) {
- case 0:
- omap_revision = OMAP5432_REV_ES1_0;
- break;
- case 1:
- default:
- omap_revision = OMAP5432_REV_ES2_0;
- }
- break;
-
- default:
- /* Unknown default to latest silicon rev as default*/
- omap_revision = OMAP5430_REV_ES2_0;
- }
-
- sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
- sprintf(soc_rev, "ES%d.0", (omap_rev() >> 12) & 0xf);
-
- pr_info("%s %s\n", soc_name, soc_rev);
-}
-
/*
* Set up things for map_io and processor detection later on. Gets called
* pretty much first thing from board init. For multi-omap, this gets
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 4a3f06f..aa28940 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -633,8 +633,7 @@ void __init omap4430_init_late(void)
#ifdef CONFIG_SOC_OMAP5
void __init omap5_init_early(void)
{
- omap2_set_globals_tap(OMAP54XX_CLASS,
- OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
+ omap2_set_globals_tap(-1, OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
OMAP2_L4_IO_ADDRESS(OMAP54XX_CTRL_BASE));
omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE));
@@ -644,7 +643,6 @@ void __init omap5_init_early(void)
omap_prm_base_init();
omap_cm_base_init();
omap44xx_prm_init();
- omap5xxx_check_revision();
omap54xx_voltagedomains_init();
omap54xx_powerdomains_init();
omap54xx_clockdomains_init();
diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h
index 8c616e4..b8339ad 100644
--- a/arch/arm/mach-omap2/soc.h
+++ b/arch/arm/mach-omap2/soc.h
@@ -35,6 +35,7 @@
#ifndef __ASSEMBLY__
#include <linux/bitops.h>
+#include <linux/of.h>
/*
* Test if multicore OMAP support is needed
@@ -194,7 +195,6 @@ IS_OMAP_CLASS(24xx, 0x24)
IS_OMAP_CLASS(34xx, 0x34)
IS_OMAP_CLASS(44xx, 0x44)
IS_AM_CLASS(35xx, 0x35)
-IS_OMAP_CLASS(54xx, 0x54)
IS_AM_CLASS(33xx, 0x33)
IS_AM_CLASS(43xx, 0x43)
@@ -207,7 +207,6 @@ IS_OMAP_SUBCLASS(363x, 0x363)
IS_OMAP_SUBCLASS(443x, 0x443)
IS_OMAP_SUBCLASS(446x, 0x446)
IS_OMAP_SUBCLASS(447x, 0x447)
-IS_OMAP_SUBCLASS(543x, 0x543)
IS_TI_SUBCLASS(816x, 0x816)
IS_TI_SUBCLASS(814x, 0x814)
@@ -373,10 +372,10 @@ IS_OMAP_TYPE(3430, 0x3430)
# endif
# if defined(CONFIG_SOC_OMAP5)
-# undef soc_is_omap54xx
-# undef soc_is_omap543x
-# define soc_is_omap54xx() is_omap54xx()
-# define soc_is_omap543x() is_omap543x()
+# undef soc_is_omap54xx
+# undef soc_is_omap543x
+# define soc_is_omap54xx() (of_machine_is_compatible("ti,omap5"))
+# define soc_is_omap543x() (soc_is_omap54xx())
#endif
/* Various silicon revisions for omap2 */
@@ -437,16 +436,9 @@ IS_OMAP_TYPE(3430, 0x3430)
#define OMAP447X_CLASS 0x44700044
#define OMAP4470_REV_ES1_0 (OMAP447X_CLASS | (0x10 << 8))
-#define OMAP54XX_CLASS 0x54000054
-#define OMAP5430_REV_ES1_0 (OMAP54XX_CLASS | (0x30 << 16) | (0x10 << 8))
-#define OMAP5430_REV_ES2_0 (OMAP54XX_CLASS | (0x30 << 16) | (0x20 << 8))
-#define OMAP5432_REV_ES1_0 (OMAP54XX_CLASS | (0x32 << 16) | (0x10 << 8))
-#define OMAP5432_REV_ES2_0 (OMAP54XX_CLASS | (0x32 << 16) | (0x20 << 8))
-
void omap2xxx_check_revision(void);
void omap3xxx_check_revision(void);
void omap4xxx_check_revision(void);
-void omap5xxx_check_revision(void);
void omap3xxx_check_features(void);
void ti81xx_check_features(void);
void am33xx_check_features(void);
--
balbi
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^ permalink raw reply related [flat|nested] 41+ messages in thread
* Re: [PATCH v2 1/8] ARM: DRA7: id: Add cpu detection support for DRA7xx based SoCs'
2013-07-30 13:10 ` Felipe Balbi
@ 2013-07-30 13:18 ` Felipe Balbi
2013-07-30 13:55 ` Tony Lindgren
2013-07-30 14:18 ` Sricharan R
1 sibling, 1 reply; 41+ messages in thread
From: Felipe Balbi @ 2013-07-30 13:18 UTC (permalink / raw)
To: Felipe Balbi
Cc: Rajendra Nayak, linux-omap, linux-arm-kernel, tony, paul, khilman,
benoit.cousson, r.sricharan, ambresh, sourav.poddar
[-- Attachment #1: Type: text/plain, Size: 649 bytes --]
On Tue, Jul 30, 2013 at 04:10:09PM +0300, Felipe Balbi wrote:
> Hi,
>
> On Tue, Jul 30, 2013 at 04:55:39PM +0530, Rajendra Nayak wrote:
> > @@ -379,6 +407,13 @@ IS_OMAP_TYPE(3430, 0x3430)
> > # define soc_is_omap543x() is_omap543x()
> > #endif
> >
> > +# if defined(CONFIG_SOC_DRA7XX)
> > +# undef soc_is_dra7xx
> > +# undef soc_is_dra75x
> > +# define soc_is_dra7xx() is_dra7xx()
> > +# define soc_is_dra75x() is_dra75x()
>
> since this platform is DT-only, couldn't we just believe DT-data to be
> correct of_machine_is_compatible() ? 2/3 of this patch would be removed.
s/correct of_/correct and use of_
--
balbi
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^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v2 1/8] ARM: DRA7: id: Add cpu detection support for DRA7xx based SoCs'
2013-07-30 13:18 ` Felipe Balbi
@ 2013-07-30 13:55 ` Tony Lindgren
0 siblings, 0 replies; 41+ messages in thread
From: Tony Lindgren @ 2013-07-30 13:55 UTC (permalink / raw)
To: Felipe Balbi
Cc: Rajendra Nayak, linux-omap, linux-arm-kernel, paul, khilman,
benoit.cousson, r.sricharan, ambresh, sourav.poddar
* Felipe Balbi <balbi@ti.com> [130730 06:25]:
> On Tue, Jul 30, 2013 at 04:10:09PM +0300, Felipe Balbi wrote:
> > Hi,
> >
> > On Tue, Jul 30, 2013 at 04:55:39PM +0530, Rajendra Nayak wrote:
> > > @@ -379,6 +407,13 @@ IS_OMAP_TYPE(3430, 0x3430)
> > > # define soc_is_omap543x() is_omap543x()
> > > #endif
> > >
> > > +# if defined(CONFIG_SOC_DRA7XX)
> > > +# undef soc_is_dra7xx
> > > +# undef soc_is_dra75x
> > > +# define soc_is_dra7xx() is_dra7xx()
> > > +# define soc_is_dra75x() is_dra75x()
> >
> > since this platform is DT-only, couldn't we just believe DT-data to be
> > correct of_machine_is_compatible() ? 2/3 of this patch would be removed.
>
> s/correct of_/correct and use of_
Makes sense to me. AFAIK we no longer need to initialize much
anything super early.
Regards,
Tony
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v2 1/8] ARM: DRA7: id: Add cpu detection support for DRA7xx based SoCs'
2013-07-30 13:10 ` Felipe Balbi
2013-07-30 13:18 ` Felipe Balbi
@ 2013-07-30 14:18 ` Sricharan R
2013-07-30 14:23 ` Felipe Balbi
1 sibling, 1 reply; 41+ messages in thread
From: Sricharan R @ 2013-07-30 14:18 UTC (permalink / raw)
To: balbi
Cc: Rajendra Nayak, linux-omap, linux-arm-kernel, tony, paul, khilman,
benoit.cousson, ambresh, sourav.poddar
On Tuesday 30 July 2013 06:40 PM, Felipe Balbi wrote:
> Hi,
>
> On Tue, Jul 30, 2013 at 04:55:39PM +0530, Rajendra Nayak wrote:
>> @@ -379,6 +407,13 @@ IS_OMAP_TYPE(3430, 0x3430)
>> # define soc_is_omap543x() is_omap543x()
>> #endif
>>
>> +# if defined(CONFIG_SOC_DRA7XX)
>> +# undef soc_is_dra7xx
>> +# undef soc_is_dra75x
>> +# define soc_is_dra7xx() is_dra7xx()
>> +# define soc_is_dra75x() is_dra75x()
> since this platform is DT-only, couldn't we just believe DT-data to be
> correct of_machine_is_compatible() ? 2/3 of this patch would be removed.
>
> I patched this for OMAP5 (compile-tested only, no boards available) and
> came out with the patch below (still needs to be split):
>
> diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts
> index 08b7267..b3136e5 100644
> --- a/arch/arm/boot/dts/omap5-uevm.dts
> +++ b/arch/arm/boot/dts/omap5-uevm.dts
> @@ -13,7 +13,7 @@
>
> / {
> model = "TI OMAP5 uEVM board";
> - compatible = "ti,omap5-uevm", "ti,omap5";
> + compatible = "ti,omap5-uevm", "ti,omap5432-es2.0", "ti,omap5";
>
ok, nice and simpler way.
But would this make different revisions, to appear the same ?
Regards,
Sricharan
> memory {
> device_type = "memory";
> diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
> index 07be2cd..a7bc906 100644
> --- a/arch/arm/boot/dts/omap5.dtsi
> +++ b/arch/arm/boot/dts/omap5.dtsi
> @@ -17,7 +17,7 @@
> #address-cells = <1>;
> #size-cells = <1>;
>
> - compatible = "ti,omap5";
> + compatible = "ti,omap5432-es2.0", "ti,omap5430-es2.0", "ti,omap5";
> interrupt-parent = <&gic>;
>
> aliases {
> diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
> index 2dc62a2..ee94309 100644
> --- a/arch/arm/mach-omap2/id.c
> +++ b/arch/arm/mach-omap2/id.c
> @@ -563,49 +563,6 @@ void __init omap4xxx_check_revision(void)
> pr_info("%s %s\n", soc_name, soc_rev);
> }
>
> -void __init omap5xxx_check_revision(void)
> -{
> - u32 idcode;
> - u16 hawkeye;
> - u8 rev;
> -
> - idcode = read_tap_reg(OMAP_TAP_IDCODE);
> - hawkeye = (idcode >> 12) & 0xffff;
> - rev = (idcode >> 28) & 0xff;
> - switch (hawkeye) {
> - case 0xb942:
> - switch (rev) {
> - case 0:
> - omap_revision = OMAP5430_REV_ES1_0;
> - break;
> - case 1:
> - default:
> - omap_revision = OMAP5430_REV_ES2_0;
> - }
> - break;
> -
> - case 0xb998:
> - switch (rev) {
> - case 0:
> - omap_revision = OMAP5432_REV_ES1_0;
> - break;
> - case 1:
> - default:
> - omap_revision = OMAP5432_REV_ES2_0;
> - }
> - break;
> -
> - default:
> - /* Unknown default to latest silicon rev as default*/
> - omap_revision = OMAP5430_REV_ES2_0;
> - }
> -
> - sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
> - sprintf(soc_rev, "ES%d.0", (omap_rev() >> 12) & 0xf);
> -
> - pr_info("%s %s\n", soc_name, soc_rev);
> -}
> -
> /*
> * Set up things for map_io and processor detection later on. Gets called
> * pretty much first thing from board init. For multi-omap, this gets
> diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
> index 4a3f06f..aa28940 100644
> --- a/arch/arm/mach-omap2/io.c
> +++ b/arch/arm/mach-omap2/io.c
> @@ -633,8 +633,7 @@ void __init omap4430_init_late(void)
> #ifdef CONFIG_SOC_OMAP5
> void __init omap5_init_early(void)
> {
> - omap2_set_globals_tap(OMAP54XX_CLASS,
> - OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
> + omap2_set_globals_tap(-1, OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
> omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
> OMAP2_L4_IO_ADDRESS(OMAP54XX_CTRL_BASE));
> omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE));
> @@ -644,7 +643,6 @@ void __init omap5_init_early(void)
> omap_prm_base_init();
> omap_cm_base_init();
> omap44xx_prm_init();
> - omap5xxx_check_revision();
> omap54xx_voltagedomains_init();
> omap54xx_powerdomains_init();
> omap54xx_clockdomains_init();
> diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h
> index 8c616e4..b8339ad 100644
> --- a/arch/arm/mach-omap2/soc.h
> +++ b/arch/arm/mach-omap2/soc.h
> @@ -35,6 +35,7 @@
> #ifndef __ASSEMBLY__
>
> #include <linux/bitops.h>
> +#include <linux/of.h>
>
> /*
> * Test if multicore OMAP support is needed
> @@ -194,7 +195,6 @@ IS_OMAP_CLASS(24xx, 0x24)
> IS_OMAP_CLASS(34xx, 0x34)
> IS_OMAP_CLASS(44xx, 0x44)
> IS_AM_CLASS(35xx, 0x35)
> -IS_OMAP_CLASS(54xx, 0x54)
> IS_AM_CLASS(33xx, 0x33)
> IS_AM_CLASS(43xx, 0x43)
>
> @@ -207,7 +207,6 @@ IS_OMAP_SUBCLASS(363x, 0x363)
> IS_OMAP_SUBCLASS(443x, 0x443)
> IS_OMAP_SUBCLASS(446x, 0x446)
> IS_OMAP_SUBCLASS(447x, 0x447)
> -IS_OMAP_SUBCLASS(543x, 0x543)
>
> IS_TI_SUBCLASS(816x, 0x816)
> IS_TI_SUBCLASS(814x, 0x814)
> @@ -373,10 +372,10 @@ IS_OMAP_TYPE(3430, 0x3430)
> # endif
>
> # if defined(CONFIG_SOC_OMAP5)
> -# undef soc_is_omap54xx
> -# undef soc_is_omap543x
> -# define soc_is_omap54xx() is_omap54xx()
> -# define soc_is_omap543x() is_omap543x()
> +# undef soc_is_omap54xx
> +# undef soc_is_omap543x
> +# define soc_is_omap54xx() (of_machine_is_compatible("ti,omap5"))
> +# define soc_is_omap543x() (soc_is_omap54xx())
> #endif
>
> /* Various silicon revisions for omap2 */
> @@ -437,16 +436,9 @@ IS_OMAP_TYPE(3430, 0x3430)
> #define OMAP447X_CLASS 0x44700044
> #define OMAP4470_REV_ES1_0 (OMAP447X_CLASS | (0x10 << 8))
>
> -#define OMAP54XX_CLASS 0x54000054
> -#define OMAP5430_REV_ES1_0 (OMAP54XX_CLASS | (0x30 << 16) | (0x10 << 8))
> -#define OMAP5430_REV_ES2_0 (OMAP54XX_CLASS | (0x30 << 16) | (0x20 << 8))
> -#define OMAP5432_REV_ES1_0 (OMAP54XX_CLASS | (0x32 << 16) | (0x10 << 8))
> -#define OMAP5432_REV_ES2_0 (OMAP54XX_CLASS | (0x32 << 16) | (0x20 << 8))
> -
> void omap2xxx_check_revision(void);
> void omap3xxx_check_revision(void);
> void omap4xxx_check_revision(void);
> -void omap5xxx_check_revision(void);
> void omap3xxx_check_features(void);
> void ti81xx_check_features(void);
> void am33xx_check_features(void);
>
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v2 1/8] ARM: DRA7: id: Add cpu detection support for DRA7xx based SoCs'
2013-07-30 14:18 ` Sricharan R
@ 2013-07-30 14:23 ` Felipe Balbi
2013-07-30 14:36 ` Sricharan R
0 siblings, 1 reply; 41+ messages in thread
From: Felipe Balbi @ 2013-07-30 14:23 UTC (permalink / raw)
To: Sricharan R
Cc: balbi, Rajendra Nayak, linux-omap, linux-arm-kernel, tony, paul,
khilman, benoit.cousson, ambresh, sourav.poddar
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Hi,
On Tue, Jul 30, 2013 at 07:48:23PM +0530, Sricharan R wrote:
> On Tuesday 30 July 2013 06:40 PM, Felipe Balbi wrote:
> > Hi,
> >
> > On Tue, Jul 30, 2013 at 04:55:39PM +0530, Rajendra Nayak wrote:
> >> @@ -379,6 +407,13 @@ IS_OMAP_TYPE(3430, 0x3430)
> >> # define soc_is_omap543x() is_omap543x()
> >> #endif
> >>
> >> +# if defined(CONFIG_SOC_DRA7XX)
> >> +# undef soc_is_dra7xx
> >> +# undef soc_is_dra75x
> >> +# define soc_is_dra7xx() is_dra7xx()
> >> +# define soc_is_dra75x() is_dra75x()
> > since this platform is DT-only, couldn't we just believe DT-data to be
> > correct of_machine_is_compatible() ? 2/3 of this patch would be removed.
> >
> > I patched this for OMAP5 (compile-tested only, no boards available) and
> > came out with the patch below (still needs to be split):
> >
> > diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts
> > index 08b7267..b3136e5 100644
> > --- a/arch/arm/boot/dts/omap5-uevm.dts
> > +++ b/arch/arm/boot/dts/omap5-uevm.dts
> > @@ -13,7 +13,7 @@
> >
> > / {
> > model = "TI OMAP5 uEVM board";
> > - compatible = "ti,omap5-uevm", "ti,omap5";
> > + compatible = "ti,omap5-uevm", "ti,omap5432-es2.0", "ti,omap5";
> >
> ok, nice and simpler way.
> But would this make different revisions, to appear the same ?
well omap5-uevm is omap5432 es2.0 only, right ? If a new board comes up,
it should be treated as such, then you can pass a different string to
that new board's compatible attribute.
--
balbi
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^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v2 1/8] ARM: DRA7: id: Add cpu detection support for DRA7xx based SoCs'
2013-07-30 14:23 ` Felipe Balbi
@ 2013-07-30 14:36 ` Sricharan R
2013-07-30 15:32 ` Felipe Balbi
0 siblings, 1 reply; 41+ messages in thread
From: Sricharan R @ 2013-07-30 14:36 UTC (permalink / raw)
To: balbi
Cc: Rajendra Nayak, linux-omap, linux-arm-kernel, tony, paul, khilman,
benoit.cousson, ambresh, sourav.poddar
On Tuesday 30 July 2013 07:53 PM, Felipe Balbi wrote:
> Hi,
>
> On Tue, Jul 30, 2013 at 07:48:23PM +0530, Sricharan R wrote:
>> On Tuesday 30 July 2013 06:40 PM, Felipe Balbi wrote:
>>> Hi,
>>>
>>> On Tue, Jul 30, 2013 at 04:55:39PM +0530, Rajendra Nayak wrote:
>>>> @@ -379,6 +407,13 @@ IS_OMAP_TYPE(3430, 0x3430)
>>>> # define soc_is_omap543x() is_omap543x()
>>>> #endif
>>>>
>>>> +# if defined(CONFIG_SOC_DRA7XX)
>>>> +# undef soc_is_dra7xx
>>>> +# undef soc_is_dra75x
>>>> +# define soc_is_dra7xx() is_dra7xx()
>>>> +# define soc_is_dra75x() is_dra75x()
>>> since this platform is DT-only, couldn't we just believe DT-data to be
>>> correct of_machine_is_compatible() ? 2/3 of this patch would be removed.
>>>
>>> I patched this for OMAP5 (compile-tested only, no boards available) and
>>> came out with the patch below (still needs to be split):
>>>
>>> diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts
>>> index 08b7267..b3136e5 100644
>>> --- a/arch/arm/boot/dts/omap5-uevm.dts
>>> +++ b/arch/arm/boot/dts/omap5-uevm.dts
>>> @@ -13,7 +13,7 @@
>>>
>>> / {
>>> model = "TI OMAP5 uEVM board";
>>> - compatible = "ti,omap5-uevm", "ti,omap5";
>>> + compatible = "ti,omap5-uevm", "ti,omap5432-es2.0", "ti,omap5";
>>>
>> ok, nice and simpler way.
>> But would this make different revisions, to appear the same ?
> well omap5-uevm is omap5432 es2.0 only, right ? If a new board comes up,
> it should be treated as such, then you can pass a different string to
> that new board's compatible attribute.
>
Yes for OMAP5. I was thinking in general about this approach.
For example, for OMAP4 we have same board and
different revisions can be socketed there.
For OMAP5, this is good.
Regards,
Sricharan
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v2 1/8] ARM: DRA7: id: Add cpu detection support for DRA7xx based SoCs'
2013-07-30 14:36 ` Sricharan R
@ 2013-07-30 15:32 ` Felipe Balbi
2013-07-30 18:37 ` Sricharan R
0 siblings, 1 reply; 41+ messages in thread
From: Felipe Balbi @ 2013-07-30 15:32 UTC (permalink / raw)
To: Sricharan R
Cc: balbi, Rajendra Nayak, linux-omap, linux-arm-kernel, tony, paul,
khilman, benoit.cousson, ambresh, sourav.poddar
[-- Attachment #1: Type: text/plain, Size: 2195 bytes --]
Hi,
On Tue, Jul 30, 2013 at 08:06:31PM +0530, Sricharan R wrote:
> On Tuesday 30 July 2013 07:53 PM, Felipe Balbi wrote:
> > Hi,
> >
> > On Tue, Jul 30, 2013 at 07:48:23PM +0530, Sricharan R wrote:
> >> On Tuesday 30 July 2013 06:40 PM, Felipe Balbi wrote:
> >>> Hi,
> >>>
> >>> On Tue, Jul 30, 2013 at 04:55:39PM +0530, Rajendra Nayak wrote:
> >>>> @@ -379,6 +407,13 @@ IS_OMAP_TYPE(3430, 0x3430)
> >>>> # define soc_is_omap543x() is_omap543x()
> >>>> #endif
> >>>>
> >>>> +# if defined(CONFIG_SOC_DRA7XX)
> >>>> +# undef soc_is_dra7xx
> >>>> +# undef soc_is_dra75x
> >>>> +# define soc_is_dra7xx() is_dra7xx()
> >>>> +# define soc_is_dra75x() is_dra75x()
> >>> since this platform is DT-only, couldn't we just believe DT-data to be
> >>> correct of_machine_is_compatible() ? 2/3 of this patch would be removed.
> >>>
> >>> I patched this for OMAP5 (compile-tested only, no boards available) and
> >>> came out with the patch below (still needs to be split):
> >>>
> >>> diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts
> >>> index 08b7267..b3136e5 100644
> >>> --- a/arch/arm/boot/dts/omap5-uevm.dts
> >>> +++ b/arch/arm/boot/dts/omap5-uevm.dts
> >>> @@ -13,7 +13,7 @@
> >>>
> >>> / {
> >>> model = "TI OMAP5 uEVM board";
> >>> - compatible = "ti,omap5-uevm", "ti,omap5";
> >>> + compatible = "ti,omap5-uevm", "ti,omap5432-es2.0", "ti,omap5";
> >>>
> >> ok, nice and simpler way.
> >> But would this make different revisions, to appear the same ?
> > well omap5-uevm is omap5432 es2.0 only, right ? If a new board comes up,
> > it should be treated as such, then you can pass a different string to
> > that new board's compatible attribute.
> >
> Yes for OMAP5. I was thinking in general about this approach.
> For example, for OMAP4 we have same board and
> different revisions can be socketed there.
>
> For OMAP5, this is good.
do we really production socketed boards? Well, at least Blaze has such
thing. But do we have too many differences that need to be trated at
arch/arm or should/could those be handled by reading IP's revision
register (e.g. usb host erratas)
--
balbi
[-- Attachment #2: Digital signature --]
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^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v2 1/8] ARM: DRA7: id: Add cpu detection support for DRA7xx based SoCs'
2013-07-30 15:32 ` Felipe Balbi
@ 2013-07-30 18:37 ` Sricharan R
2013-07-30 18:43 ` Nishanth Menon
0 siblings, 1 reply; 41+ messages in thread
From: Sricharan R @ 2013-07-30 18:37 UTC (permalink / raw)
To: balbi
Cc: Rajendra Nayak, linux-omap, linux-arm-kernel, tony, paul, khilman,
benoit.cousson, ambresh, sourav.poddar
Hi,
On Tuesday 30 July 2013 09:02 PM, Felipe Balbi wrote:
> Hi,
>
> On Tue, Jul 30, 2013 at 08:06:31PM +0530, Sricharan R wrote:
>> On Tuesday 30 July 2013 07:53 PM, Felipe Balbi wrote:
>>> Hi,
>>>
>>> On Tue, Jul 30, 2013 at 07:48:23PM +0530, Sricharan R wrote:
>>>> On Tuesday 30 July 2013 06:40 PM, Felipe Balbi wrote:
>>>>> Hi,
>>>>>
>>>>> On Tue, Jul 30, 2013 at 04:55:39PM +0530, Rajendra Nayak wrote:
>>>>>> @@ -379,6 +407,13 @@ IS_OMAP_TYPE(3430, 0x3430)
>>>>>> # define soc_is_omap543x() is_omap543x()
>>>>>> #endif
>>>>>>
>>>>>> +# if defined(CONFIG_SOC_DRA7XX)
>>>>>> +# undef soc_is_dra7xx
>>>>>> +# undef soc_is_dra75x
>>>>>> +# define soc_is_dra7xx() is_dra7xx()
>>>>>> +# define soc_is_dra75x() is_dra75x()
>>>>> since this platform is DT-only, couldn't we just believe DT-data to be
>>>>> correct of_machine_is_compatible() ? 2/3 of this patch would be removed.
>>>>>
>>>>> I patched this for OMAP5 (compile-tested only, no boards available) and
>>>>> came out with the patch below (still needs to be split):
>>>>>
>>>>> diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts
>>>>> index 08b7267..b3136e5 100644
>>>>> --- a/arch/arm/boot/dts/omap5-uevm.dts
>>>>> +++ b/arch/arm/boot/dts/omap5-uevm.dts
>>>>> @@ -13,7 +13,7 @@
>>>>>
>>>>> / {
>>>>> model = "TI OMAP5 uEVM board";
>>>>> - compatible = "ti,omap5-uevm", "ti,omap5";
>>>>> + compatible = "ti,omap5-uevm", "ti,omap5432-es2.0", "ti,omap5";
>>>>>
>>>> ok, nice and simpler way.
>>>> But would this make different revisions, to appear the same ?
>>> well omap5-uevm is omap5432 es2.0 only, right ? If a new board comes up,
>>> it should be treated as such, then you can pass a different string to
>>> that new board's compatible attribute.
>>> s
>> Yes for OMAP5. I was thinking in general about this approach.
>> For example, for OMAP4 we have same board and
>> different revisions can be socketed there.
>>
>> For OMAP5, this is good.
> do we really production socketed boards? Well, at least Blaze has such
> thing. But do we have too many differences that need to be trated at
> arch/arm or should/could those be handled by reading IP's revision
> register (e.g. usb host erratas)
>
OMAP4 SDP is socketed as well.
Ya, revision checks used only in few places and as you said
we handle them using IP revisions, but that we have to look and clean
up those places, if we really intend to do this for other socs.
Regards,
Sricharan
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v2 1/8] ARM: DRA7: id: Add cpu detection support for DRA7xx based SoCs'
2013-07-30 18:37 ` Sricharan R
@ 2013-07-30 18:43 ` Nishanth Menon
2013-07-31 6:02 ` Rajendra Nayak
0 siblings, 1 reply; 41+ messages in thread
From: Nishanth Menon @ 2013-07-30 18:43 UTC (permalink / raw)
To: Sricharan R
Cc: balbi, Rajendra Nayak, linux-omap, linux-arm-kernel, tony, paul,
khilman, benoit.cousson, ambresh, sourav.poddar
On 07/30/2013 01:37 PM, Sricharan R wrote:
> Hi,
> On Tuesday 30 July 2013 09:02 PM, Felipe Balbi wrote:
>> Hi,
>>
>> On Tue, Jul 30, 2013 at 08:06:31PM +0530, Sricharan R wrote:
>>> On Tuesday 30 July 2013 07:53 PM, Felipe Balbi wrote:
>>>> Hi,
>>>>
>>>> On Tue, Jul 30, 2013 at 07:48:23PM +0530, Sricharan R wrote:
>>>>> On Tuesday 30 July 2013 06:40 PM, Felipe Balbi wrote:
>>>>>> Hi,
>>>>>>
>>>>>> On Tue, Jul 30, 2013 at 04:55:39PM +0530, Rajendra Nayak wrote:
>>>>>>> @@ -379,6 +407,13 @@ IS_OMAP_TYPE(3430, 0x3430)
>>>>>>> # define soc_is_omap543x() is_omap543x()
>>>>>>> #endif
>>>>>>>
>>>>>>> +# if defined(CONFIG_SOC_DRA7XX)
>>>>>>> +# undef soc_is_dra7xx
>>>>>>> +# undef soc_is_dra75x
>>>>>>> +# define soc_is_dra7xx() is_dra7xx()
>>>>>>> +# define soc_is_dra75x() is_dra75x()
>>>>>> since this platform is DT-only, couldn't we just believe DT-data to be
>>>>>> correct of_machine_is_compatible() ? 2/3 of this patch would be removed.
>>>>>>
>>>>>> I patched this for OMAP5 (compile-tested only, no boards available) and
>>>>>> came out with the patch below (still needs to be split):
>>>>>>
>>>>>> diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts
>>>>>> index 08b7267..b3136e5 100644
>>>>>> --- a/arch/arm/boot/dts/omap5-uevm.dts
>>>>>> +++ b/arch/arm/boot/dts/omap5-uevm.dts
>>>>>> @@ -13,7 +13,7 @@
>>>>>>
>>>>>> / {
>>>>>> model = "TI OMAP5 uEVM board";
>>>>>> - compatible = "ti,omap5-uevm", "ti,omap5";
>>>>>> + compatible = "ti,omap5-uevm", "ti,omap5432-es2.0", "ti,omap5";
>>>>>>
>>>>> ok, nice and simpler way.
>>>>> But would this make different revisions, to appear the same ?
>>>> well omap5-uevm is omap5432 es2.0 only, right ? If a new board comes up,
>>>> it should be treated as such, then you can pass a different string to
>>>> that new board's compatible attribute.
>>>> s
>>> Yes for OMAP5. I was thinking in general about this approach.
>>> For example, for OMAP4 we have same board and
>>> different revisions can be socketed there.
>>>
>>> For OMAP5, this is good.
>> do we really production socketed boards? Well, at least Blaze has such
>> thing. But do we have too many differences that need to be trated at
>> arch/arm or should/could those be handled by reading IP's revision
>> register (e.g. usb host erratas)
>>
> OMAP4 SDP is socketed as well.
a) OMAP4SDP is not production device
b) OMAP4SDP uses SOM (System On Module)
c) Socketted SOMs were used only during initial days of SoC
d) almost all latest OMAP4 SDP switched to using soldered in SOM
e) we claim compatibility of OMAP4 SDP with Blaze.
So, I dont think this is a rational argument for keeping soc checks with
dts.
> Ya, revision checks used only in few places and as you said
> we handle them using IP revisions, but that we have to look and clean
> up those places, if we really intend to do this for other socs.
I agree this is the right approach :).
--
Regards,
Nishanth Menon
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v2 1/8] ARM: DRA7: id: Add cpu detection support for DRA7xx based SoCs'
2013-07-30 18:43 ` Nishanth Menon
@ 2013-07-31 6:02 ` Rajendra Nayak
2013-07-31 6:42 ` Tony Lindgren
0 siblings, 1 reply; 41+ messages in thread
From: Rajendra Nayak @ 2013-07-31 6:02 UTC (permalink / raw)
To: Nishanth Menon
Cc: paul, khilman, tony, benoit.cousson, balbi, Sricharan R, ambresh,
sourav.poddar, linux-omap, linux-arm-kernel
On Wednesday 31 July 2013 12:13 AM, Nishanth Menon wrote:
> On 07/30/2013 01:37 PM, Sricharan R wrote:
>> Hi,
>> On Tuesday 30 July 2013 09:02 PM, Felipe Balbi wrote:
>>> Hi,
>>>
>>> On Tue, Jul 30, 2013 at 08:06:31PM +0530, Sricharan R wrote:
>>>> On Tuesday 30 July 2013 07:53 PM, Felipe Balbi wrote:
>>>>> Hi,
>>>>>
>>>>> On Tue, Jul 30, 2013 at 07:48:23PM +0530, Sricharan R wrote:
>>>>>> On Tuesday 30 July 2013 06:40 PM, Felipe Balbi wrote:
>>>>>>> Hi,
>>>>>>>
>>>>>>> On Tue, Jul 30, 2013 at 04:55:39PM +0530, Rajendra Nayak wrote:
>>>>>>>> @@ -379,6 +407,13 @@ IS_OMAP_TYPE(3430, 0x3430)
>>>>>>>> # define soc_is_omap543x() is_omap543x()
>>>>>>>> #endif
>>>>>>>>
>>>>>>>> +# if defined(CONFIG_SOC_DRA7XX)
>>>>>>>> +# undef soc_is_dra7xx
>>>>>>>> +# undef soc_is_dra75x
>>>>>>>> +# define soc_is_dra7xx() is_dra7xx()
>>>>>>>> +# define soc_is_dra75x() is_dra75x()
>>>>>>> since this platform is DT-only, couldn't we just believe DT-data to be
>>>>>>> correct of_machine_is_compatible() ? 2/3 of this patch would be removed.
>>>>>>>
>>>>>>> I patched this for OMAP5 (compile-tested only, no boards available) and
>>>>>>> came out with the patch below (still needs to be split):
>>>>>>>
>>>>>>> diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts
>>>>>>> index 08b7267..b3136e5 100644
>>>>>>> --- a/arch/arm/boot/dts/omap5-uevm.dts
>>>>>>> +++ b/arch/arm/boot/dts/omap5-uevm.dts
>>>>>>> @@ -13,7 +13,7 @@
>>>>>>>
>>>>>>> / {
>>>>>>> model = "TI OMAP5 uEVM board";
>>>>>>> - compatible = "ti,omap5-uevm", "ti,omap5";
>>>>>>> + compatible = "ti,omap5-uevm", "ti,omap5432-es2.0", "ti,omap5";
>>>>>>>
>>>>>> ok, nice and simpler way.
>>>>>> But would this make different revisions, to appear the same ?
>>>>> well omap5-uevm is omap5432 es2.0 only, right ? If a new board comes up,
>>>>> it should be treated as such, then you can pass a different string to
>>>>> that new board's compatible attribute.
>>>>> s
>>>> Yes for OMAP5. I was thinking in general about this approach.
>>>> For example, for OMAP4 we have same board and
>>>> different revisions can be socketed there.
>>>>
>>>> For OMAP5, this is good.
>>> do we really production socketed boards? Well, at least Blaze has such
>>> thing. But do we have too many differences that need to be trated at
>>> arch/arm or should/could those be handled by reading IP's revision
>>> register (e.g. usb host erratas)
>>>
>> OMAP4 SDP is socketed as well.
> a) OMAP4SDP is not production device
> b) OMAP4SDP uses SOM (System On Module)
> c) Socketted SOMs were used only during initial days of SoC
> d) almost all latest OMAP4 SDP switched to using soldered in SOM
> e) we claim compatibility of OMAP4 SDP with Blaze.
>
> So, I dont think this is a rational argument for keeping soc checks with dts.
What about OMAP4 pandas? I for instance, have an old 4430 panda and I have no idea
if its a es2.1 or a es2.3 or something else. If we start relying on dt to pass the
right revision check then (we need to create different dts files for these to begin with) I
need to know exactly what silicon rev I am running on.
I know its good to completely get rid of all silicon rev checks and depend on IP revisions
but we have had various IPs which do not have proper rev checks. We have I guess most often
used these to identify PRCM differences.
Tony, what do you suggest we do for this series? Since we have just an es1.0 and one board
at this point for dra7xx, things would be fine even if we do a dt based parsing to identify
the device, and I am fine with it if thats what we feel is the right way forward.
For the rest of the DT only platforms (omap4/5/am335x) anyway getting rid of these rev checks
from the kernel and depending on DT parsing needs to be a separate series anyway and I dont
plan to address those as part of this series.
>
>> Ya, revision checks used only in few places and as you said
>> we handle them using IP revisions, but that we have to look and clean
>> up those places, if we really intend to do this for other socs.
>
> I agree this is the right approach :).
>
>
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v2 1/8] ARM: DRA7: id: Add cpu detection support for DRA7xx based SoCs'
2013-07-31 6:02 ` Rajendra Nayak
@ 2013-07-31 6:42 ` Tony Lindgren
2013-07-31 6:49 ` Rajendra Nayak
0 siblings, 1 reply; 41+ messages in thread
From: Tony Lindgren @ 2013-07-31 6:42 UTC (permalink / raw)
To: Rajendra Nayak
Cc: Nishanth Menon, Sricharan R, balbi, linux-omap, linux-arm-kernel,
paul, khilman, benoit.cousson, ambresh, sourav.poddar
* Rajendra Nayak <rnayak@ti.com> [130730 23:09]:
>
> Tony, what do you suggest we do for this series? Since we have just an es1.0 and one board
> at this point for dra7xx, things would be fine even if we do a dt based parsing to identify
> the device, and I am fine with it if thats what we feel is the right way forward.
> For the rest of the DT only platforms (omap4/5/am335x) anyway getting rid of these rev checks
> from the kernel and depending on DT parsing needs to be a separate series anyway and I dont
> plan to address those as part of this series.
Well I'd say there's no need to drop the hardware revision checks
at this point at least for existing hardware. That's a very minimal
piece of code and there are way bigger issues to tackle.
For new SoCs, we could do it based on the compatible flag. If it
helps booting newer hardware with older kernels, then that's a good
reason to do it.
Regards,
Tony
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v2 1/8] ARM: DRA7: id: Add cpu detection support for DRA7xx based SoCs'
2013-07-31 6:42 ` Tony Lindgren
@ 2013-07-31 6:49 ` Rajendra Nayak
0 siblings, 0 replies; 41+ messages in thread
From: Rajendra Nayak @ 2013-07-31 6:49 UTC (permalink / raw)
To: Tony Lindgren
Cc: Nishanth Menon, Sricharan R, balbi, linux-omap, linux-arm-kernel,
paul, khilman, benoit.cousson, ambresh, sourav.poddar
On Wednesday 31 July 2013 12:12 PM, Tony Lindgren wrote:
> * Rajendra Nayak <rnayak@ti.com> [130730 23:09]:
>>
>> Tony, what do you suggest we do for this series? Since we have just an es1.0 and one board
>> at this point for dra7xx, things would be fine even if we do a dt based parsing to identify
>> the device, and I am fine with it if thats what we feel is the right way forward.
>> For the rest of the DT only platforms (omap4/5/am335x) anyway getting rid of these rev checks
>> from the kernel and depending on DT parsing needs to be a separate series anyway and I dont
>> plan to address those as part of this series.
>
> Well I'd say there's no need to drop the hardware revision checks
> at this point at least for existing hardware. That's a very minimal
> piece of code and there are way bigger issues to tackle.
right, makes sense.
>
> For new SoCs, we could do it based on the compatible flag. If it
> helps booting newer hardware with older kernels, then that's a good
> reason to do it.
Sure, we can have dra7xx use the compatible flag and not add all the rev checks.
That said, I would be glad if the latest kernels at least boot on newer hardware
let alone older kernels :) But I guess we have bigger issues to tackle before
even that happens. Thanks for the quick response.
regards,
Rajendra
>
> Regards,
>
> Tony
>
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v2 0/8] DRA7xx core support
2013-07-30 11:25 [PATCH v2 0/8] DRA7xx core support Rajendra Nayak
` (7 preceding siblings ...)
2013-07-30 11:25 ` [PATCH v2 8/8] ARM: DRA7: dts: Add the dts files for dra7 SoC and dra7-evm board Rajendra Nayak
@ 2013-08-02 22:28 ` Santosh Shilimkar
2013-08-04 16:14 ` Rajendra Nayak
8 siblings, 1 reply; 41+ messages in thread
From: Santosh Shilimkar @ 2013-08-02 22:28 UTC (permalink / raw)
To: Rajendra Nayak
Cc: linux-omap, linux-arm-kernel, tony, paul, khilman, benoit.cousson,
r.sricharan, ambresh, sourav.poddar
On Tuesday 30 July 2013 07:25 AM, Rajendra Nayak wrote:
> Changes in v2:
> -1- Fixed minor changelog details
> -2- Dropped the SRAM support patch since we need to move to drivers/misc/sram.c
> -3- Added DTS update patches to this series which were earlier posted as
> part of the data series (Since they don't have much objections as against the
> other in-kernel data files)
> -4- Updated the EVM dts file with pin config details for uart/mcspi and i2c
>
> DRA7xx based SoCs' are high-performance, infotainment application devices,
> based on enhanced OMAP architecture integrated on a 28nm
> technology.
>
> The DRA7xx family is composed of DRA75x and DRA74x devices.
> The current device for which the patches add support is the
> DRA752 SoC.
>
> Most of the core IPs are similar to those found on the OMAP5
> devices, including the dual cortex-A15 based MPU subsystem,
> which has helped quite some reuse from existing OMAP5 support.
>
> This series contains only core support patches and none of
> the PRCM and hwmod data needed for the device to boot.
>
> The bootloader support for the platform is already available
> in mainline u-boot.
>
> The patches posted in this series are available at:
> git://github.com/rrnayak/linux.git for-3.12/dra-core-v2
>
> The patches (including the ones for in-kernel data) which boot
> on dra7xx evm are available at:
> t://github.com/rrnayak/linux.git out-of-tree/dra-integrated-v2
>
> R Sricharan (7):
> ARM: DRA7: id: Add cpu detection support for DRA7xx based SoCs'
> ARM: DRA7: Reuse all of PRCM and MPUSS SMP infra
> ARM: DRA7: Reuse io tables and add a new .init_early
> ARM: DRA7: Resue the clocksource, clockevent support
> ARM: DRA7: board-generic: Add basic DT support
> ARM: DRA7: Kconfig: Make ARCH_NR_GPIO default to 512
> ARM: DRA7: dts: Add the dts files for dra7 SoC and dra7-evm board
>
> Rajendra Nayak (1):
> ARM: DRA7: hwmod: Reuse the soc_ops used for OMAP4/5
>
I quickly scanned the series and largely it looks good to me.
The suggestion on dts and soc_id seems to be the valid ones and good
to address them. Feel free to add my ack when you respin the series
with those couple of issues addressed.
Regards,
Santosh
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v2 0/8] DRA7xx core support
2013-08-02 22:28 ` [PATCH v2 0/8] DRA7xx core support Santosh Shilimkar
@ 2013-08-04 16:14 ` Rajendra Nayak
0 siblings, 0 replies; 41+ messages in thread
From: Rajendra Nayak @ 2013-08-04 16:14 UTC (permalink / raw)
To: Santosh Shilimkar
Cc: paul, khilman, tony, benoit.cousson, r.sricharan, ambresh,
sourav.poddar, linux-omap, linux-arm-kernel
On Saturday 03 August 2013 03:58 AM, Santosh Shilimkar wrote:
> On Tuesday 30 July 2013 07:25 AM, Rajendra Nayak wrote:
>> Changes in v2:
>> -1- Fixed minor changelog details
>> -2- Dropped the SRAM support patch since we need to move to drivers/misc/sram.c
>> -3- Added DTS update patches to this series which were earlier posted as
>> part of the data series (Since they don't have much objections as against the
>> other in-kernel data files)
>> -4- Updated the EVM dts file with pin config details for uart/mcspi and i2c
>>
>> DRA7xx based SoCs' are high-performance, infotainment application devices,
>> based on enhanced OMAP architecture integrated on a 28nm
>> technology.
>>
>> The DRA7xx family is composed of DRA75x and DRA74x devices.
>> The current device for which the patches add support is the
>> DRA752 SoC.
>>
>> Most of the core IPs are similar to those found on the OMAP5
>> devices, including the dual cortex-A15 based MPU subsystem,
>> which has helped quite some reuse from existing OMAP5 support.
>>
>> This series contains only core support patches and none of
>> the PRCM and hwmod data needed for the device to boot.
>>
>> The bootloader support for the platform is already available
>> in mainline u-boot.
>>
>> The patches posted in this series are available at:
>> git://github.com/rrnayak/linux.git for-3.12/dra-core-v2
>>
>> The patches (including the ones for in-kernel data) which boot
>> on dra7xx evm are available at:
>> t://github.com/rrnayak/linux.git out-of-tree/dra-integrated-v2
>>
>> R Sricharan (7):
>> ARM: DRA7: id: Add cpu detection support for DRA7xx based SoCs'
>> ARM: DRA7: Reuse all of PRCM and MPUSS SMP infra
>> ARM: DRA7: Reuse io tables and add a new .init_early
>> ARM: DRA7: Resue the clocksource, clockevent support
>> ARM: DRA7: board-generic: Add basic DT support
>> ARM: DRA7: Kconfig: Make ARCH_NR_GPIO default to 512
>> ARM: DRA7: dts: Add the dts files for dra7 SoC and dra7-evm board
>>
>> Rajendra Nayak (1):
>> ARM: DRA7: hwmod: Reuse the soc_ops used for OMAP4/5
>>
> I quickly scanned the series and largely it looks good to me.
> The suggestion on dts and soc_id seems to be the valid ones and good
> to address them. Feel free to add my ack when you respin the series
> with those couple of issues addressed.
Thanks, will do.
>
> Regards,
> Santosh
>
>
>
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v2 8/8] ARM: DRA7: dts: Add the dts files for dra7 SoC and dra7-evm board
2013-07-30 11:25 ` [PATCH v2 8/8] ARM: DRA7: dts: Add the dts files for dra7 SoC and dra7-evm board Rajendra Nayak
2013-07-30 12:30 ` Nishanth Menon
@ 2013-08-12 11:44 ` Mark Rutland
2013-08-13 7:24 ` Rajendra Nayak
1 sibling, 1 reply; 41+ messages in thread
From: Mark Rutland @ 2013-08-12 11:44 UTC (permalink / raw)
To: Rajendra Nayak
Cc: paul@pwsan.com, khilman@linaro.org, tony@atomide.com,
benoit.cousson@gmail.com, r.sricharan@ti.com, ambresh@ti.com,
sourav.poddar@ti.com, linux-omap@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
On Tue, Jul 30, 2013 at 12:25:46PM +0100, Rajendra Nayak wrote:
> From: R Sricharan <r.sricharan@ti.com>
>
> Add minimal device tree source needed for DRA7 based SoCs.
> Also add a board dts file for the dra7-evm (based on dra752)
> which contains 1.5G of memory with 1G interleaved and 512MB
> non-interleaved. Also added in the board file are pin configuration
> details for i2c, mcspi and uart devices on board.
>
> Signed-off-by: R Sricharan <r.sricharan@ti.com>
> Signed-off-by: Rajendra Nayak <rnayak@ti.com>
> Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
> ---
> arch/arm/boot/dts/Makefile | 3 +-
> arch/arm/boot/dts/dra7-evm.dts | 163 ++++++++++++++
> arch/arm/boot/dts/dra7.dtsi | 488 ++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 653 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/boot/dts/dra7-evm.dts
> create mode 100644 arch/arm/boot/dts/dra7.dtsi
[...]
> diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
> new file mode 100644
> index 0000000..8a0c08e
> --- /dev/null
> +++ b/arch/arm/boot/dts/dra7.dtsi
> @@ -0,0 +1,488 @@
> +/*
> + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + * Based on "omap4.dtsi"
> + */
> +
> +/include/ "skeleton.dtsi"
> +
> +/ {
> + compatible = "ti,dra7xx";
> + interrupt-parent = <&gic>;
> +
> + aliases {
> + serial0 = &uart1;
> + serial1 = &uart2;
> + serial2 = &uart3;
> + serial3 = &uart4;
> + serial4 = &uart5;
> + serial5 = &uart6;
> + };
> +
> + cpus {
> + cpu@0 {
> + compatible = "arm,cortex-a15";
> + timer {
> + compatible = "arm,armv7-timer";
> + /*
> + * PPI secure/nonsecure IRQ,
> + * active low level-sensitive
> + */
> + interrupts = <1 13 0x308>,
> + <1 14 0x308>;
> + clock-frequency = <6144000>;
> + };
> + };
The cpu nodes should have a reg matching their unit-address, and a
device_type = "cpu".
The timer nodes should *not* be under the CPU nodes. They should be
under under the root node. I realise that it makes intuitive sense to
describe per-cpu resources this way, but that's not the way the bindings
are intended to be used (does thei DT even work?).
No virtual/hypervisor interrupts?
Do you really need the clock-frequency property? It's far preferrable to
have your bootloader do the right thing and program CNTFRQ with the
correct value.
> +
> + gic: interrupt-controller@48211000 {
> + compatible = "arm,cortex-a15-gic";
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + reg = <0x48211000 0x1000>,
> + <0x48212000 0x1000>;
Similarly, no GICH/GICV registers?
Thanks,
Mark.
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v2 8/8] ARM: DRA7: dts: Add the dts files for dra7 SoC and dra7-evm board
2013-07-30 13:01 ` Rajendra Nayak
@ 2013-08-12 13:46 ` Benoit Cousson
0 siblings, 0 replies; 41+ messages in thread
From: Benoit Cousson @ 2013-08-12 13:46 UTC (permalink / raw)
To: Rajendra Nayak
Cc: Nishanth Menon, linux-omap, linux-arm-kernel, tony, paul, khilman,
r.sricharan, ambresh, sourav.poddar
Hi Rajendra,
On 30/07/2013 15:01, Rajendra Nayak wrote:
> On Tuesday 30 July 2013 06:29 PM, Nishanth Menon wrote:
>> On 07/30/2013 07:56 AM, Rajendra Nayak wrote:
>>> On Tuesday 30 July 2013 06:16 PM, Nishanth Menon wrote:
>>>> On 07/30/2013 07:41 AM, Rajendra Nayak wrote:
>>>>> On Tuesday 30 July 2013 06:00 PM, Nishanth Menon wrote:
>>>>>> On 07/30/2013 06:25 AM, Rajendra Nayak wrote:
>>>>>>> From: R Sricharan <r.sricharan@ti.com>
>>>> [...]
>>>>>>> + mcspi4: spi@480ba000 {
>>>>>>> + compatible = "ti,omap4-mcspi";
>>>>>>> + reg = <0x480ba000 0x200>;
>>>>>>> + interrupts = <0 48 0x4>;
>>>>>>> + #address-cells = <1>;
>>>>>>> + #size-cells = <0>;
>>>>>>> + ti,hwmods = "mcspi4";
>>>>>>> + ti,spi-num-cs = <1>;
>>>>>>> + dmas = <&sdma 70>, <&sdma 71>;
>>>>>>> + dma-names = "tx0", "rx0";
>>>>>>> + };
>>>>>>> + };
>>>>>>> +};
>>>>>>>
>>>>>> ref: [1], we discussed that we should now be able to introduce all instances of h/w blocks into the dra7.dts. Further, considering [2]
>>>>> hmm, thats a long discussion on crossbar driver that [1] points to. Do you want to summarize what you mean by 'introduce all instances of h/w blocks'
>>>> I recommend reading the last few emails on the thread about how we could do this with pinctrl. unfortunately, this patch is not informative enough to indicate that not all instances of the potential IP blocks are listed here.
>>>>
>>>>>> would you not want to follow "status = disabled" for all modules by default and enable required modules in board file, so that we dont have to respin this yet again?
>>>>> Well, I was just following the convention of whats already followed on existing OMAPs. See [3] for some views on these.
>>>> DRA7 case, I would not think it makes sense due to the number of product variants being done, not all will use the same set. Further, rationale for DRA7 and my suggestion for Grant's option (1) is mainly because the product variants will require more dtsis rather than board files using the product variants use just the necessary modules from a common dtsi. Makes support of variants like OMAP57xx etc trivial and constrainted to board file usage, rather than spinning off new dtsis.
>>> Makes sense with the different product variants for DRA7, AM335x already does it this way, but the rest of OMAP3/4/5 are doing it the other way.
>>> I think its just too confusing to follow different conventions for different SoCs. We should stick to just one, either this way or that.
>>>
>> I think bucketing DRA7(with multitude of SoC variants) with OMAP family(usually with <5 variants) will be a wrong approach. we should choose the approach appropriate for the SoC. hence, OMAPx having all default enabled makes sense (as the delta is usually trivial), but on DRA7, the variants are larger :(
>>
>> just my 2 cents.
> I can respin with the changes, but before I do so, Benoit do you agree with the rationale for these and fine with the approach?
>
>
Sorry for the very late reply. I've just seen it because Mark's answer
put in again in my gmail box.
I'm not sure to understand what Nishanth and you are arguing for :-)
If this is about the default status state, I think that this flag is
anyway confusing because you cannot know if we are considering an IP
that does not exist at all in a variant or an IP that is not used on a
certain board...
This potential issue we can have with the second case is that the IP
might be enabled by the boot loader and never disabled because
status="disabled" prevent DT to create the device, and thus prevent the
driver to properly idle the device.
That's why I did not like the usage of status="disabled" by default,
because the way DT core handle that might not be appropriate for an IP
that is there but not use.
For a variant that does not contain physically the IP, that flag can be
relevant.
Regarding which default status is the best, I guess as soon as it is
consistant across a chip family, both are fine to me.
Not necessarily related to your discussion, but I still think that DT is
missing a flag to make the difference between the two cases.
Regards,
Benoit
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v2 8/8] ARM: DRA7: dts: Add the dts files for dra7 SoC and dra7-evm board
2013-08-12 11:44 ` Mark Rutland
@ 2013-08-13 7:24 ` Rajendra Nayak
2013-08-13 9:46 ` Mark Rutland
0 siblings, 1 reply; 41+ messages in thread
From: Rajendra Nayak @ 2013-08-13 7:24 UTC (permalink / raw)
To: Mark Rutland
Cc: linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
paul@pwsan.com, khilman@linaro.org, tony@atomide.com,
benoit.cousson@gmail.com, r.sricharan@ti.com, ambresh@ti.com,
sourav.poddar@ti.com
[]..
>> +
>> + cpus {
>> + cpu@0 {
>> + compatible = "arm,cortex-a15";
>> + timer {
>> + compatible = "arm,armv7-timer";
>> + /*
>> + * PPI secure/nonsecure IRQ,
>> + * active low level-sensitive
>> + */
>> + interrupts = <1 13 0x308>,
>> + <1 14 0x308>;
>> + clock-frequency = <6144000>;
>> + };
>> + };
>
> The cpu nodes should have a reg matching their unit-address, and a
> device_type = "cpu".
>
> The timer nodes should *not* be under the CPU nodes. They should be
> under under the root node. I realise that it makes intuitive sense to
> describe per-cpu resources this way, but that's not the way the bindings
> are intended to be used (does thei DT even work?).
>
> No virtual/hypervisor interrupts?
Mark, all valid points. I just updated the patch to include all the missing
interrupts and registers for timer and gic and moved the timer node out as
its supposed to be.
>
> Do you really need the clock-frequency property? It's far preferrable to
> have your bootloader do the right thing and program CNTFRQ with the
> correct value.
I kept the clock-frequency property since our bootloader does not handle this
and I am not sure if its a good idea to have the dependency on bootloader
to do this.
Updated patch:
----
>From 4d2e7cfe8a44448a37686a4af26f320ab0d66acb Mon Sep 17 00:00:00 2001
From: R Sricharan <r.sricharan@ti.com>
Date: Thu, 7 Feb 2013 16:14:00 +0530
Subject: [PATCH] ARM: DRA7: dts: Add the dts files for dra7 SoC and dra7-evm
board
Add minimal device tree source needed for DRA7 based SoCs.
Also add a board dts file for the dra7-evm (based on dra752)
which contains 1.5G of memory with 1G interleaved and 512MB
non-interleaved. Also added in the board file are pin configuration
details for i2c, mcspi and uart devices on board.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
---
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/dra7-evm.dts | 140 ++++++++++
arch/arm/boot/dts/dra7.dtsi | 568 ++++++++++++++++++++++++++++++++++++++++
3 files changed, 710 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/dra7-evm.dts
create mode 100644 arch/arm/boot/dts/dra7.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 641b3c9..e2f8566 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -173,7 +173,8 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
am335x-bone.dtb \
am3517-evm.dtb \
am3517_mt_ventoux.dtb \
- am43x-epos-evm.dtb
+ am43x-epos-evm.dtb \
+ dra7-evm.dtb
dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb
dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
dtb-$(CONFIG_ARCH_U8500) += snowball.dtb \
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
new file mode 100644
index 0000000..21fe16b
--- /dev/null
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -0,0 +1,140 @@
+/*
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+#include "dra7.dtsi"
+
+/ {
+ model = "TI DRA7";
+ compatible = "ti,dra7-evm", "ti,dra752", "ti,dra7";
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x60000000>; /* 1536 MB */
+ };
+};
+
+&dra7_pmx_core {
+ i2c1_pins: pinmux_i2c1_pins {
+ pinctrl-single,pins = <
+ 0x400 0x60000 /* i2c1_sda */
+ 0x404 0x60000 /* i2c1_scl */
+ >;
+ };
+
+ i2c2_pins: pinmux_i2c2_pins {
+ pinctrl-single,pins = <
+ 0x408 0x60000 /* i2c2_sda */
+ 0x40c 0x60000 /* i2c2_scl */
+ >;
+ };
+
+ i2c3_pins: pinmux_i2c3_pins {
+ pinctrl-single,pins = <
+ 0x410 0x60000 /* i2c3_sda */
+ 0x414 0x60000 /* i2c3_scl */
+ >;
+ };
+
+ mcspi1_pins: pinmux_mcspi1_pins {
+ pinctrl-single,pins = <
+ 0x3a4 0x40000 /* spi2_clk */
+ 0x3a8 0x40000 /* spi2_d1 */
+ 0x3ac 0x40000 /* spi2_d0 */
+ 0x3b0 0xc0000 /* spi2_cs0 */
+ 0x3b4 0xc0000 /* spi2_cs1 */
+ 0x3b8 0xe0006 /* spi2_cs2 */
+ 0x3bc 0xe0006 /* spi2_cs3 */
+ >;
+ };
+
+ mcspi2_pins: pinmux_mcspi2_pins {
+ pinctrl-single,pins = <
+ 0x3c0 0x40000 /* spi2_sclk */
+ 0x3c4 0xc0000 /* spi2_d1 */
+ 0x3c8 0xc0000 /* spi2_d1 */
+ 0x3cc 0xe0000 /* spi2_cs0 */
+ >;
+ };
+
+ uart1_pins: pinmux_uart1_pins {
+ pinctrl-single,pins = <
+ 0x3e0 0xe0000 /* uart1_rxd */
+ 0x3e4 0xe0000 /* uart1_txd */
+ 0x3e8 0x60003 /* uart1_ctsn */
+ 0x3ec 0x60003 /* uart1_rtsn */
+ >;
+ };
+
+ uart2_pins: pinmux_uart2_pins {
+ pinctrl-single,pins = <
+ 0x3f0 0x60000 /* uart2_rxd */
+ 0x3f4 0x60000 /* uart2_txd */
+ 0x3f8 0x60000 /* uart2_ctsn */
+ 0x3fc 0x60000 /* uart2_rtsn */
+ >;
+ };
+
+ uart3_pins: pinmux_uart3_pins {
+ pinctrl-single,pins = <
+ 0x248 0xc0000 /* uart3_rxd */
+ 0x24c 0xc0000 /* uart3_txd */
+ >;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+ clock-frequency = <400000>;
+};
+
+&i2c2 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins>;
+ clock-frequency = <400000>;
+};
+
+&i2c3 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3_pins>;
+ clock-frequency = <3400000>;
+};
+
+&mcspi1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcspi1_pins>;
+};
+
+&mcspi2 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcspi2_pins>;
+};
+
+&uart1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>;
+};
+
+&uart2 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
+};
+
+&uart3 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pins>;
+};
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
new file mode 100644
index 0000000..3b154a0
--- /dev/null
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -0,0 +1,568 @@
+/*
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ * Based on "omap4.dtsi"
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "skeleton.dtsi"
+
+/ {
+ compatible = "ti,dra7xx";
+ interrupt-parent = <&gic>;
+
+ aliases {
+ serial0 = &uart1;
+ serial1 = &uart2;
+ serial2 = &uart3;
+ serial3 = &uart4;
+ serial4 = &uart5;
+ serial5 = &uart6;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0>;
+ };
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <1>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ /* PPI secure/nonsecure IRQ */
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
+ clock-frequency = <6144000>;
+ };
+
+ gic: interrupt-controller@48211000 {
+ compatible = "arm,cortex-a15-gic";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ reg = <0x48211000 0x1000>,
+ <0x48212000 0x1000>,
+ <0x48214000 0x2000>,
+ <0x48216000 0x2000>;
+ };
+
+ /*
+ * The soc node represents the soc top level view. It is uses for IPs
+ * that are not memory mapped in the MPU view or for the MPU itself.
+ */
+ soc {
+ compatible = "ti,omap-infra";
+ mpu {
+ compatible = "ti,omap5-mpu";
+ ti,hwmods = "mpu";
+ };
+ };
+
+ /*
+ * XXX: Use a flat representation of the SOC interconnect.
+ * The real OMAP interconnect network is quite complex.
+ * Since that will not bring real advantage to represent that in DT for
+ * the moment, just use a fake OCP bus entry to represent the whole bus
+ * hierarchy.
+ */
+ ocp {
+ compatible = "ti,omap4-l3-noc", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ ti,hwmods = "l3_main_1", "l3_main_2";
+
+ counter32k: counter@4ae04000 {
+ compatible = "ti,omap-counter32k";
+ reg = <0x4ae04000 0x40>;
+ ti,hwmods = "counter_32k";
+ };
+
+ dra7_pmx_core: pinmux@4a003400 {
+ compatible = "pinctrl-single";
+ reg = <0x4a003400 0x0464>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x3fffffff>;
+ };
+
+ sdma: dma-controller@4a056000 {
+ compatible = "ti,omap4430-sdma";
+ reg = <0x4a056000 0x1000>;
+ interrupts = <0 12 0x4>,
+ <0 13 0x4>,
+ <0 14 0x4>,
+ <0 15 0x4>;
+ #dma-cells = <1>;
+ #dma-channels = <32>;
+ #dma-requests = <127>;
+ };
+
+ gpio1: gpio@4ae10000 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x4ae10000 0x200>;
+ interrupts = <0 29 0x4>;
+ ti,hwmods = "gpio1";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ gpio2: gpio@48055000 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x48055000 0x200>;
+ interrupts = <0 30 0x4>;
+ ti,hwmods = "gpio2";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ gpio3: gpio@48057000 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x48057000 0x200>;
+ interrupts = <0 31 0x4>;
+ ti,hwmods = "gpio3";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ gpio4: gpio@48059000 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x48059000 0x200>;
+ interrupts = <0 32 0x4>;
+ ti,hwmods = "gpio4";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ gpio5: gpio@4805b000 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x4805b000 0x200>;
+ interrupts = <0 33 0x4>;
+ ti,hwmods = "gpio5";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ gpio6: gpio@4805d000 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x4805d000 0x200>;
+ interrupts = <0 34 0x4>;
+ ti,hwmods = "gpio6";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ gpio7: gpio@48051000 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x48051000 0x200>;
+ interrupts = <0 35 0x4>;
+ ti,hwmods = "gpio7";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ gpio8: gpio@48053000 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x48053000 0x200>;
+ interrupts = <0 121 0x4>;
+ ti,hwmods = "gpio8";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ uart1: serial@4806a000 {
+ compatible = "ti,omap4-uart";
+ reg = <0x4806a000 0x100>;
+ interrupts = <0 72 0x4>;
+ ti,hwmods = "uart1";
+ clock-frequency = <48000000>;
+ status = "disabled";
+ };
+
+ uart2: serial@4806c000 {
+ compatible = "ti,omap4-uart";
+ reg = <0x4806c000 0x100>;
+ interrupts = <0 73 0x4>;
+ ti,hwmods = "uart2";
+ clock-frequency = <48000000>;
+ status = "disabled";
+ };
+
+ uart3: serial@48020000 {
+ compatible = "ti,omap4-uart";
+ reg = <0x48020000 0x100>;
+ interrupts = <0 74 0x4>;
+ ti,hwmods = "uart3";
+ clock-frequency = <48000000>;
+ status = "disabled";
+ };
+
+ uart4: serial@4806e000 {
+ compatible = "ti,omap4-uart";
+ reg = <0x4806e000 0x100>;
+ interrupts = <0 70 0x4>;
+ ti,hwmods = "uart4";
+ clock-frequency = <48000000>;
+ status = "disabled";
+ };
+
+ uart5: serial@48066000 {
+ compatible = "ti,omap4-uart";
+ reg = <0x48066000 0x100>;
+ interrupts = <0 105 0x4>;
+ ti,hwmods = "uart5";
+ clock-frequency = <48000000>;
+ status = "disabled";
+ };
+
+ uart6: serial@48068000 {
+ compatible = "ti,omap4-uart";
+ reg = <0x48068000 0x100>;
+ interrupts = <0 106 0x4>;
+ ti,hwmods = "uart6";
+ clock-frequency = <48000000>;
+ status = "disabled";
+ };
+
+ uart7: serial@48420000 {
+ compatible = "ti,omap4-uart";
+ reg = <0x48420000 0x100>;
+ ti,hwmods = "uart7";
+ clock-frequency = <48000000>;
+ status = "disabled";
+ };
+
+ uart8: serial@48422000 {
+ compatible = "ti,omap4-uart";
+ reg = <0x48422000 0x100>;
+ ti,hwmods = "uart8";
+ clock-frequency = <48000000>;
+ status = "disabled";
+ };
+
+ uart9: serial@48424000 {
+ compatible = "ti,omap4-uart";
+ reg = <0x48424000 0x100>;
+ ti,hwmods = "uart9";
+ clock-frequency = <48000000>;
+ status = "disabled";
+ };
+
+ uart10: serial@4ae2b000 {
+ compatible = "ti,omap4-uart";
+ reg = <0x4ae2b000 0x100>;
+ ti,hwmods = "uart10";
+ clock-frequency = <48000000>;
+ status = "disabled";
+ };
+
+ timer1: timer@4ae18000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x4ae18000 0x80>;
+ interrupts = <0 37 0x4>;
+ ti,hwmods = "timer1";
+ ti,timer-alwon;
+ };
+
+ timer2: timer@48032000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x48032000 0x80>;
+ interrupts = <0 38 0x4>;
+ ti,hwmods = "timer2";
+ };
+
+ timer3: timer@48034000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x48034000 0x80>;
+ interrupts = <0 39 0x4>;
+ ti,hwmods = "timer3";
+ };
+
+ timer4: timer@48036000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x48036000 0x80>;
+ interrupts = <0 40 0x4>;
+ ti,hwmods = "timer4";
+ };
+
+ timer5: timer@48820000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x48820000 0x80>;
+ interrupts = <0 41 0x4>;
+ ti,hwmods = "timer5";
+ ti,timer-dsp;
+ };
+
+ timer6: timer@48822000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x48822000 0x80>;
+ interrupts = <0 42 0x4>;
+ ti,hwmods = "timer6";
+ ti,timer-dsp;
+ ti,timer-pwm;
+ };
+
+ timer7: timer@48824000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x48824000 0x80>;
+ interrupts = <0 43 0x4>;
+ ti,hwmods = "timer7";
+ ti,timer-dsp;
+ };
+
+ timer8: timer@48826000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x48826000 0x80>;
+ interrupts = <0 44 0x4>;
+ ti,hwmods = "timer8";
+ ti,timer-dsp;
+ ti,timer-pwm;
+ };
+
+ timer9: timer@4803e000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x4803e000 0x80>;
+ interrupts = <0 45 0x4>;
+ ti,hwmods = "timer9";
+ };
+
+ timer10: timer@48086000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x48086000 0x80>;
+ interrupts = <0 46 0x4>;
+ ti,hwmods = "timer10";
+ };
+
+ timer11: timer@48088000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x48088000 0x80>;
+ interrupts = <0 47 0x4>;
+ ti,hwmods = "timer11";
+ ti,timer-pwm;
+ };
+
+ timer13: timer@48828000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x48828000 0x80>;
+ ti,hwmods = "timer13";
+ status = "disabled";
+ };
+
+ timer14: timer@4882a000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x4882a000 0x80>;
+ ti,hwmods = "timer14";
+ status = "disabled";
+ };
+
+ timer15: timer@4882c000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x4882c000 0x80>;
+ ti,hwmods = "timer15";
+ status = "disabled";
+ };
+
+ timer16: timer@4882e000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x4882e000 0x80>;
+ ti,hwmods = "timer16";
+ status = "disabled";
+ };
+
+ wdt2: wdt@4ae14000 {
+ compatible = "ti,omap4-wdt";
+ reg = <0x4ae14000 0x80>;
+ interrupts = <0 80 0x4>;
+ ti,hwmods = "wd_timer2";
+ };
+
+ i2c1: i2c@48070000 {
+ compatible = "ti,omap4-i2c";
+ reg = <0x48070000 0x100>;
+ interrupts = <0 56 0x4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "i2c1";
+ status = "disabled";
+ };
+
+ i2c2: i2c@48072000 {
+ compatible = "ti,omap4-i2c";
+ reg = <0x48072000 0x100>;
+ interrupts = <0 57 0x4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "i2c2";
+ status = "disabled";
+ };
+
+ i2c3: i2c@48060000 {
+ compatible = "ti,omap4-i2c";
+ reg = <0x48060000 0x100>;
+ interrupts = <0 61 0x4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "i2c3";
+ status = "disabled";
+ };
+
+ i2c4: i2c@4807a000 {
+ compatible = "ti,omap4-i2c";
+ reg = <0x4807a000 0x100>;
+ interrupts = <0 62 0x4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "i2c4";
+ status = "disabled";
+ };
+
+ i2c5: i2c@4807c000 {
+ compatible = "ti,omap4-i2c";
+ reg = <0x4807c000 0x100>;
+ interrupts = <0 60 0x4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "i2c5";
+ status = "disabled";
+ };
+
+ mmc1: mmc@4809c000 {
+ compatible = "ti,omap4-hsmmc";
+ reg = <0x4809c000 0x400>;
+ interrupts = <0 83 0x4>;
+ ti,hwmods = "mmc1";
+ ti,dual-volt;
+ ti,needs-special-reset;
+ dmas = <&sdma 61>, <&sdma 62>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ mmc2: mmc@480b4000 {
+ compatible = "ti,omap4-hsmmc";
+ reg = <0x480b4000 0x400>;
+ interrupts = <0 86 0x4>;
+ ti,hwmods = "mmc2";
+ ti,needs-special-reset;
+ dmas = <&sdma 47>, <&sdma 48>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ mmc3: mmc@480ad000 {
+ compatible = "ti,omap4-hsmmc";
+ reg = <0x480ad000 0x400>;
+ interrupts = <0 94 0x4>;
+ ti,hwmods = "mmc3";
+ ti,needs-special-reset;
+ dmas = <&sdma 77>, <&sdma 78>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ mmc4: mmc@480d1000 {
+ compatible = "ti,omap4-hsmmc";
+ reg = <0x480d1000 0x400>;
+ interrupts = <0 96 0x4>;
+ ti,hwmods = "mmc4";
+ ti,needs-special-reset;
+ dmas = <&sdma 57>, <&sdma 58>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ mcspi1: spi@48098000 {
+ compatible = "ti,omap4-mcspi";
+ reg = <0x48098000 0x200>;
+ interrupts = <0 65 0x4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "mcspi1";
+ ti,spi-num-cs = <4>;
+ dmas = <&sdma 35>,
+ <&sdma 36>,
+ <&sdma 37>,
+ <&sdma 38>,
+ <&sdma 39>,
+ <&sdma 40>,
+ <&sdma 41>,
+ <&sdma 42>;
+ dma-names = "tx0", "rx0", "tx1", "rx1",
+ "tx2", "rx2", "tx3", "rx3";
+ status = "disabled";
+ };
+
+ mcspi2: spi@4809a000 {
+ compatible = "ti,omap4-mcspi";
+ reg = <0x4809a000 0x200>;
+ interrupts = <0 66 0x4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "mcspi2";
+ ti,spi-num-cs = <2>;
+ dmas = <&sdma 43>,
+ <&sdma 44>,
+ <&sdma 45>,
+ <&sdma 46>;
+ dma-names = "tx0", "rx0", "tx1", "rx1";
+ status = "disabled";
+ };
+
+ mcspi3: spi@480b8000 {
+ compatible = "ti,omap4-mcspi";
+ reg = <0x480b8000 0x200>;
+ interrupts = <0 91 0x4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "mcspi3";
+ ti,spi-num-cs = <2>;
+ dmas = <&sdma 15>, <&sdma 16>;
+ dma-names = "tx0", "rx0";
+ status = "disabled";
+ };
+
+ mcspi4: spi@480ba000 {
+ compatible = "ti,omap4-mcspi";
+ reg = <0x480ba000 0x200>;
+ interrupts = <0 48 0x4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "mcspi4";
+ ti,spi-num-cs = <1>;
+ dmas = <&sdma 70>, <&sdma 71>;
+ dma-names = "tx0", "rx0";
+ status = "disabled";
+ };
+ };
+};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 41+ messages in thread
* Re: [PATCH v2 8/8] ARM: DRA7: dts: Add the dts files for dra7 SoC and dra7-evm board
2013-08-13 7:24 ` Rajendra Nayak
@ 2013-08-13 9:46 ` Mark Rutland
2013-08-13 10:05 ` Marc Zyngier
0 siblings, 1 reply; 41+ messages in thread
From: Mark Rutland @ 2013-08-13 9:46 UTC (permalink / raw)
To: Rajendra Nayak
Cc: linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
paul@pwsan.com, khilman@linaro.org, tony@atomide.com,
benoit.cousson@gmail.com, r.sricharan@ti.com, ambresh@ti.com,
sourav.poddar@ti.com, marc.zyngier
[Adding Marc to Cc]
On Tue, Aug 13, 2013 at 08:24:31AM +0100, Rajendra Nayak wrote:
> []..
>
> >> +
> >> + cpus {
> >> + cpu@0 {
> >> + compatible = "arm,cortex-a15";
> >> + timer {
> >> + compatible = "arm,armv7-timer";
> >> + /*
> >> + * PPI secure/nonsecure IRQ,
> >> + * active low level-sensitive
> >> + */
> >> + interrupts = <1 13 0x308>,
> >> + <1 14 0x308>;
> >> + clock-frequency = <6144000>;
> >> + };
> >> + };
> >
> > The cpu nodes should have a reg matching their unit-address, and a
> > device_type = "cpu".
> >
> > The timer nodes should *not* be under the CPU nodes. They should be
> > under under the root node. I realise that it makes intuitive sense to
> > describe per-cpu resources this way, but that's not the way the bindings
> > are intended to be used (does thei DT even work?).
> >
> > No virtual/hypervisor interrupts?
>
> Mark, all valid points. I just updated the patch to include all the missing
> interrupts and registers for timer and gic and moved the timer node out as
> its supposed to be.
Great!
>
> >
> > Do you really need the clock-frequency property? It's far preferrable to
> > have your bootloader do the right thing and program CNTFRQ with the
> > correct value.
>
> I kept the clock-frequency property since our bootloader does not handle this
> and I am not sure if its a good idea to have the dependency on bootloader
> to do this.
There is precedent for handling it this way, but it would be far nicer
to fix the bootloader to set CNTFRQ. For one thing it's only writeable
from the secure side, so a host os can't fix it up for guests that might
depend on it rather than dt. I realise it's not necessarily as simple as
it sounds to fix that up, however.
[...]
> + timer {
> + compatible = "arm,armv7-timer";
> + /* PPI secure/nonsecure IRQ */
The comment's now stale, and I don't think it's necessary - the binding
defines the order these are in.
> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
> + clock-frequency = <6144000>;
> + };
Thanks,
Mark.
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v2 8/8] ARM: DRA7: dts: Add the dts files for dra7 SoC and dra7-evm board
2013-08-13 9:46 ` Mark Rutland
@ 2013-08-13 10:05 ` Marc Zyngier
2013-08-14 9:40 ` Rajendra Nayak
0 siblings, 1 reply; 41+ messages in thread
From: Marc Zyngier @ 2013-08-13 10:05 UTC (permalink / raw)
To: Mark Rutland
Cc: Rajendra Nayak, paul, khilman, tony, benoit.cousson, r.sricharan,
ambresh, sourav.poddar, linux-omap, linux-arm-kernel
On 2013-08-13 10:46, Mark Rutland wrote:
> [Adding Marc to Cc]
>
> On Tue, Aug 13, 2013 at 08:24:31AM +0100, Rajendra Nayak wrote:
>> []..
>>
>> >> +
>> >> + cpus {
>> >> + cpu@0 {
>> >> + compatible = "arm,cortex-a15";
>> >> + timer {
>> >> + compatible = "arm,armv7-timer";
>> >> + /*
>> >> + * PPI secure/nonsecure IRQ,
>> >> + * active low level-sensitive
>> >> + */
>> >> + interrupts = <1 13 0x308>,
>> >> + <1 14 0x308>;
>> >> + clock-frequency = <6144000>;
>> >> + };
>> >> + };
>> >
>> > The cpu nodes should have a reg matching their unit-address, and a
>> > device_type = "cpu".
>> >
>> > The timer nodes should *not* be under the CPU nodes. They should
>> be
>> > under under the root node. I realise that it makes intuitive sense
>> to
>> > describe per-cpu resources this way, but that's not the way the
>> bindings
>> > are intended to be used (does thei DT even work?).
>> >
>> > No virtual/hypervisor interrupts?
>>
>> Mark, all valid points. I just updated the patch to include all the
>> missing
>> interrupts and registers for timer and gic and moved the timer node
>> out as
>> its supposed to be.
>
> Great!
>
>>
>> >
>> > Do you really need the clock-frequency property? It's far
>> preferrable to
>> > have your bootloader do the right thing and program CNTFRQ with
>> the
>> > correct value.
>>
>> I kept the clock-frequency property since our bootloader does not
>> handle this
>> and I am not sure if its a good idea to have the dependency on
>> bootloader
>> to do this.
>
> There is precedent for handling it this way, but it would be far
> nicer
> to fix the bootloader to set CNTFRQ. For one thing it's only
> writeable
> from the secure side, so a host os can't fix it up for guests that
> might
> depend on it rather than dt. I realise it's not necessarily as simple
> as
> it sounds to fix that up, however.
Indeed, having the wrong CNTFRQ in the host has the unfortunate effect
of propagating the crap into the guests.
While this can be worked around for Linux guests (you have to hack the
DT passed to the guests, which is very unpleasant at best and varies
from one host to another), there is nothing you can do for non-DT
guests.
So please, fix it in your firmware/boot-ROM while it is still time.
Thanks,
M.
--
Fast, cheap, reliable. Pick two.
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v2 8/8] ARM: DRA7: dts: Add the dts files for dra7 SoC and dra7-evm board
2013-08-13 10:05 ` Marc Zyngier
@ 2013-08-14 9:40 ` Rajendra Nayak
0 siblings, 0 replies; 41+ messages in thread
From: Rajendra Nayak @ 2013-08-14 9:40 UTC (permalink / raw)
To: Marc Zyngier
Cc: Mark Rutland, paul, khilman, tony, benoit.cousson, r.sricharan,
ambresh, sourav.poddar, linux-omap, linux-arm-kernel
On Tuesday 13 August 2013 03:35 PM, Marc Zyngier wrote:
> On 2013-08-13 10:46, Mark Rutland wrote:
>> [Adding Marc to Cc]
>>
>> On Tue, Aug 13, 2013 at 08:24:31AM +0100, Rajendra Nayak wrote:
>>> []..
>>>
>>> >> +
>>> >> + cpus {
>>> >> + cpu@0 {
>>> >> + compatible = "arm,cortex-a15";
>>> >> + timer {
>>> >> + compatible = "arm,armv7-timer";
>>> >> + /*
>>> >> + * PPI secure/nonsecure IRQ,
>>> >> + * active low level-sensitive
>>> >> + */
>>> >> + interrupts = <1 13 0x308>,
>>> >> + <1 14 0x308>;
>>> >> + clock-frequency = <6144000>;
>>> >> + };
>>> >> + };
>>> >
>>> > The cpu nodes should have a reg matching their unit-address, and a
>>> > device_type = "cpu".
>>> >
>>> > The timer nodes should *not* be under the CPU nodes. They should be
>>> > under under the root node. I realise that it makes intuitive sense to
>>> > describe per-cpu resources this way, but that's not the way the bindings
>>> > are intended to be used (does thei DT even work?).
>>> >
>>> > No virtual/hypervisor interrupts?
>>>
>>> Mark, all valid points. I just updated the patch to include all the missing
>>> interrupts and registers for timer and gic and moved the timer node out as
>>> its supposed to be.
>>
>> Great!
>>
>>>
>>> >
>>> > Do you really need the clock-frequency property? It's far preferrable to
>>> > have your bootloader do the right thing and program CNTFRQ with the
>>> > correct value.
>>>
>>> I kept the clock-frequency property since our bootloader does not handle this
>>> and I am not sure if its a good idea to have the dependency on bootloader
>>> to do this.
>>
>> There is precedent for handling it this way, but it would be far nicer
>> to fix the bootloader to set CNTFRQ. For one thing it's only writeable
>> from the secure side, so a host os can't fix it up for guests that might
>> depend on it rather than dt. I realise it's not necessarily as simple as
>> it sounds to fix that up, however.
>
> Indeed, having the wrong CNTFRQ in the host has the unfortunate effect of propagating the crap into the guests.
>
> While this can be worked around for Linux guests (you have to hack the DT passed to the guests, which is very unpleasant at best and varies from one host to another), there is nothing you can do for non-DT guests.
>
> So please, fix it in your firmware/boot-ROM while it is still time.
Marc, makes sense. Turns out our bootROM (for dra7) does not do this today but does have an api to do it.
So while we figure how to do this some place else, I will go ahead and drop this from dt for now.
Thanks for the review.
regards,
Rajendra
>
> Thanks,
>
> M.
^ permalink raw reply [flat|nested] 41+ messages in thread
end of thread, other threads:[~2013-08-14 9:41 UTC | newest]
Thread overview: 41+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2013-07-30 11:25 [PATCH v2 0/8] DRA7xx core support Rajendra Nayak
2013-07-30 11:25 ` [PATCH v2 1/8] ARM: DRA7: id: Add cpu detection support for DRA7xx based SoCs' Rajendra Nayak
2013-07-30 13:10 ` Felipe Balbi
2013-07-30 13:18 ` Felipe Balbi
2013-07-30 13:55 ` Tony Lindgren
2013-07-30 14:18 ` Sricharan R
2013-07-30 14:23 ` Felipe Balbi
2013-07-30 14:36 ` Sricharan R
2013-07-30 15:32 ` Felipe Balbi
2013-07-30 18:37 ` Sricharan R
2013-07-30 18:43 ` Nishanth Menon
2013-07-31 6:02 ` Rajendra Nayak
2013-07-31 6:42 ` Tony Lindgren
2013-07-31 6:49 ` Rajendra Nayak
2013-07-30 11:25 ` [PATCH v2 2/8] ARM: DRA7: hwmod: Reuse the soc_ops used for OMAP4/5 Rajendra Nayak
2013-07-30 11:25 ` [PATCH v2 3/8] ARM: DRA7: Reuse all of PRCM and MPUSS SMP infra Rajendra Nayak
2013-07-30 12:26 ` Nishanth Menon
2013-07-30 12:38 ` Rajendra Nayak
2013-07-30 12:41 ` Nishanth Menon
2013-07-30 12:48 ` Rajendra Nayak
2013-07-30 12:57 ` Nishanth Menon
2013-07-30 12:59 ` Rajendra Nayak
2013-07-30 11:25 ` [PATCH v2 4/8] ARM: DRA7: Reuse io tables and add a new .init_early Rajendra Nayak
2013-07-30 11:25 ` [PATCH v2 5/8] ARM: DRA7: Resue the clocksource, clockevent support Rajendra Nayak
2013-07-30 11:25 ` [PATCH v2 6/8] ARM: DRA7: board-generic: Add basic DT support Rajendra Nayak
2013-07-30 11:25 ` [PATCH v2 7/8] ARM: DRA7: Kconfig: Make ARCH_NR_GPIO default to 512 Rajendra Nayak
2013-07-30 11:25 ` [PATCH v2 8/8] ARM: DRA7: dts: Add the dts files for dra7 SoC and dra7-evm board Rajendra Nayak
2013-07-30 12:30 ` Nishanth Menon
2013-07-30 12:41 ` Rajendra Nayak
2013-07-30 12:46 ` Nishanth Menon
2013-07-30 12:56 ` Rajendra Nayak
2013-07-30 12:59 ` Nishanth Menon
2013-07-30 13:01 ` Rajendra Nayak
2013-08-12 13:46 ` Benoit Cousson
2013-08-12 11:44 ` Mark Rutland
2013-08-13 7:24 ` Rajendra Nayak
2013-08-13 9:46 ` Mark Rutland
2013-08-13 10:05 ` Marc Zyngier
2013-08-14 9:40 ` Rajendra Nayak
2013-08-02 22:28 ` [PATCH v2 0/8] DRA7xx core support Santosh Shilimkar
2013-08-04 16:14 ` Rajendra Nayak
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