[PATCH 00/55]: ARM: OMAP2+: PRCM move to drivers

[PATCH 00/55]: ARM: OMAP2+: PRCM move to drivers

[Tero Kristo]

Hi,

This set is continuation for the work started earlier to cleanup the CM/PRM
and attempt to make it a separate driver. This set depends on these
two sets:

CM/PRM cleanup set:
http://marc.info/?l=linux-omap&m=139395000918201&w=2

OMAP2 clock DT set:
http://comments.gmane.org/gmane.linux.ports.arm.omap/111257

This set is pretty huge but the patches can be applied in stages if need be.
Anyway, it would be good to get some feedback whether the driver folder
locations etc. are good, and whether the effort taken here will be enough
to actually move the driver. Clockdomain / powerdomain code can also be
moved easily under the drivers/power/omap folder (or someplace else if
requested) once this set is in. Also, clockdomain / powerdomain data
should be possible to convert to DT format or some sort of firmware
blob once this is done.

Patch #55 in this set is pretty massive as it moves all the C files at
the same time, this should probably be split up as multiple patches.

Testing branch pushed here (contains also the CM/PRM cleanup set and OMAP2
clock DT conversion):

tree: https://github.com/t-kristo/linux-pm.git
branch: 3.14-rc4-cm-prm-driver-v1

Testing done:
- am335x-bone: boot
- omap3-beagle: boot, suspend-resume (ret/off)
- omap4-panda-es: boot, suspend-resume (ret)
- omap5-uevm: boot

-Tero

[PATCH 01/55] ARM: OMAP4: CM: use cm_base* in register address calculations

[Tero Kristo]

OMAP44XX_CM*_REGADDR macros should be avoided, instead use the cm_base*
iomaps.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/cm44xx.c |    8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-omap2/cm44xx.c b/arch/arm/mach-omap2/cm44xx.c
index 535d66e..5627072 100644
--- a/arch/arm/mach-omap2/cm44xx.c
+++ b/arch/arm/mach-omap2/cm44xx.c
@@ -30,23 +30,23 @@
 /* Read a register in CM1 */
 u32 omap4_cm1_read_inst_reg(s16 inst, u16 reg)
 {
-	return __raw_readl(OMAP44XX_CM1_REGADDR(inst, reg));
+	return __raw_readl(cm_base + inst + reg);
 }
 
 /* Write into a register in CM1 */
 void omap4_cm1_write_inst_reg(u32 val, s16 inst, u16 reg)
 {
-	__raw_writel(val, OMAP44XX_CM1_REGADDR(inst, reg));
+	__raw_writel(val, cm_base + inst + reg);
 }
 
 /* Read a register in CM2 */
 u32 omap4_cm2_read_inst_reg(s16 inst, u16 reg)
 {
-	return __raw_readl(OMAP44XX_CM2_REGADDR(inst, reg));
+	return __raw_readl(cm2_base + inst + reg);
 }
 
 /* Write into a register in CM2 */
 void omap4_cm2_write_inst_reg(u32 val, s16 inst, u16 reg)
 {
-	__raw_writel(val, OMAP44XX_CM2_REGADDR(inst, reg));
+	__raw_writel(val, cm2_base + inst + reg);
 }
-- 
1.7.9.5

Re: [PATCH 01/55] ARM: OMAP4: CM: use cm_base* in register address calculations

[Felipe Balbi]

[-- Attachment #1: Type: text/plain, Size: 824 bytes --]

On Mon, Mar 31, 2014 at 06:15:40PM +0300, Tero Kristo wrote:
> OMAP44XX_CM*_REGADDR macros should be avoided, instead use the cm_base*
> iomaps.
> 
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> ---
>  arch/arm/mach-omap2/cm44xx.c |    8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/cm44xx.c b/arch/arm/mach-omap2/cm44xx.c
> index 535d66e..5627072 100644
> --- a/arch/arm/mach-omap2/cm44xx.c
> +++ b/arch/arm/mach-omap2/cm44xx.c
> @@ -30,23 +30,23 @@
>  /* Read a register in CM1 */
>  u32 omap4_cm1_read_inst_reg(s16 inst, u16 reg)
>  {
> -	return __raw_readl(OMAP44XX_CM1_REGADDR(inst, reg));
> +	return __raw_readl(cm_base + inst + reg);

should you use readl() or readl_relaxed() instead ? It'll take care of
endianness, right ?

-- 
balbi

[-- Attachment #2: Digital signature --]
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[PATCH 02/55] ARM: OMAP2+: PRCM: cleanup some header includes

[Tero Kristo]

Some of the includes are totally unnecessary, remove some others in
preparation to make the PRCM its own driver.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/clockdomain.h                  |    3 ++-
 arch/arm/mach-omap2/cm33xx.h                       |    3 ---
 arch/arm/mach-omap2/cm44xx.c                       |    2 --
 arch/arm/mach-omap2/cm_common.c                    |    1 -
 arch/arm/mach-omap2/cminst44xx.c                   |    2 --
 .../mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c |    1 +
 arch/arm/mach-omap2/powerdomain.c                  |    1 +
 arch/arm/mach-omap2/powerdomain.h                  |    3 +--
 arch/arm/mach-omap2/prcm-common.h                  |    2 ++
 arch/arm/mach-omap2/prcm_mpu44xx.h                 |    1 -
 arch/arm/mach-omap2/prm2xxx_3xxx.c                 |    1 -
 arch/arm/mach-omap2/prm33xx.c                      |    1 -
 12 files changed, 7 insertions(+), 14 deletions(-)

diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
index f17f006..82c37b1 100644
--- a/arch/arm/mach-omap2/clockdomain.h
+++ b/arch/arm/mach-omap2/clockdomain.h
@@ -18,7 +18,6 @@
 
 #include "powerdomain.h"
 #include "clock.h"
-#include "omap_hwmod.h"
 
 /*
  * Clockdomain flags
@@ -98,6 +97,8 @@ struct clkdm_dep {
 /* Possible flags for struct clockdomain._flags */
 #define _CLKDM_FLAG_HWSUP_ENABLED		BIT(0)
 
+struct omap_hwmod;
+
 /**
  * struct clockdomain - OMAP clockdomain
  * @name: clockdomain name
diff --git a/arch/arm/mach-omap2/cm33xx.h b/arch/arm/mach-omap2/cm33xx.h
index cfb8891..15a778c 100644
--- a/arch/arm/mach-omap2/cm33xx.h
+++ b/arch/arm/mach-omap2/cm33xx.h
@@ -17,11 +17,8 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_CM_33XX_H
 #define __ARCH_ARM_MACH_OMAP2_CM_33XX_H
 
-#include "common.h"
-
 #include "cm.h"
 #include "cm-regbits-33xx.h"
-#include "iomap.h"
 
 /* CM base address */
 #define AM33XX_CM_BASE		0x44e00000
diff --git a/arch/arm/mach-omap2/cm44xx.c b/arch/arm/mach-omap2/cm44xx.c
index 5627072..37ba6e8 100644
--- a/arch/arm/mach-omap2/cm44xx.c
+++ b/arch/arm/mach-omap2/cm44xx.c
@@ -18,8 +18,6 @@
 #include <linux/err.h>
 #include <linux/io.h>
 
-#include "iomap.h"
-#include "common.h"
 #include "cm.h"
 #include "cm1_44xx.h"
 #include "cm2_44xx.h"
diff --git a/arch/arm/mach-omap2/cm_common.c b/arch/arm/mach-omap2/cm_common.c
index 40b3b5a..9e2482a 100644
--- a/arch/arm/mach-omap2/cm_common.c
+++ b/arch/arm/mach-omap2/cm_common.c
@@ -18,7 +18,6 @@
 #include "cm2xxx.h"
 #include "cm3xxx.h"
 #include "cm44xx.h"
-#include "common.h"
 
 /*
  * cm_ll_data: function pointers to SoC-specific implementations of
diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c
index 731ca13..d27d2bd 100644
--- a/arch/arm/mach-omap2/cminst44xx.c
+++ b/arch/arm/mach-omap2/cminst44xx.c
@@ -21,8 +21,6 @@
 #include <linux/err.h>
 #include <linux/io.h>
 
-#include "iomap.h"
-#include "common.h"
 #include "clockdomain.h"
 #include "cm.h"
 #include "cm1_44xx.h"
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c
index 0f17862..a579b89 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c
@@ -24,6 +24,7 @@
 #include "prm33xx.h"
 #include "omap_hwmod_33xx_43xx_common_data.h"
 #include "prcm43xx.h"
+#include "common.h"
 
 #define CLKCTRL(oh, clkctrl) ((oh).prcm.omap4.clkctrl_offs = (clkctrl))
 #define RSTCTRL(oh, rstctrl) ((oh).prcm.omap4.rstctrl_offs = (rstctrl))
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 93a2a6e..faebd5f 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -32,6 +32,7 @@
 
 #include "powerdomain.h"
 #include "clockdomain.h"
+#include "voltage.h"
 
 #include "soc.h"
 #include "pm.h"
diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
index da5a59a..f472711 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -21,8 +21,6 @@
 #include <linux/list.h>
 #include <linux/spinlock.h>
 
-#include "voltage.h"
-
 /* Powerdomain basic power states */
 #define PWRDM_POWER_OFF		0x0
 #define PWRDM_POWER_RET		0x1
@@ -75,6 +73,7 @@
 
 struct clockdomain;
 struct powerdomain;
+struct voltagedomain;
 
 /**
  * struct powerdomain - OMAP powerdomain
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index e982598..ee2384a 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -428,6 +428,8 @@
 #define MAX_IOPAD_LATCH_TIME			100
 # ifndef __ASSEMBLER__
 
+#include <linux/delay.h>
+
 /**
  * omap_test_timeout - busy-loop, testing a condition
  * @cond: condition to test until it evaluates to true
diff --git a/arch/arm/mach-omap2/prcm_mpu44xx.h b/arch/arm/mach-omap2/prcm_mpu44xx.h
index 059bd4f..ac9cb45 100644
--- a/arch/arm/mach-omap2/prcm_mpu44xx.h
+++ b/arch/arm/mach-omap2/prcm_mpu44xx.h
@@ -26,7 +26,6 @@
 #define __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H
 
 #include "prcm_mpu_44xx_54xx.h"
-#include "common.h"
 
 #define OMAP4430_PRCM_MPU_BASE			0x48243000
 
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c
index 5209823..d891499 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c
@@ -16,7 +16,6 @@
 #include <linux/err.h>
 #include <linux/io.h>
 
-#include "common.h"
 #include "powerdomain.h"
 #include "prm2xxx_3xxx_private.h"
 #include "prm-regbits-24xx.h"
diff --git a/arch/arm/mach-omap2/prm33xx.c b/arch/arm/mach-omap2/prm33xx.c
index 7204407..0660105 100644
--- a/arch/arm/mach-omap2/prm33xx.c
+++ b/arch/arm/mach-omap2/prm33xx.c
@@ -19,7 +19,6 @@
 #include <linux/err.h>
 #include <linux/io.h>
 
-#include "common.h"
 #include "powerdomain.h"
 #include "prm33xx.h"
 #include "prm-regbits-33xx.h"
-- 
1.7.9.5

[PATCH 03/55] ARM: OMAP2+: PRM: remove unnecessary cpu_is_XXX calls from prm_init / exit

[Tero Kristo]

Done in preparation to make PRM its own driver, as the cpu_is_XXX calls are
not available outside mach-omap2 folder.

The init functions are called only from cpu specific init chain, and thus
don't need to double check against cpu type.

The exit calls check against the data provided during init-time registration
and thus don't need cpu check either.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/prm2xxx.c |   13 +------------
 arch/arm/mach-omap2/prm3xxx.c |   10 +---------
 arch/arm/mach-omap2/prm44xx.c |   10 +---------
 3 files changed, 3 insertions(+), 30 deletions(-)

diff --git a/arch/arm/mach-omap2/prm2xxx.c b/arch/arm/mach-omap2/prm2xxx.c
index 45f83dd..a7f1cac 100644
--- a/arch/arm/mach-omap2/prm2xxx.c
+++ b/arch/arm/mach-omap2/prm2xxx.c
@@ -18,9 +18,6 @@
 #include <linux/io.h>
 #include <linux/irq.h>
 
-#include "soc.h"
-#include "common.h"
-#include "vp.h"
 #include "powerdomain.h"
 #include "clockdomain.h"
 #include "prm2xxx_3xxx_private.h"
@@ -261,19 +258,11 @@ static struct prm_ll_data omap2xxx_prm_ll_data = {
 
 int __init omap2xxx_prm_init(void)
 {
-	if (!cpu_is_omap24xx())
-		return 0;
-
 	return prm_register(&omap2xxx_prm_ll_data);
 }
 
 static void __exit omap2xxx_prm_exit(void)
 {
-	if (!cpu_is_omap24xx())
-		return;
-
-	/* Should never happen */
-	WARN(prm_unregister(&omap2xxx_prm_ll_data),
-	     "%s: prm_ll_data function pointer mismatch\n", __func__);
+	prm_unregister(&omap2xxx_prm_ll_data);
 }
 __exitcall(omap2xxx_prm_exit);
diff --git a/arch/arm/mach-omap2/prm3xxx.c b/arch/arm/mach-omap2/prm3xxx.c
index 6d3e9c2..1a39954 100644
--- a/arch/arm/mach-omap2/prm3xxx.c
+++ b/arch/arm/mach-omap2/prm3xxx.c
@@ -639,9 +639,6 @@ static struct prm_ll_data omap3xxx_prm_ll_data = {
 
 int __init omap3xxx_prm_init(void)
 {
-	if (!cpu_is_omap34xx())
-		return 0;
-
 	return prm_register(&omap3xxx_prm_ll_data);
 }
 
@@ -664,11 +661,6 @@ omap_subsys_initcall(omap3xxx_prm_late_init);
 
 static void __exit omap3xxx_prm_exit(void)
 {
-	if (!cpu_is_omap34xx())
-		return;
-
-	/* Should never happen */
-	WARN(prm_unregister(&omap3xxx_prm_ll_data),
-	     "%s: prm_ll_data function pointer mismatch\n", __func__);
+	prm_unregister(&omap3xxx_prm_ll_data);
 }
 __exitcall(omap3xxx_prm_exit);
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index 3655e16..be96881 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -660,9 +660,6 @@ static struct prm_ll_data omap44xx_prm_ll_data = {
 
 int __init omap44xx_prm_init(void)
 {
-	if (!cpu_is_omap44xx() && !soc_is_omap54xx() && !soc_is_dra7xx())
-		return 0;
-
 	return prm_register(&omap44xx_prm_ll_data);
 }
 
@@ -679,11 +676,6 @@ omap_subsys_initcall(omap44xx_prm_late_init);
 
 static void __exit omap44xx_prm_exit(void)
 {
-	if (!cpu_is_omap44xx())
-		return;
-
-	/* Should never happen */
-	WARN(prm_unregister(&omap44xx_prm_ll_data),
-	     "%s: prm_ll_data function pointer mismatch\n", __func__);
+	prm_unregister(&omap44xx_prm_ll_data);
 }
 __exitcall(omap44xx_prm_exit);
-- 
1.7.9.5

[PATCH 04/55] ARM: OMAP3/4: PRM: provide io chain reconfig function through irq setup

[Tero Kristo]

This helps to make the PRM registration modular, and also gets rid of a
cpu type check done later.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/prcm-common.h |    2 ++
 arch/arm/mach-omap2/prm3xxx.c     |    1 +
 arch/arm/mach-omap2/prm44xx.c     |    1 +
 arch/arm/mach-omap2/prm_common.c  |    7 +------
 4 files changed, 5 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index ee2384a..a8e4b58 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -480,6 +480,7 @@ struct omap_prcm_irq {
  * @ocp_barrier: fn ptr to force buffered PRM writes to complete
  * @save_and_clear_irqen: fn ptr to save and clear IRQENABLE regs
  * @restore_irqen: fn ptr to save and clear IRQENABLE regs
+ * @reconfigure_io_chain: fn ptr to reconfigure IO chain
  * @saved_mask: IRQENABLE regs are saved here during suspend
  * @priority_mask: 1 bit per IRQ, set to 1 if omap_prcm_irq.priority = true
  * @base_irq: base dynamic IRQ number, returned from irq_alloc_descs() in init
@@ -501,6 +502,7 @@ struct omap_prcm_irq_setup {
 	void (*ocp_barrier)(void);
 	void (*save_and_clear_irqen)(u32 *saved_mask);
 	void (*restore_irqen)(u32 *saved_mask);
+	void (*reconfigure_io_chain)(void);
 	u32 *saved_mask;
 	u32 *priority_mask;
 	int base_irq;
diff --git a/arch/arm/mach-omap2/prm3xxx.c b/arch/arm/mach-omap2/prm3xxx.c
index 1a39954..dab93f4 100644
--- a/arch/arm/mach-omap2/prm3xxx.c
+++ b/arch/arm/mach-omap2/prm3xxx.c
@@ -45,6 +45,7 @@ static struct omap_prcm_irq_setup omap3_prcm_irq_setup = {
 	.ocp_barrier		= &omap3xxx_prm_ocp_barrier,
 	.save_and_clear_irqen	= &omap3xxx_prm_save_and_clear_irqen,
 	.restore_irqen		= &omap3xxx_prm_restore_irqen,
+	.reconfigure_io_chain	= &omap3xxx_prm_reconfigure_io_chain,
 };
 
 /*
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index be96881..10834cb 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -47,6 +47,7 @@ static struct omap_prcm_irq_setup omap4_prcm_irq_setup = {
 	.ocp_barrier		= &omap44xx_prm_ocp_barrier,
 	.save_and_clear_irqen	= &omap44xx_prm_save_and_clear_irqen,
 	.restore_irqen		= &omap44xx_prm_restore_irqen,
+	.reconfigure_io_chain	= &omap44xx_prm_reconfigure_io_chain,
 };
 
 /*
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index 878ae9f..b3c593b 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -330,12 +330,7 @@ int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup)
 
 	if (of_have_populated_dt()) {
 		int irq = omap_prcm_event_to_irq("io");
-		if (cpu_is_omap34xx())
-			omap_pcs_legacy_init(irq,
-				omap3xxx_prm_reconfigure_io_chain);
-		else
-			omap_pcs_legacy_init(irq,
-				omap44xx_prm_reconfigure_io_chain);
+		omap_pcs_legacy_init(irq, irq_setup->reconfigure_io_chain);
 	}
 
 	return 0;
-- 
1.7.9.5

[PATCH 05/55] ARM: OMAP3/OMAP4: PRM: add prm_features flags and add IO wakeup under it

[Tero Kristo]

prm_features flag will contain SoC specific feature enabler flags. Initially
IO wakeup is added under this. Helps to get rid of runtime cpu_is_X checks.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/prm.h        |    8 ++++++++
 arch/arm/mach-omap2/prm3xxx.c    |    8 +++++++-
 arch/arm/mach-omap2/prm44xx.c    |    6 ++++++
 arch/arm/mach-omap2/prm_common.c |    2 ++
 4 files changed, 23 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index 623db40..04426c4 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -17,10 +17,18 @@
 
 # ifndef __ASSEMBLER__
 extern void __iomem *prm_base;
+extern u16 prm_features;
 extern void omap2_set_globals_prm(void __iomem *prm);
 int of_prcm_init(void);
 # endif
 
+/*
+ * prm_features flag values
+ *
+ * PRM_HAS_IO_WAKEUP: has IO wakeup capability
+ * PRM_HAS_VOLTAGE: has voltage domains
+ */
+#define PRM_HAS_IO_WAKEUP	(1 << 0)
 
 /*
  * MAX_MODULE_SOFTRESET_WAIT: Maximum microseconds to wait for OMAP
diff --git a/arch/arm/mach-omap2/prm3xxx.c b/arch/arm/mach-omap2/prm3xxx.c
index dab93f4..fcbe854 100644
--- a/arch/arm/mach-omap2/prm3xxx.c
+++ b/arch/arm/mach-omap2/prm3xxx.c
@@ -410,7 +410,7 @@ void omap3xxx_prm_reconfigure_io_chain(void)
  */
 static void __init omap3xxx_prm_enable_io_wakeup(void)
 {
-	if (omap3_has_io_wakeup())
+	if (prm_features & PRM_HAS_IO_WAKEUP)
 		omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
 					   PM_WKEN);
 }
@@ -640,6 +640,9 @@ static struct prm_ll_data omap3xxx_prm_ll_data = {
 
 int __init omap3xxx_prm_init(void)
 {
+	if (omap3_has_io_wakeup())
+		prm_features |= PRM_HAS_IO_WAKEUP;
+
 	return prm_register(&omap3xxx_prm_ll_data);
 }
 
@@ -650,6 +653,9 @@ static int __init omap3xxx_prm_late_init(void)
 	if (!cpu_is_omap34xx())
 		return 0;
 
+	if (!(prm_features & PRM_HAS_IO_WAKEUP))
+		return 0;
+
 	omap3xxx_prm_enable_io_wakeup();
 	ret = omap_prcm_register_chain_handler(&omap3_prcm_irq_setup);
 	if (!ret)
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index 10834cb..dc357df 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -661,6 +661,9 @@ static struct prm_ll_data omap44xx_prm_ll_data = {
 
 int __init omap44xx_prm_init(void)
 {
+	if (cpu_is_omap44xx())
+		prm_features |= PRM_HAS_IO_WAKEUP;
+
 	return prm_register(&omap44xx_prm_ll_data);
 }
 
@@ -669,6 +672,9 @@ static int __init omap44xx_prm_late_init(void)
 	if (!cpu_is_omap44xx())
 		return 0;
 
+	if (!(prm_features & PRM_HAS_IO_WAKEUP))
+		return 0;
+
 	omap44xx_prm_enable_io_wakeup();
 
 	return omap_prcm_register_chain_handler(&omap4_prcm_irq_setup);
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index b3c593b..f98c01a 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -62,6 +62,8 @@ static struct omap_prcm_irq_setup *prcm_irq_setup;
 /* prm_base: base virtual address of the PRM IP block */
 void __iomem *prm_base;
 
+u16 prm_features;
+
 /*
  * prm_ll_data: function pointers to SoC-specific implementations of
  * common PRM functions
-- 
1.7.9.5

[PATCH 06/55] ARM: OMAP3/4: PRM: add support of late_init call to prm_ll_ops

[Tero Kristo]

SoC specific late_init call is now registered during PRM init, and will
be called automatically by PRM core. This helps to get rid of some
redundant initcalls and cpu_is_X checks from the PRM code.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/prm.h        |    2 ++
 arch/arm/mach-omap2/prm3xxx.c    |    7 +++----
 arch/arm/mach-omap2/prm44xx.c    |    7 +++----
 arch/arm/mach-omap2/prm_common.c |    8 ++++++++
 4 files changed, 16 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index 04426c4..48480d5 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -126,6 +126,7 @@ struct prm_reset_src_map {
  * @read_reset_sources: ptr to the SoC PRM-specific get_reset_source impl
  * @was_any_context_lost_old: ptr to the SoC PRM context loss test fn
  * @clear_context_loss_flags_old: ptr to the SoC PRM context loss flag clear fn
+ * @late_init: ptr to the late init function
  *
  * XXX @was_any_context_lost_old and @clear_context_loss_flags_old are
  * deprecated.
@@ -134,6 +135,7 @@ struct prm_ll_data {
 	u32 (*read_reset_sources)(void);
 	bool (*was_any_context_lost_old)(u8 part, s16 inst, u16 idx);
 	void (*clear_context_loss_flags_old)(u8 part, s16 inst, u16 idx);
+	int (*late_init)(void);
 };
 
 extern int prm_register(struct prm_ll_data *pld);
diff --git a/arch/arm/mach-omap2/prm3xxx.c b/arch/arm/mach-omap2/prm3xxx.c
index fcbe854..f92de79 100644
--- a/arch/arm/mach-omap2/prm3xxx.c
+++ b/arch/arm/mach-omap2/prm3xxx.c
@@ -634,8 +634,11 @@ struct pwrdm_ops omap3_pwrdm_operations = {
  *
  */
 
+static int omap3xxx_prm_late_init(void);
+
 static struct prm_ll_data omap3xxx_prm_ll_data = {
 	.read_reset_sources = &omap3xxx_prm_read_reset_sources,
+	.late_init = &omap3xxx_prm_late_init,
 };
 
 int __init omap3xxx_prm_init(void)
@@ -650,9 +653,6 @@ static int __init omap3xxx_prm_late_init(void)
 {
 	int ret;
 
-	if (!cpu_is_omap34xx())
-		return 0;
-
 	if (!(prm_features & PRM_HAS_IO_WAKEUP))
 		return 0;
 
@@ -664,7 +664,6 @@ static int __init omap3xxx_prm_late_init(void)
 
 	return ret;
 }
-omap_subsys_initcall(omap3xxx_prm_late_init);
 
 static void __exit omap3xxx_prm_exit(void)
 {
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index dc357df..60b9b05 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -650,6 +650,8 @@ struct pwrdm_ops omap4_pwrdm_operations = {
 	.pwrdm_has_voltdm	= omap4_check_vcvp,
 };
 
+static int omap44xx_prm_late_init(void);
+
 /*
  * XXX document
  */
@@ -657,6 +659,7 @@ static struct prm_ll_data omap44xx_prm_ll_data = {
 	.read_reset_sources = &omap44xx_prm_read_reset_sources,
 	.was_any_context_lost_old = &omap44xx_prm_was_any_context_lost_old,
 	.clear_context_loss_flags_old = &omap44xx_prm_clear_context_loss_flags_old,
+	.late_init = &omap44xx_prm_late_init,
 };
 
 int __init omap44xx_prm_init(void)
@@ -669,9 +672,6 @@ int __init omap44xx_prm_init(void)
 
 static int __init omap44xx_prm_late_init(void)
 {
-	if (!cpu_is_omap44xx())
-		return 0;
-
 	if (!(prm_features & PRM_HAS_IO_WAKEUP))
 		return 0;
 
@@ -679,7 +679,6 @@ static int __init omap44xx_prm_late_init(void)
 
 	return omap_prcm_register_chain_handler(&omap4_prcm_irq_setup);
 }
-omap_subsys_initcall(omap44xx_prm_late_init);
 
 static void __exit omap44xx_prm_exit(void)
 {
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index f98c01a..76ca320 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -529,3 +529,11 @@ int __init of_prcm_init(void)
 
 	return 0;
 }
+
+static int __init prm_late_init(void)
+{
+	if (prm_ll_data->late_init)
+		return prm_ll_data->late_init();
+	return 0;
+}
+subsys_initcall(prm_late_init);
-- 
1.7.9.5

[PATCH 07/55] ARM: OMAP3+: PRM: add cpu-type as parameter to prm_init calls

[Tero Kristo]

This helps to get rid of cpu_is_X checks from within the PRM driver.
Done in preparation to make PRM a separate driver.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/io.c           |   17 +++++++++++++----
 arch/arm/mach-omap2/prm.h          |   11 +++++++++++
 arch/arm/mach-omap2/prm3xxx.c      |    4 ++--
 arch/arm/mach-omap2/prm3xxx.h      |    2 +-
 arch/arm/mach-omap2/prm44xx.c      |    4 ++--
 arch/arm/mach-omap2/prm44xx_54xx.h |    2 +-
 6 files changed, 30 insertions(+), 10 deletions(-)

diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 5b19efd..251432f 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -458,6 +458,15 @@ void __init omap2430_init_late(void)
  * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT.
  */
 #ifdef CONFIG_ARCH_OMAP3
+static inline u16 omap3_prm_type(void)
+{
+	if (cpu_is_omap3430())
+		return PRM_OMAP3430;
+	if (cpu_is_omap3630())
+		return PRM_OMAP3630;
+	return PRM_OMAP3_OTHER;
+}
+
 void __init omap3_init_early(void)
 {
 	omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000));
@@ -469,7 +478,7 @@ void __init omap3_init_early(void)
 	omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE), NULL);
 	omap3xxx_check_revision();
 	omap3xxx_check_features();
-	omap3xxx_prm_init();
+	omap3xxx_prm_init(omap3_prm_type());
 	omap3xxx_cm_init();
 	omap3xxx_voltagedomains_init();
 	omap3xxx_powerdomains_init();
@@ -636,7 +645,7 @@ void __init omap4430_init_early(void)
 	omap4xxx_check_revision();
 	omap4xxx_check_features();
 	omap4_pm_init_early();
-	omap44xx_prm_init();
+	omap44xx_prm_init(PRM_OMAP4);
 	omap44xx_voltagedomains_init();
 	omap44xx_powerdomains_init();
 	omap44xx_clockdomains_init();
@@ -666,7 +675,7 @@ void __init omap5_init_early(void)
 	omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
 	omap_prm_base_init();
 	omap_cm_base_init();
-	omap44xx_prm_init();
+	omap44xx_prm_init(PRM_OMAP5);
 	omap5xxx_check_revision();
 	omap54xx_voltagedomains_init();
 	omap54xx_powerdomains_init();
@@ -694,7 +703,7 @@ void __init dra7xx_init_early(void)
 	omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
 	omap_prm_base_init();
 	omap_cm_base_init();
-	omap44xx_prm_init();
+	omap44xx_prm_init(PRM_DRA7);
 	dra7xx_powerdomains_init();
 	dra7xx_clockdomains_init();
 	dra7xx_hwmod_init();
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index 48480d5..fd5123e 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -30,6 +30,17 @@ int of_prcm_init(void);
  */
 #define PRM_HAS_IO_WAKEUP	(1 << 0)
 
+#ifndef __ASSEMBLER__
+enum {
+	PRM_OMAP3430 = 0,
+	PRM_OMAP3630,
+	PRM_OMAP3_OTHER,
+	PRM_OMAP4,
+	PRM_OMAP5,
+	PRM_DRA7,
+};
+#endif
+
 /*
  * MAX_MODULE_SOFTRESET_WAIT: Maximum microseconds to wait for OMAP
  * module to softreset
diff --git a/arch/arm/mach-omap2/prm3xxx.c b/arch/arm/mach-omap2/prm3xxx.c
index f92de79..9915cd6 100644
--- a/arch/arm/mach-omap2/prm3xxx.c
+++ b/arch/arm/mach-omap2/prm3xxx.c
@@ -641,9 +641,9 @@ static struct prm_ll_data omap3xxx_prm_ll_data = {
 	.late_init = &omap3xxx_prm_late_init,
 };
 
-int __init omap3xxx_prm_init(void)
+int __init omap3xxx_prm_init(u16 cpu_type)
 {
-	if (omap3_has_io_wakeup())
+	if (cpu_type == PRM_OMAP3430 || cpu_type == PRM_OMAP3630)
 		prm_features |= PRM_HAS_IO_WAKEUP;
 
 	return prm_register(&omap3xxx_prm_ll_data);
diff --git a/arch/arm/mach-omap2/prm3xxx.h b/arch/arm/mach-omap2/prm3xxx.h
index 7120af9..0e759bc 100644
--- a/arch/arm/mach-omap2/prm3xxx.h
+++ b/arch/arm/mach-omap2/prm3xxx.h
@@ -160,7 +160,7 @@ extern void omap3xxx_prm_restore_irqen(u32 *saved_mask);
 
 extern void omap3xxx_prm_dpll3_reset(void);
 
-extern int __init omap3xxx_prm_init(void);
+int __init omap3xxx_prm_init(u16 cpu_type);
 extern u32 omap3xxx_prm_get_reset_sources(void);
 int omap3xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits);
 void omap3xxx_prm_iva_idle(void);
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index 60b9b05..18fae1dd 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -662,9 +662,9 @@ static struct prm_ll_data omap44xx_prm_ll_data = {
 	.late_init = &omap44xx_prm_late_init,
 };
 
-int __init omap44xx_prm_init(void)
+int __init omap44xx_prm_init(u16 cpu_type)
 {
-	if (cpu_is_omap44xx())
+	if (cpu_type == PRM_OMAP4)
 		prm_features |= PRM_HAS_IO_WAKEUP;
 
 	return prm_register(&omap44xx_prm_ll_data);
diff --git a/arch/arm/mach-omap2/prm44xx_54xx.h b/arch/arm/mach-omap2/prm44xx_54xx.h
index 8d95aa5..73734b2 100644
--- a/arch/arm/mach-omap2/prm44xx_54xx.h
+++ b/arch/arm/mach-omap2/prm44xx_54xx.h
@@ -57,7 +57,7 @@ extern void omap44xx_prm_ocp_barrier(void);
 extern void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask);
 extern void omap44xx_prm_restore_irqen(u32 *saved_mask);
 
-extern int __init omap44xx_prm_init(void);
+int __init omap44xx_prm_init(u16 cpu_type);
 extern u32 omap44xx_prm_get_reset_sources(void);
 
 #endif
-- 
1.7.9.5

Re: [PATCH 07/55] ARM: OMAP3+: PRM: add cpu-type as parameter to prm_init calls

[Felipe Balbi]

[-- Attachment #1: Type: text/plain, Size: 607 bytes --]

Hi,

On Mon, Mar 31, 2014 at 06:15:46PM +0300, Tero Kristo wrote:
> diff --git a/arch/arm/mach-omap2/prm44xx_54xx.h b/arch/arm/mach-omap2/prm44xx_54xx.h
> index 8d95aa5..73734b2 100644
> --- a/arch/arm/mach-omap2/prm44xx_54xx.h
> +++ b/arch/arm/mach-omap2/prm44xx_54xx.h
> @@ -57,7 +57,7 @@ extern void omap44xx_prm_ocp_barrier(void);
>  extern void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask);
>  extern void omap44xx_prm_restore_irqen(u32 *saved_mask);
>  
> -extern int __init omap44xx_prm_init(void);
> +int __init omap44xx_prm_init(u16 cpu_type);

trailing change ?

-- 
balbi

[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 819 bytes --]

[PATCH 08/55] ARM: DRA7: PRM: add voltage processor check behind a prm_feature flag

[Tero Kristo]

This is done in attempt to get rid of cpu_is_X calls from the PRM core.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/prm.h     |    1 +
 arch/arm/mach-omap2/prm44xx.c |    4 +++-
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index fd5123e..8d40a5d 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -29,6 +29,7 @@ int of_prcm_init(void);
  * PRM_HAS_VOLTAGE: has voltage domains
  */
 #define PRM_HAS_IO_WAKEUP	(1 << 0)
+#define PRM_HAS_VOLTAGE		(1 << 1)
 
 #ifndef __ASSEMBLER__
 enum {
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index 18fae1dd..fb05abc 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -624,7 +624,7 @@ static int omap4_pwrdm_wait_transition(struct powerdomain *pwrdm)
 static int omap4_check_vcvp(void)
 {
 	/* No VC/VP on dra7xx devices */
-	if (soc_is_dra7xx())
+	if (!(prm_features & PRM_HAS_VOLTAGE))
 		return 0;
 
 	return 1;
@@ -664,6 +664,8 @@ static struct prm_ll_data omap44xx_prm_ll_data = {
 
 int __init omap44xx_prm_init(u16 cpu_type)
 {
+	if (cpu_type != PRM_DRA7)
+		prm_features |= PRM_HAS_VOLTAGE;
 	if (cpu_type == PRM_OMAP4)
 		prm_features |= PRM_HAS_IO_WAKEUP;
 
-- 
1.7.9.5

[PATCH 09/55] ARM: OMAP4+: PRM: add prm_dev_inst offset as a global parameter

[Tero Kristo]

This is different for OMAP4, OMAP5 and DRA7, and is currently checked
runtime with a cpu_is_X check. Replace this with an init time setting.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/prm.h         |    1 +
 arch/arm/mach-omap2/prm44xx.c     |   20 +++++++++++++++++---
 arch/arm/mach-omap2/prm_common.c  |    1 +
 arch/arm/mach-omap2/prminst44xx.c |   22 ++++++----------------
 4 files changed, 25 insertions(+), 19 deletions(-)

diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index 8d40a5d..8caa7af 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -17,6 +17,7 @@
 
 # ifndef __ASSEMBLER__
 extern void __iomem *prm_base;
+extern u16 prm_dev_inst;
 extern u16 prm_features;
 extern void omap2_set_globals_prm(void __iomem *prm);
 int of_prcm_init(void);
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index fb05abc..206dcd9 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -24,6 +24,8 @@
 #include "common.h"
 #include "vp.h"
 #include "prm44xx.h"
+#include "prm54xx.h"
+#include "prm7xx.h"
 #include "prm-regbits-44xx.h"
 #include "prcm44xx.h"
 #include "prminst44xx_private.h"
@@ -664,10 +666,22 @@ static struct prm_ll_data omap44xx_prm_ll_data = {
 
 int __init omap44xx_prm_init(u16 cpu_type)
 {
-	if (cpu_type != PRM_DRA7)
+	switch (cpu_type) {
+	case PRM_OMAP4:
+		prm_features |= PRM_HAS_IO_WAKEUP | PRM_HAS_VOLTAGE;
+		prm_dev_inst = OMAP4430_PRM_DEVICE_INST;
+		break;
+	case PRM_OMAP5:
 		prm_features |= PRM_HAS_VOLTAGE;
-	if (cpu_type == PRM_OMAP4)
-		prm_features |= PRM_HAS_IO_WAKEUP;
+		prm_dev_inst = OMAP54XX_PRM_DEVICE_INST;
+		break;
+	case PRM_DRA7:
+		prm_dev_inst = DRA7XX_PRM_DEVICE_INST;
+		break;
+	default:
+		pr_err("%s: unsupported cpu type: %d\n", __func__, cpu_type);
+		return -EINVAL;
+	}
 
 	return prm_register(&omap44xx_prm_ll_data);
 }
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index 76ca320..5d5d564 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -63,6 +63,7 @@ static struct omap_prcm_irq_setup *prcm_irq_setup;
 void __iomem *prm_base;
 
 u16 prm_features;
+u16 prm_dev_inst;
 
 /*
  * prm_ll_data: function pointers to SoC-specific implementations of
diff --git a/arch/arm/mach-omap2/prminst44xx.c b/arch/arm/mach-omap2/prminst44xx.c
index 00b69d1..d4a7919 100644
--- a/arch/arm/mach-omap2/prminst44xx.c
+++ b/arch/arm/mach-omap2/prminst44xx.c
@@ -168,28 +168,18 @@ int omap4_prminst_deassert_hardreset(u8 shift, u8 part, s16 inst,
 void omap4_prminst_global_warm_sw_reset(void)
 {
 	u32 v;
-	s16 dev_inst;
-
-	if (cpu_is_omap44xx())
-		dev_inst = OMAP4430_PRM_DEVICE_INST;
-	else if (soc_is_omap54xx())
-		dev_inst = OMAP54XX_PRM_DEVICE_INST;
-	else if (soc_is_dra7xx())
-		dev_inst = DRA7XX_PRM_DEVICE_INST;
-	else
-		return;
-
-	v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, dev_inst,
+
+	v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, prm_dev_inst,
 					OMAP4_PRM_RSTCTRL_OFFSET);
 	v |= OMAP4430_RST_GLOBAL_WARM_SW_MASK;
 	omap4_prminst_write_inst_reg(v, OMAP4430_PRM_PARTITION,
-				 OMAP4430_PRM_DEVICE_INST,
-				 OMAP4_PRM_RSTCTRL_OFFSET);
+				     prm_dev_inst,
+				     OMAP4_PRM_RSTCTRL_OFFSET);
 
 	/* OCP barrier */
 	v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
-				    OMAP4430_PRM_DEVICE_INST,
-				    OMAP4_PRM_RSTCTRL_OFFSET);
+					prm_dev_inst,
+					OMAP4_PRM_RSTCTRL_OFFSET);
 }
 
 void omap4_prminst_mpuss_clear_prev_logic_pwrst(void)
-- 
1.7.9.5

[PATCH 10/55] ARM: OMAP3+: PRM: get rid of some unnecessary header files

[Tero Kristo]

Done in preparation to make PRM a separate driver.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/prcm-common.h |    1 +
 arch/arm/mach-omap2/prm3xxx.c     |    4 +---
 arch/arm/mach-omap2/prm44xx.c     |    5 ++---
 arch/arm/mach-omap2/prm_common.c  |    2 --
 arch/arm/mach-omap2/prminst44xx.c |    3 ---
 5 files changed, 4 insertions(+), 11 deletions(-)

diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index a8e4b58..9da4c17 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -523,6 +523,7 @@ extern int omap_prcm_register_chain_handler(
 extern int omap_prcm_event_to_irq(const char *event);
 extern void omap_prcm_irq_prepare(void);
 extern void omap_prcm_irq_complete(void);
+void omap_pcs_legacy_init(int irq, void (*rearm)(void));
 
 # endif
 
diff --git a/arch/arm/mach-omap2/prm3xxx.c b/arch/arm/mach-omap2/prm3xxx.c
index 9915cd6..f1d3e15 100644
--- a/arch/arm/mach-omap2/prm3xxx.c
+++ b/arch/arm/mach-omap2/prm3xxx.c
@@ -18,8 +18,6 @@
 #include <linux/io.h>
 #include <linux/irq.h>
 
-#include "soc.h"
-#include "common.h"
 #include "vp.h"
 #include "powerdomain.h"
 #include "prm3xxx.h"
@@ -40,7 +38,7 @@ static struct omap_prcm_irq_setup omap3_prcm_irq_setup = {
 	.nr_regs		= 1,
 	.irqs			= omap3_prcm_irqs,
 	.nr_irqs		= ARRAY_SIZE(omap3_prcm_irqs),
-	.irq			= 11 + OMAP_INTC_START,
+	.irq			= 11 + NR_IRQS,
 	.read_pending_irqs	= &omap3xxx_prm_read_pending_irqs,
 	.ocp_barrier		= &omap3xxx_prm_ocp_barrier,
 	.save_and_clear_irqen	= &omap3xxx_prm_save_and_clear_irqen,
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index 206dcd9..27f4603 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -19,9 +19,6 @@
 #include <linux/io.h>
 
 
-#include "soc.h"
-#include "iomap.h"
-#include "common.h"
 #include "vp.h"
 #include "prm44xx.h"
 #include "prm54xx.h"
@@ -33,6 +30,8 @@
 
 /* Static data */
 
+#define OMAP44XX_IRQ_GIC_START	32
+
 static const struct omap_prcm_irq omap4_prcm_irqs[] = {
 	OMAP_PRCM_IRQ("wkup",   0,      0),
 	OMAP_PRCM_IRQ("io",     9,      1),
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index 5d5d564..b4ef9e4 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -28,12 +28,10 @@
 #include <linux/clk-provider.h>
 #include <linux/clk/ti.h>
 
-#include "soc.h"
 #include "prm2xxx_3xxx.h"
 #include "prm2xxx.h"
 #include "prm3xxx.h"
 #include "prm44xx.h"
-#include "common.h"
 #include "clock.h"
 
 /*
diff --git a/arch/arm/mach-omap2/prminst44xx.c b/arch/arm/mach-omap2/prminst44xx.c
index d4a7919..bd0e0da 100644
--- a/arch/arm/mach-omap2/prminst44xx.c
+++ b/arch/arm/mach-omap2/prminst44xx.c
@@ -16,8 +16,6 @@
 #include <linux/err.h>
 #include <linux/io.h>
 
-#include "iomap.h"
-#include "common.h"
 #include "prcm-common.h"
 #include "prm44xx.h"
 #include "prm54xx.h"
@@ -26,7 +24,6 @@
 #include "prm-regbits-44xx.h"
 #include "prcm44xx.h"
 #include "prcm_mpu44xx.h"
-#include "soc.h"
 
 static void __iomem *_prm_bases[OMAP4_MAX_PRCM_PARTITIONS];
 
-- 
1.7.9.5

[PATCH 11/55] CLK: TI: clockdomain: add support for retrying init

[Tero Kristo]

Retry init is needed if clockdomains are registered before the corresponding
clocks are ready. In this case, the clockdomain info is added to a list
which will be processed once the clockdomains for next PRCM module are
processed.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/prm_common.c |    3 +-
 drivers/clk/ti/clockdomain.c     |   77 ++++++++++++++++++++++++++++++++------
 include/linux/clk/ti.h           |    2 +-
 3 files changed, 68 insertions(+), 14 deletions(-)

diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index b4ef9e4..2d63196 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -521,11 +521,10 @@ int __init of_prcm_init(void)
 		mem = of_iomap(np, 0);
 		clk_memmaps[memmap_index] = mem;
 		ti_dt_clk_init_provider(np, memmap_index);
+		ti_dt_clockdomains_setup(np);
 		memmap_index++;
 	}
 
-	ti_dt_clockdomains_setup();
-
 	return 0;
 }
 
diff --git a/drivers/clk/ti/clockdomain.c b/drivers/clk/ti/clockdomain.c
index f1e0038..29fa543 100644
--- a/drivers/clk/ti/clockdomain.c
+++ b/drivers/clk/ti/clockdomain.c
@@ -24,26 +24,60 @@
 #undef pr_fmt
 #define pr_fmt(fmt) "%s: " fmt, __func__
 
-static void __init of_ti_clockdomain_setup(struct device_node *node)
+struct clkdm_init_item {
+	struct device_node *node;
+	int index;
+	struct list_head link;
+};
+
+static LIST_HEAD(retry_list);
+
+static int of_ti_init_clk_clkdm(struct device_node *node, int index)
 {
 	struct clk *clk;
 	struct clk_hw *clk_hw;
-	const char *clkdm_name = node->name;
+
+	clk = of_clk_get(node, index);
+
+	if (IS_ERR_OR_NULL(clk)) {
+		pr_debug("%s[%d] = %08x\n", node->name, index, (u32)clk);
+		return -EBUSY;
+	}
+
+	if (__clk_get_flags(clk) & CLK_IS_BASIC) {
+		pr_warn("can't setup clkdm for basic clk %s\n",
+			__clk_get_name(clk));
+		return -EINVAL;
+	}
+
+	clk_hw = __clk_get_hw(clk);
+	to_clk_hw_omap(clk_hw)->clkdm_name = node->name;
+	omap2_init_clk_clkdm(clk_hw);
+
+	return 0;
+}
+
+static void __init of_ti_clockdomain_setup(struct device_node *node)
+{
 	int i;
 	int num_clks;
+	struct clkdm_init_item *retry;
+	int ret;
 
 	num_clks = of_count_phandle_with_args(node, "clocks", "#clock-cells");
 
 	for (i = 0; i < num_clks; i++) {
-		clk = of_clk_get(node, i);
-		if (__clk_get_flags(clk) & CLK_IS_BASIC) {
-			pr_warn("can't setup clkdm for basic clk %s\n",
-				__clk_get_name(clk));
+		ret = of_ti_init_clk_clkdm(node, i);
+
+		if (ret == -EBUSY) {
+			retry = kzalloc(sizeof(*retry), GFP_KERNEL);
+			if (!retry)
+				return;
+			retry->node = node;
+			retry->index = i;
+			list_add(&retry->link, &retry_list);
 			continue;
 		}
-		clk_hw = __clk_get_hw(clk);
-		to_clk_hw_omap(clk_hw)->clkdm_name = clkdm_name;
-		omap2_init_clk_clkdm(clk_hw);
 	}
 }
 
@@ -61,10 +95,31 @@ static struct of_device_id ti_clkdm_match_table[] __initdata = {
  * called after rest of the DT clock init has completed and all
  * clock nodes have been registered.
  */
-void __init ti_dt_clockdomains_setup(void)
+void __init ti_dt_clockdomains_setup(struct device_node *node)
 {
 	struct device_node *np;
-	for_each_matching_node(np, ti_clkdm_match_table) {
+	struct device_node *clkdms;
+	struct clkdm_init_item *retry, *tmp;
+	int ret;
+
+	clkdms = of_get_child_by_name(node, "clockdomains");
+	if (!clkdms)
+		return;
+
+	list_for_each_entry_safe(retry, tmp, &retry_list, link) {
+		pr_debug("retry-init: %s [%d]\n", retry->node->name,
+			 retry->index);
+		ret = of_ti_init_clk_clkdm(retry->node, retry->index);
+		if (!ret) {
+			list_del(&retry->link);
+			kfree(retry);
+		}
+	}
+
+	for_each_child_of_node(clkdms, np) {
+		if (!of_match_node(ti_clkdm_match_table, np))
+			continue;
+
 		of_ti_clockdomain_setup(np);
 	}
 }
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 03decc2..86e8ae4 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -284,7 +284,7 @@ void omap2xxx_clkt_vps_init(void);
 void __iomem *ti_clk_get_reg_addr(struct device_node *node, int index);
 void ti_dt_clocks_register(struct ti_dt_clk *oclks);
 void ti_dt_clk_init_provider(struct device_node *np, int index);
-void ti_dt_clockdomains_setup(void);
+void ti_dt_clockdomains_setup(struct device_node *node);
 int ti_clk_retry_init(struct device_node *node, struct clk_hw *hw,
 		      ti_of_clk_init_cb_t func);
 int of_ti_clk_autoidle_setup(struct device_node *node);
-- 
1.7.9.5

[PATCH 12/55] ARM: PRCM: split PRCM module init to their own driver files

[Tero Kristo]

Previously this was done for all modules under prm_common.c.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/cm_common.c   |   18 +++++++++++++
 arch/arm/mach-omap2/control.c     |   15 +++++++++++
 arch/arm/mach-omap2/control.h     |    1 +
 arch/arm/mach-omap2/io.c          |    4 +++
 arch/arm/mach-omap2/prcm-common.h |    4 +++
 arch/arm/mach-omap2/prm_common.c  |   54 +++++++++++++++++++++----------------
 6 files changed, 73 insertions(+), 23 deletions(-)

diff --git a/arch/arm/mach-omap2/cm_common.c b/arch/arm/mach-omap2/cm_common.c
index 9e2482a..c334d38 100644
--- a/arch/arm/mach-omap2/cm_common.c
+++ b/arch/arm/mach-omap2/cm_common.c
@@ -14,6 +14,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/errno.h>
+#include <linux/of.h>
 
 #include "cm2xxx.h"
 #include "cm3xxx.h"
@@ -137,3 +138,20 @@ int cm_unregister(struct cm_ll_data *cld)
 
 	return 0;
 }
+
+static struct of_device_id omap_cm_dt_match_table[] = {
+	{ .compatible = "ti,omap3-cm" },
+	{ .compatible = "ti,omap4-cm1" },
+	{ .compatible = "ti,omap4-cm2" },
+	{ .compatible = "ti,omap5-cm-core-aon" },
+	{ .compatible = "ti,omap5-cm-core" },
+	{ .compatible = "ti,dra7-cm-core-aon" },
+	{ .compatible = "ti,dra7-cm-core" },
+	{ }
+};
+
+
+int __init of_cm_init(void)
+{
+	return of_prcm_module_init(omap_cm_dt_match_table);
+}
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index 5854b3c..90a7add 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -611,3 +611,18 @@ void __init omap3_ctrl_init(void)
 	omap3_ctrl_setup_d2d_padconf();
 }
 #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
+
+static struct of_device_id omap_scrm_dt_match_table[] = {
+	{ .compatible = "ti,am3-scrm" },
+	{ .compatible = "ti,am4-scrm" },
+	{ .compatible = "ti,omap2-scrm" },
+	{ .compatible = "ti,omap3-scrm" },
+	{ .compatible = "ti,omap4-scrm" },
+	{ .compatible = "ti,omap5-scrm" },
+	{ }
+};
+
+int __init of_scrm_init(void)
+{
+	return of_prcm_module_init(omap_scrm_dt_match_table);
+}
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index ccbd70c..8a5c025 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -428,6 +428,7 @@ extern void omap_ctrl_write_dsp_boot_mode(u8 bootmode);
 extern void omap3630_ctrl_disable_rta(void);
 extern int omap3_ctrl_save_padconf(void);
 void omap3_ctrl_init(void);
+int of_scrm_init(void);
 extern void omap2_set_globals_control(void __iomem *ctrl,
 				      void __iomem *ctrl_pad);
 #else
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 251432f..dfba898 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -736,6 +736,10 @@ int __init omap_clk_init(void)
 	if (!omap_clk_soc_init)
 		return 0;
 
+	ret = of_scrm_init();
+	if (ret)
+		return ret;
+
 	ret = of_prcm_init();
 	if (!ret)
 		ret = omap_clk_soc_init();
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index 9da4c17..f356532 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -517,6 +517,8 @@ struct omap_prcm_irq_setup {
 	.priority = _priority				\
 	}
 
+struct of_device_id;
+
 extern void omap_prcm_irq_cleanup(void);
 extern int omap_prcm_register_chain_handler(
 	struct omap_prcm_irq_setup *irq_setup);
@@ -524,6 +526,8 @@ extern int omap_prcm_event_to_irq(const char *event);
 extern void omap_prcm_irq_prepare(void);
 extern void omap_prcm_irq_complete(void);
 void omap_pcs_legacy_init(int irq, void (*rearm)(void));
+int of_prcm_module_init(struct of_device_id *match_table);
+int of_cm_init(void);
 
 # endif
 
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index 2d63196..080b3ed 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -466,27 +466,18 @@ int prm_unregister(struct prm_ll_data *pld)
 	return 0;
 }
 
-static struct of_device_id omap_prcm_dt_match_table[] = {
-	{ .compatible = "ti,am3-prcm" },
-	{ .compatible = "ti,am3-scrm" },
-	{ .compatible = "ti,am4-prcm" },
-	{ .compatible = "ti,am4-scrm" },
-	{ .compatible = "ti,omap2-prcm" },
-	{ .compatible = "ti,omap2-scrm" },
+static struct of_device_id omap_prm_dt_match_table[] = {
 	{ .compatible = "ti,omap3-prm" },
-	{ .compatible = "ti,omap3-cm" },
-	{ .compatible = "ti,omap3-scrm" },
-	{ .compatible = "ti,omap4-cm1" },
 	{ .compatible = "ti,omap4-prm" },
-	{ .compatible = "ti,omap4-cm2" },
-	{ .compatible = "ti,omap4-scrm" },
 	{ .compatible = "ti,omap5-prm" },
-	{ .compatible = "ti,omap5-cm-core-aon" },
-	{ .compatible = "ti,omap5-scrm" },
-	{ .compatible = "ti,omap5-cm-core" },
 	{ .compatible = "ti,dra7-prm" },
-	{ .compatible = "ti,dra7-cm-core-aon" },
-	{ .compatible = "ti,dra7-cm-core" },
+	{ }
+};
+
+static struct of_device_id omap_prcm_dt_match_table[] = {
+	{ .compatible = "ti,am3-prcm" },
+	{ .compatible = "ti,am4-prcm" },
+	{ .compatible = "ti,omap2-prcm" },
 	{ }
 };
 
@@ -509,25 +500,42 @@ static struct ti_clk_ll_ops omap_clk_ll_ops = {
 	.clk_writel = prm_clk_writel,
 };
 
-int __init of_prcm_init(void)
+static int prcm_memmap_index;
+
+int __init of_prcm_module_init(struct of_device_id *match_table)
 {
 	struct device_node *np;
 	void __iomem *mem;
-	int memmap_index = 0;
 
 	ti_clk_ll_ops = &omap_clk_ll_ops;
 
-	for_each_matching_node(np, omap_prcm_dt_match_table) {
+	for_each_matching_node(np, match_table) {
 		mem = of_iomap(np, 0);
-		clk_memmaps[memmap_index] = mem;
-		ti_dt_clk_init_provider(np, memmap_index);
+		clk_memmaps[prcm_memmap_index] = mem;
+		ti_dt_clk_init_provider(np, prcm_memmap_index);
 		ti_dt_clockdomains_setup(np);
-		memmap_index++;
+		prcm_memmap_index++;
 	}
 
 	return 0;
 }
 
+int __init of_prm_init(void)
+{
+	return of_prcm_module_init(omap_prm_dt_match_table);
+}
+
+int __init of_prcm_init(void)
+{
+	int ret;
+
+	ret = of_prm_init();
+	ret |= of_cm_init();
+	ret |= of_prcm_module_init(omap_prcm_dt_match_table);
+
+	return ret;
+}
+
 static int __init prm_late_init(void)
 {
 	if (prm_ll_data->late_init)
-- 
1.7.9.5

[PATCH 13/55] ARM: OMAP4: PRCM: remove references to cm-regbits-44xx.h from PRCM core files

[Tero Kristo]

Done in preparation to make PRCM a standalone driver.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/cm44xx.c             |    1 -
 arch/arm/mach-omap2/cminst44xx.c         |    8 +++++++-
 arch/arm/mach-omap2/powerdomain-common.c |    1 -
 3 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-omap2/cm44xx.c b/arch/arm/mach-omap2/cm44xx.c
index 37ba6e8..c440ba7 100644
--- a/arch/arm/mach-omap2/cm44xx.c
+++ b/arch/arm/mach-omap2/cm44xx.c
@@ -21,7 +21,6 @@
 #include "cm.h"
 #include "cm1_44xx.h"
 #include "cm2_44xx.h"
-#include "cm-regbits-44xx.h"
 
 /* CM1 hardware module low-level functions */
 
diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c
index d27d2bd..c2712d3 100644
--- a/arch/arm/mach-omap2/cminst44xx.c
+++ b/arch/arm/mach-omap2/cminst44xx.c
@@ -28,12 +28,18 @@
 #include "cm44xx.h"
 #include "cminst44xx.h"
 #include "cm-regbits-34xx.h"
-#include "cm-regbits-44xx.h"
 #include "prcm44xx.h"
 #include "prm44xx.h"
 #include "prcm_mpu44xx.h"
 #include "prcm-common.h"
 
+#define OMAP4430_IDLEST_SHIFT		16
+#define OMAP4430_IDLEST_MASK		(0x3 << 16)
+#define OMAP4430_CLKTRCTRL_SHIFT	0
+#define OMAP4430_CLKTRCTRL_MASK		(0x3 << 0)
+#define OMAP4430_MODULEMODE_SHIFT	0
+#define OMAP4430_MODULEMODE_MASK	(0x3 << 0)
+
 /*
  * CLKCTRL_IDLEST_*: possible values for the CM_*_CLKCTRL.IDLEST bitfield:
  *
diff --git a/arch/arm/mach-omap2/powerdomain-common.c b/arch/arm/mach-omap2/powerdomain-common.c
index c0aeabf..c40e5f0 100644
--- a/arch/arm/mach-omap2/powerdomain-common.c
+++ b/arch/arm/mach-omap2/powerdomain-common.c
@@ -17,7 +17,6 @@
 #include "pm.h"
 #include "cm.h"
 #include "cm-regbits-34xx.h"
-#include "cm-regbits-44xx.h"
 #include "prm-regbits-34xx.h"
 #include "prm-regbits-44xx.h"
 
-- 
1.7.9.5

[PATCH 14/55] ARM: OMAP2: CM: remove references to cm-regbits-24xx.h from CM core code

[Tero Kristo]

Done in preparation to make CM a standalone driver.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/cm2xxx.c |   19 ++++++++++++++++++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-omap2/cm2xxx.c b/arch/arm/mach-omap2/cm2xxx.c
index 4c29f63..e74484a 100644
--- a/arch/arm/mach-omap2/cm2xxx.c
+++ b/arch/arm/mach-omap2/cm2xxx.c
@@ -22,7 +22,6 @@
 #include "cm.h"
 #include "cm2xxx_3xxx_private.h"
 #include "cm2xxx.h"
-#include "cm-regbits-24xx.h"
 #include "clockdomain.h"
 
 /* CM_AUTOIDLE_PLL.AUTO_* bit values for DPLLs */
@@ -36,6 +35,24 @@
 /* CM_IDLEST_PLL bit value offset for APLLs (OMAP2xxx only) */
 #define EN_APLL_LOCKED					3
 
+#define OMAP24XX_CLKSTCTRL_DISABLE_AUTO			0x0
+#define OMAP24XX_CLKSTCTRL_ENABLE_AUTO			0x1
+
+#define OMAP24XX_CORE_CLK_SRC_MASK			(0x3 << 0)
+
+#define OMAP24XX_EN_54M_PLL_SHIFT			6
+#define OMAP24XX_EN_96M_PLL_SHIFT			2
+#define OMAP24XX_ST_54M_APLL_SHIFT			9
+#define OMAP24XX_ST_96M_APLL_SHIFT			8
+#define OMAP24XX_AUTO_54M_MASK				(0x3 << 6)
+#define OMAP24XX_AUTO_96M_MASK				(0x3 << 2)
+#define OMAP24XX_AUTO_DPLL_SHIFT			0
+#define OMAP24XX_AUTO_DPLL_MASK				(0x3 << 0)
+
+#define OMAP24XX_EN_DSS1_MASK				(1 << 0)
+
+#define OMAP24XX_CLKSEL_DSS2_MASK			(0x1 << 13)
+
 static const u8 omap2xxx_cm_idlest_offs[] = {
 	CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3, OMAP24XX_CM_IDLEST4
 };
-- 
1.7.9.5

[PATCH 15/55] ARM: AM33xx: CM: remove references to cm-regbits-33xx.h from CM core code

[Tero Kristo]

Done in preparation to make CM a standalone driver.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/cm33xx.c |    9 ++++++++-
 arch/arm/mach-omap2/cm33xx.h |    1 -
 2 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-omap2/cm33xx.c b/arch/arm/mach-omap2/cm33xx.c
index 40a22e5..728ac3f 100644
--- a/arch/arm/mach-omap2/cm33xx.c
+++ b/arch/arm/mach-omap2/cm33xx.c
@@ -26,9 +26,16 @@
 #include "cm.h"
 #include "cm33xx.h"
 #include "cm-regbits-34xx.h"
-#include "cm-regbits-33xx.h"
 #include "prm33xx.h"
 
+#define AM33XX_MODULEMODE_SHIFT			0
+#define AM33XX_MODULEMODE_MASK			(0x3 << 0)
+
+#define AM33XX_CLKTRCTRL_SHIFT			0
+#define AM33XX_CLKTRCTRL_MASK			(0x3 << 0)
+#define AM33XX_IDLEST_SHIFT			16
+#define AM33XX_IDLEST_MASK			(0x3 << 16)
+
 /*
  * CLKCTRL_IDLEST_*: possible values for the CM_*_CLKCTRL.IDLEST bitfield:
  *
diff --git a/arch/arm/mach-omap2/cm33xx.h b/arch/arm/mach-omap2/cm33xx.h
index 15a778c..8f9e479 100644
--- a/arch/arm/mach-omap2/cm33xx.h
+++ b/arch/arm/mach-omap2/cm33xx.h
@@ -18,7 +18,6 @@
 #define __ARCH_ARM_MACH_OMAP2_CM_33XX_H
 
 #include "cm.h"
-#include "cm-regbits-33xx.h"
 
 /* CM base address */
 #define AM33XX_CM_BASE		0x44e00000
-- 
1.7.9.5

[PATCH 16/55] ARM: OMAP2: PRM: remove references to prm-regbits-24xx.h from PRM core code

[Tero Kristo]

Done in preparation to make PRM a standalone driver.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/prm2xxx.c      |   16 +++++++++++++++-
 arch/arm/mach-omap2/prm2xxx_3xxx.c |    1 -
 2 files changed, 15 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-omap2/prm2xxx.c b/arch/arm/mach-omap2/prm2xxx.c
index a7f1cac..7264ae6 100644
--- a/arch/arm/mach-omap2/prm2xxx.c
+++ b/arch/arm/mach-omap2/prm2xxx.c
@@ -20,9 +20,23 @@
 
 #include "powerdomain.h"
 #include "clockdomain.h"
+#include "prm2xxx.h"
 #include "prm2xxx_3xxx_private.h"
 #include "cm2xxx_3xxx.h"
-#include "prm-regbits-24xx.h"
+
+#define OMAP24XX_FORCESTATE_MASK		(1 << 18)
+#define OMAP24XX_AUTOIDLE_MASK			(1 << 0)
+#define OMAP24XX_AUTO_EXTVOLT_MASK		(1 << 15)
+
+#define OMAP24XX_SETOFF_LEVEL_SHIFT		12
+#define OMAP24XX_MEMRETCTRL_MASK		(1 << 8)
+#define OMAP24XX_SETRET_LEVEL_SHIFT		6
+#define OMAP24XX_VOLT_LEVEL_SHIFT		0
+
+#define OMAP24XX_EXTWMPU_RST_SHIFT		6
+#define OMAP24XX_SECU_WD_RST_SHIFT		5
+#define OMAP24XX_MPU_WD_RST_SHIFT		4
+#define OMAP24XX_SECU_VIOL_RST_SHIFT		3
 
 /*
  * OMAP24xx PM_PWSTCTRL_*.POWERSTATE and PM_PWSTST_*.LASTSTATEENTERED bits -
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c
index d891499..d8044f9 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c
@@ -18,7 +18,6 @@
 
 #include "powerdomain.h"
 #include "prm2xxx_3xxx_private.h"
-#include "prm-regbits-24xx.h"
 #include "clockdomain.h"
 
 /**
-- 
1.7.9.5

[PATCH 17/55] ARM: AM33xx: PRM: remove references to prm-regbits-33xx.h from PRM core code

[Tero Kristo]

Done in preparation to make PRM a standalone driver.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/prm33xx.c |    8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-omap2/prm33xx.c b/arch/arm/mach-omap2/prm33xx.c
index 0660105..877d7c7 100644
--- a/arch/arm/mach-omap2/prm33xx.c
+++ b/arch/arm/mach-omap2/prm33xx.c
@@ -21,7 +21,13 @@
 
 #include "powerdomain.h"
 #include "prm33xx.h"
-#include "prm-regbits-33xx.h"
+
+#define AM33XX_LASTPOWERSTATEENTERED_SHIFT	24
+#define AM33XX_LASTPOWERSTATEENTERED_MASK	(0x3 << 24)
+#define AM33XX_LOGICSTATEST_SHIFT		2
+#define AM33XX_LOGICSTATEST_MASK		(1 << 2)
+#define AM33XX_LOWPOWERSTATECHANGE_SHIFT	4
+#define AM33XX_LOWPOWERSTATECHANGE_MASK		(1 << 4)
 
 /* Read a register in a PRM instance */
 u32 am33xx_prm_read_reg(s16 inst, u16 idx)
-- 
1.7.9.5

[PATCH 18/55] ARM: OMAP4: PRM: remove references to prm-regbits-44xx.h from PRM core code

[Tero Kristo]

Done in preparation to make PRM a standalone driver.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/prm44xx.c     |   33 ++++++++++++++++++++++++++++++++-
 arch/arm/mach-omap2/prminst44xx.c |    3 ++-
 2 files changed, 34 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index 27f4603..5033cd3 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -23,11 +23,42 @@
 #include "prm44xx.h"
 #include "prm54xx.h"
 #include "prm7xx.h"
-#include "prm-regbits-44xx.h"
 #include "prcm44xx.h"
 #include "prminst44xx_private.h"
 #include "powerdomain.h"
 
+#define OMAP4430_GLOBAL_COLD_RST_SHIFT			0
+#define OMAP4430_GLOBAL_WARM_SW_RST_SHIFT		1
+#define OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT		2
+#define OMAP4430_MPU_WDT_RST_SHIFT			3
+#define OMAP4430_SECURE_WDT_RST_SHIFT			4
+#define OMAP4430_EXTERNAL_WARM_RST_SHIFT		5
+#define OMAP4430_VDD_MPU_VOLT_MGR_RST_SHIFT		6
+#define OMAP4430_VDD_IVA_VOLT_MGR_RST_SHIFT		7
+#define OMAP4430_VDD_CORE_VOLT_MGR_RST_SHIFT		8
+#define OMAP4430_ICEPICK_RST_SHIFT			9
+#define OMAP4430_C2C_RST_SHIFT				10
+
+#define OMAP4430_GLOBAL_WUEN_MASK			(1 << 16)
+
+#define OMAP4430_LASTPOWERSTATEENTERED_SHIFT		24
+#define OMAP4430_LASTPOWERSTATEENTERED_MASK		(0x3 << 24)
+#define OMAP4430_LOWPOWERSTATECHANGE_SHIFT		4
+#define OMAP4430_LOWPOWERSTATECHANGE_MASK		(1 << 4)
+
+#define OMAP4430_LOGICRETSTATE_SHIFT			2
+#define OMAP4430_LOGICRETSTATE_MASK			(1 << 2)
+#define OMAP4430_LOGICSTATEST_SHIFT			2
+#define OMAP4430_LOGICSTATEST_MASK			(1 << 2)
+
+#define OMAP4430_VP_CORE_TRANXDONE_ST_MASK		(1 << 21)
+#define OMAP4430_VP_IVA_TRANXDONE_ST_MASK		(1 << 29)
+#define OMAP4430_VP_MPU_TRANXDONE_ST_MASK		(1 << 5)
+
+#define OMAP4430_WUCLK_CTRL_MASK			(1 << 8)
+#define OMAP4430_WUCLK_STATUS_SHIFT			9
+#define OMAP4430_WUCLK_STATUS_MASK			(1 << 9)
+
 /* Static data */
 
 #define OMAP44XX_IRQ_GIC_START	32
diff --git a/arch/arm/mach-omap2/prminst44xx.c b/arch/arm/mach-omap2/prminst44xx.c
index bd0e0da..74349e1 100644
--- a/arch/arm/mach-omap2/prminst44xx.c
+++ b/arch/arm/mach-omap2/prminst44xx.c
@@ -21,10 +21,11 @@
 #include "prm54xx.h"
 #include "prm7xx.h"
 #include "prminst44xx.h"
-#include "prm-regbits-44xx.h"
 #include "prcm44xx.h"
 #include "prcm_mpu44xx.h"
 
+#define OMAP4430_RST_GLOBAL_WARM_SW_MASK		(1 << 0)
+
 static void __iomem *_prm_bases[OMAP4_MAX_PRCM_PARTITIONS];
 
 /**
-- 
1.7.9.5

[PATCH 19/55] ARM: OMAP3: PRM: remove references to prm-regbits-34xx.h from PRM core code

[Tero Kristo]

Done in preparation to make PRM a standalone driver.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/prm3xxx.c |   54 ++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 53 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-omap2/prm3xxx.c b/arch/arm/mach-omap2/prm3xxx.c
index f1d3e15..8ae209a 100644
--- a/arch/arm/mach-omap2/prm3xxx.c
+++ b/arch/arm/mach-omap2/prm3xxx.c
@@ -23,10 +23,62 @@
 #include "prm3xxx.h"
 #include "prm2xxx_3xxx_private.h"
 #include "cm2xxx_3xxx_private.h"
-#include "prm-regbits-34xx.h"
 #include "cm3xxx.h"
 #include "cm-regbits-34xx.h"
 
+#define OMAP3430_GLOBAL_COLD_RST_MASK			(1 << 0)
+#define OMAP3430_GLOBAL_COLD_RST_SHIFT			0
+#define OMAP3430_GLOBAL_SW_RST_SHIFT			1
+#define OMAP3430_SECURITY_VIOL_RST_SHIFT		3
+#define OMAP3430_MPU_WD_RST_SHIFT			4
+#define OMAP3430_SECURE_WD_RST_SHIFT			5
+#define OMAP3430_EXTERNAL_WARM_RST_SHIFT		6
+#define OMAP3430_VDD1_VOLTAGE_MANAGER_RST_SHIFT		7
+#define OMAP3430_VDD2_VOLTAGE_MANAGER_RST_SHIFT		8
+#define OMAP3430_ICEPICK_RST_SHIFT			9
+#define OMAP3430_ICECRUSHER_RST_SHIFT			10
+
+#define OMAP3430_VP1_TRANXDONE_ST_MASK			(1 << 15)
+#define OMAP3430_VP2_TRANXDONE_ST_MASK			(1 << 21)
+
+#define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK	(1 << 0)
+#define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK	(1 << 1)
+
+#define OMAP3430_PM_WKEN_DSS_EN_DSS_MASK		(1 << 0)
+
+#define OMAP3430_GRPSEL_GPT1_MASK			(1 << 0)
+#define OMAP3430_GRPSEL_GPT12_MASK			(1 << 1)
+#define OMAP3430_GRPSEL_GPIO1_MASK			(1 << 3)
+#define OMAP3430_GRPSEL_MCBSP2_MASK			(1 << 0)
+#define OMAP3430_GRPSEL_MCBSP3_MASK			(1 << 1)
+#define OMAP3430_GRPSEL_MCBSP4_MASK			(1 << 2)
+#define OMAP3430_GRPSEL_UART3_MASK			(1 << 11)
+#define OMAP3430_GRPSEL_GPIO2_MASK			(1 << 13)
+#define OMAP3430_GRPSEL_GPIO3_MASK			(1 << 14)
+#define OMAP3430_GRPSEL_GPIO4_MASK			(1 << 15)
+#define OMAP3430_GRPSEL_GPIO5_MASK			(1 << 16)
+#define OMAP3430_GRPSEL_GPIO6_MASK			(1 << 17)
+#define OMAP3630_GRPSEL_UART4_MASK			(1 << 18)
+
+#define OMAP3430_EN_IO_MASK				(1 << 8)
+#define OMAP3430_EN_IO_CHAIN_MASK			(1 << 16)
+#define OMAP3430_ST_IO_CHAIN_MASK			(1 << 16)
+
+#define OMAP3430ES2_SAVEANDRESTORE_SHIFT		4
+
+#define OMAP3430_LASTLOGICSTATEENTERED_MASK		(1 << 2)
+#define OMAP3430_LASTMEM1STATEENTERED_MASK		(0x3 << 4)
+#define OMAP3430_LASTMEM2STATEENTERED_MASK		(0x3 << 6)
+#define OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK	(0x3 << 8)
+#define OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK		(0x3 << 10)
+
+#define OMAP3430_RST1_IVA2_MASK				(1 << 0)
+#define OMAP3430_RST2_IVA2_MASK				(1 << 1)
+#define OMAP3430_RST3_IVA2_MASK				(1 << 2)
+
+#define OMAP3430_LASTPOWERSTATEENTERED_MASK		(0x3 << 0)
+#define OMAP3430_LOGICSTATEST_MASK			(1 << 2)
+
 static const struct omap_prcm_irq omap3_prcm_irqs[] = {
 	OMAP_PRCM_IRQ("wkup",	0,	0),
 	OMAP_PRCM_IRQ("io",	9,	1),
-- 
1.7.9.5

[PATCH 20/55] ARM: OMAP3+: PRCM: remove references to cm-regbits-34xx.h from PRCM core code

[Tero Kristo]

Done in preparation to make PRCM a standalone driver.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/cm33xx.c             |    6 +++++-
 arch/arm/mach-omap2/cm3xxx.c             |    8 +++++++-
 arch/arm/mach-omap2/cminst44xx.c         |    6 +++++-
 arch/arm/mach-omap2/powerdomain-common.c |    1 -
 arch/arm/mach-omap2/prm3xxx.c            |    7 ++++++-
 5 files changed, 23 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-omap2/cm33xx.c b/arch/arm/mach-omap2/cm33xx.c
index 728ac3f..c7be4e4 100644
--- a/arch/arm/mach-omap2/cm33xx.c
+++ b/arch/arm/mach-omap2/cm33xx.c
@@ -25,7 +25,6 @@
 #include "clockdomain.h"
 #include "cm.h"
 #include "cm33xx.h"
-#include "cm-regbits-34xx.h"
 #include "prm33xx.h"
 
 #define AM33XX_MODULEMODE_SHIFT			0
@@ -36,6 +35,11 @@
 #define AM33XX_IDLEST_SHIFT			16
 #define AM33XX_IDLEST_MASK			(0x3 << 16)
 
+#define OMAP34XX_CLKSTCTRL_DISABLE_AUTO		0x0
+#define OMAP34XX_CLKSTCTRL_FORCE_SLEEP		0x1
+#define OMAP34XX_CLKSTCTRL_FORCE_WAKEUP		0x2
+#define OMAP34XX_CLKSTCTRL_ENABLE_AUTO		0x3
+
 /*
  * CLKCTRL_IDLEST_*: possible values for the CM_*_CLKCTRL.IDLEST bitfield:
  *
diff --git a/arch/arm/mach-omap2/cm3xxx.c b/arch/arm/mach-omap2/cm3xxx.c
index 989590e..859c2fd 100644
--- a/arch/arm/mach-omap2/cm3xxx.c
+++ b/arch/arm/mach-omap2/cm3xxx.c
@@ -22,9 +22,15 @@
 #include "cm.h"
 #include "cm2xxx_3xxx_private.h"
 #include "cm3xxx.h"
-#include "cm-regbits-34xx.h"
 #include "clockdomain.h"
 
+#define OMAP34XX_CLKSTCTRL_DISABLE_AUTO		0x0
+#define OMAP34XX_CLKSTCTRL_FORCE_SLEEP		0x1
+#define OMAP34XX_CLKSTCTRL_FORCE_WAKEUP		0x2
+#define OMAP34XX_CLKSTCTRL_ENABLE_AUTO		0x3
+
+#define OMAP3430_AUTO_PERIPH_DPLL_MASK		(0x7 << 3)
+
 static const u8 omap3xxx_cm_idlest_offs[] = {
 	CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3
 };
diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c
index c2712d3..58e01c7 100644
--- a/arch/arm/mach-omap2/cminst44xx.c
+++ b/arch/arm/mach-omap2/cminst44xx.c
@@ -27,7 +27,6 @@
 #include "cm2_44xx.h"
 #include "cm44xx.h"
 #include "cminst44xx.h"
-#include "cm-regbits-34xx.h"
 #include "prcm44xx.h"
 #include "prm44xx.h"
 #include "prcm_mpu44xx.h"
@@ -40,6 +39,11 @@
 #define OMAP4430_MODULEMODE_SHIFT	0
 #define OMAP4430_MODULEMODE_MASK	(0x3 << 0)
 
+#define OMAP34XX_CLKSTCTRL_DISABLE_AUTO	0x0
+#define OMAP34XX_CLKSTCTRL_FORCE_SLEEP	0x1
+#define OMAP34XX_CLKSTCTRL_FORCE_WAKEUP	0x2
+#define OMAP34XX_CLKSTCTRL_ENABLE_AUTO	0x3
+
 /*
  * CLKCTRL_IDLEST_*: possible values for the CM_*_CLKCTRL.IDLEST bitfield:
  *
diff --git a/arch/arm/mach-omap2/powerdomain-common.c b/arch/arm/mach-omap2/powerdomain-common.c
index c40e5f0..2c62cd9 100644
--- a/arch/arm/mach-omap2/powerdomain-common.c
+++ b/arch/arm/mach-omap2/powerdomain-common.c
@@ -16,7 +16,6 @@
 #include <linux/bug.h>
 #include "pm.h"
 #include "cm.h"
-#include "cm-regbits-34xx.h"
 #include "prm-regbits-34xx.h"
 #include "prm-regbits-44xx.h"
 
diff --git a/arch/arm/mach-omap2/prm3xxx.c b/arch/arm/mach-omap2/prm3xxx.c
index 8ae209a..852bc4d 100644
--- a/arch/arm/mach-omap2/prm3xxx.c
+++ b/arch/arm/mach-omap2/prm3xxx.c
@@ -24,7 +24,6 @@
 #include "prm2xxx_3xxx_private.h"
 #include "cm2xxx_3xxx_private.h"
 #include "cm3xxx.h"
-#include "cm-regbits-34xx.h"
 
 #define OMAP3430_GLOBAL_COLD_RST_MASK			(1 << 0)
 #define OMAP3430_GLOBAL_COLD_RST_SHIFT			0
@@ -79,6 +78,12 @@
 #define OMAP3430_LASTPOWERSTATEENTERED_MASK		(0x3 << 0)
 #define OMAP3430_LOGICSTATEST_MASK			(1 << 2)
 
+#define OMAP3430ES2_EN_USBHOST2_SHIFT			1
+
+#define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK		(1 << 0)
+
+#define OMAP3430_CLKACTIVITY_IVA2_MASK			(1 << 0)
+
 static const struct omap_prcm_irq omap3_prcm_irqs[] = {
 	OMAP_PRCM_IRQ("wkup",	0,	0),
 	OMAP_PRCM_IRQ("io",	9,	1),
-- 
1.7.9.5

[PATCH 21/55] ARM: OMAP2+: PRCM: remove references to clock.h from PRCM core code

[Tero Kristo]

Done in preparation to make PRCM a standalone driver.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/clockdomain.c |    1 -
 arch/arm/mach-omap2/clockdomain.h |    2 +-
 arch/arm/mach-omap2/prcm-common.h |    2 ++
 arch/arm/mach-omap2/prm_common.c  |   11 ++++-------
 4 files changed, 7 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index 2da3b5e..9a59efb 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -29,7 +29,6 @@
 #include <linux/bitops.h>
 
 #include "soc.h"
-#include "clock.h"
 #include "clockdomain.h"
 
 /* clkdm_list contains all registered struct clockdomains */
diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
index 82c37b1..4322a28 100644
--- a/arch/arm/mach-omap2/clockdomain.h
+++ b/arch/arm/mach-omap2/clockdomain.h
@@ -17,7 +17,6 @@
 #include <linux/init.h>
 
 #include "powerdomain.h"
-#include "clock.h"
 
 /*
  * Clockdomain flags
@@ -98,6 +97,7 @@ struct clkdm_dep {
 #define _CLKDM_FLAG_HWSUP_ENABLED		BIT(0)
 
 struct omap_hwmod;
+struct clk;
 
 /**
  * struct clockdomain - OMAP clockdomain
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index f356532..1a05d04 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -519,6 +519,8 @@ struct omap_prcm_irq_setup {
 
 struct of_device_id;
 
+extern void __iomem *clk_memmaps[];
+
 extern void omap_prcm_irq_cleanup(void);
 extern int omap_prcm_register_chain_handler(
 	struct omap_prcm_irq_setup *irq_setup);
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index 080b3ed..090d13f 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -32,7 +32,6 @@
 #include "prm2xxx.h"
 #include "prm3xxx.h"
 #include "prm44xx.h"
-#include "clock.h"
 
 /*
  * OMAP_PRCM_MAX_NR_PENDING_REG: maximum number of PRM_IRQ*_MPU regs
@@ -481,18 +480,16 @@ static struct of_device_id omap_prcm_dt_match_table[] = {
 	{ }
 };
 
-static struct clk_hw_omap memmap_dummy_ck = {
-	.flags = MEMMAP_ADDRESSING,
-};
-
 static u32 prm_clk_readl(void __iomem *reg)
 {
-	return omap2_clk_readl(&memmap_dummy_ck, reg);
+	struct clk_omap_reg *r = (struct clk_omap_reg *)&reg;
+	return readl_relaxed(clk_memmaps[r->index] + r->offset);
 }
 
 static void prm_clk_writel(u32 val, void __iomem *reg)
 {
-	omap2_clk_writel(val, &memmap_dummy_ck, reg);
+	struct clk_omap_reg *r = (struct clk_omap_reg *)&reg;
+	writel_relaxed(val, clk_memmaps[r->index] + r->offset);
 }
 
 static struct ti_clk_ll_ops omap_clk_ll_ops = {
-- 
1.7.9.5

[PATCH 22/55] ARM: OMAP2: CM: move cm2xxx.h header to a public location

[Tero Kristo]

This file needs to be accessible from the PRCM core and mach-omap2 board
support code.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/cm2xxx.c      |    2 +-
 arch/arm/mach-omap2/cm2xxx.h      |   52 +--------------------------
 arch/arm/mach-omap2/cm_common.c   |    2 +-
 include/linux/power/omap/cm2xxx.h |   70 +++++++++++++++++++++++++++++++++++++
 4 files changed, 73 insertions(+), 53 deletions(-)
 create mode 100644 include/linux/power/omap/cm2xxx.h

diff --git a/arch/arm/mach-omap2/cm2xxx.c b/arch/arm/mach-omap2/cm2xxx.c
index e74484a..6f04031 100644
--- a/arch/arm/mach-omap2/cm2xxx.c
+++ b/arch/arm/mach-omap2/cm2xxx.c
@@ -21,7 +21,7 @@
 #include "prm2xxx.h"
 #include "cm.h"
 #include "cm2xxx_3xxx_private.h"
-#include "cm2xxx.h"
+#include <linux/power/omap/cm2xxx.h>
 #include "clockdomain.h"
 
 /* CM_AUTOIDLE_PLL.AUTO_* bit values for DPLLs */
diff --git a/arch/arm/mach-omap2/cm2xxx.h b/arch/arm/mach-omap2/cm2xxx.h
index 891d81c..5eaa007 100644
--- a/arch/arm/mach-omap2/cm2xxx.h
+++ b/arch/arm/mach-omap2/cm2xxx.h
@@ -18,61 +18,11 @@
 
 #include "prcm-common.h"
 #include "cm2xxx_3xxx.h"
+#include <linux/power/omap/cm2xxx.h>
 
 #define OMAP2420_CM_REGADDR(module, reg)				\
 			OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg))
 #define OMAP2430_CM_REGADDR(module, reg)				\
 			OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg))
 
-/*
- * Module specific CM register offsets from CM_BASE + domain offset
- * Use cm_{read,write}_mod_reg() with these registers.
- * These register offsets generally appear in more than one PRCM submodule.
- */
-
-/* OMAP2-specific register offsets */
-
-#define OMAP24XX_CM_FCLKEN2				0x0004
-#define OMAP24XX_CM_ICLKEN4				0x001c
-#define OMAP24XX_CM_AUTOIDLE4				0x003c
-#define OMAP24XX_CM_IDLEST4				0x002c
-
-/* CM_IDLEST bit field values to indicate deasserted IdleReq */
-
-#define OMAP24XX_CM_IDLEST_VAL				0
-
-
-/* Clock management domain register get/set */
-
-#ifndef __ASSEMBLER__
-
-extern void omap2xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask);
-extern void omap2xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask);
-
-extern void omap2xxx_cm_set_dpll_disable_autoidle(void);
-extern void omap2xxx_cm_set_dpll_auto_low_power_stop(void);
-
-extern void omap2xxx_cm_set_apll54_disable_autoidle(void);
-extern void omap2xxx_cm_set_apll54_auto_low_power_stop(void);
-extern void omap2xxx_cm_set_apll96_disable_autoidle(void);
-extern void omap2xxx_cm_set_apll96_auto_low_power_stop(void);
-
-extern bool omap2xxx_cm_is_clkdm_in_hwsup(s16 module, u32 mask);
-extern int omap2xxx_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id,
-					 u8 idlest_shift);
-extern int omap2xxx_cm_split_idlest_reg(void __iomem *idlest_reg,
-					s16 *prcm_inst, u8 *idlest_reg_id);
-extern int omap2xxx_cm_fclks_active(void);
-extern int omap2xxx_cm_mpu_retention_allowed(void);
-extern u32 omap2xxx_cm_get_core_clk_src(void);
-extern u32 omap2xxx_cm_get_core_pll_config(void);
-extern u32 omap2xxx_cm_get_pll_config(void);
-extern u32 omap2xxx_cm_get_pll_status(void);
-extern void omap2xxx_cm_set_mod_dividers(u32 mpu, u32 dsp, u32 gfx, u32 core,
-					 u32 mdm);
-
-extern int __init omap2xxx_cm_init(void);
-
-#endif
-
 #endif
diff --git a/arch/arm/mach-omap2/cm_common.c b/arch/arm/mach-omap2/cm_common.c
index c334d38..9a53eb5 100644
--- a/arch/arm/mach-omap2/cm_common.c
+++ b/arch/arm/mach-omap2/cm_common.c
@@ -16,7 +16,7 @@
 #include <linux/errno.h>
 #include <linux/of.h>
 
-#include "cm2xxx.h"
+#include <linux/power/omap/cm2xxx.h>
 #include "cm3xxx.h"
 #include "cm44xx.h"
 
diff --git a/include/linux/power/omap/cm2xxx.h b/include/linux/power/omap/cm2xxx.h
new file mode 100644
index 0000000..df496b4
--- /dev/null
+++ b/include/linux/power/omap/cm2xxx.h
@@ -0,0 +1,70 @@
+/*
+ * OMAP2xxx Clock Management (CM) register definitions
+ *
+ * Copyright (C) 2007-2009, 2012 Texas Instruments, Inc.
+ * Copyright (C) 2007-2010 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * The CM hardware modules on the OMAP2/3 are quite similar to each
+ * other.  The CM modules/instances on OMAP4 are quite different, so
+ * they are handled in a separate file.
+ */
+#ifndef __LINUX_POWER_OMAP_CM2XXX_H
+#define __LINUX_POWER_OMAP_CM2XXX_H
+
+/*
+ * Module specific CM register offsets from CM_BASE + domain offset
+ * Use cm_{read,write}_mod_reg() with these registers.
+ * These register offsets generally appear in more than one PRCM submodule.
+ */
+
+/* OMAP2-specific register offsets */
+
+#define OMAP24XX_CM_FCLKEN2				0x0004
+#define OMAP24XX_CM_ICLKEN4				0x001c
+#define OMAP24XX_CM_AUTOIDLE4				0x003c
+#define OMAP24XX_CM_IDLEST4				0x002c
+
+/* CM_IDLEST bit field values to indicate deasserted IdleReq */
+
+#define OMAP24XX_CM_IDLEST_VAL				0
+
+
+/* Clock management domain register get/set */
+
+#ifndef __ASSEMBLER__
+
+void omap2xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask);
+void omap2xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask);
+
+void omap2xxx_cm_set_dpll_disable_autoidle(void);
+void omap2xxx_cm_set_dpll_auto_low_power_stop(void);
+
+void omap2xxx_cm_set_apll54_disable_autoidle(void);
+void omap2xxx_cm_set_apll54_auto_low_power_stop(void);
+void omap2xxx_cm_set_apll96_disable_autoidle(void);
+void omap2xxx_cm_set_apll96_auto_low_power_stop(void);
+
+bool omap2xxx_cm_is_clkdm_in_hwsup(s16 module, u32 mask);
+int omap2xxx_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id,
+				  u8 idlest_shift);
+int omap2xxx_cm_split_idlest_reg(void __iomem *idlest_reg,
+				 s16 *prcm_inst, u8 *idlest_reg_id);
+int omap2xxx_cm_fclks_active(void);
+int omap2xxx_cm_mpu_retention_allowed(void);
+u32 omap2xxx_cm_get_core_clk_src(void);
+u32 omap2xxx_cm_get_core_pll_config(void);
+u32 omap2xxx_cm_get_pll_config(void);
+u32 omap2xxx_cm_get_pll_status(void);
+void omap2xxx_cm_set_mod_dividers(u32 mpu, u32 dsp, u32 gfx, u32 core,
+				  u32 mdm);
+
+int __init omap2xxx_cm_init(void);
+
+#endif
+
+#endif
-- 
1.7.9.5

[PATCH 23/55] ARM: AM33xx: CM: move cm33xx.h header to a public location

[Tero Kristo]

This file needs to be accessible from the PRCM core and mach-omap2 board
support code.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/cm33xx.c      |    2 +-
 arch/arm/mach-omap2/cm33xx.h      |   50 +--------------------------
 include/linux/power/omap/cm33xx.h |   68 +++++++++++++++++++++++++++++++++++++
 3 files changed, 70 insertions(+), 50 deletions(-)
 create mode 100644 include/linux/power/omap/cm33xx.h

diff --git a/arch/arm/mach-omap2/cm33xx.c b/arch/arm/mach-omap2/cm33xx.c
index c7be4e4..7a7b2e7 100644
--- a/arch/arm/mach-omap2/cm33xx.c
+++ b/arch/arm/mach-omap2/cm33xx.c
@@ -24,7 +24,7 @@
 
 #include "clockdomain.h"
 #include "cm.h"
-#include "cm33xx.h"
+#include <linux/power/omap/cm33xx.h>
 #include "prm33xx.h"
 
 #define AM33XX_MODULEMODE_SHIFT			0
diff --git a/arch/arm/mach-omap2/cm33xx.h b/arch/arm/mach-omap2/cm33xx.h
index 8f9e479..67f1d49 100644
--- a/arch/arm/mach-omap2/cm33xx.h
+++ b/arch/arm/mach-omap2/cm33xx.h
@@ -18,6 +18,7 @@
 #define __ARCH_ARM_MACH_OMAP2_CM_33XX_H
 
 #include "cm.h"
+#include <linux/power/omap/cm33xx.h>
 
 /* CM base address */
 #define AM33XX_CM_BASE		0x44e00000
@@ -25,16 +26,6 @@
 #define AM33XX_CM_REGADDR(inst, reg)				\
 	AM33XX_L4_WK_IO_ADDRESS(AM33XX_CM_BASE + (inst) + (reg))
 
-/* CM instances */
-#define AM33XX_CM_PER_MOD		0x0000
-#define AM33XX_CM_WKUP_MOD		0x0400
-#define AM33XX_CM_DPLL_MOD		0x0500
-#define AM33XX_CM_MPU_MOD		0x0600
-#define AM33XX_CM_DEVICE_MOD		0x0700
-#define AM33XX_CM_RTC_MOD		0x0800
-#define AM33XX_CM_GFX_MOD		0x0900
-#define AM33XX_CM_CEFUSE_MOD		0x0A00
-
 /* CM */
 
 /* CM.PER_CM register offsets */
@@ -371,43 +362,4 @@
 #define AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET		0x0020
 #define AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_CEFUSE_MOD, 0x0020)
 
-
-#ifndef __ASSEMBLER__
-bool am33xx_cm_is_clkdm_in_hwsup(u16 inst, u16 cdoffs);
-void am33xx_cm_clkdm_enable_hwsup(u16 inst, u16 cdoffs);
-void am33xx_cm_clkdm_disable_hwsup(u16 inst, u16 cdoffs);
-void am33xx_cm_clkdm_force_sleep(u16 inst, u16 cdoffs);
-void am33xx_cm_clkdm_force_wakeup(u16 inst, u16 cdoffs);
-
-#ifdef CONFIG_SOC_AM33XX
-extern int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs,
-					u16 clkctrl_offs);
-extern void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs,
-					u16 clkctrl_offs);
-extern void am33xx_cm_module_disable(u16 inst, s16 cdoffs,
-					u16 clkctrl_offs);
-extern int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs,
-					u16 clkctrl_offs);
-#else
-static inline int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs,
-					u16 clkctrl_offs)
-{
-	return 0;
-}
-static inline void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs,
-					u16 clkctrl_offs)
-{
-}
-static inline void am33xx_cm_module_disable(u16 inst, s16 cdoffs,
-					u16 clkctrl_offs)
-{
-}
-static inline int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs,
-					u16 clkctrl_offs)
-{
-	return 0;
-}
-#endif
-
-#endif /* ASSEMBLER */
 #endif
diff --git a/include/linux/power/omap/cm33xx.h b/include/linux/power/omap/cm33xx.h
new file mode 100644
index 0000000..2449ba8
--- /dev/null
+++ b/include/linux/power/omap/cm33xx.h
@@ -0,0 +1,68 @@
+/*
+ * AM33XX CM offset macros
+ *
+ * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Vaibhav Hiremath <hvaibhav@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __LINUX_POWER_OMAP_CM33XX_H
+#define __LINUX_POWER_OMAP_CM33XX_H
+
+/* CM instances */
+#define AM33XX_CM_PER_MOD		0x0000
+#define AM33XX_CM_WKUP_MOD		0x0400
+#define AM33XX_CM_DPLL_MOD		0x0500
+#define AM33XX_CM_MPU_MOD		0x0600
+#define AM33XX_CM_DEVICE_MOD		0x0700
+#define AM33XX_CM_RTC_MOD		0x0800
+#define AM33XX_CM_GFX_MOD		0x0900
+#define AM33XX_CM_CEFUSE_MOD		0x0A00
+
+#ifndef __ASSEMBLER__
+bool am33xx_cm_is_clkdm_in_hwsup(u16 inst, u16 cdoffs);
+void am33xx_cm_clkdm_enable_hwsup(u16 inst, u16 cdoffs);
+void am33xx_cm_clkdm_disable_hwsup(u16 inst, u16 cdoffs);
+void am33xx_cm_clkdm_force_sleep(u16 inst, u16 cdoffs);
+void am33xx_cm_clkdm_force_wakeup(u16 inst, u16 cdoffs);
+
+#ifdef CONFIG_SOC_AM33XX
+int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs,
+			       u16 clkctrl_offs);
+void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs,
+			     u16 clkctrl_offs);
+void am33xx_cm_module_disable(u16 inst, s16 cdoffs,
+			      u16 clkctrl_offs);
+int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs,
+				u16 clkctrl_offs);
+#else
+static inline int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs,
+					u16 clkctrl_offs)
+{
+	return 0;
+}
+static inline void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs,
+					u16 clkctrl_offs)
+{
+}
+static inline void am33xx_cm_module_disable(u16 inst, s16 cdoffs,
+					u16 clkctrl_offs)
+{
+}
+static inline int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs,
+					u16 clkctrl_offs)
+{
+	return 0;
+}
+#endif
+
+#endif /* ASSEMBLER */
+#endif
-- 
1.7.9.5

[PATCH 24/55] ARM: OMAP3: CM: move cm3xxx.h header to public location

[Tero Kristo]

This file needs to be accessible from the PRCM core and mach-omap2 board
support code.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/cm3xxx.c      |    2 +-
 arch/arm/mach-omap2/cm3xxx.h      |   66 +----------------------------
 arch/arm/mach-omap2/cm_common.c   |    2 +-
 arch/arm/mach-omap2/prm3xxx.c     |    2 +-
 include/linux/power/omap/cm3xxx.h |   82 +++++++++++++++++++++++++++++++++++++
 5 files changed, 86 insertions(+), 68 deletions(-)
 create mode 100644 include/linux/power/omap/cm3xxx.h

diff --git a/arch/arm/mach-omap2/cm3xxx.c b/arch/arm/mach-omap2/cm3xxx.c
index 859c2fd..cbba617 100644
--- a/arch/arm/mach-omap2/cm3xxx.c
+++ b/arch/arm/mach-omap2/cm3xxx.c
@@ -21,7 +21,7 @@
 #include "prm2xxx_3xxx.h"
 #include "cm.h"
 #include "cm2xxx_3xxx_private.h"
-#include "cm3xxx.h"
+#include <linux/power/omap/cm3xxx.h>
 #include "clockdomain.h"
 
 #define OMAP34XX_CLKSTCTRL_DISABLE_AUTO		0x0
diff --git a/arch/arm/mach-omap2/cm3xxx.h b/arch/arm/mach-omap2/cm3xxx.h
index 0301557..9c2047f 100644
--- a/arch/arm/mach-omap2/cm3xxx.h
+++ b/arch/arm/mach-omap2/cm3xxx.h
@@ -18,73 +18,9 @@
 
 #include "prcm-common.h"
 #include "cm2xxx_3xxx.h"
+#include <linux/power/omap/cm3xxx.h>
 
 #define OMAP34XX_CM_REGADDR(module, reg)				\
 			OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg))
 
-
-/*
- * OMAP3-specific global CM registers
- * Use cm_{read,write}_reg() with these registers.
- * These registers appear once per CM module.
- */
-
-#define OMAP3430_CM_SYSCONFIG		0x0010
-#define OMAP3430_CM_POLCTRL		0x009c
-
-#define OMAP3_CM_CLKOUT_CTRL_OFFSET	0x0070
-
-/*
- * Module specific CM register offsets from CM_BASE + domain offset
- * Use cm_{read,write}_mod_reg() with these registers.
- * These register offsets generally appear in more than one PRCM submodule.
- */
-
-/* OMAP3-specific register offsets */
-
-#define OMAP3430_CM_CLKEN_PLL				0x0004
-#define OMAP3430ES2_CM_CLKEN2				0x0004
-#define OMAP3430ES2_CM_FCLKEN3				0x0008
-#define OMAP3430_CM_IDLEST_PLL				CM_IDLEST2
-#define OMAP3430_CM_AUTOIDLE_PLL			CM_AUTOIDLE2
-#define OMAP3430ES2_CM_AUTOIDLE2_PLL			CM_AUTOIDLE2
-#define OMAP3430_CM_CLKSEL1				CM_CLKSEL
-#define OMAP3430_CM_CLKSEL1_PLL				CM_CLKSEL
-#define OMAP3430_CM_CLKSEL2_PLL				CM_CLKSEL2
-#define OMAP3430_CM_SLEEPDEP				CM_CLKSEL2
-#define OMAP3430_CM_CLKSEL3				OMAP2_CM_CLKSTCTRL
-#define OMAP3430_CM_CLKSTST				0x004c
-#define OMAP3430ES2_CM_CLKSEL4				0x004c
-#define OMAP3430ES2_CM_CLKSEL5				0x0050
-#define OMAP3430_CM_CLKSEL2_EMU				0x0050
-#define OMAP3430_CM_CLKSEL3_EMU				0x0054
-
-
-/* CM_IDLEST bit field values to indicate deasserted IdleReq */
-
-#define OMAP34XX_CM_IDLEST_VAL				1
-
-
-#ifndef __ASSEMBLER__
-
-extern void omap3xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask);
-extern void omap3xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask);
-extern void omap3xxx_cm_clkdm_force_sleep(s16 module, u32 mask);
-extern void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask);
-
-extern bool omap3xxx_cm_is_clkdm_in_hwsup(s16 module, u32 mask);
-extern int omap3xxx_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id,
-					 u8 idlest_shift);
-
-extern int omap3xxx_cm_split_idlest_reg(void __iomem *idlest_reg,
-					s16 *prcm_inst, u8 *idlest_reg_id);
-
-extern void omap3_cm_save_context(void);
-extern void omap3_cm_restore_context(void);
-extern void omap3_cm_save_scratchpad_contents(u32 *ptr);
-
-extern int __init omap3xxx_cm_init(void);
-
-#endif
-
 #endif
diff --git a/arch/arm/mach-omap2/cm_common.c b/arch/arm/mach-omap2/cm_common.c
index 9a53eb5..f8f9343 100644
--- a/arch/arm/mach-omap2/cm_common.c
+++ b/arch/arm/mach-omap2/cm_common.c
@@ -17,7 +17,7 @@
 #include <linux/of.h>
 
 #include <linux/power/omap/cm2xxx.h>
-#include "cm3xxx.h"
+#include <linux/power/omap/cm3xxx.h>
 #include "cm44xx.h"
 
 /*
diff --git a/arch/arm/mach-omap2/prm3xxx.c b/arch/arm/mach-omap2/prm3xxx.c
index 852bc4d..4700605 100644
--- a/arch/arm/mach-omap2/prm3xxx.c
+++ b/arch/arm/mach-omap2/prm3xxx.c
@@ -23,7 +23,7 @@
 #include "prm3xxx.h"
 #include "prm2xxx_3xxx_private.h"
 #include "cm2xxx_3xxx_private.h"
-#include "cm3xxx.h"
+#include <linux/power/omap/cm3xxx.h>
 
 #define OMAP3430_GLOBAL_COLD_RST_MASK			(1 << 0)
 #define OMAP3430_GLOBAL_COLD_RST_SHIFT			0
diff --git a/include/linux/power/omap/cm3xxx.h b/include/linux/power/omap/cm3xxx.h
new file mode 100644
index 0000000..ef3204b
--- /dev/null
+++ b/include/linux/power/omap/cm3xxx.h
@@ -0,0 +1,82 @@
+/*
+ * OMAP2/3 Clock Management (CM) register definitions
+ *
+ * Copyright (C) 2007-2009 Texas Instruments, Inc.
+ * Copyright (C) 2007-2010 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * The CM hardware modules on the OMAP2/3 are quite similar to each
+ * other.  The CM modules/instances on OMAP4 are quite different, so
+ * they are handled in a separate file.
+ */
+#ifndef __LINUX_POWER_OMAP_CM3XXX_H
+#define __LINUX_POWER_OMAP_CM3XXX_H
+
+/*
+ * OMAP3-specific global CM registers
+ * Use cm_{read,write}_reg() with these registers.
+ * These registers appear once per CM module.
+ */
+
+#define OMAP3430_CM_SYSCONFIG		0x0010
+#define OMAP3430_CM_POLCTRL		0x009c
+
+#define OMAP3_CM_CLKOUT_CTRL_OFFSET	0x0070
+
+/*
+ * Module specific CM register offsets from CM_BASE + domain offset
+ * Use cm_{read,write}_mod_reg() with these registers.
+ * These register offsets generally appear in more than one PRCM submodule.
+ */
+
+/* OMAP3-specific register offsets */
+
+#define OMAP3430_CM_CLKEN_PLL				0x0004
+#define OMAP3430ES2_CM_CLKEN2				0x0004
+#define OMAP3430ES2_CM_FCLKEN3				0x0008
+#define OMAP3430_CM_IDLEST_PLL				CM_IDLEST2
+#define OMAP3430_CM_AUTOIDLE_PLL			CM_AUTOIDLE2
+#define OMAP3430ES2_CM_AUTOIDLE2_PLL			CM_AUTOIDLE2
+#define OMAP3430_CM_CLKSEL1				CM_CLKSEL
+#define OMAP3430_CM_CLKSEL1_PLL				CM_CLKSEL
+#define OMAP3430_CM_CLKSEL2_PLL				CM_CLKSEL2
+#define OMAP3430_CM_SLEEPDEP				CM_CLKSEL2
+#define OMAP3430_CM_CLKSEL3				OMAP2_CM_CLKSTCTRL
+#define OMAP3430_CM_CLKSTST				0x004c
+#define OMAP3430ES2_CM_CLKSEL4				0x004c
+#define OMAP3430ES2_CM_CLKSEL5				0x0050
+#define OMAP3430_CM_CLKSEL2_EMU				0x0050
+#define OMAP3430_CM_CLKSEL3_EMU				0x0054
+
+
+/* CM_IDLEST bit field values to indicate deasserted IdleReq */
+
+#define OMAP34XX_CM_IDLEST_VAL				1
+
+#ifndef __ASSEMBLER__
+
+void omap3xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask);
+void omap3xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask);
+void omap3xxx_cm_clkdm_force_sleep(s16 module, u32 mask);
+void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask);
+
+bool omap3xxx_cm_is_clkdm_in_hwsup(s16 module, u32 mask);
+int omap3xxx_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id,
+				  u8 idlest_shift);
+
+int omap3xxx_cm_split_idlest_reg(void __iomem *idlest_reg,
+				 s16 *prcm_inst, u8 *idlest_reg_id);
+
+void omap3_cm_save_context(void);
+void omap3_cm_restore_context(void);
+void omap3_cm_save_scratchpad_contents(u32 *ptr);
+
+int __init omap3xxx_cm_init(void);
+
+#endif
+
+#endif
-- 
1.7.9.5

[PATCH 25/55] ARM: OMAP4: CM: remove unnecessary cm44xx.h header file

[Tero Kristo]

Contains only two defines used by a single source code file, so move the
definitions over and delete the file.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/cm44xx.h      |   26 --------------------------
 arch/arm/mach-omap2/cm_common.c   |    3 ++-
 arch/arm/mach-omap2/cminst44xx.c  |    4 +++-
 arch/arm/mach-omap2/powerdomain.c |    1 -
 4 files changed, 5 insertions(+), 29 deletions(-)
 delete mode 100644 arch/arm/mach-omap2/cm44xx.h

diff --git a/arch/arm/mach-omap2/cm44xx.h b/arch/arm/mach-omap2/cm44xx.h
deleted file mode 100644
index 3380bee..0000000
--- a/arch/arm/mach-omap2/cm44xx.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * OMAP4 Clock Management (CM) definitions
- *
- * Copyright (C) 2007-2011 Texas Instruments, Inc.
- * Copyright (C) 2007-2009 Nokia Corporation
- *
- * Written by Paul Walmsley
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * OMAP4 has two separate CM blocks, CM1 and CM2.  This file contains
- * macros and function prototypes that are applicable to both.
- */
-#ifndef __ARCH_ASM_MACH_OMAP2_CM44XX_H
-#define __ARCH_ASM_MACH_OMAP2_CM44XX_H
-
-
-#include "prcm-common.h"
-#include "cm.h"
-
-#define OMAP4_CM_CLKSTCTRL				0x0000
-#define OMAP4_CM_STATICDEP				0x0004
-
-#endif
diff --git a/arch/arm/mach-omap2/cm_common.c b/arch/arm/mach-omap2/cm_common.c
index f8f9343..8655538 100644
--- a/arch/arm/mach-omap2/cm_common.c
+++ b/arch/arm/mach-omap2/cm_common.c
@@ -18,7 +18,8 @@
 
 #include <linux/power/omap/cm2xxx.h>
 #include <linux/power/omap/cm3xxx.h>
-#include "cm44xx.h"
+#include "cm.h"
+#include "prcm-common.h"
 
 /*
  * cm_ll_data: function pointers to SoC-specific implementations of
diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c
index 58e01c7..dfb1a93 100644
--- a/arch/arm/mach-omap2/cminst44xx.c
+++ b/arch/arm/mach-omap2/cminst44xx.c
@@ -25,7 +25,6 @@
 #include "cm.h"
 #include "cm1_44xx.h"
 #include "cm2_44xx.h"
-#include "cm44xx.h"
 #include "cminst44xx.h"
 #include "prcm44xx.h"
 #include "prm44xx.h"
@@ -44,6 +43,9 @@
 #define OMAP34XX_CLKSTCTRL_FORCE_WAKEUP	0x2
 #define OMAP34XX_CLKSTCTRL_ENABLE_AUTO	0x3
 
+#define OMAP4_CM_CLKSTCTRL		0x0000
+#define OMAP4_CM_STATICDEP		0x0004
+
 /*
  * CLKCTRL_IDLEST_*: possible values for the CM_*_CLKCTRL.IDLEST bitfield:
  *
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index faebd5f..62649ba 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -24,7 +24,6 @@
 
 #include "cm2xxx_3xxx.h"
 #include "prcm44xx.h"
-#include "cm44xx.h"
 #include "prm2xxx_3xxx.h"
 #include "prm44xx.h"
 
-- 
1.7.9.5

[PATCH 26/55] ARM: OMAP3: move cm2xxx_3xxx.h header to public location

[Tero Kristo]

This file needs to be accessible from the PRCM core and mach-omap2 board
support code.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/clkt_iclk.c                  |    2 +-
 arch/arm/mach-omap2/clock3xxx.c                  |    2 +-
 arch/arm/mach-omap2/clockdomains2420_data.c      |    2 +-
 arch/arm/mach-omap2/clockdomains2430_data.c      |    2 +-
 arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c |    2 +-
 arch/arm/mach-omap2/clockdomains3xxx_data.c      |    2 +-
 arch/arm/mach-omap2/cm2xxx.h                     |    2 +-
 arch/arm/mach-omap2/cm2xxx_3xxx.h                |   72 ----------------------
 arch/arm/mach-omap2/cm2xxx_3xxx_private.h        |    2 +-
 arch/arm/mach-omap2/cm3xxx.h                     |    2 +-
 arch/arm/mach-omap2/dpll3xxx.c                   |    2 +-
 arch/arm/mach-omap2/dsp.c                        |    2 +-
 arch/arm/mach-omap2/pm-debug.c                   |    2 +-
 arch/arm/mach-omap2/powerdomain.c                |    2 +-
 arch/arm/mach-omap2/powerdomains3xxx_data.c      |    2 +-
 arch/arm/mach-omap2/prm2xxx.c                    |    2 +-
 arch/arm/mach-omap2/serial.c                     |    2 +-
 include/linux/power/omap/cm2xxx_3xxx.h           |   70 +++++++++++++++++++++
 18 files changed, 86 insertions(+), 88 deletions(-)
 delete mode 100644 arch/arm/mach-omap2/cm2xxx_3xxx.h
 create mode 100644 include/linux/power/omap/cm2xxx_3xxx.h

diff --git a/arch/arm/mach-omap2/clkt_iclk.c b/arch/arm/mach-omap2/clkt_iclk.c
index 333f0a6..b4cf577 100644
--- a/arch/arm/mach-omap2/clkt_iclk.c
+++ b/arch/arm/mach-omap2/clkt_iclk.c
@@ -17,7 +17,7 @@
 
 #include "clock.h"
 #include "clock2xxx.h"
-#include "cm2xxx_3xxx.h"
+#include <linux/power/omap/cm2xxx_3xxx.h>
 #include "cm-regbits-24xx.h"
 
 /* Private functions */
diff --git a/arch/arm/mach-omap2/clock3xxx.c b/arch/arm/mach-omap2/clock3xxx.c
index 0b02b41..4706f2f 100644
--- a/arch/arm/mach-omap2/clock3xxx.c
+++ b/arch/arm/mach-omap2/clock3xxx.c
@@ -26,7 +26,7 @@
 #include "clock3xxx.h"
 #include "prm2xxx_3xxx.h"
 #include "prm-regbits-34xx.h"
-#include "cm2xxx_3xxx.h"
+#include <linux/power/omap/cm2xxx_3xxx.h>
 #include "cm-regbits-34xx.h"
 
 /*
diff --git a/arch/arm/mach-omap2/clockdomains2420_data.c b/arch/arm/mach-omap2/clockdomains2420_data.c
index 7e76bec..7931fd1 100644
--- a/arch/arm/mach-omap2/clockdomains2420_data.c
+++ b/arch/arm/mach-omap2/clockdomains2420_data.c
@@ -38,7 +38,7 @@
 #include "soc.h"
 #include "clockdomain.h"
 #include "prm2xxx_3xxx.h"
-#include "cm2xxx_3xxx.h"
+#include <linux/power/omap/cm2xxx_3xxx.h>
 #include "cm-regbits-24xx.h"
 #include "prm-regbits-24xx.h"
 
diff --git a/arch/arm/mach-omap2/clockdomains2430_data.c b/arch/arm/mach-omap2/clockdomains2430_data.c
index b923007..2e3918c 100644
--- a/arch/arm/mach-omap2/clockdomains2430_data.c
+++ b/arch/arm/mach-omap2/clockdomains2430_data.c
@@ -38,7 +38,7 @@
 #include "soc.h"
 #include "clockdomain.h"
 #include "prm2xxx_3xxx.h"
-#include "cm2xxx_3xxx.h"
+#include <linux/power/omap/cm2xxx_3xxx.h>
 #include "cm-regbits-24xx.h"
 #include "prm-regbits-24xx.h"
 
diff --git a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
index 4972219..b728d6e 100644
--- a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
+++ b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
@@ -37,7 +37,7 @@
 
 #include "clockdomain.h"
 #include "prm2xxx_3xxx.h"
-#include "cm2xxx_3xxx.h"
+#include <linux/power/omap/cm2xxx_3xxx.h>
 #include "cm-regbits-24xx.h"
 #include "cm-regbits-34xx.h"
 #include "cm-regbits-44xx.h"
diff --git a/arch/arm/mach-omap2/clockdomains3xxx_data.c b/arch/arm/mach-omap2/clockdomains3xxx_data.c
index e6b91e5..27851ac 100644
--- a/arch/arm/mach-omap2/clockdomains3xxx_data.c
+++ b/arch/arm/mach-omap2/clockdomains3xxx_data.c
@@ -36,7 +36,7 @@
 #include "soc.h"
 #include "clockdomain.h"
 #include "prm2xxx_3xxx.h"
-#include "cm2xxx_3xxx.h"
+#include <linux/power/omap/cm2xxx_3xxx.h>
 #include "cm-regbits-34xx.h"
 #include "prm-regbits-34xx.h"
 
diff --git a/arch/arm/mach-omap2/cm2xxx.h b/arch/arm/mach-omap2/cm2xxx.h
index 5eaa007..80e9892 100644
--- a/arch/arm/mach-omap2/cm2xxx.h
+++ b/arch/arm/mach-omap2/cm2xxx.h
@@ -17,7 +17,7 @@
 #define __ARCH_ASM_MACH_OMAP2_CM2XXX_H
 
 #include "prcm-common.h"
-#include "cm2xxx_3xxx.h"
+#include <linux/power/omap/cm2xxx_3xxx.h>
 #include <linux/power/omap/cm2xxx.h>
 
 #define OMAP2420_CM_REGADDR(module, reg)				\
diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.h b/arch/arm/mach-omap2/cm2xxx_3xxx.h
deleted file mode 100644
index b40b5bd..0000000
--- a/arch/arm/mach-omap2/cm2xxx_3xxx.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * OMAP2/3 Clock Management (CM) register definitions
- *
- * Copyright (C) 2007-2009 Texas Instruments, Inc.
- * Copyright (C) 2007-2010 Nokia Corporation
- * Paul Walmsley
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * The CM hardware modules on the OMAP2/3 are quite similar to each
- * other.  The CM modules/instances on OMAP4 are quite different, so
- * they are handled in a separate file.
- */
-#ifndef __ARCH_ASM_MACH_OMAP2_CM2XXX_3XXX_H
-#define __ARCH_ASM_MACH_OMAP2_CM2XXX_3XXX_H
-
-#include "cm.h"
-
-/*
- * Module specific CM register offsets from CM_BASE + domain offset
- * Use cm_{read,write}_mod_reg() with these registers.
- * These register offsets generally appear in more than one PRCM submodule.
- */
-
-/* Common between OMAP2 and OMAP3 */
-
-#define CM_FCLKEN					0x0000
-#define CM_FCLKEN1					CM_FCLKEN
-#define CM_CLKEN					CM_FCLKEN
-#define CM_ICLKEN					0x0010
-#define CM_ICLKEN1					CM_ICLKEN
-#define CM_ICLKEN2					0x0014
-#define CM_ICLKEN3					0x0018
-#define CM_IDLEST					0x0020
-#define CM_IDLEST1					CM_IDLEST
-#define CM_IDLEST2					0x0024
-#define OMAP2430_CM_IDLEST3				0x0028
-#define CM_AUTOIDLE					0x0030
-#define CM_AUTOIDLE1					CM_AUTOIDLE
-#define CM_AUTOIDLE2					0x0034
-#define CM_AUTOIDLE3					0x0038
-#define CM_CLKSEL					0x0040
-#define CM_CLKSEL1					CM_CLKSEL
-#define CM_CLKSEL2					0x0044
-#define OMAP2_CM_CLKSTCTRL				0x0048
-
-#ifndef __ASSEMBLER__
-
-extern int omap2xxx_cm_apll54_enable(void);
-extern void omap2xxx_cm_apll54_disable(void);
-extern int omap2xxx_cm_apll96_enable(void);
-extern void omap2xxx_cm_apll96_disable(void);
-
-#endif
-
-/* CM register bits shared between 24XX and 3430 */
-
-/* CM_CLKSEL_GFX */
-#define OMAP_CLKSEL_GFX_SHIFT				0
-#define OMAP_CLKSEL_GFX_MASK				(0x7 << 0)
-#define OMAP_CLKSEL_GFX_WIDTH				3
-
-/* CM_ICLKEN_GFX */
-#define OMAP_EN_GFX_SHIFT				0
-#define OMAP_EN_GFX_MASK				(1 << 0)
-
-/* CM_IDLEST_GFX */
-#define OMAP_ST_GFX_MASK				(1 << 0)
-
-#endif
diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx_private.h b/arch/arm/mach-omap2/cm2xxx_3xxx_private.h
index 9131829..ca7ca94 100644
--- a/arch/arm/mach-omap2/cm2xxx_3xxx_private.h
+++ b/arch/arm/mach-omap2/cm2xxx_3xxx_private.h
@@ -17,7 +17,7 @@
 #define __ARCH_ARM_MACH_OMAP2_CM2XXX_3XXX_PRIVATE_H
 
 #include "cm.h"
-#include "cm2xxx_3xxx.h"
+#include <linux/power/omap/cm2xxx_3xxx.h>
 
 #ifndef __ASSEMBLER__
 
diff --git a/arch/arm/mach-omap2/cm3xxx.h b/arch/arm/mach-omap2/cm3xxx.h
index 9c2047f..5fdc14c 100644
--- a/arch/arm/mach-omap2/cm3xxx.h
+++ b/arch/arm/mach-omap2/cm3xxx.h
@@ -17,7 +17,7 @@
 #define __ARCH_ASM_MACH_OMAP2_CM3XXX_H
 
 #include "prcm-common.h"
-#include "cm2xxx_3xxx.h"
+#include <linux/power/omap/cm2xxx_3xxx.h>
 #include <linux/power/omap/cm3xxx.h>
 
 #define OMAP34XX_CM_REGADDR(module, reg)				\
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index 3185ced..79ce6e8 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -31,7 +31,7 @@
 #include "soc.h"
 #include "clockdomain.h"
 #include "clock.h"
-#include "cm2xxx_3xxx.h"
+#include <linux/power/omap/cm2xxx_3xxx.h>
 #include "cm-regbits-34xx.h"
 
 /* CM_AUTOIDLE_PLL*.AUTO_* bit values */
diff --git a/arch/arm/mach-omap2/dsp.c b/arch/arm/mach-omap2/dsp.c
index b8208b4..1d802fe 100644
--- a/arch/arm/mach-omap2/dsp.c
+++ b/arch/arm/mach-omap2/dsp.c
@@ -24,7 +24,7 @@
 #include <asm/memblock.h>
 
 #include "control.h"
-#include "cm2xxx_3xxx.h"
+#include <linux/power/omap/cm2xxx_3xxx.h>
 #include "prm2xxx_3xxx.h"
 #ifdef CONFIG_TIDSPBRIDGE_DVFS
 #include "omap-pm.h"
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index 0b33986..95f28b2 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -33,7 +33,7 @@
 #include "omap-pm.h"
 
 #include "soc.h"
-#include "cm2xxx_3xxx.h"
+#include <linux/power/omap/cm2xxx_3xxx.h>
 #include "prm2xxx_3xxx.h"
 #include "pm.h"
 
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 62649ba..e532d2b 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -22,7 +22,7 @@
 #include <linux/spinlock.h>
 #include <trace/events/power.h>
 
-#include "cm2xxx_3xxx.h"
+#include <linux/power/omap/cm2xxx_3xxx.h>
 #include "prcm44xx.h"
 #include "prm2xxx_3xxx.h"
 #include "prm44xx.h"
diff --git a/arch/arm/mach-omap2/powerdomains3xxx_data.c b/arch/arm/mach-omap2/powerdomains3xxx_data.c
index 328c103..9db6a8e 100644
--- a/arch/arm/mach-omap2/powerdomains3xxx_data.c
+++ b/arch/arm/mach-omap2/powerdomains3xxx_data.c
@@ -21,7 +21,7 @@
 #include "prcm-common.h"
 #include "prm2xxx_3xxx.h"
 #include "prm-regbits-34xx.h"
-#include "cm2xxx_3xxx.h"
+#include <linux/power/omap/cm2xxx_3xxx.h>
 #include "cm-regbits-34xx.h"
 
 /*
diff --git a/arch/arm/mach-omap2/prm2xxx.c b/arch/arm/mach-omap2/prm2xxx.c
index 7264ae6..5b5260c 100644
--- a/arch/arm/mach-omap2/prm2xxx.c
+++ b/arch/arm/mach-omap2/prm2xxx.c
@@ -22,7 +22,7 @@
 #include "clockdomain.h"
 #include "prm2xxx.h"
 #include "prm2xxx_3xxx_private.h"
-#include "cm2xxx_3xxx.h"
+#include <linux/power/omap/cm2xxx_3xxx.h>
 
 #define OMAP24XX_FORCESTATE_MASK		(1 << 18)
 #define OMAP24XX_AUTOIDLE_MASK			(1 << 0)
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index a388f8c..90e06b3 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -36,7 +36,7 @@
 #include "soc.h"
 #include "prm2xxx_3xxx.h"
 #include "pm.h"
-#include "cm2xxx_3xxx.h"
+#include <linux/power/omap/cm2xxx_3xxx.h>
 #include "prm-regbits-34xx.h"
 #include "control.h"
 #include "mux.h"
diff --git a/include/linux/power/omap/cm2xxx_3xxx.h b/include/linux/power/omap/cm2xxx_3xxx.h
new file mode 100644
index 0000000..c4a8ea7
--- /dev/null
+++ b/include/linux/power/omap/cm2xxx_3xxx.h
@@ -0,0 +1,70 @@
+/*
+ * OMAP2/3 Clock Management (CM) register definitions
+ *
+ * Copyright (C) 2007-2009 Texas Instruments, Inc.
+ * Copyright (C) 2007-2010 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * The CM hardware modules on the OMAP2/3 are quite similar to each
+ * other.  The CM modules/instances on OMAP4 are quite different, so
+ * they are handled in a separate file.
+ */
+#ifndef __LINUX_POWER_OMAP_CM2XXX_3XXX_H
+#define __LINUX_POWER_OMAP_CM2XXX_3XXX_H
+
+/*
+ * Module specific CM register offsets from CM_BASE + domain offset
+ * Use cm_{read,write}_mod_reg() with these registers.
+ * These register offsets generally appear in more than one PRCM submodule.
+ */
+
+/* Common between OMAP2 and OMAP3 */
+
+#define CM_FCLKEN					0x0000
+#define CM_FCLKEN1					CM_FCLKEN
+#define CM_CLKEN					CM_FCLKEN
+#define CM_ICLKEN					0x0010
+#define CM_ICLKEN1					CM_ICLKEN
+#define CM_ICLKEN2					0x0014
+#define CM_ICLKEN3					0x0018
+#define CM_IDLEST					0x0020
+#define CM_IDLEST1					CM_IDLEST
+#define CM_IDLEST2					0x0024
+#define OMAP2430_CM_IDLEST3				0x0028
+#define CM_AUTOIDLE					0x0030
+#define CM_AUTOIDLE1					CM_AUTOIDLE
+#define CM_AUTOIDLE2					0x0034
+#define CM_AUTOIDLE3					0x0038
+#define CM_CLKSEL					0x0040
+#define CM_CLKSEL1					CM_CLKSEL
+#define CM_CLKSEL2					0x0044
+#define OMAP2_CM_CLKSTCTRL				0x0048
+
+#ifndef __ASSEMBLER__
+
+int omap2xxx_cm_apll54_enable(void);
+void omap2xxx_cm_apll54_disable(void);
+int omap2xxx_cm_apll96_enable(void);
+void omap2xxx_cm_apll96_disable(void);
+
+#endif
+
+/* CM register bits shared between 24XX and 3430 */
+
+/* CM_CLKSEL_GFX */
+#define OMAP_CLKSEL_GFX_SHIFT				0
+#define OMAP_CLKSEL_GFX_MASK				(0x7 << 0)
+#define OMAP_CLKSEL_GFX_WIDTH				3
+
+/* CM_ICLKEN_GFX */
+#define OMAP_EN_GFX_SHIFT				0
+#define OMAP_EN_GFX_MASK				(1 << 0)
+
+/* CM_IDLEST_GFX */
+#define OMAP_ST_GFX_MASK				(1 << 0)
+
+#endif
-- 
1.7.9.5

[PATCH 27/55] ARM: OMAP4+: CM: remove unused cm_44xx_54xx.h header file

[Tero Kristo]

This is not used for anything, so removed.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/cm1_44xx.h     |    2 --
 arch/arm/mach-omap2/cm1_54xx.h     |    2 --
 arch/arm/mach-omap2/cm1_7xx.h      |    2 --
 arch/arm/mach-omap2/cm2_44xx.h     |    2 --
 arch/arm/mach-omap2/cm2_54xx.h     |    2 --
 arch/arm/mach-omap2/cm2_7xx.h      |    2 --
 arch/arm/mach-omap2/cm_44xx_54xx.h |   36 ------------------------------------
 7 files changed, 48 deletions(-)
 delete mode 100644 arch/arm/mach-omap2/cm_44xx_54xx.h

diff --git a/arch/arm/mach-omap2/cm1_44xx.h b/arch/arm/mach-omap2/cm1_44xx.h
index 5ae8fe3..a594992 100644
--- a/arch/arm/mach-omap2/cm1_44xx.h
+++ b/arch/arm/mach-omap2/cm1_44xx.h
@@ -25,8 +25,6 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_CM1_44XX_H
 #define __ARCH_ARM_MACH_OMAP2_CM1_44XX_H
 
-#include "cm_44xx_54xx.h"
-
 /* CM1 base address */
 #define OMAP4430_CM1_BASE		0x4a004000
 
diff --git a/arch/arm/mach-omap2/cm1_54xx.h b/arch/arm/mach-omap2/cm1_54xx.h
index 90b3348..fd245df 100644
--- a/arch/arm/mach-omap2/cm1_54xx.h
+++ b/arch/arm/mach-omap2/cm1_54xx.h
@@ -22,8 +22,6 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_CM1_54XX_H
 #define __ARCH_ARM_MACH_OMAP2_CM1_54XX_H
 
-#include "cm_44xx_54xx.h"
-
 /* CM1 base address */
 #define OMAP54XX_CM_CORE_AON_BASE		0x4a004000
 
diff --git a/arch/arm/mach-omap2/cm1_7xx.h b/arch/arm/mach-omap2/cm1_7xx.h
index ca6fa1f..2f1c09e 100644
--- a/arch/arm/mach-omap2/cm1_7xx.h
+++ b/arch/arm/mach-omap2/cm1_7xx.h
@@ -23,8 +23,6 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_CM1_7XX_H
 #define __ARCH_ARM_MACH_OMAP2_CM1_7XX_H
 
-#include "cm_44xx_54xx.h"
-
 /* CM1 base address */
 #define DRA7XX_CM_CORE_AON_BASE		0x4a005000
 
diff --git a/arch/arm/mach-omap2/cm2_44xx.h b/arch/arm/mach-omap2/cm2_44xx.h
index ee5136d..7521abf 100644
--- a/arch/arm/mach-omap2/cm2_44xx.h
+++ b/arch/arm/mach-omap2/cm2_44xx.h
@@ -25,8 +25,6 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_CM2_44XX_H
 #define __ARCH_ARM_MACH_OMAP2_CM2_44XX_H
 
-#include "cm_44xx_54xx.h"
-
 /* CM2 base address */
 #define OMAP4430_CM2_BASE		0x4a008000
 
diff --git a/arch/arm/mach-omap2/cm2_54xx.h b/arch/arm/mach-omap2/cm2_54xx.h
index 2683231..ff4040c 100644
--- a/arch/arm/mach-omap2/cm2_54xx.h
+++ b/arch/arm/mach-omap2/cm2_54xx.h
@@ -21,8 +21,6 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_CM2_54XX_H
 #define __ARCH_ARM_MACH_OMAP2_CM2_54XX_H
 
-#include "cm_44xx_54xx.h"
-
 /* CM2 base address */
 #define OMAP54XX_CM_CORE_BASE		0x4a008000
 
diff --git a/arch/arm/mach-omap2/cm2_7xx.h b/arch/arm/mach-omap2/cm2_7xx.h
index 9ad7594..ef00a9d 100644
--- a/arch/arm/mach-omap2/cm2_7xx.h
+++ b/arch/arm/mach-omap2/cm2_7xx.h
@@ -22,8 +22,6 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_CM2_7XX_H
 #define __ARCH_ARM_MACH_OMAP2_CM2_7XX_H
 
-#include "cm_44xx_54xx.h"
-
 /* CM2 base address */
 #define DRA7XX_CM_CORE_BASE		0x4a008000
 
diff --git a/arch/arm/mach-omap2/cm_44xx_54xx.h b/arch/arm/mach-omap2/cm_44xx_54xx.h
deleted file mode 100644
index cbb2116..0000000
--- a/arch/arm/mach-omap2/cm_44xx_54xx.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * OMAP44xx and OMAP54xx CM1/CM2 function prototypes
- *
- * Copyright (C) 2009-2013 Texas Instruments, Inc.
- * Copyright (C) 2009-2010 Nokia Corporation
- *
- * Paul Walmsley (paul@pwsan.com)
- * Rajendra Nayak (rnayak@ti.com)
- * Benoit Cousson (b-cousson@ti.com)
- *
- * This file is automatically generated from the OMAP hardware databases.
- * We respectfully ask that any modifications to this file be coordinated
- * with the public linux-omap@vger.kernel.org mailing list and the
- * authors above to ensure that the autogeneration scripts are kept
- * up-to-date with the file contents.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef __ARCH_ARM_MACH_OMAP2_CM_44XX_54XX_H
-#define __ARCH_ARM_MACH_OMAP2_CM_44XX_55XX_H
-
-/* CM1 Function prototypes */
-extern u32 omap4_cm1_read_inst_reg(s16 inst, u16 idx);
-extern void omap4_cm1_write_inst_reg(u32 val, s16 inst, u16 idx);
-extern u32 omap4_cm1_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
-
-/* CM2 Function prototypes */
-extern u32 omap4_cm2_read_inst_reg(s16 inst, u16 idx);
-extern void omap4_cm2_write_inst_reg(u32 val, s16 inst, u16 idx);
-extern u32 omap4_cm2_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
-
-#endif
-- 
1.7.9.5

[PATCH 28/55] ARM: OMAP4: CM: make all omap4_cminst_read/write calls static

[Tero Kristo]

These are not used outside the cminst44xx.c anymore, thus make them static.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/cminst44xx.c |   23 +++++++++++------------
 arch/arm/mach-omap2/cminst44xx.h |   14 --------------
 2 files changed, 11 insertions(+), 26 deletions(-)

diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c
index dfb1a93..20681de 100644
--- a/arch/arm/mach-omap2/cminst44xx.c
+++ b/arch/arm/mach-omap2/cminst44xx.c
@@ -80,6 +80,8 @@ void omap_cm_base_init(void)
 
 /* Private functions */
 
+static u32 omap4_cminst_read_inst_reg(u8 part, u16 inst, u16 idx);
+
 /**
  * _clkctrl_idlest - read a CM_*_CLKCTRL register; mask & shift IDLEST bitfield
  * @part: PRCM partition ID that the CM_CLKCTRL register exists in
@@ -118,10 +120,8 @@ static bool _is_module_ready(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs)
 		v == CLKCTRL_IDLEST_INTERFACE_IDLE) ? true : false;
 }
 
-/* Public functions */
-
 /* Read a register in a CM instance */
-u32 omap4_cminst_read_inst_reg(u8 part, u16 inst, u16 idx)
+static u32 omap4_cminst_read_inst_reg(u8 part, u16 inst, u16 idx)
 {
 	BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
 	       part == OMAP4430_INVALID_PRCM_PARTITION ||
@@ -130,7 +130,7 @@ u32 omap4_cminst_read_inst_reg(u8 part, u16 inst, u16 idx)
 }
 
 /* Write into a register in a CM instance */
-void omap4_cminst_write_inst_reg(u32 val, u8 part, u16 inst, u16 idx)
+static void omap4_cminst_write_inst_reg(u32 val, u8 part, u16 inst, u16 idx)
 {
 	BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
 	       part == OMAP4430_INVALID_PRCM_PARTITION ||
@@ -139,8 +139,8 @@ void omap4_cminst_write_inst_reg(u32 val, u8 part, u16 inst, u16 idx)
 }
 
 /* Read-modify-write a register in CM1. Caller must lock */
-u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, u16 inst,
-				   s16 idx)
+static u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, u16 inst,
+					  s16 idx)
 {
 	u32 v;
 
@@ -152,17 +152,18 @@ u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, u16 inst,
 	return v;
 }
 
-u32 omap4_cminst_set_inst_reg_bits(u32 bits, u8 part, u16 inst, s16 idx)
+static u32 omap4_cminst_set_inst_reg_bits(u32 bits, u8 part, u16 inst, s16 idx)
 {
 	return omap4_cminst_rmw_inst_reg_bits(bits, bits, part, inst, idx);
 }
 
-u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, u16 inst, s16 idx)
+static u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, u16 inst,
+					    s16 idx)
 {
 	return omap4_cminst_rmw_inst_reg_bits(bits, 0x0, part, inst, idx);
 }
 
-u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, s16 idx, u32 mask)
+static u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, s16 idx, u32 mask)
 {
 	u32 v;
 
@@ -173,9 +174,7 @@ u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, s16 idx, u32 mask)
 	return v;
 }
 
-/*
- *
- */
+/* Public functions */
 
 /**
  * _clktrctrl_write - write @c to a CM_CLKSTCTRL.CLKTRCTRL register bitfield
diff --git a/arch/arm/mach-omap2/cminst44xx.h b/arch/arm/mach-omap2/cminst44xx.h
index 7f56ea4..ad06525 100644
--- a/arch/arm/mach-omap2/cminst44xx.h
+++ b/arch/arm/mach-omap2/cminst44xx.h
@@ -23,20 +23,6 @@ extern void omap4_cminst_module_enable(u8 mode, u8 part, u16 inst, s16 cdoffs,
 				       u16 clkctrl_offs);
 extern void omap4_cminst_module_disable(u8 part, u16 inst, s16 cdoffs,
 					u16 clkctrl_offs);
-/*
- * In an ideal world, we would not export these low-level functions,
- * but this will probably take some time to fix properly
- */
-u32 omap4_cminst_read_inst_reg(u8 part, u16 inst, u16 idx);
-void omap4_cminst_write_inst_reg(u32 val, u8 part, u16 inst, u16 idx);
-u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part,
-				   u16 inst, s16 idx);
-u32 omap4_cminst_set_inst_reg_bits(u32 bits, u8 part, u16 inst,
-				   s16 idx);
-u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, u16 inst,
-				     s16 idx);
-extern u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, s16 idx,
-					   u32 mask);
 
 extern void omap_cm_base_init(void);
 
-- 
1.7.9.5

[PATCH 29/55] ARM: OMAP4: CM: rename cminst44xx.h to cm44xx.h and move it to public location

[Tero Kristo]

The new name follows the naming convention of the other public CM header
files.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/cminst44xx.c  |    2 +-
 arch/arm/mach-omap2/cminst44xx.h  |   29 -----------------------------
 arch/arm/mach-omap2/io.c          |    2 +-
 arch/arm/mach-omap2/omap_hwmod.c  |    2 +-
 include/linux/power/omap/cm44xx.h |   30 ++++++++++++++++++++++++++++++
 5 files changed, 33 insertions(+), 32 deletions(-)
 delete mode 100644 arch/arm/mach-omap2/cminst44xx.h
 create mode 100644 include/linux/power/omap/cm44xx.h

diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c
index 20681de..2f780df 100644
--- a/arch/arm/mach-omap2/cminst44xx.c
+++ b/arch/arm/mach-omap2/cminst44xx.c
@@ -25,7 +25,7 @@
 #include "cm.h"
 #include "cm1_44xx.h"
 #include "cm2_44xx.h"
-#include "cminst44xx.h"
+#include <linux/power/omap/cm44xx.h>
 #include "prcm44xx.h"
 #include "prm44xx.h"
 #include "prcm_mpu44xx.h"
diff --git a/arch/arm/mach-omap2/cminst44xx.h b/arch/arm/mach-omap2/cminst44xx.h
deleted file mode 100644
index ad06525..0000000
--- a/arch/arm/mach-omap2/cminst44xx.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * OMAP4 Clock Management (CM) function prototypes
- *
- * Copyright (C) 2010 Nokia Corporation
- * Paul Walmsley
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __ARCH_ASM_MACH_OMAP2_CMINST44XX_H
-#define __ARCH_ASM_MACH_OMAP2_CMINST44XX_H
-
-bool omap4_cminst_is_clkdm_in_hwsup(u8 part, u16 inst, u16 cdoffs);
-void omap4_cminst_clkdm_enable_hwsup(u8 part, u16 inst, u16 cdoffs);
-void omap4_cminst_clkdm_disable_hwsup(u8 part, u16 inst, u16 cdoffs);
-void omap4_cminst_clkdm_force_sleep(u8 part, u16 inst, u16 cdoffs);
-void omap4_cminst_clkdm_force_wakeup(u8 part, u16 inst, u16 cdoffs);
-extern int omap4_cminst_wait_module_ready(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs);
-extern int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs,
-					 u16 clkctrl_offs);
-extern void omap4_cminst_module_enable(u8 mode, u8 part, u16 inst, s16 cdoffs,
-				       u16 clkctrl_offs);
-extern void omap4_cminst_module_disable(u8 part, u16 inst, s16 cdoffs,
-					u16 clkctrl_offs);
-
-extern void omap_cm_base_init(void);
-
-#endif
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index dfba898..6212c10 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -49,7 +49,7 @@
 #include "cm.h"
 #include "prcm_mpu44xx.h"
 #include "prminst44xx.h"
-#include "cminst44xx.h"
+#include <linux/power/omap/cm44xx.h>
 #include "prm2xxx.h"
 #include "prm3xxx.h"
 #include "prm44xx.h"
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 54c24e1..4576f0b 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -153,7 +153,7 @@
 #include "powerdomain.h"
 #include "cm2xxx.h"
 #include "cm3xxx.h"
-#include "cminst44xx.h"
+#include <linux/power/omap/cm44xx.h>
 #include "cm33xx.h"
 #include "prm.h"
 #include "prm3xxx.h"
diff --git a/include/linux/power/omap/cm44xx.h b/include/linux/power/omap/cm44xx.h
new file mode 100644
index 0000000..eda5670
--- /dev/null
+++ b/include/linux/power/omap/cm44xx.h
@@ -0,0 +1,30 @@
+/*
+ * OMAP4 Clock Management (CM) function prototypes
+ *
+ * Copyright (C) 2010 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __LINUX_POWER_OMAP_CM44XX_H
+#define __LINUX_POWER_OMAP_CM44XX_H
+
+bool omap4_cminst_is_clkdm_in_hwsup(u8 part, u16 inst, u16 cdoffs);
+void omap4_cminst_clkdm_enable_hwsup(u8 part, u16 inst, u16 cdoffs);
+void omap4_cminst_clkdm_disable_hwsup(u8 part, u16 inst, u16 cdoffs);
+void omap4_cminst_clkdm_force_sleep(u8 part, u16 inst, u16 cdoffs);
+void omap4_cminst_clkdm_force_wakeup(u8 part, u16 inst, u16 cdoffs);
+int omap4_cminst_wait_module_ready(u8 part, u16 inst, s16 cdoffs,
+				   u16 clkctrl_offs);
+int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs,
+				  u16 clkctrl_offs);
+void omap4_cminst_module_enable(u8 mode, u8 part, u16 inst, s16 cdoffs,
+				u16 clkctrl_offs);
+void omap4_cminst_module_disable(u8 part, u16 inst, s16 cdoffs,
+				 u16 clkctrl_offs);
+
+void omap_cm_base_init(void);
+
+#endif
-- 
1.7.9.5

[PATCH 30/55] ARM: OMAP2+: CM: move cm.h header to public location

[Tero Kristo]

This file needs to be accessible from the PRCM core and mach-omap2 board
support code.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/clock.c                 |    2 +-
 arch/arm/mach-omap2/clock2xxx.c             |    2 +-
 arch/arm/mach-omap2/clockdomains33xx_data.c |    2 +-
 arch/arm/mach-omap2/cm.h                    |   64 ---------------------------
 arch/arm/mach-omap2/cm2xxx.c                |    2 +-
 arch/arm/mach-omap2/cm2xxx_3xxx_private.h   |    2 +-
 arch/arm/mach-omap2/cm33xx.c                |    2 +-
 arch/arm/mach-omap2/cm33xx.h                |    2 +-
 arch/arm/mach-omap2/cm3xxx.c                |    2 +-
 arch/arm/mach-omap2/cm44xx.c                |    2 +-
 arch/arm/mach-omap2/cm_common.c             |    2 +-
 arch/arm/mach-omap2/cminst44xx.c            |    2 +-
 arch/arm/mach-omap2/io.c                    |    2 +-
 arch/arm/mach-omap2/powerdomain-common.c    |    2 +-
 include/linux/power/omap/cm.h               |   64 +++++++++++++++++++++++++++
 15 files changed, 77 insertions(+), 77 deletions(-)
 delete mode 100644 arch/arm/mach-omap2/cm.h
 create mode 100644 include/linux/power/omap/cm.h

diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 4ac6e3d..4276c46 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -31,7 +31,7 @@
 #include "soc.h"
 #include "clockdomain.h"
 #include "clock.h"
-#include "cm.h"
+#include <linux/power/omap/cm.h>
 #include "cm2xxx.h"
 #include "cm3xxx.h"
 #include "cm-regbits-24xx.h"
diff --git a/arch/arm/mach-omap2/clock2xxx.c b/arch/arm/mach-omap2/clock2xxx.c
index b870f6a..4c996dd 100644
--- a/arch/arm/mach-omap2/clock2xxx.c
+++ b/arch/arm/mach-omap2/clock2xxx.c
@@ -25,7 +25,7 @@
 #include "soc.h"
 #include "clock.h"
 #include "clock2xxx.h"
-#include "cm.h"
+#include <linux/power/omap/cm.h>
 #include "cm-regbits-24xx.h"
 
 struct clk_hw *dclk_hw;
diff --git a/arch/arm/mach-omap2/clockdomains33xx_data.c b/arch/arm/mach-omap2/clockdomains33xx_data.c
index 32c90fd..e86f84e 100644
--- a/arch/arm/mach-omap2/clockdomains33xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains33xx_data.c
@@ -18,7 +18,7 @@
 #include <linux/io.h>
 
 #include "clockdomain.h"
-#include "cm.h"
+#include <linux/power/omap/cm.h>
 #include "cm33xx.h"
 #include "cm-regbits-33xx.h"
 
diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h
deleted file mode 100644
index 93473f9..0000000
--- a/arch/arm/mach-omap2/cm.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * OMAP2+ Clock Management prototypes
- *
- * Copyright (C) 2007-2009, 2012 Texas Instruments, Inc.
- * Copyright (C) 2007-2009 Nokia Corporation
- *
- * Written by Paul Walmsley
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __ARCH_ASM_MACH_OMAP2_CM_H
-#define __ARCH_ASM_MACH_OMAP2_CM_H
-
-/*
- * MAX_MODULE_READY_TIME: max duration in microseconds to wait for the
- * PRCM to request that a module exit the inactive state in the case of
- * OMAP2 & 3.
- * In the case of OMAP4 this is the max duration in microseconds for the
- * module to reach the functionnal state from an inactive state.
- */
-#define MAX_MODULE_READY_TIME		2000
-
-# ifndef __ASSEMBLER__
-extern void __iomem *cm_base;
-extern void __iomem *cm2_base;
-extern void omap2_set_globals_cm(void __iomem *cm, void __iomem *cm2);
-# endif
-
-/*
- * MAX_MODULE_DISABLE_TIME: max duration in microseconds to wait for
- * the PRCM to request that a module enter the inactive state in the
- * case of OMAP2 & 3.  In the case of OMAP4 this is the max duration
- * in microseconds for the module to reach the inactive state from
- * a functional state.
- * XXX FSUSB on OMAP4430 takes ~4ms to idle after reset during
- * kernel init.
- */
-#define MAX_MODULE_DISABLE_TIME		5000
-
-# ifndef __ASSEMBLER__
-
-/**
- * struct cm_ll_data - fn ptrs to per-SoC CM function implementations
- * @split_idlest_reg: ptr to the SoC CM-specific split_idlest_reg impl
- * @wait_module_ready: ptr to the SoC CM-specific wait_module_ready impl
- */
-struct cm_ll_data {
-	int (*split_idlest_reg)(void __iomem *idlest_reg, s16 *prcm_inst,
-				u8 *idlest_reg_id);
-	int (*wait_module_ready)(s16 prcm_mod, u8 idlest_id, u8 idlest_shift);
-};
-
-extern int cm_split_idlest_reg(void __iomem *idlest_reg, s16 *prcm_inst,
-			       u8 *idlest_reg_id);
-extern int cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift);
-
-extern int cm_register(struct cm_ll_data *cld);
-extern int cm_unregister(struct cm_ll_data *cld);
-
-# endif
-
-#endif
diff --git a/arch/arm/mach-omap2/cm2xxx.c b/arch/arm/mach-omap2/cm2xxx.c
index 6f04031..f4a070c 100644
--- a/arch/arm/mach-omap2/cm2xxx.c
+++ b/arch/arm/mach-omap2/cm2xxx.c
@@ -19,7 +19,7 @@
 #include <linux/io.h>
 
 #include "prm2xxx.h"
-#include "cm.h"
+#include <linux/power/omap/cm.h>
 #include "cm2xxx_3xxx_private.h"
 #include <linux/power/omap/cm2xxx.h>
 #include "clockdomain.h"
diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx_private.h b/arch/arm/mach-omap2/cm2xxx_3xxx_private.h
index ca7ca94..a28dff0 100644
--- a/arch/arm/mach-omap2/cm2xxx_3xxx_private.h
+++ b/arch/arm/mach-omap2/cm2xxx_3xxx_private.h
@@ -16,7 +16,7 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_CM2XXX_3XXX_PRIVATE_H
 #define __ARCH_ARM_MACH_OMAP2_CM2XXX_3XXX_PRIVATE_H
 
-#include "cm.h"
+#include <linux/power/omap/cm.h>
 #include <linux/power/omap/cm2xxx_3xxx.h>
 
 #ifndef __ASSEMBLER__
diff --git a/arch/arm/mach-omap2/cm33xx.c b/arch/arm/mach-omap2/cm33xx.c
index 7a7b2e7..7717eeb 100644
--- a/arch/arm/mach-omap2/cm33xx.c
+++ b/arch/arm/mach-omap2/cm33xx.c
@@ -23,7 +23,7 @@
 #include <linux/io.h>
 
 #include "clockdomain.h"
-#include "cm.h"
+#include <linux/power/omap/cm.h>
 #include <linux/power/omap/cm33xx.h>
 #include "prm33xx.h"
 
diff --git a/arch/arm/mach-omap2/cm33xx.h b/arch/arm/mach-omap2/cm33xx.h
index 67f1d49..d8c4278 100644
--- a/arch/arm/mach-omap2/cm33xx.h
+++ b/arch/arm/mach-omap2/cm33xx.h
@@ -17,7 +17,7 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_CM_33XX_H
 #define __ARCH_ARM_MACH_OMAP2_CM_33XX_H
 
-#include "cm.h"
+#include <linux/power/omap/cm.h>
 #include <linux/power/omap/cm33xx.h>
 
 /* CM base address */
diff --git a/arch/arm/mach-omap2/cm3xxx.c b/arch/arm/mach-omap2/cm3xxx.c
index cbba617..0818156 100644
--- a/arch/arm/mach-omap2/cm3xxx.c
+++ b/arch/arm/mach-omap2/cm3xxx.c
@@ -19,7 +19,7 @@
 #include <linux/io.h>
 
 #include "prm2xxx_3xxx.h"
-#include "cm.h"
+#include <linux/power/omap/cm.h>
 #include "cm2xxx_3xxx_private.h"
 #include <linux/power/omap/cm3xxx.h>
 #include "clockdomain.h"
diff --git a/arch/arm/mach-omap2/cm44xx.c b/arch/arm/mach-omap2/cm44xx.c
index c440ba7..506974b 100644
--- a/arch/arm/mach-omap2/cm44xx.c
+++ b/arch/arm/mach-omap2/cm44xx.c
@@ -18,7 +18,7 @@
 #include <linux/err.h>
 #include <linux/io.h>
 
-#include "cm.h"
+#include <linux/power/omap/cm.h>
 #include "cm1_44xx.h"
 #include "cm2_44xx.h"
 
diff --git a/arch/arm/mach-omap2/cm_common.c b/arch/arm/mach-omap2/cm_common.c
index 8655538..3843f1f 100644
--- a/arch/arm/mach-omap2/cm_common.c
+++ b/arch/arm/mach-omap2/cm_common.c
@@ -18,7 +18,7 @@
 
 #include <linux/power/omap/cm2xxx.h>
 #include <linux/power/omap/cm3xxx.h>
-#include "cm.h"
+#include <linux/power/omap/cm.h>
 #include "prcm-common.h"
 
 /*
diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c
index 2f780df..b577a8e 100644
--- a/arch/arm/mach-omap2/cminst44xx.c
+++ b/arch/arm/mach-omap2/cminst44xx.c
@@ -22,7 +22,7 @@
 #include <linux/io.h>
 
 #include "clockdomain.h"
-#include "cm.h"
+#include <linux/power/omap/cm.h>
 #include "cm1_44xx.h"
 #include "cm2_44xx.h"
 #include <linux/power/omap/cm44xx.h>
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 6212c10..ed677bb 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -46,7 +46,7 @@
 #include "cm2xxx.h"
 #include "cm3xxx.h"
 #include "prm.h"
-#include "cm.h"
+#include <linux/power/omap/cm.h>
 #include "prcm_mpu44xx.h"
 #include "prminst44xx.h"
 #include <linux/power/omap/cm44xx.h>
diff --git a/arch/arm/mach-omap2/powerdomain-common.c b/arch/arm/mach-omap2/powerdomain-common.c
index 2c62cd9..8c511e3 100644
--- a/arch/arm/mach-omap2/powerdomain-common.c
+++ b/arch/arm/mach-omap2/powerdomain-common.c
@@ -15,7 +15,7 @@
 #include <linux/kernel.h>
 #include <linux/bug.h>
 #include "pm.h"
-#include "cm.h"
+#include <linux/power/omap/cm.h>
 #include "prm-regbits-34xx.h"
 #include "prm-regbits-44xx.h"
 
diff --git a/include/linux/power/omap/cm.h b/include/linux/power/omap/cm.h
new file mode 100644
index 0000000..cff447a
--- /dev/null
+++ b/include/linux/power/omap/cm.h
@@ -0,0 +1,64 @@
+/*
+ * OMAP2+ Clock Management prototypes
+ *
+ * Copyright (C) 2007-2009, 2012 Texas Instruments, Inc.
+ * Copyright (C) 2007-2009 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __LINUX_POWER_OMAP_CM_H
+#define __LINUX_POWER_OMAP_CM_H
+
+/*
+ * MAX_MODULE_READY_TIME: max duration in microseconds to wait for the
+ * PRCM to request that a module exit the inactive state in the case of
+ * OMAP2 & 3.
+ * In the case of OMAP4 this is the max duration in microseconds for the
+ * module to reach the functionnal state from an inactive state.
+ */
+#define MAX_MODULE_READY_TIME		2000
+
+# ifndef __ASSEMBLER__
+extern void __iomem *cm_base;
+extern void __iomem *cm2_base;
+void omap2_set_globals_cm(void __iomem *cm, void __iomem *cm2);
+# endif
+
+/*
+ * MAX_MODULE_DISABLE_TIME: max duration in microseconds to wait for
+ * the PRCM to request that a module enter the inactive state in the
+ * case of OMAP2 & 3.  In the case of OMAP4 this is the max duration
+ * in microseconds for the module to reach the inactive state from
+ * a functional state.
+ * XXX FSUSB on OMAP4430 takes ~4ms to idle after reset during
+ * kernel init.
+ */
+#define MAX_MODULE_DISABLE_TIME		5000
+
+# ifndef __ASSEMBLER__
+
+/**
+ * struct cm_ll_data - fn ptrs to per-SoC CM function implementations
+ * @split_idlest_reg: ptr to the SoC CM-specific split_idlest_reg impl
+ * @wait_module_ready: ptr to the SoC CM-specific wait_module_ready impl
+ */
+struct cm_ll_data {
+	int (*split_idlest_reg)(void __iomem *idlest_reg, s16 *prcm_inst,
+				u8 *idlest_reg_id);
+	int (*wait_module_ready)(s16 prcm_mod, u8 idlest_id, u8 idlest_shift);
+};
+
+int cm_split_idlest_reg(void __iomem *idlest_reg, s16 *prcm_inst,
+			u8 *idlest_reg_id);
+int cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift);
+
+int cm_register(struct cm_ll_data *cld);
+int cm_unregister(struct cm_ll_data *cld);
+
+# endif
+
+#endif
-- 
1.7.9.5

[PATCH 31/55] ARM: OMAP2: export parts of prm2xxx.h header file

[Tero Kristo]

Some of these are shared between the PRM driver and mach-omap2 board code.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/cm2xxx.c       |    4 +++-
 arch/arm/mach-omap2/prm2xxx.c      |    2 +-
 arch/arm/mach-omap2/prm2xxx.h      |   20 +-----------------
 arch/arm/mach-omap2/prm_common.c   |    2 +-
 include/linux/power/omap/prm2xxx.h |   39 ++++++++++++++++++++++++++++++++++++
 5 files changed, 45 insertions(+), 22 deletions(-)
 create mode 100644 include/linux/power/omap/prm2xxx.h

diff --git a/arch/arm/mach-omap2/cm2xxx.c b/arch/arm/mach-omap2/cm2xxx.c
index f4a070c..b37783a 100644
--- a/arch/arm/mach-omap2/cm2xxx.c
+++ b/arch/arm/mach-omap2/cm2xxx.c
@@ -18,11 +18,13 @@
 #include <linux/err.h>
 #include <linux/io.h>
 
-#include "prm2xxx.h"
+#include <linux/power/omap/prm2xxx.h>
 #include <linux/power/omap/cm.h>
 #include "cm2xxx_3xxx_private.h"
 #include <linux/power/omap/cm2xxx.h>
 #include "clockdomain.h"
+#include "prcm-common.h"
+#include "prm2xxx_3xxx.h"
 
 /* CM_AUTOIDLE_PLL.AUTO_* bit values for DPLLs */
 #define DPLL_AUTOIDLE_DISABLE				0x0
diff --git a/arch/arm/mach-omap2/prm2xxx.c b/arch/arm/mach-omap2/prm2xxx.c
index 5b5260c..849b415 100644
--- a/arch/arm/mach-omap2/prm2xxx.c
+++ b/arch/arm/mach-omap2/prm2xxx.c
@@ -20,7 +20,7 @@
 
 #include "powerdomain.h"
 #include "clockdomain.h"
-#include "prm2xxx.h"
+#include <linux/power/omap/prm2xxx.h>
 #include "prm2xxx_3xxx_private.h"
 #include <linux/power/omap/cm2xxx_3xxx.h>
 
diff --git a/arch/arm/mach-omap2/prm2xxx.h b/arch/arm/mach-omap2/prm2xxx.h
index 071bb6d..19ff266 100644
--- a/arch/arm/mach-omap2/prm2xxx.h
+++ b/arch/arm/mach-omap2/prm2xxx.h
@@ -19,6 +19,7 @@
 #include "prcm-common.h"
 #include "prm.h"
 #include "prm2xxx_3xxx.h"
+#include <linux/power/omap/prm2xxx.h>
 
 #define OMAP2420_PRM_REGADDR(module, reg)				\
 		OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg))
@@ -35,9 +36,7 @@
  *
  */
 
-#define OMAP2_PRCM_REVISION_OFFSET	0x0000
 #define OMAP2420_PRCM_REVISION		OMAP2420_PRM_REGADDR(OCP_MOD, 0x0000)
-#define OMAP2_PRCM_SYSCONFIG_OFFSET	0x0010
 #define OMAP2420_PRCM_SYSCONFIG		OMAP2420_PRM_REGADDR(OCP_MOD, 0x0010)
 
 #define OMAP2_PRCM_IRQSTATUS_MPU_OFFSET	0x0018
@@ -45,11 +44,9 @@
 #define OMAP2_PRCM_IRQENABLE_MPU_OFFSET	0x001c
 #define OMAP2420_PRCM_IRQENABLE_MPU	OMAP2420_PRM_REGADDR(OCP_MOD, 0x001c)
 
-#define OMAP2_PRCM_VOLTCTRL_OFFSET	0x0050
 #define OMAP2420_PRCM_VOLTCTRL		OMAP2420_PRM_REGADDR(OCP_MOD, 0x0050)
 #define OMAP2_PRCM_VOLTST_OFFSET	0x0054
 #define OMAP2420_PRCM_VOLTST		OMAP2420_PRM_REGADDR(OCP_MOD, 0x0054)
-#define OMAP2_PRCM_CLKSRC_CTRL_OFFSET	0x0060
 #define OMAP2420_PRCM_CLKSRC_CTRL	OMAP2420_PRM_REGADDR(OCP_MOD, 0x0060)
 #define OMAP2_PRCM_CLKOUT_CTRL_OFFSET	0x0070
 #define OMAP2420_PRCM_CLKOUT_CTRL	OMAP2420_PRM_REGADDR(OCP_MOD, 0x0070)
@@ -59,9 +56,7 @@
 #define OMAP2420_PRCM_CLKCFG_CTRL	OMAP2420_PRM_REGADDR(OCP_MOD, 0x0080)
 #define OMAP2_PRCM_CLKCFG_STATUS_OFFSET	0x0084
 #define OMAP2420_PRCM_CLKCFG_STATUS	OMAP2420_PRM_REGADDR(OCP_MOD, 0x0084)
-#define OMAP2_PRCM_VOLTSETUP_OFFSET	0x0090
 #define OMAP2420_PRCM_VOLTSETUP		OMAP2420_PRM_REGADDR(OCP_MOD, 0x0090)
-#define OMAP2_PRCM_CLKSSETUP_OFFSET	0x0094
 #define OMAP2420_PRCM_CLKSSETUP		OMAP2420_PRM_REGADDR(OCP_MOD, 0x0094)
 #define OMAP2_PRCM_POLCTRL_OFFSET	0x0098
 #define OMAP2420_PRCM_POLCTRL		OMAP2420_PRM_REGADDR(OCP_MOD, 0x0098)
@@ -119,17 +114,4 @@
 #define OMAP24XX_PRCM_IRQSTATUS_IVA			0x00f8
 #define OMAP24XX_PRCM_IRQENABLE_IVA			0x00fc
 
-#ifndef __ASSEMBLER__
-/* Function prototypes */
-extern int omap2xxx_clkdm_sleep(struct clockdomain *clkdm);
-extern int omap2xxx_clkdm_wakeup(struct clockdomain *clkdm);
-
-extern void omap2xxx_prm_dpll_reset(void);
-void omap2xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask);
-void omap2xxx_prm_init_pm(void);
-
-extern int __init omap2xxx_prm_init(void);
-
-#endif
-
 #endif
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index 090d13f..273a338 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -29,7 +29,7 @@
 #include <linux/clk/ti.h>
 
 #include "prm2xxx_3xxx.h"
-#include "prm2xxx.h"
+#include <linux/power/omap/prm2xxx.h>
 #include "prm3xxx.h"
 #include "prm44xx.h"
 
diff --git a/include/linux/power/omap/prm2xxx.h b/include/linux/power/omap/prm2xxx.h
new file mode 100644
index 0000000..32b76d5
--- /dev/null
+++ b/include/linux/power/omap/prm2xxx.h
@@ -0,0 +1,39 @@
+/*
+ * OMAP2xxx Power/Reset Management (PRM) register definitions
+ *
+ * Copyright (C) 2007-2009, 2011-2012 Texas Instruments, Inc.
+ * Copyright (C) 2008-2010 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * The PRM hardware modules on the OMAP2/3 are quite similar to each
+ * other.  The PRM on OMAP4 has a new register layout, and is handled
+ * in a separate file.
+ */
+#ifndef __LINUX_POWER_OMAP_PRM2XXX_H
+#define __LINUX_POWER_OMAP_PRM2XXX_H
+
+#define OMAP2_PRCM_REVISION_OFFSET		0x0000
+#define OMAP2_PRCM_SYSCONFIG_OFFSET		0x0010
+#define OMAP2_PRCM_VOLTCTRL_OFFSET		0x0050
+#define OMAP2_PRCM_CLKSRC_CTRL_OFFSET		0x0060
+#define OMAP2_PRCM_VOLTSETUP_OFFSET		0x0090
+#define OMAP2_PRCM_CLKSSETUP_OFFSET		0x0094
+
+#ifndef __ASSEMBLER__
+
+struct clockdomain;
+
+/* Function prototypes */
+int omap2xxx_clkdm_sleep(struct clockdomain *clkdm);
+int omap2xxx_clkdm_wakeup(struct clockdomain *clkdm);
+void omap2xxx_prm_dpll_reset(void);
+void omap2xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask);
+void omap2xxx_prm_init_pm(void);
+int __init omap2xxx_prm_init(void);
+#endif
+
+#endif
-- 
1.7.9.5

[PATCH 32/55] ARM: OMAP2+: PRM: move prm2xxx_3xxx.h to public location

[Tero Kristo]

This file needs to be accessible from the PRCM core and mach-omap2 board
support code.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/clock3xxx.c                  |    2 +-
 arch/arm/mach-omap2/clockdomains2420_data.c      |    2 +-
 arch/arm/mach-omap2/clockdomains2430_data.c      |    2 +-
 arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c |    2 +-
 arch/arm/mach-omap2/clockdomains3xxx_data.c      |    2 +-
 arch/arm/mach-omap2/cm2xxx.c                     |    2 +-
 arch/arm/mach-omap2/cm3xxx.c                     |    3 +-
 arch/arm/mach-omap2/dsp.c                        |    2 +-
 arch/arm/mach-omap2/pm-debug.c                   |    2 +-
 arch/arm/mach-omap2/powerdomain.c                |    2 +-
 arch/arm/mach-omap2/powerdomains2xxx_data.c      |    2 +-
 arch/arm/mach-omap2/powerdomains3xxx_data.c      |    2 +-
 arch/arm/mach-omap2/prm2xxx.h                    |    2 +-
 arch/arm/mach-omap2/prm2xxx_3xxx.h               |  198 ----------------------
 arch/arm/mach-omap2/prm2xxx_3xxx_private.h       |    2 +-
 arch/arm/mach-omap2/prm3xxx.h                    |    2 +-
 arch/arm/mach-omap2/prm_common.c                 |    2 +-
 arch/arm/mach-omap2/serial.c                     |    2 +-
 arch/arm/mach-omap2/sram.c                       |    2 +-
 arch/arm/mach-omap2/vp3xxx_data.c                |    2 +-
 include/linux/power/omap/prm2xxx_3xxx.h          |  197 +++++++++++++++++++++
 21 files changed, 217 insertions(+), 217 deletions(-)
 delete mode 100644 arch/arm/mach-omap2/prm2xxx_3xxx.h
 create mode 100644 include/linux/power/omap/prm2xxx_3xxx.h

diff --git a/arch/arm/mach-omap2/clock3xxx.c b/arch/arm/mach-omap2/clock3xxx.c
index 4706f2f..aebe66b 100644
--- a/arch/arm/mach-omap2/clock3xxx.c
+++ b/arch/arm/mach-omap2/clock3xxx.c
@@ -24,7 +24,7 @@
 #include "soc.h"
 #include "clock.h"
 #include "clock3xxx.h"
-#include "prm2xxx_3xxx.h"
+#include <linux/power/omap/prm2xxx_3xxx.h>
 #include "prm-regbits-34xx.h"
 #include <linux/power/omap/cm2xxx_3xxx.h>
 #include "cm-regbits-34xx.h"
diff --git a/arch/arm/mach-omap2/clockdomains2420_data.c b/arch/arm/mach-omap2/clockdomains2420_data.c
index 7931fd1..432cb14 100644
--- a/arch/arm/mach-omap2/clockdomains2420_data.c
+++ b/arch/arm/mach-omap2/clockdomains2420_data.c
@@ -37,7 +37,7 @@
 
 #include "soc.h"
 #include "clockdomain.h"
-#include "prm2xxx_3xxx.h"
+#include <linux/power/omap/prm2xxx_3xxx.h>
 #include <linux/power/omap/cm2xxx_3xxx.h>
 #include "cm-regbits-24xx.h"
 #include "prm-regbits-24xx.h"
diff --git a/arch/arm/mach-omap2/clockdomains2430_data.c b/arch/arm/mach-omap2/clockdomains2430_data.c
index 2e3918c..48df0fb 100644
--- a/arch/arm/mach-omap2/clockdomains2430_data.c
+++ b/arch/arm/mach-omap2/clockdomains2430_data.c
@@ -37,7 +37,7 @@
 
 #include "soc.h"
 #include "clockdomain.h"
-#include "prm2xxx_3xxx.h"
+#include <linux/power/omap/prm2xxx_3xxx.h>
 #include <linux/power/omap/cm2xxx_3xxx.h>
 #include "cm-regbits-24xx.h"
 #include "prm-regbits-24xx.h"
diff --git a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
index b728d6e..435e5c3 100644
--- a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
+++ b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
@@ -36,7 +36,7 @@
 #include <linux/io.h>
 
 #include "clockdomain.h"
-#include "prm2xxx_3xxx.h"
+#include <linux/power/omap/prm2xxx_3xxx.h>
 #include <linux/power/omap/cm2xxx_3xxx.h>
 #include "cm-regbits-24xx.h"
 #include "cm-regbits-34xx.h"
diff --git a/arch/arm/mach-omap2/clockdomains3xxx_data.c b/arch/arm/mach-omap2/clockdomains3xxx_data.c
index 27851ac..9272baf 100644
--- a/arch/arm/mach-omap2/clockdomains3xxx_data.c
+++ b/arch/arm/mach-omap2/clockdomains3xxx_data.c
@@ -35,7 +35,7 @@
 
 #include "soc.h"
 #include "clockdomain.h"
-#include "prm2xxx_3xxx.h"
+#include <linux/power/omap/prm2xxx_3xxx.h>
 #include <linux/power/omap/cm2xxx_3xxx.h>
 #include "cm-regbits-34xx.h"
 #include "prm-regbits-34xx.h"
diff --git a/arch/arm/mach-omap2/cm2xxx.c b/arch/arm/mach-omap2/cm2xxx.c
index b37783a..2385498 100644
--- a/arch/arm/mach-omap2/cm2xxx.c
+++ b/arch/arm/mach-omap2/cm2xxx.c
@@ -24,7 +24,7 @@
 #include <linux/power/omap/cm2xxx.h>
 #include "clockdomain.h"
 #include "prcm-common.h"
-#include "prm2xxx_3xxx.h"
+#include <linux/power/omap/prm2xxx_3xxx.h>
 
 /* CM_AUTOIDLE_PLL.AUTO_* bit values for DPLLs */
 #define DPLL_AUTOIDLE_DISABLE				0x0
diff --git a/arch/arm/mach-omap2/cm3xxx.c b/arch/arm/mach-omap2/cm3xxx.c
index 0818156..a80cd3e 100644
--- a/arch/arm/mach-omap2/cm3xxx.c
+++ b/arch/arm/mach-omap2/cm3xxx.c
@@ -18,11 +18,12 @@
 #include <linux/err.h>
 #include <linux/io.h>
 
-#include "prm2xxx_3xxx.h"
+#include <linux/power/omap/prm2xxx_3xxx.h>
 #include <linux/power/omap/cm.h>
 #include "cm2xxx_3xxx_private.h"
 #include <linux/power/omap/cm3xxx.h>
 #include "clockdomain.h"
+#include "prcm-common.h"
 
 #define OMAP34XX_CLKSTCTRL_DISABLE_AUTO		0x0
 #define OMAP34XX_CLKSTCTRL_FORCE_SLEEP		0x1
diff --git a/arch/arm/mach-omap2/dsp.c b/arch/arm/mach-omap2/dsp.c
index 1d802fe..a48b6d9 100644
--- a/arch/arm/mach-omap2/dsp.c
+++ b/arch/arm/mach-omap2/dsp.c
@@ -25,7 +25,7 @@
 
 #include "control.h"
 #include <linux/power/omap/cm2xxx_3xxx.h>
-#include "prm2xxx_3xxx.h"
+#include <linux/power/omap/prm2xxx_3xxx.h>
 #ifdef CONFIG_TIDSPBRIDGE_DVFS
 #include "omap-pm.h"
 #endif
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index 95f28b2..d2e4fb8 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -34,7 +34,7 @@
 
 #include "soc.h"
 #include <linux/power/omap/cm2xxx_3xxx.h>
-#include "prm2xxx_3xxx.h"
+#include <linux/power/omap/prm2xxx_3xxx.h>
 #include "pm.h"
 
 u32 enable_off_mode;
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index e532d2b..fdb6172 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -24,7 +24,7 @@
 
 #include <linux/power/omap/cm2xxx_3xxx.h>
 #include "prcm44xx.h"
-#include "prm2xxx_3xxx.h"
+#include <linux/power/omap/prm2xxx_3xxx.h>
 #include "prm44xx.h"
 
 #include <asm/cpu.h>
diff --git a/arch/arm/mach-omap2/powerdomains2xxx_data.c b/arch/arm/mach-omap2/powerdomains2xxx_data.c
index 578eef8..266bd96 100644
--- a/arch/arm/mach-omap2/powerdomains2xxx_data.c
+++ b/arch/arm/mach-omap2/powerdomains2xxx_data.c
@@ -19,7 +19,7 @@
 #include "powerdomains2xxx_3xxx_data.h"
 
 #include "prcm-common.h"
-#include "prm2xxx_3xxx.h"
+#include <linux/power/omap/prm2xxx_3xxx.h>
 #include "prm-regbits-24xx.h"
 
 /* 24XX powerdomains and dependencies */
diff --git a/arch/arm/mach-omap2/powerdomains3xxx_data.c b/arch/arm/mach-omap2/powerdomains3xxx_data.c
index 9db6a8e..7ba44db 100644
--- a/arch/arm/mach-omap2/powerdomains3xxx_data.c
+++ b/arch/arm/mach-omap2/powerdomains3xxx_data.c
@@ -19,7 +19,7 @@
 #include "powerdomain.h"
 #include "powerdomains2xxx_3xxx_data.h"
 #include "prcm-common.h"
-#include "prm2xxx_3xxx.h"
+#include <linux/power/omap/prm2xxx_3xxx.h>
 #include "prm-regbits-34xx.h"
 #include <linux/power/omap/cm2xxx_3xxx.h>
 #include "cm-regbits-34xx.h"
diff --git a/arch/arm/mach-omap2/prm2xxx.h b/arch/arm/mach-omap2/prm2xxx.h
index 19ff266..feeaf00 100644
--- a/arch/arm/mach-omap2/prm2xxx.h
+++ b/arch/arm/mach-omap2/prm2xxx.h
@@ -18,8 +18,8 @@
 
 #include "prcm-common.h"
 #include "prm.h"
-#include "prm2xxx_3xxx.h"
 #include <linux/power/omap/prm2xxx.h>
+#include <linux/power/omap/prm2xxx_3xxx.h>
 
 #define OMAP2420_PRM_REGADDR(module, reg)				\
 		OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg))
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.h b/arch/arm/mach-omap2/prm2xxx_3xxx.h
deleted file mode 100644
index 1c5d998..0000000
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.h
+++ /dev/null
@@ -1,198 +0,0 @@
-/*
- * OMAP2xxx/3xxx-common Power/Reset Management (PRM) register definitions
- *
- * Copyright (C) 2007-2009, 2011-2012 Texas Instruments, Inc.
- * Copyright (C) 2008-2010 Nokia Corporation
- * Paul Walmsley
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * The PRM hardware modules on the OMAP2/3 are quite similar to each
- * other.  The PRM on OMAP4 has a new register layout, and is handled
- * in a separate file.
- */
-#ifndef __ARCH_ARM_MACH_OMAP2_PRM2XXX_3XXX_H
-#define __ARCH_ARM_MACH_OMAP2_PRM2XXX_3XXX_H
-
-#include "prcm-common.h"
-#include "prm.h"
-
-/*
- * Module specific PRM register offsets from PRM_BASE + domain offset
- *
- * Use prm_{read,write}_mod_reg() with these registers.
- *
- * With a few exceptions, these are the register names beginning with
- * {PM,RM}_* on both OMAP2/3 SoC families..  (The exceptions are the
- * IRQSTATUS and IRQENABLE bits.)
- */
-
-/* Register offsets appearing on both OMAP2 and OMAP3 */
-
-#define OMAP2_RM_RSTCTRL				0x0050
-#define OMAP2_RM_RSTTIME				0x0054
-#define OMAP2_RM_RSTST					0x0058
-#define OMAP2_PM_PWSTCTRL				0x00e0
-#define OMAP2_PM_PWSTST					0x00e4
-
-#define PM_WKEN						0x00a0
-#define PM_WKEN1					PM_WKEN
-#define PM_WKST						0x00b0
-#define PM_WKST1					PM_WKST
-#define PM_WKDEP					0x00c8
-#define PM_EVGENCTRL					0x00d4
-#define PM_EVGENONTIM					0x00d8
-#define PM_EVGENOFFTIM					0x00dc
-
-
-#ifndef __ASSEMBLER__
-
-#include <linux/io.h>
-#include "powerdomain.h"
-
-/* These omap2_ PRM functions apply to both OMAP2 and 3 */
-extern int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift);
-extern int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift);
-extern int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift);
-
-extern int omap2_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
-extern int omap2_pwrdm_read_next_pwrst(struct powerdomain *pwrdm);
-extern int omap2_pwrdm_read_pwrst(struct powerdomain *pwrdm);
-extern int omap2_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
-				    u8 pwrst);
-extern int omap2_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
-				     u8 pwrst);
-extern int omap2_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
-extern int omap2_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank);
-extern int omap2_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst);
-extern int omap2_pwrdm_wait_transition(struct powerdomain *pwrdm);
-
-extern int omap2_clkdm_add_wkdep(struct clockdomain *clkdm1,
-				 struct clockdomain *clkdm2);
-extern int omap2_clkdm_del_wkdep(struct clockdomain *clkdm1,
-				 struct clockdomain *clkdm2);
-extern int omap2_clkdm_read_wkdep(struct clockdomain *clkdm1,
-				  struct clockdomain *clkdm2);
-extern int omap2_clkdm_clear_all_wkdeps(struct clockdomain *clkdm);
-
-#endif /* __ASSEMBLER */
-
-/*
- * Bits common to specific registers
- *
- * The 3430 register and bit names are generally used,
- * since they tend to make more sense
- */
-
-/* PM_EVGENONTIM_MPU */
-/* Named PM_EVEGENONTIM_MPU on the 24XX */
-#define OMAP_ONTIMEVAL_SHIFT				0
-#define OMAP_ONTIMEVAL_MASK				(0xffffffff << 0)
-
-/* PM_EVGENOFFTIM_MPU */
-/* Named PM_EVEGENOFFTIM_MPU on the 24XX */
-#define OMAP_OFFTIMEVAL_SHIFT				0
-#define OMAP_OFFTIMEVAL_MASK				(0xffffffff << 0)
-
-/* PRM_CLKSETUP and PRCM_VOLTSETUP */
-/* Named PRCM_CLKSSETUP on the 24XX */
-#define OMAP_SETUP_TIME_SHIFT				0
-#define OMAP_SETUP_TIME_MASK				(0xffff << 0)
-
-/* PRM_CLKSRC_CTRL */
-/* Named PRCM_CLKSRC_CTRL on the 24XX */
-#define OMAP_SYSCLKDIV_SHIFT				6
-#define OMAP_SYSCLKDIV_MASK				(0x3 << 6)
-#define OMAP_SYSCLKDIV_WIDTH				2
-#define OMAP_AUTOEXTCLKMODE_SHIFT			3
-#define OMAP_AUTOEXTCLKMODE_MASK			(0x3 << 3)
-#define OMAP_SYSCLKSEL_SHIFT				0
-#define OMAP_SYSCLKSEL_MASK				(0x3 << 0)
-
-/* PM_EVGENCTRL_MPU */
-#define OMAP_OFFLOADMODE_SHIFT				3
-#define OMAP_OFFLOADMODE_MASK				(0x3 << 3)
-#define OMAP_ONLOADMODE_SHIFT				1
-#define OMAP_ONLOADMODE_MASK				(0x3 << 1)
-#define OMAP_ENABLE_MASK				(1 << 0)
-
-/* PRM_RSTTIME */
-/* Named RM_RSTTIME_WKUP on the 24xx */
-#define OMAP_RSTTIME2_SHIFT				8
-#define OMAP_RSTTIME2_MASK				(0x1f << 8)
-#define OMAP_RSTTIME1_SHIFT				0
-#define OMAP_RSTTIME1_MASK				(0xff << 0)
-
-/* PRM_RSTCTRL */
-/* Named RM_RSTCTRL_WKUP on the 24xx */
-/* 2420 calls RST_DPLL3 'RST_DPLL' */
-#define OMAP_RST_DPLL3_MASK				(1 << 2)
-#define OMAP_RST_GS_MASK				(1 << 1)
-
-
-/*
- * Bits common to module-shared registers
- *
- * Not all registers of a particular type support all of these bits -
- * check TRM if you are unsure
- */
-
-/*
- * 24XX: RM_RSTST_MPU and RM_RSTST_DSP - on 24XX, 'COREDOMAINWKUP_RST' is
- *	 called 'COREWKUP_RST'
- *
- * 3430: RM_RSTST_IVA2, RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSS,
- *	 RM_RSTST_CAM, RM_RSTST_PER, RM_RSTST_NEON
- */
-#define OMAP_COREDOMAINWKUP_RST_MASK			(1 << 3)
-
-/*
- * 24XX: RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSP
- *
- * 2430: RM_RSTST_MDM
- *
- * 3430: RM_RSTST_CORE, RM_RSTST_EMU
- */
-#define OMAP_DOMAINWKUP_RST_MASK			(1 << 2)
-
-/*
- * 24XX: RM_RSTST_MPU, RM_RSTST_WKUP, RM_RSTST_DSP
- *	 On 24XX, 'GLOBALWARM_RST' is called 'GLOBALWMPU_RST'.
- *
- * 2430: RM_RSTST_MDM
- *
- * 3430: RM_RSTST_CORE, RM_RSTST_EMU
- */
-#define OMAP_GLOBALWARM_RST_SHIFT			1
-#define OMAP_GLOBALWARM_RST_MASK			(1 << 1)
-#define OMAP_GLOBALCOLD_RST_SHIFT			0
-#define OMAP_GLOBALCOLD_RST_MASK			(1 << 0)
-
-/*
- * 24XX: PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_CORE, PM_WKDEP_DSP
- *	 2420 TRM sometimes uses "EN_WAKEUP" instead of "EN_WKUP"
- *
- * 2430: PM_WKDEP_MDM
- *
- * 3430: PM_WKDEP_IVA2, PM_WKDEP_GFX, PM_WKDEP_DSS, PM_WKDEP_CAM,
- *	 PM_WKDEP_PER
- */
-#define OMAP_EN_WKUP_SHIFT				4
-#define OMAP_EN_WKUP_MASK				(1 << 4)
-
-/*
- * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
- *	 PM_PWSTCTRL_DSP
- *
- * 2430: PM_PWSTCTRL_MDM
- *
- * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
- *	 PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
- *	 PM_PWSTCTRL_NEON
- */
-#define OMAP_LOGICRETSTATE_MASK				(1 << 2)
-
-
-#endif
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx_private.h b/arch/arm/mach-omap2/prm2xxx_3xxx_private.h
index 6e007e9..ebd6a09 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx_private.h
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx_private.h
@@ -18,7 +18,7 @@
 
 #include "prcm-common.h"
 #include "prm.h"
-#include "prm2xxx_3xxx.h"
+#include <linux/power/omap/prm2xxx_3xxx.h>
 
 #ifndef __ASSEMBLER__
 
diff --git a/arch/arm/mach-omap2/prm3xxx.h b/arch/arm/mach-omap2/prm3xxx.h
index 0e759bc..c79f4c6 100644
--- a/arch/arm/mach-omap2/prm3xxx.h
+++ b/arch/arm/mach-omap2/prm3xxx.h
@@ -18,7 +18,7 @@
 
 #include "prcm-common.h"
 #include "prm.h"
-#include "prm2xxx_3xxx.h"
+#include <linux/power/omap/prm2xxx_3xxx.h>
 
 #define OMAP34XX_PRM_REGADDR(module, reg)				\
 		OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index 273a338..c3eef62 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -28,7 +28,7 @@
 #include <linux/clk-provider.h>
 #include <linux/clk/ti.h>
 
-#include "prm2xxx_3xxx.h"
+#include <linux/power/omap/prm2xxx_3xxx.h>
 #include <linux/power/omap/prm2xxx.h>
 #include "prm3xxx.h"
 #include "prm44xx.h"
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 90e06b3..0413d7e 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -34,7 +34,7 @@
 #include "omap_device.h"
 #include "omap-pm.h"
 #include "soc.h"
-#include "prm2xxx_3xxx.h"
+#include <linux/power/omap/prm2xxx_3xxx.h>
 #include "pm.h"
 #include <linux/power/omap/cm2xxx_3xxx.h>
 #include "prm-regbits-34xx.h"
diff --git a/arch/arm/mach-omap2/sram.c b/arch/arm/mach-omap2/sram.c
index 4bd0968..d18dc7b 100644
--- a/arch/arm/mach-omap2/sram.c
+++ b/arch/arm/mach-omap2/sram.c
@@ -26,7 +26,7 @@
 
 #include "soc.h"
 #include "iomap.h"
-#include "prm2xxx_3xxx.h"
+#include <linux/power/omap/prm2xxx_3xxx.h>
 #include "sdrc.h"
 #include "sram.h"
 
diff --git a/arch/arm/mach-omap2/vp3xxx_data.c b/arch/arm/mach-omap2/vp3xxx_data.c
index 1914e02..8507479 100644
--- a/arch/arm/mach-omap2/vp3xxx_data.c
+++ b/arch/arm/mach-omap2/vp3xxx_data.c
@@ -25,7 +25,7 @@
 #include "voltage.h"
 
 #include "vp.h"
-#include "prm2xxx_3xxx.h"
+#include <linux/power/omap/prm2xxx_3xxx.h>
 
 static const struct omap_vp_ops omap3_vp_ops = {
 	.check_txdone = omap3_prm_vp_check_txdone,
diff --git a/include/linux/power/omap/prm2xxx_3xxx.h b/include/linux/power/omap/prm2xxx_3xxx.h
new file mode 100644
index 0000000..26a7ba1
--- /dev/null
+++ b/include/linux/power/omap/prm2xxx_3xxx.h
@@ -0,0 +1,197 @@
+/*
+ * OMAP2xxx/3xxx-common Power/Reset Management (PRM) register definitions
+ *
+ * Copyright (C) 2007-2009, 2011-2012 Texas Instruments, Inc.
+ * Copyright (C) 2008-2010 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * The PRM hardware modules on the OMAP2/3 are quite similar to each
+ * other.  The PRM on OMAP4 has a new register layout, and is handled
+ * in a separate file.
+ */
+#ifndef __LINUX_POWER_OMAP_PRM2XXX_3XXX_H
+#define __LINUX_POWER_OMAP_PRM2XXX_3XXX_H
+
+/*
+ * Module specific PRM register offsets from PRM_BASE + domain offset
+ *
+ * Use prm_{read,write}_mod_reg() with these registers.
+ *
+ * With a few exceptions, these are the register names beginning with
+ * {PM,RM}_* on both OMAP2/3 SoC families..  (The exceptions are the
+ * IRQSTATUS and IRQENABLE bits.)
+ */
+
+/* Register offsets appearing on both OMAP2 and OMAP3 */
+
+#define OMAP2_RM_RSTCTRL				0x0050
+#define OMAP2_RM_RSTTIME				0x0054
+#define OMAP2_RM_RSTST					0x0058
+#define OMAP2_PM_PWSTCTRL				0x00e0
+#define OMAP2_PM_PWSTST					0x00e4
+
+#define PM_WKEN						0x00a0
+#define PM_WKEN1					PM_WKEN
+#define PM_WKST						0x00b0
+#define PM_WKST1					PM_WKST
+#define PM_WKDEP					0x00c8
+#define PM_EVGENCTRL					0x00d4
+#define PM_EVGENONTIM					0x00d8
+#define PM_EVGENOFFTIM					0x00dc
+
+
+#ifndef __ASSEMBLER__
+
+#include <linux/io.h>
+
+struct powerdomain;
+struct clockdomain;
+
+/* These omap2_ PRM functions apply to both OMAP2 and 3 */
+int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift);
+int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift);
+int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift);
+
+int omap2_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
+int omap2_pwrdm_read_next_pwrst(struct powerdomain *pwrdm);
+int omap2_pwrdm_read_pwrst(struct powerdomain *pwrdm);
+int omap2_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
+			     u8 pwrst);
+int omap2_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
+			      u8 pwrst);
+int omap2_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
+int omap2_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank);
+int omap2_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst);
+int omap2_pwrdm_wait_transition(struct powerdomain *pwrdm);
+
+int omap2_clkdm_add_wkdep(struct clockdomain *clkdm1,
+			  struct clockdomain *clkdm2);
+int omap2_clkdm_del_wkdep(struct clockdomain *clkdm1,
+			  struct clockdomain *clkdm2);
+int omap2_clkdm_read_wkdep(struct clockdomain *clkdm1,
+			   struct clockdomain *clkdm2);
+int omap2_clkdm_clear_all_wkdeps(struct clockdomain *clkdm);
+
+#endif /* __ASSEMBLER */
+
+/*
+ * Bits common to specific registers
+ *
+ * The 3430 register and bit names are generally used,
+ * since they tend to make more sense
+ */
+
+/* PM_EVGENONTIM_MPU */
+/* Named PM_EVEGENONTIM_MPU on the 24XX */
+#define OMAP_ONTIMEVAL_SHIFT				0
+#define OMAP_ONTIMEVAL_MASK				(0xffffffff << 0)
+
+/* PM_EVGENOFFTIM_MPU */
+/* Named PM_EVEGENOFFTIM_MPU on the 24XX */
+#define OMAP_OFFTIMEVAL_SHIFT				0
+#define OMAP_OFFTIMEVAL_MASK				(0xffffffff << 0)
+
+/* PRM_CLKSETUP and PRCM_VOLTSETUP */
+/* Named PRCM_CLKSSETUP on the 24XX */
+#define OMAP_SETUP_TIME_SHIFT				0
+#define OMAP_SETUP_TIME_MASK				(0xffff << 0)
+
+/* PRM_CLKSRC_CTRL */
+/* Named PRCM_CLKSRC_CTRL on the 24XX */
+#define OMAP_SYSCLKDIV_SHIFT				6
+#define OMAP_SYSCLKDIV_MASK				(0x3 << 6)
+#define OMAP_SYSCLKDIV_WIDTH				2
+#define OMAP_AUTOEXTCLKMODE_SHIFT			3
+#define OMAP_AUTOEXTCLKMODE_MASK			(0x3 << 3)
+#define OMAP_SYSCLKSEL_SHIFT				0
+#define OMAP_SYSCLKSEL_MASK				(0x3 << 0)
+
+/* PM_EVGENCTRL_MPU */
+#define OMAP_OFFLOADMODE_SHIFT				3
+#define OMAP_OFFLOADMODE_MASK				(0x3 << 3)
+#define OMAP_ONLOADMODE_SHIFT				1
+#define OMAP_ONLOADMODE_MASK				(0x3 << 1)
+#define OMAP_ENABLE_MASK				(1 << 0)
+
+/* PRM_RSTTIME */
+/* Named RM_RSTTIME_WKUP on the 24xx */
+#define OMAP_RSTTIME2_SHIFT				8
+#define OMAP_RSTTIME2_MASK				(0x1f << 8)
+#define OMAP_RSTTIME1_SHIFT				0
+#define OMAP_RSTTIME1_MASK				(0xff << 0)
+
+/* PRM_RSTCTRL */
+/* Named RM_RSTCTRL_WKUP on the 24xx */
+/* 2420 calls RST_DPLL3 'RST_DPLL' */
+#define OMAP_RST_DPLL3_MASK				(1 << 2)
+#define OMAP_RST_GS_MASK				(1 << 1)
+
+
+/*
+ * Bits common to module-shared registers
+ *
+ * Not all registers of a particular type support all of these bits -
+ * check TRM if you are unsure
+ */
+
+/*
+ * 24XX: RM_RSTST_MPU and RM_RSTST_DSP - on 24XX, 'COREDOMAINWKUP_RST' is
+ *	 called 'COREWKUP_RST'
+ *
+ * 3430: RM_RSTST_IVA2, RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSS,
+ *	 RM_RSTST_CAM, RM_RSTST_PER, RM_RSTST_NEON
+ */
+#define OMAP_COREDOMAINWKUP_RST_MASK			(1 << 3)
+
+/*
+ * 24XX: RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSP
+ *
+ * 2430: RM_RSTST_MDM
+ *
+ * 3430: RM_RSTST_CORE, RM_RSTST_EMU
+ */
+#define OMAP_DOMAINWKUP_RST_MASK			(1 << 2)
+
+/*
+ * 24XX: RM_RSTST_MPU, RM_RSTST_WKUP, RM_RSTST_DSP
+ *	 On 24XX, 'GLOBALWARM_RST' is called 'GLOBALWMPU_RST'.
+ *
+ * 2430: RM_RSTST_MDM
+ *
+ * 3430: RM_RSTST_CORE, RM_RSTST_EMU
+ */
+#define OMAP_GLOBALWARM_RST_SHIFT			1
+#define OMAP_GLOBALWARM_RST_MASK			(1 << 1)
+#define OMAP_GLOBALCOLD_RST_SHIFT			0
+#define OMAP_GLOBALCOLD_RST_MASK			(1 << 0)
+
+/*
+ * 24XX: PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_CORE, PM_WKDEP_DSP
+ *	 2420 TRM sometimes uses "EN_WAKEUP" instead of "EN_WKUP"
+ *
+ * 2430: PM_WKDEP_MDM
+ *
+ * 3430: PM_WKDEP_IVA2, PM_WKDEP_GFX, PM_WKDEP_DSS, PM_WKDEP_CAM,
+ *	 PM_WKDEP_PER
+ */
+#define OMAP_EN_WKUP_SHIFT				4
+#define OMAP_EN_WKUP_MASK				(1 << 4)
+
+/*
+ * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
+ *	 PM_PWSTCTRL_DSP
+ *
+ * 2430: PM_PWSTCTRL_MDM
+ *
+ * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
+ *	 PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
+ *	 PM_PWSTCTRL_NEON
+ */
+#define OMAP_LOGICRETSTATE_MASK				(1 << 2)
+
+
+#endif
-- 
1.7.9.5

[PATCH 33/55] ARM: AM33xx: PRM: move global warm reset implementation to driver

[Tero Kristo]

Moved the implementation from am33xx-restart.c to the prm33xx.c file to
isolate the PRM register accesses to be private for PRM driver.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/am33xx-restart.c |    9 +--------
 arch/arm/mach-omap2/prm33xx.c        |   16 ++++++++++++++++
 2 files changed, 17 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mach-omap2/am33xx-restart.c b/arch/arm/mach-omap2/am33xx-restart.c
index c88d8df7..7286389 100644
--- a/arch/arm/mach-omap2/am33xx-restart.c
+++ b/arch/arm/mach-omap2/am33xx-restart.c
@@ -24,12 +24,5 @@ void am33xx_restart(enum reboot_mode mode, const char *cmd)
 {
 	/* TODO: Handle mode and cmd if necessary */
 
-	am33xx_prm_rmw_reg_bits(AM33XX_RST_GLOBAL_WARM_SW_MASK,
-				AM33XX_RST_GLOBAL_WARM_SW_MASK,
-				AM33XX_PRM_DEVICE_MOD,
-				AM33XX_PRM_RSTCTRL_OFFSET);
-
-	/* OCP barrier */
-	(void)am33xx_prm_read_reg(AM33XX_PRM_DEVICE_MOD,
-				  AM33XX_PRM_RSTCTRL_OFFSET);
+	am33xx_prm_global_warm_sw_reset();
 }
diff --git a/arch/arm/mach-omap2/prm33xx.c b/arch/arm/mach-omap2/prm33xx.c
index 877d7c7..a08b1da 100644
--- a/arch/arm/mach-omap2/prm33xx.c
+++ b/arch/arm/mach-omap2/prm33xx.c
@@ -29,6 +29,10 @@
 #define AM33XX_LOWPOWERSTATECHANGE_SHIFT	4
 #define AM33XX_LOWPOWERSTATECHANGE_MASK		(1 << 4)
 
+#define AM33XX_PRM_RSTCTRL_OFFSET		0x0000
+
+#define AM33XX_RST_GLOBAL_WARM_SW_MASK		(1 << 0)
+
 /* Read a register in a PRM instance */
 u32 am33xx_prm_read_reg(s16 inst, u16 idx)
 {
@@ -331,6 +335,18 @@ static int am33xx_check_vcvp(void)
 	return 0;
 }
 
+void am33xx_prm_global_warm_sw_reset(void)
+{
+	am33xx_prm_rmw_reg_bits(AM33XX_RST_GLOBAL_WARM_SW_MASK,
+				AM33XX_RST_GLOBAL_WARM_SW_MASK,
+				AM33XX_PRM_DEVICE_MOD,
+				AM33XX_PRM_RSTCTRL_OFFSET);
+
+	/* OCP barrier */
+	(void)am33xx_prm_read_reg(AM33XX_PRM_DEVICE_MOD,
+				  AM33XX_PRM_RSTCTRL_OFFSET);
+}
+
 struct pwrdm_ops am33xx_pwrdm_operations = {
 	.pwrdm_set_next_pwrst		= am33xx_pwrdm_set_next_pwrst,
 	.pwrdm_read_next_pwrst		= am33xx_pwrdm_read_next_pwrst,
-- 
1.7.9.5

[PATCH 34/55] ARM: AM33XX: PRM: move parts of the prm33xx.h header file to public location

[Tero Kristo]

Parts of this file are needed from both the driver and mach-omap2 board
code.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/am33xx-restart.c |    2 +-
 arch/arm/mach-omap2/cm33xx.c         |    3 ++-
 arch/arm/mach-omap2/prm33xx.c        |    3 ++-
 arch/arm/mach-omap2/prm33xx.h        |   23 +---------------------
 include/linux/power/omap/prm33xx.h   |   36 ++++++++++++++++++++++++++++++++++
 5 files changed, 42 insertions(+), 25 deletions(-)
 create mode 100644 include/linux/power/omap/prm33xx.h

diff --git a/arch/arm/mach-omap2/am33xx-restart.c b/arch/arm/mach-omap2/am33xx-restart.c
index 7286389..9ae249c 100644
--- a/arch/arm/mach-omap2/am33xx-restart.c
+++ b/arch/arm/mach-omap2/am33xx-restart.c
@@ -10,7 +10,7 @@
 
 #include "common.h"
 #include "prm-regbits-33xx.h"
-#include "prm33xx.h"
+#include <linux/power/omap/prm33xx.h>
 
 /**
  * am3xx_restart - trigger a software restart of the SoC
diff --git a/arch/arm/mach-omap2/cm33xx.c b/arch/arm/mach-omap2/cm33xx.c
index 7717eeb..43e4f26 100644
--- a/arch/arm/mach-omap2/cm33xx.c
+++ b/arch/arm/mach-omap2/cm33xx.c
@@ -25,7 +25,8 @@
 #include "clockdomain.h"
 #include <linux/power/omap/cm.h>
 #include <linux/power/omap/cm33xx.h>
-#include "prm33xx.h"
+#include <linux/power/omap/prm33xx.h>
+#include "prcm-common.h"
 
 #define AM33XX_MODULEMODE_SHIFT			0
 #define AM33XX_MODULEMODE_MASK			(0x3 << 0)
diff --git a/arch/arm/mach-omap2/prm33xx.c b/arch/arm/mach-omap2/prm33xx.c
index a08b1da..436cd12 100644
--- a/arch/arm/mach-omap2/prm33xx.c
+++ b/arch/arm/mach-omap2/prm33xx.c
@@ -18,9 +18,10 @@
 #include <linux/errno.h>
 #include <linux/err.h>
 #include <linux/io.h>
+#include <linux/power/omap/prm33xx.h>
 
 #include "powerdomain.h"
-#include "prm33xx.h"
+#include "prm.h"
 
 #define AM33XX_LASTPOWERSTATEENTERED_SHIFT	24
 #define AM33XX_LASTPOWERSTATEENTERED_MASK	(0x3 << 24)
diff --git a/arch/arm/mach-omap2/prm33xx.h b/arch/arm/mach-omap2/prm33xx.h
index 9b9918d..7825b1c 100644
--- a/arch/arm/mach-omap2/prm33xx.h
+++ b/arch/arm/mach-omap2/prm33xx.h
@@ -18,23 +18,13 @@
 
 #include "prcm-common.h"
 #include "prm.h"
+#include <linux/power/omap/prm33xx.h>
 
 #define AM33XX_PRM_BASE               0x44E00000
 
 #define AM33XX_PRM_REGADDR(inst, reg)                         \
 	AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRM_BASE + (inst) + (reg))
 
-
-/* PRM instances */
-#define AM33XX_PRM_OCP_SOCKET_MOD	0x0B00
-#define AM33XX_PRM_PER_MOD		0x0C00
-#define AM33XX_PRM_WKUP_MOD		0x0D00
-#define AM33XX_PRM_MPU_MOD		0x0E00
-#define AM33XX_PRM_DEVICE_MOD		0x0F00
-#define AM33XX_PRM_RTC_MOD		0x1000
-#define AM33XX_PRM_GFX_MOD		0x1100
-#define AM33XX_PRM_CEFUSE_MOD		0x1200
-
 /* PRM */
 
 /* PRM.OCP_SOCKET_PRM register offsets */
@@ -117,15 +107,4 @@
 #define AM33XX_PM_CEFUSE_PWRSTST_OFFSET		0x0004
 #define AM33XX_PM_CEFUSE_PWRSTST		AM33XX_PRM_REGADDR(AM33XX_PRM_CEFUSE_MOD, 0x0004)
 
-#ifndef __ASSEMBLER__
-extern u32 am33xx_prm_read_reg(s16 inst, u16 idx);
-extern void am33xx_prm_write_reg(u32 val, s16 inst, u16 idx);
-extern u32 am33xx_prm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
-extern void am33xx_prm_global_warm_sw_reset(void);
-extern int am33xx_prm_is_hardreset_asserted(u8 shift, s16 inst,
-		u16 rstctrl_offs);
-extern int am33xx_prm_assert_hardreset(u8 shift, s16 inst, u16 rstctrl_offs);
-extern int am33xx_prm_deassert_hardreset(u8 shift, u8 st_shift, s16 inst,
-		u16 rstctrl_offs, u16 rstst_offs);
-#endif /* ASSEMBLER */
 #endif
diff --git a/include/linux/power/omap/prm33xx.h b/include/linux/power/omap/prm33xx.h
new file mode 100644
index 0000000..ea72bf0
--- /dev/null
+++ b/include/linux/power/omap/prm33xx.h
@@ -0,0 +1,36 @@
+/*
+ * AM33XX PRM instance offset macros
+ *
+ * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __LINUX_POWER_OMAP_PRM33XX_H
+#define __LINUX_POWER_OMAP_PRM33XX_H
+
+/* PRM instances */
+#define AM33XX_PRM_OCP_SOCKET_MOD	0x0B00
+#define AM33XX_PRM_PER_MOD		0x0C00
+#define AM33XX_PRM_WKUP_MOD		0x0D00
+#define AM33XX_PRM_MPU_MOD		0x0E00
+#define AM33XX_PRM_DEVICE_MOD		0x0F00
+#define AM33XX_PRM_RTC_MOD		0x1000
+#define AM33XX_PRM_GFX_MOD		0x1100
+#define AM33XX_PRM_CEFUSE_MOD		0x1200
+
+#ifndef __ASSEMBLER__
+void am33xx_prm_global_warm_sw_reset(void);
+int am33xx_prm_is_hardreset_asserted(u8 shift, s16 inst, u16 rstctrl_offs);
+int am33xx_prm_assert_hardreset(u8 shift, s16 inst, u16 rstctrl_offs);
+int am33xx_prm_deassert_hardreset(u8 shift, u8 st_shift, s16 inst,
+				  u16 rstctrl_offs, u16 rstst_offs);
+#endif /* ASSEMBLER */
+#endif
-- 
1.7.9.5

[PATCH 35/55] ARM: OMAP3: PRM: remove direct register declaration macros

[Tero Kristo]

Only a handful of these are currently used in the kernel, so cleanup.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/cclock3xxx_data.c |   14 ++++++++-----
 arch/arm/mach-omap2/prm3xxx.h         |   37 ---------------------------------
 2 files changed, 9 insertions(+), 42 deletions(-)

diff --git a/arch/arm/mach-omap2/cclock3xxx_data.c b/arch/arm/mach-omap2/cclock3xxx_data.c
index d5fefb9..6d7aea5 100644
--- a/arch/arm/mach-omap2/cclock3xxx_data.c
+++ b/arch/arm/mach-omap2/cclock3xxx_data.c
@@ -79,12 +79,15 @@ static const char *osc_sys_ck_parent_names[] = {
 };
 
 DEFINE_CLK_MUX(osc_sys_ck, osc_sys_ck_parent_names, NULL, 0x0,
-	       OMAP3430_PRM_CLKSEL, OMAP3430_SYS_CLKIN_SEL_SHIFT,
-	       OMAP3430_SYS_CLKIN_SEL_WIDTH, 0x0, NULL);
+	       OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, OMAP3_PRM_CLKSEL_OFFSET),
+	       OMAP3430_SYS_CLKIN_SEL_SHIFT, OMAP3430_SYS_CLKIN_SEL_WIDTH, 0x0,
+	       NULL);
 
 DEFINE_CLK_DIVIDER(sys_ck, "osc_sys_ck", &osc_sys_ck, 0x0,
-		   OMAP3430_PRM_CLKSRC_CTRL, OMAP_SYSCLKDIV_SHIFT,
-		   OMAP_SYSCLKDIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
+		   OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD,
+					OMAP3_PRM_CLKSRC_CTRL_OFFSET),
+		   OMAP_SYSCLKDIV_SHIFT, OMAP_SYSCLKDIV_WIDTH,
+		   CLK_DIVIDER_ONE_BASED, NULL);
 
 static struct dpll_data dpll3_dd = {
 	.mult_div1_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
@@ -2824,7 +2827,8 @@ static struct clk_hw_omap sys_clkout1_hw = {
 	.hw = {
 		.clk = &sys_clkout1,
 	},
-	.enable_reg	= OMAP3430_PRM_CLKOUT_CTRL,
+	.enable_reg	= OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD,
+					       OMAP3_PRM_CLKOUT_CTRL_OFFSET),
 	.enable_bit	= OMAP3430_CLKOUT_EN_SHIFT,
 };
 
diff --git a/arch/arm/mach-omap2/prm3xxx.h b/arch/arm/mach-omap2/prm3xxx.h
index c79f4c6..ffc8177 100644
--- a/arch/arm/mach-omap2/prm3xxx.h
+++ b/arch/arm/mach-omap2/prm3xxx.h
@@ -34,83 +34,46 @@
  */
 
 #define OMAP3_PRM_REVISION_OFFSET	0x0004
-#define OMAP3430_PRM_REVISION		OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0004)
 #define OMAP3_PRM_SYSCONFIG_OFFSET	0x0014
-#define OMAP3430_PRM_SYSCONFIG		OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0014)
 
 #define OMAP3_PRM_IRQSTATUS_MPU_OFFSET	0x0018
-#define OMAP3430_PRM_IRQSTATUS_MPU	OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0018)
 #define OMAP3_PRM_IRQENABLE_MPU_OFFSET	0x001c
-#define OMAP3430_PRM_IRQENABLE_MPU	OMAP34XX_PRM_REGADDR(OCP_MOD, 0x001c)
 
 
 #define OMAP3_PRM_VC_SMPS_SA_OFFSET	0x0020
-#define OMAP3430_PRM_VC_SMPS_SA		OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020)
 #define OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET	0x0024
-#define OMAP3430_PRM_VC_SMPS_VOL_RA	OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0024)
 #define OMAP3_PRM_VC_SMPS_CMD_RA_OFFSET	0x0028
-#define OMAP3430_PRM_VC_SMPS_CMD_RA	OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0028)
 #define OMAP3_PRM_VC_CMD_VAL_0_OFFSET	0x002c
-#define OMAP3430_PRM_VC_CMD_VAL_0	OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x002c)
 #define OMAP3_PRM_VC_CMD_VAL_1_OFFSET	0x0030
-#define OMAP3430_PRM_VC_CMD_VAL_1	OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0030)
 #define OMAP3_PRM_VC_CH_CONF_OFFSET	0x0034
-#define OMAP3430_PRM_VC_CH_CONF		OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0034)
 #define OMAP3_PRM_VC_I2C_CFG_OFFSET	0x0038
-#define OMAP3430_PRM_VC_I2C_CFG		OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0038)
 #define OMAP3_PRM_VC_BYPASS_VAL_OFFSET	0x003c
-#define OMAP3430_PRM_VC_BYPASS_VAL	OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x003c)
 #define OMAP3_PRM_RSTCTRL_OFFSET	0x0050
-#define OMAP3430_PRM_RSTCTRL		OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0050)
 #define OMAP3_PRM_RSTTIME_OFFSET	0x0054
-#define OMAP3430_PRM_RSTTIME		OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0054)
 #define OMAP3_PRM_RSTST_OFFSET	0x0058
-#define OMAP3430_PRM_RSTST		OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0058)
 #define OMAP3_PRM_VOLTCTRL_OFFSET	0x0060
-#define OMAP3430_PRM_VOLTCTRL		OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0060)
 #define OMAP3_PRM_SRAM_PCHARGE_OFFSET	0x0064
-#define OMAP3430_PRM_SRAM_PCHARGE	OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0064)
 #define OMAP3_PRM_CLKSRC_CTRL_OFFSET	0x0070
-#define OMAP3430_PRM_CLKSRC_CTRL	OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0070)
 #define OMAP3_PRM_VOLTSETUP1_OFFSET	0x0090
-#define OMAP3430_PRM_VOLTSETUP1		OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0090)
 #define OMAP3_PRM_VOLTOFFSET_OFFSET	0x0094
-#define OMAP3430_PRM_VOLTOFFSET		OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0094)
 #define OMAP3_PRM_CLKSETUP_OFFSET	0x0098
-#define OMAP3430_PRM_CLKSETUP		OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0098)
 #define OMAP3_PRM_POLCTRL_OFFSET	0x009c
-#define OMAP3430_PRM_POLCTRL		OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x009c)
 #define OMAP3_PRM_VOLTSETUP2_OFFSET	0x00a0
-#define OMAP3430_PRM_VOLTSETUP2		OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00a0)
 #define OMAP3_PRM_VP1_CONFIG_OFFSET	0x00b0
-#define OMAP3430_PRM_VP1_CONFIG		OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b0)
 #define OMAP3_PRM_VP1_VSTEPMIN_OFFSET	0x00b4
-#define OMAP3430_PRM_VP1_VSTEPMIN	OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b4)
 #define OMAP3_PRM_VP1_VSTEPMAX_OFFSET	0x00b8
-#define OMAP3430_PRM_VP1_VSTEPMAX	OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b8)
 #define OMAP3_PRM_VP1_VLIMITTO_OFFSET	0x00bc
-#define OMAP3430_PRM_VP1_VLIMITTO	OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00bc)
 #define OMAP3_PRM_VP1_VOLTAGE_OFFSET	0x00c0
-#define OMAP3430_PRM_VP1_VOLTAGE	OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c0)
 #define OMAP3_PRM_VP1_STATUS_OFFSET	0x00c4
-#define OMAP3430_PRM_VP1_STATUS		OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c4)
 #define OMAP3_PRM_VP2_CONFIG_OFFSET	0x00d0
-#define OMAP3430_PRM_VP2_CONFIG		OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d0)
 #define OMAP3_PRM_VP2_VSTEPMIN_OFFSET	0x00d4
-#define OMAP3430_PRM_VP2_VSTEPMIN	OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d4)
 #define OMAP3_PRM_VP2_VSTEPMAX_OFFSET	0x00d8
-#define OMAP3430_PRM_VP2_VSTEPMAX	OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d8)
 #define OMAP3_PRM_VP2_VLIMITTO_OFFSET	0x00dc
-#define OMAP3430_PRM_VP2_VLIMITTO	OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00dc)
 #define OMAP3_PRM_VP2_VOLTAGE_OFFSET	0x00e0
-#define OMAP3430_PRM_VP2_VOLTAGE	OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e0)
 #define OMAP3_PRM_VP2_STATUS_OFFSET	0x00e4
-#define OMAP3430_PRM_VP2_STATUS		OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e4)
 
 #define OMAP3_PRM_CLKSEL_OFFSET	0x0040
-#define OMAP3430_PRM_CLKSEL		OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0040)
 #define OMAP3_PRM_CLKOUT_CTRL_OFFSET	0x0070
-#define OMAP3430_PRM_CLKOUT_CTRL	OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
 
 /* OMAP3 specific register offsets */
 #define OMAP3430ES2_PM_WKEN3				0x00f0
-- 
1.7.9.5

[PATCH 36/55] ARM: OMAP3: PRM: move prm3xxx.h header to public location

[Tero Kristo]

This file needs to be accessible from the PRCM core and mach-omap2 board
support code.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/prm3xxx.c      |    2 +-
 arch/arm/mach-omap2/prm3xxx.h      |  113 +-----------------------------
 arch/arm/mach-omap2/prm_common.c   |    2 +-
 include/linux/power/omap/prm3xxx.h |  132 ++++++++++++++++++++++++++++++++++++
 4 files changed, 135 insertions(+), 114 deletions(-)
 create mode 100644 include/linux/power/omap/prm3xxx.h

diff --git a/arch/arm/mach-omap2/prm3xxx.c b/arch/arm/mach-omap2/prm3xxx.c
index 4700605..93f87e1 100644
--- a/arch/arm/mach-omap2/prm3xxx.c
+++ b/arch/arm/mach-omap2/prm3xxx.c
@@ -20,7 +20,7 @@
 
 #include "vp.h"
 #include "powerdomain.h"
-#include "prm3xxx.h"
+#include <linux/power/omap/prm3xxx.h>
 #include "prm2xxx_3xxx_private.h"
 #include "cm2xxx_3xxx_private.h"
 #include <linux/power/omap/cm3xxx.h>
diff --git a/arch/arm/mach-omap2/prm3xxx.h b/arch/arm/mach-omap2/prm3xxx.h
index ffc8177..6c06fce 100644
--- a/arch/arm/mach-omap2/prm3xxx.h
+++ b/arch/arm/mach-omap2/prm3xxx.h
@@ -19,120 +19,9 @@
 #include "prcm-common.h"
 #include "prm.h"
 #include <linux/power/omap/prm2xxx_3xxx.h>
+#include <linux/power/omap/prm3xxx.h>
 
 #define OMAP34XX_PRM_REGADDR(module, reg)				\
 		OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
 
-
-/*
- * OMAP3-specific global PRM registers
- * Use __raw_{read,write}l() with these registers.
- *
- * With a few exceptions, these are the register names beginning with
- * PRM_* on 34xx.  (The exceptions are the IRQSTATUS and IRQENABLE
- * bits.)
- */
-
-#define OMAP3_PRM_REVISION_OFFSET	0x0004
-#define OMAP3_PRM_SYSCONFIG_OFFSET	0x0014
-
-#define OMAP3_PRM_IRQSTATUS_MPU_OFFSET	0x0018
-#define OMAP3_PRM_IRQENABLE_MPU_OFFSET	0x001c
-
-
-#define OMAP3_PRM_VC_SMPS_SA_OFFSET	0x0020
-#define OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET	0x0024
-#define OMAP3_PRM_VC_SMPS_CMD_RA_OFFSET	0x0028
-#define OMAP3_PRM_VC_CMD_VAL_0_OFFSET	0x002c
-#define OMAP3_PRM_VC_CMD_VAL_1_OFFSET	0x0030
-#define OMAP3_PRM_VC_CH_CONF_OFFSET	0x0034
-#define OMAP3_PRM_VC_I2C_CFG_OFFSET	0x0038
-#define OMAP3_PRM_VC_BYPASS_VAL_OFFSET	0x003c
-#define OMAP3_PRM_RSTCTRL_OFFSET	0x0050
-#define OMAP3_PRM_RSTTIME_OFFSET	0x0054
-#define OMAP3_PRM_RSTST_OFFSET	0x0058
-#define OMAP3_PRM_VOLTCTRL_OFFSET	0x0060
-#define OMAP3_PRM_SRAM_PCHARGE_OFFSET	0x0064
-#define OMAP3_PRM_CLKSRC_CTRL_OFFSET	0x0070
-#define OMAP3_PRM_VOLTSETUP1_OFFSET	0x0090
-#define OMAP3_PRM_VOLTOFFSET_OFFSET	0x0094
-#define OMAP3_PRM_CLKSETUP_OFFSET	0x0098
-#define OMAP3_PRM_POLCTRL_OFFSET	0x009c
-#define OMAP3_PRM_VOLTSETUP2_OFFSET	0x00a0
-#define OMAP3_PRM_VP1_CONFIG_OFFSET	0x00b0
-#define OMAP3_PRM_VP1_VSTEPMIN_OFFSET	0x00b4
-#define OMAP3_PRM_VP1_VSTEPMAX_OFFSET	0x00b8
-#define OMAP3_PRM_VP1_VLIMITTO_OFFSET	0x00bc
-#define OMAP3_PRM_VP1_VOLTAGE_OFFSET	0x00c0
-#define OMAP3_PRM_VP1_STATUS_OFFSET	0x00c4
-#define OMAP3_PRM_VP2_CONFIG_OFFSET	0x00d0
-#define OMAP3_PRM_VP2_VSTEPMIN_OFFSET	0x00d4
-#define OMAP3_PRM_VP2_VSTEPMAX_OFFSET	0x00d8
-#define OMAP3_PRM_VP2_VLIMITTO_OFFSET	0x00dc
-#define OMAP3_PRM_VP2_VOLTAGE_OFFSET	0x00e0
-#define OMAP3_PRM_VP2_STATUS_OFFSET	0x00e4
-
-#define OMAP3_PRM_CLKSEL_OFFSET	0x0040
-#define OMAP3_PRM_CLKOUT_CTRL_OFFSET	0x0070
-
-/* OMAP3 specific register offsets */
-#define OMAP3430ES2_PM_WKEN3				0x00f0
-#define OMAP3430ES2_PM_WKST3				0x00b8
-
-#define OMAP3430_PM_MPUGRPSEL				0x00a4
-#define OMAP3430_PM_MPUGRPSEL1				OMAP3430_PM_MPUGRPSEL
-#define OMAP3430ES2_PM_MPUGRPSEL3			0x00f8
-
-#define OMAP3430_PM_IVAGRPSEL				0x00a8
-#define OMAP3430_PM_IVAGRPSEL1				OMAP3430_PM_IVAGRPSEL
-#define OMAP3430ES2_PM_IVAGRPSEL3			0x00f4
-
-#define OMAP3430_PM_PREPWSTST				0x00e8
-
-#define OMAP3430_PRM_IRQSTATUS_IVA2			0x00f8
-#define OMAP3430_PRM_IRQENABLE_IVA2			0x00fc
-
-
-#ifndef __ASSEMBLER__
-
-/* OMAP3-specific VP functions */
-u32 omap3_prm_vp_check_txdone(u8 vp_id);
-void omap3_prm_vp_clear_txdone(u8 vp_id);
-
-/*
- * OMAP3 access functions for voltage controller (VC) and
- * voltage proccessor (VP) in the PRM.
- */
-extern u32 omap3_prm_vcvp_read(u8 offset);
-extern void omap3_prm_vcvp_write(u32 val, u8 offset);
-extern u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
-
-#ifdef CONFIG_ARCH_OMAP3
-void omap3xxx_prm_reconfigure_io_chain(void);
-#else
-static inline void omap3xxx_prm_reconfigure_io_chain(void)
-{
-}
-#endif
-
-/* PRM interrupt-related functions */
-extern void omap3xxx_prm_read_pending_irqs(unsigned long *events);
-extern void omap3xxx_prm_ocp_barrier(void);
-extern void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask);
-extern void omap3xxx_prm_restore_irqen(u32 *saved_mask);
-
-extern void omap3xxx_prm_dpll3_reset(void);
-
-int __init omap3xxx_prm_init(u16 cpu_type);
-extern u32 omap3xxx_prm_get_reset_sources(void);
-int omap3xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits);
-void omap3xxx_prm_iva_idle(void);
-void omap3_prm_reset_modem(void);
-int omap3xxx_prm_clear_global_cold_reset(void);
-void omap3_prm_save_scratchpad_contents(u32 *ptr);
-void omap3_prm_init_pm(bool has_uart4, bool has_iva);
-
-#endif /* __ASSEMBLER */
-
-
 #endif
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index c3eef62..40e94e7 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -30,7 +30,7 @@
 
 #include <linux/power/omap/prm2xxx_3xxx.h>
 #include <linux/power/omap/prm2xxx.h>
-#include "prm3xxx.h"
+#include <linux/power/omap/prm3xxx.h>
 #include "prm44xx.h"
 
 /*
diff --git a/include/linux/power/omap/prm3xxx.h b/include/linux/power/omap/prm3xxx.h
new file mode 100644
index 0000000..3bdc372
--- /dev/null
+++ b/include/linux/power/omap/prm3xxx.h
@@ -0,0 +1,132 @@
+/*
+ * OMAP3xxx Power/Reset Management (PRM) register definitions
+ *
+ * Copyright (C) 2007-2009, 2011-2012 Texas Instruments, Inc.
+ * Copyright (C) 2008-2010 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * The PRM hardware modules on the OMAP2/3 are quite similar to each
+ * other.  The PRM on OMAP4 has a new register layout, and is handled
+ * in a separate file.
+ */
+#ifndef __LINUX_POWER_OMAP_PRM3XXX_H
+#define __LINUX_POWER_OMAP_PRM3XXX_H
+
+#include <linux/power/omap/prm2xxx_3xxx.h>
+
+/*
+ * OMAP3-specific global PRM registers
+ * Use __raw_{read,write}l() with these registers.
+ *
+ * With a few exceptions, these are the register names beginning with
+ * PRM_* on 34xx.  (The exceptions are the IRQSTATUS and IRQENABLE
+ * bits.)
+ */
+
+#define OMAP3_PRM_REVISION_OFFSET	0x0004
+#define OMAP3_PRM_SYSCONFIG_OFFSET	0x0014
+
+#define OMAP3_PRM_IRQSTATUS_MPU_OFFSET	0x0018
+#define OMAP3_PRM_IRQENABLE_MPU_OFFSET	0x001c
+
+
+#define OMAP3_PRM_VC_SMPS_SA_OFFSET	0x0020
+#define OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET	0x0024
+#define OMAP3_PRM_VC_SMPS_CMD_RA_OFFSET	0x0028
+#define OMAP3_PRM_VC_CMD_VAL_0_OFFSET	0x002c
+#define OMAP3_PRM_VC_CMD_VAL_1_OFFSET	0x0030
+#define OMAP3_PRM_VC_CH_CONF_OFFSET	0x0034
+#define OMAP3_PRM_VC_I2C_CFG_OFFSET	0x0038
+#define OMAP3_PRM_VC_BYPASS_VAL_OFFSET	0x003c
+#define OMAP3_PRM_RSTCTRL_OFFSET	0x0050
+#define OMAP3_PRM_RSTTIME_OFFSET	0x0054
+#define OMAP3_PRM_RSTST_OFFSET	0x0058
+#define OMAP3_PRM_VOLTCTRL_OFFSET	0x0060
+#define OMAP3_PRM_SRAM_PCHARGE_OFFSET	0x0064
+#define OMAP3_PRM_CLKSRC_CTRL_OFFSET	0x0070
+#define OMAP3_PRM_VOLTSETUP1_OFFSET	0x0090
+#define OMAP3_PRM_VOLTOFFSET_OFFSET	0x0094
+#define OMAP3_PRM_CLKSETUP_OFFSET	0x0098
+#define OMAP3_PRM_POLCTRL_OFFSET	0x009c
+#define OMAP3_PRM_VOLTSETUP2_OFFSET	0x00a0
+#define OMAP3_PRM_VP1_CONFIG_OFFSET	0x00b0
+#define OMAP3_PRM_VP1_VSTEPMIN_OFFSET	0x00b4
+#define OMAP3_PRM_VP1_VSTEPMAX_OFFSET	0x00b8
+#define OMAP3_PRM_VP1_VLIMITTO_OFFSET	0x00bc
+#define OMAP3_PRM_VP1_VOLTAGE_OFFSET	0x00c0
+#define OMAP3_PRM_VP1_STATUS_OFFSET	0x00c4
+#define OMAP3_PRM_VP2_CONFIG_OFFSET	0x00d0
+#define OMAP3_PRM_VP2_VSTEPMIN_OFFSET	0x00d4
+#define OMAP3_PRM_VP2_VSTEPMAX_OFFSET	0x00d8
+#define OMAP3_PRM_VP2_VLIMITTO_OFFSET	0x00dc
+#define OMAP3_PRM_VP2_VOLTAGE_OFFSET	0x00e0
+#define OMAP3_PRM_VP2_STATUS_OFFSET	0x00e4
+
+#define OMAP3_PRM_CLKSEL_OFFSET	0x0040
+#define OMAP3_PRM_CLKOUT_CTRL_OFFSET	0x0070
+
+/* OMAP3 specific register offsets */
+#define OMAP3430ES2_PM_WKEN3				0x00f0
+#define OMAP3430ES2_PM_WKST3				0x00b8
+
+#define OMAP3430_PM_MPUGRPSEL				0x00a4
+#define OMAP3430_PM_MPUGRPSEL1				OMAP3430_PM_MPUGRPSEL
+#define OMAP3430ES2_PM_MPUGRPSEL3			0x00f8
+
+#define OMAP3430_PM_IVAGRPSEL				0x00a8
+#define OMAP3430_PM_IVAGRPSEL1				OMAP3430_PM_IVAGRPSEL
+#define OMAP3430ES2_PM_IVAGRPSEL3			0x00f4
+
+#define OMAP3430_PM_PREPWSTST				0x00e8
+
+#define OMAP3430_PRM_IRQSTATUS_IVA2			0x00f8
+#define OMAP3430_PRM_IRQENABLE_IVA2			0x00fc
+
+
+#ifndef __ASSEMBLER__
+
+/* OMAP3-specific VP functions */
+u32 omap3_prm_vp_check_txdone(u8 vp_id);
+void omap3_prm_vp_clear_txdone(u8 vp_id);
+
+/*
+ * OMAP3 access functions for voltage controller (VC) and
+ * voltage proccessor (VP) in the PRM.
+ */
+u32 omap3_prm_vcvp_read(u8 offset);
+void omap3_prm_vcvp_write(u32 val, u8 offset);
+u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
+
+#ifdef CONFIG_ARCH_OMAP3
+void omap3xxx_prm_reconfigure_io_chain(void);
+#else
+static inline void omap3xxx_prm_reconfigure_io_chain(void)
+{
+}
+#endif
+
+/* PRM interrupt-related functions */
+void omap3xxx_prm_read_pending_irqs(unsigned long *events);
+void omap3xxx_prm_ocp_barrier(void);
+void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask);
+void omap3xxx_prm_restore_irqen(u32 *saved_mask);
+
+void omap3xxx_prm_dpll3_reset(void);
+
+int __init omap3xxx_prm_init(u16 cpu_type);
+u32 omap3xxx_prm_get_reset_sources(void);
+int omap3xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits);
+void omap3xxx_prm_iva_idle(void);
+void omap3_prm_reset_modem(void);
+int omap3xxx_prm_clear_global_cold_reset(void);
+void omap3_prm_save_scratchpad_contents(u32 *ptr);
+void omap3_prm_init_pm(bool has_uart4, bool has_iva);
+
+#endif /* __ASSEMBLER */
+
+
+#endif
-- 
1.7.9.5

[PATCH 37/55] ARM: OMAP4: PRM: remove direct register declaration macros

[Tero Kristo]

None of these are currently used, so cleanup.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/prm44xx.h |  318 -----------------------------------------
 1 file changed, 318 deletions(-)

diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h
index 7db2422..7fc277b 100644
--- a/arch/arm/mach-omap2/prm44xx.h
+++ b/arch/arm/mach-omap2/prm44xx.h
@@ -73,676 +73,358 @@
 
 /* PRM.OCP_SOCKET_PRM register offsets */
 #define OMAP4_REVISION_PRM_OFFSET			0x0000
-#define OMAP4430_REVISION_PRM				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0000)
 #define OMAP4_PRM_IRQSTATUS_MPU_OFFSET			0x0010
-#define OMAP4430_PRM_IRQSTATUS_MPU			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0010)
 #define OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET		0x0014
-#define OMAP4430_PRM_IRQSTATUS_MPU_2			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0014)
 #define OMAP4_PRM_IRQENABLE_MPU_OFFSET			0x0018
-#define OMAP4430_PRM_IRQENABLE_MPU			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0018)
 #define OMAP4_PRM_IRQENABLE_MPU_2_OFFSET		0x001c
-#define OMAP4430_PRM_IRQENABLE_MPU_2			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x001c)
 #define OMAP4_PRM_IRQSTATUS_DUCATI_OFFSET		0x0020
-#define OMAP4430_PRM_IRQSTATUS_DUCATI			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0020)
 #define OMAP4_PRM_IRQENABLE_DUCATI_OFFSET		0x0028
-#define OMAP4430_PRM_IRQENABLE_DUCATI			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0028)
 #define OMAP4_PRM_IRQSTATUS_TESLA_OFFSET		0x0030
-#define OMAP4430_PRM_IRQSTATUS_TESLA			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0030)
 #define OMAP4_PRM_IRQENABLE_TESLA_OFFSET		0x0038
-#define OMAP4430_PRM_IRQENABLE_TESLA			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0038)
 #define OMAP4_CM_PRM_PROFILING_CLKCTRL_OFFSET		0x0040
-#define OMAP4430_CM_PRM_PROFILING_CLKCTRL		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0040)
 
 /* PRM.CKGEN_PRM register offsets */
 #define OMAP4_CM_ABE_DSS_SYS_CLKSEL_OFFSET		0x0000
-#define OMAP4430_CM_ABE_DSS_SYS_CLKSEL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_INST, 0x0000)
 #define OMAP4_CM_L4_WKUP_CLKSEL_OFFSET			0x0008
-#define OMAP4430_CM_L4_WKUP_CLKSEL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_INST, 0x0008)
 #define OMAP4_CM_ABE_PLL_REF_CLKSEL_OFFSET		0x000c
-#define OMAP4430_CM_ABE_PLL_REF_CLKSEL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_INST, 0x000c)
 #define OMAP4_CM_SYS_CLKSEL_OFFSET			0x0010
-#define OMAP4430_CM_SYS_CLKSEL				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_INST, 0x0010)
 
 /* PRM.MPU_PRM register offsets */
 #define OMAP4_PM_MPU_PWRSTCTRL_OFFSET			0x0000
-#define OMAP4430_PM_MPU_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_INST, 0x0000)
 #define OMAP4_PM_MPU_PWRSTST_OFFSET			0x0004
-#define OMAP4430_PM_MPU_PWRSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_INST, 0x0004)
 #define OMAP4_RM_MPU_RSTST_OFFSET			0x0014
-#define OMAP4430_RM_MPU_RSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_INST, 0x0014)
 #define OMAP4_RM_MPU_MPU_CONTEXT_OFFSET			0x0024
-#define OMAP4430_RM_MPU_MPU_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_INST, 0x0024)
 
 /* PRM.TESLA_PRM register offsets */
 #define OMAP4_PM_TESLA_PWRSTCTRL_OFFSET			0x0000
-#define OMAP4430_PM_TESLA_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0000)
 #define OMAP4_PM_TESLA_PWRSTST_OFFSET			0x0004
-#define OMAP4430_PM_TESLA_PWRSTST			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0004)
 #define OMAP4_RM_TESLA_RSTCTRL_OFFSET			0x0010
-#define OMAP4430_RM_TESLA_RSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0010)
 #define OMAP4_RM_TESLA_RSTST_OFFSET			0x0014
-#define OMAP4430_RM_TESLA_RSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0014)
 #define OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET		0x0024
-#define OMAP4430_RM_TESLA_TESLA_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0024)
 
 /* PRM.ABE_PRM register offsets */
 #define OMAP4_PM_ABE_PWRSTCTRL_OFFSET			0x0000
-#define OMAP4430_PM_ABE_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0000)
 #define OMAP4_PM_ABE_PWRSTST_OFFSET			0x0004
-#define OMAP4430_PM_ABE_PWRSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0004)
 #define OMAP4_RM_ABE_AESS_CONTEXT_OFFSET		0x002c
-#define OMAP4430_RM_ABE_AESS_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x002c)
 #define OMAP4_PM_ABE_PDM_WKDEP_OFFSET			0x0030
-#define OMAP4430_PM_ABE_PDM_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0030)
 #define OMAP4_RM_ABE_PDM_CONTEXT_OFFSET			0x0034
-#define OMAP4430_RM_ABE_PDM_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0034)
 #define OMAP4_PM_ABE_DMIC_WKDEP_OFFSET			0x0038
-#define OMAP4430_PM_ABE_DMIC_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0038)
 #define OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET		0x003c
-#define OMAP4430_RM_ABE_DMIC_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x003c)
 #define OMAP4_PM_ABE_MCASP_WKDEP_OFFSET			0x0040
-#define OMAP4430_PM_ABE_MCASP_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0040)
 #define OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET		0x0044
-#define OMAP4430_RM_ABE_MCASP_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0044)
 #define OMAP4_PM_ABE_MCBSP1_WKDEP_OFFSET		0x0048
-#define OMAP4430_PM_ABE_MCBSP1_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0048)
 #define OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET		0x004c
-#define OMAP4430_RM_ABE_MCBSP1_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x004c)
 #define OMAP4_PM_ABE_MCBSP2_WKDEP_OFFSET		0x0050
-#define OMAP4430_PM_ABE_MCBSP2_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0050)
 #define OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET		0x0054
-#define OMAP4430_RM_ABE_MCBSP2_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0054)
 #define OMAP4_PM_ABE_MCBSP3_WKDEP_OFFSET		0x0058
-#define OMAP4430_PM_ABE_MCBSP3_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0058)
 #define OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET		0x005c
-#define OMAP4430_RM_ABE_MCBSP3_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x005c)
 #define OMAP4_PM_ABE_SLIMBUS_WKDEP_OFFSET		0x0060
-#define OMAP4430_PM_ABE_SLIMBUS_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0060)
 #define OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET		0x0064
-#define OMAP4430_RM_ABE_SLIMBUS_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0064)
 #define OMAP4_PM_ABE_TIMER5_WKDEP_OFFSET		0x0068
-#define OMAP4430_PM_ABE_TIMER5_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0068)
 #define OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET		0x006c
-#define OMAP4430_RM_ABE_TIMER5_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x006c)
 #define OMAP4_PM_ABE_TIMER6_WKDEP_OFFSET		0x0070
-#define OMAP4430_PM_ABE_TIMER6_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0070)
 #define OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET		0x0074
-#define OMAP4430_RM_ABE_TIMER6_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0074)
 #define OMAP4_PM_ABE_TIMER7_WKDEP_OFFSET		0x0078
-#define OMAP4430_PM_ABE_TIMER7_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0078)
 #define OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET		0x007c
-#define OMAP4430_RM_ABE_TIMER7_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x007c)
 #define OMAP4_PM_ABE_TIMER8_WKDEP_OFFSET		0x0080
-#define OMAP4430_PM_ABE_TIMER8_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0080)
 #define OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET		0x0084
-#define OMAP4430_RM_ABE_TIMER8_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0084)
 #define OMAP4_PM_ABE_WDT3_WKDEP_OFFSET			0x0088
-#define OMAP4430_PM_ABE_WDT3_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0088)
 #define OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET		0x008c
-#define OMAP4430_RM_ABE_WDT3_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x008c)
 
 /* PRM.ALWAYS_ON_PRM register offsets */
 #define OMAP4_RM_ALWON_MDMINTC_CONTEXT_OFFSET		0x0024
-#define OMAP4430_RM_ALWON_MDMINTC_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0024)
 #define OMAP4_PM_ALWON_SR_MPU_WKDEP_OFFSET		0x0028
-#define OMAP4430_PM_ALWON_SR_MPU_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0028)
 #define OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET		0x002c
-#define OMAP4430_RM_ALWON_SR_MPU_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x002c)
 #define OMAP4_PM_ALWON_SR_IVA_WKDEP_OFFSET		0x0030
-#define OMAP4430_PM_ALWON_SR_IVA_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0030)
 #define OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET		0x0034
-#define OMAP4430_RM_ALWON_SR_IVA_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0034)
 #define OMAP4_PM_ALWON_SR_CORE_WKDEP_OFFSET		0x0038
-#define OMAP4430_PM_ALWON_SR_CORE_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0038)
 #define OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET		0x003c
-#define OMAP4430_RM_ALWON_SR_CORE_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x003c)
 
 /* PRM.CORE_PRM register offsets */
 #define OMAP4_PM_CORE_PWRSTCTRL_OFFSET			0x0000
-#define OMAP4430_PM_CORE_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0000)
 #define OMAP4_PM_CORE_PWRSTST_OFFSET			0x0004
-#define OMAP4430_PM_CORE_PWRSTST			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0004)
 #define OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET		0x0024
-#define OMAP4430_RM_L3_1_L3_1_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0024)
 #define OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET		0x0124
-#define OMAP4430_RM_L3_2_L3_2_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0124)
 #define OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET		0x012c
-#define OMAP4430_RM_L3_2_GPMC_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x012c)
 #define OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET		0x0134
-#define OMAP4430_RM_L3_2_OCMC_RAM_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0134)
 #define OMAP4_RM_DUCATI_RSTCTRL_OFFSET			0x0210
-#define OMAP4430_RM_DUCATI_RSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0210)
 #define OMAP4_RM_DUCATI_RSTST_OFFSET			0x0214
-#define OMAP4430_RM_DUCATI_RSTST			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0214)
 #define OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET		0x0224
-#define OMAP4430_RM_DUCATI_DUCATI_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0224)
 #define OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET		0x0324
-#define OMAP4430_RM_SDMA_SDMA_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0324)
 #define OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET		0x0424
-#define OMAP4430_RM_MEMIF_DMM_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0424)
 #define OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET		0x042c
-#define OMAP4430_RM_MEMIF_EMIF_FW_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x042c)
 #define OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET		0x0434
-#define OMAP4430_RM_MEMIF_EMIF_1_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0434)
 #define OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET		0x043c
-#define OMAP4430_RM_MEMIF_EMIF_2_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x043c)
 #define OMAP4_RM_MEMIF_DLL_CONTEXT_OFFSET		0x0444
-#define OMAP4430_RM_MEMIF_DLL_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0444)
 #define OMAP4_RM_MEMIF_EMIF_H1_CONTEXT_OFFSET		0x0454
-#define OMAP4430_RM_MEMIF_EMIF_H1_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0454)
 #define OMAP4_RM_MEMIF_EMIF_H2_CONTEXT_OFFSET		0x045c
-#define OMAP4430_RM_MEMIF_EMIF_H2_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x045c)
 #define OMAP4_RM_MEMIF_DLL_H_CONTEXT_OFFSET		0x0464
-#define OMAP4430_RM_MEMIF_DLL_H_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0464)
 #define OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET		0x0524
-#define OMAP4430_RM_D2D_SAD2D_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0524)
 #define OMAP4_RM_D2D_MODEM_ICR_CONTEXT_OFFSET		0x052c
-#define OMAP4430_RM_D2D_MODEM_ICR_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x052c)
 #define OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET		0x0534
-#define OMAP4430_RM_D2D_SAD2D_FW_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0534)
 #define OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET		0x0624
-#define OMAP4430_RM_L4CFG_L4_CFG_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0624)
 #define OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET		0x062c
-#define OMAP4430_RM_L4CFG_HW_SEM_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x062c)
 #define OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET		0x0634
-#define OMAP4430_RM_L4CFG_MAILBOX_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0634)
 #define OMAP4_RM_L4CFG_SAR_ROM_CONTEXT_OFFSET		0x063c
-#define OMAP4430_RM_L4CFG_SAR_ROM_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x063c)
 #define OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET		0x0724
-#define OMAP4430_RM_L3INSTR_L3_3_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0724)
 #define OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET	0x072c
-#define OMAP4430_RM_L3INSTR_L3_INSTR_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x072c)
 #define OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET		0x0744
-#define OMAP4430_RM_L3INSTR_OCP_WP1_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0744)
 
 /* PRM.IVAHD_PRM register offsets */
 #define OMAP4_PM_IVAHD_PWRSTCTRL_OFFSET			0x0000
-#define OMAP4430_PM_IVAHD_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0000)
 #define OMAP4_PM_IVAHD_PWRSTST_OFFSET			0x0004
-#define OMAP4430_PM_IVAHD_PWRSTST			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0004)
 #define OMAP4_RM_IVAHD_RSTCTRL_OFFSET			0x0010
-#define OMAP4430_RM_IVAHD_RSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0010)
 #define OMAP4_RM_IVAHD_RSTST_OFFSET			0x0014
-#define OMAP4430_RM_IVAHD_RSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0014)
 #define OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET		0x0024
-#define OMAP4430_RM_IVAHD_IVAHD_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0024)
 #define OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET		0x002c
-#define OMAP4430_RM_IVAHD_SL2_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x002c)
 
 /* PRM.CAM_PRM register offsets */
 #define OMAP4_PM_CAM_PWRSTCTRL_OFFSET			0x0000
-#define OMAP4430_PM_CAM_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_INST, 0x0000)
 #define OMAP4_PM_CAM_PWRSTST_OFFSET			0x0004
-#define OMAP4430_PM_CAM_PWRSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_INST, 0x0004)
 #define OMAP4_RM_CAM_ISS_CONTEXT_OFFSET			0x0024
-#define OMAP4430_RM_CAM_ISS_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_INST, 0x0024)
 #define OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET		0x002c
-#define OMAP4430_RM_CAM_FDIF_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_INST, 0x002c)
 
 /* PRM.DSS_PRM register offsets */
 #define OMAP4_PM_DSS_PWRSTCTRL_OFFSET			0x0000
-#define OMAP4430_PM_DSS_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x0000)
 #define OMAP4_PM_DSS_PWRSTST_OFFSET			0x0004
-#define OMAP4430_PM_DSS_PWRSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x0004)
 #define OMAP4_PM_DSS_DSS_WKDEP_OFFSET			0x0020
-#define OMAP4430_PM_DSS_DSS_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x0020)
 #define OMAP4_RM_DSS_DSS_CONTEXT_OFFSET			0x0024
-#define OMAP4430_RM_DSS_DSS_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x0024)
 #define OMAP4_RM_DSS_DEISS_CONTEXT_OFFSET		0x002c
-#define OMAP4430_RM_DSS_DEISS_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x002c)
 
 /* PRM.GFX_PRM register offsets */
 #define OMAP4_PM_GFX_PWRSTCTRL_OFFSET			0x0000
-#define OMAP4430_PM_GFX_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_INST, 0x0000)
 #define OMAP4_PM_GFX_PWRSTST_OFFSET			0x0004
-#define OMAP4430_PM_GFX_PWRSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_INST, 0x0004)
 #define OMAP4_RM_GFX_GFX_CONTEXT_OFFSET			0x0024
-#define OMAP4430_RM_GFX_GFX_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_INST, 0x0024)
 
 /* PRM.L3INIT_PRM register offsets */
 #define OMAP4_PM_L3INIT_PWRSTCTRL_OFFSET		0x0000
-#define OMAP4430_PM_L3INIT_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0000)
 #define OMAP4_PM_L3INIT_PWRSTST_OFFSET			0x0004
-#define OMAP4430_PM_L3INIT_PWRSTST			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0004)
 #define OMAP4_PM_L3INIT_MMC1_WKDEP_OFFSET		0x0028
-#define OMAP4430_PM_L3INIT_MMC1_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0028)
 #define OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET		0x002c
-#define OMAP4430_RM_L3INIT_MMC1_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x002c)
 #define OMAP4_PM_L3INIT_MMC2_WKDEP_OFFSET		0x0030
-#define OMAP4430_PM_L3INIT_MMC2_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0030)
 #define OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET		0x0034
-#define OMAP4430_RM_L3INIT_MMC2_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0034)
 #define OMAP4_PM_L3INIT_HSI_WKDEP_OFFSET		0x0038
-#define OMAP4430_PM_L3INIT_HSI_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0038)
 #define OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET		0x003c
-#define OMAP4430_RM_L3INIT_HSI_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x003c)
 #define OMAP4_PM_L3INIT_UNIPRO1_WKDEP_OFFSET		0x0040
-#define OMAP4430_PM_L3INIT_UNIPRO1_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0040)
 #define OMAP4_RM_L3INIT_UNIPRO1_CONTEXT_OFFSET		0x0044
-#define OMAP4430_RM_L3INIT_UNIPRO1_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0044)
 #define OMAP4_PM_L3INIT_USB_HOST_WKDEP_OFFSET		0x0058
-#define OMAP4430_PM_L3INIT_USB_HOST_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0058)
 #define OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET		0x005c
-#define OMAP4430_RM_L3INIT_USB_HOST_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x005c)
 #define OMAP4_PM_L3INIT_USB_OTG_WKDEP_OFFSET		0x0060
-#define OMAP4430_PM_L3INIT_USB_OTG_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0060)
 #define OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET		0x0064
-#define OMAP4430_RM_L3INIT_USB_OTG_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0064)
 #define OMAP4_PM_L3INIT_USB_TLL_WKDEP_OFFSET		0x0068
-#define OMAP4430_PM_L3INIT_USB_TLL_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0068)
 #define OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET		0x006c
-#define OMAP4430_RM_L3INIT_USB_TLL_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x006c)
 #define OMAP4_RM_L3INIT_P1500_CONTEXT_OFFSET		0x007c
-#define OMAP4430_RM_L3INIT_P1500_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x007c)
 #define OMAP4_RM_L3INIT_EMAC_CONTEXT_OFFSET		0x0084
-#define OMAP4430_RM_L3INIT_EMAC_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0084)
 #define OMAP4_PM_L3INIT_SATA_WKDEP_OFFSET		0x0088
-#define OMAP4430_PM_L3INIT_SATA_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0088)
 #define OMAP4_RM_L3INIT_SATA_CONTEXT_OFFSET		0x008c
-#define OMAP4430_RM_L3INIT_SATA_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x008c)
 #define OMAP4_RM_L3INIT_TPPSS_CONTEXT_OFFSET		0x0094
-#define OMAP4430_RM_L3INIT_TPPSS_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0094)
 #define OMAP4_PM_L3INIT_PCIESS_WKDEP_OFFSET		0x0098
-#define OMAP4430_PM_L3INIT_PCIESS_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0098)
 #define OMAP4_RM_L3INIT_PCIESS_CONTEXT_OFFSET		0x009c
-#define OMAP4430_RM_L3INIT_PCIESS_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x009c)
 #define OMAP4_RM_L3INIT_CCPTX_CONTEXT_OFFSET		0x00ac
-#define OMAP4430_RM_L3INIT_CCPTX_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00ac)
 #define OMAP4_PM_L3INIT_XHPI_WKDEP_OFFSET		0x00c0
-#define OMAP4430_PM_L3INIT_XHPI_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00c0)
 #define OMAP4_RM_L3INIT_XHPI_CONTEXT_OFFSET		0x00c4
-#define OMAP4430_RM_L3INIT_XHPI_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00c4)
 #define OMAP4_PM_L3INIT_MMC6_WKDEP_OFFSET		0x00c8
-#define OMAP4430_PM_L3INIT_MMC6_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00c8)
 #define OMAP4_RM_L3INIT_MMC6_CONTEXT_OFFSET		0x00cc
-#define OMAP4430_RM_L3INIT_MMC6_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00cc)
 #define OMAP4_PM_L3INIT_USB_HOST_FS_WKDEP_OFFSET	0x00d0
-#define OMAP4430_PM_L3INIT_USB_HOST_FS_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00d0)
 #define OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET	0x00d4
-#define OMAP4430_RM_L3INIT_USB_HOST_FS_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00d4)
 #define OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET	0x00e4
-#define OMAP4430_RM_L3INIT_USBPHYOCP2SCP_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00e4)
 
 /* PRM.L4PER_PRM register offsets */
 #define OMAP4_PM_L4PER_PWRSTCTRL_OFFSET			0x0000
-#define OMAP4430_PM_L4PER_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0000)
 #define OMAP4_PM_L4PER_PWRSTST_OFFSET			0x0004
-#define OMAP4430_PM_L4PER_PWRSTST			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0004)
 #define OMAP4_RM_L4PER_ADC_CONTEXT_OFFSET		0x0024
-#define OMAP4430_RM_L4PER_ADC_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0024)
 #define OMAP4_PM_L4PER_DMTIMER10_WKDEP_OFFSET		0x0028
-#define OMAP4430_PM_L4PER_DMTIMER10_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0028)
 #define OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET		0x002c
-#define OMAP4430_RM_L4PER_DMTIMER10_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x002c)
 #define OMAP4_PM_L4PER_DMTIMER11_WKDEP_OFFSET		0x0030
-#define OMAP4430_PM_L4PER_DMTIMER11_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0030)
 #define OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET		0x0034
-#define OMAP4430_RM_L4PER_DMTIMER11_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0034)
 #define OMAP4_PM_L4PER_DMTIMER2_WKDEP_OFFSET		0x0038
-#define OMAP4430_PM_L4PER_DMTIMER2_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0038)
 #define OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET		0x003c
-#define OMAP4430_RM_L4PER_DMTIMER2_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x003c)
 #define OMAP4_PM_L4PER_DMTIMER3_WKDEP_OFFSET		0x0040
-#define OMAP4430_PM_L4PER_DMTIMER3_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0040)
 #define OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET		0x0044
-#define OMAP4430_RM_L4PER_DMTIMER3_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0044)
 #define OMAP4_PM_L4PER_DMTIMER4_WKDEP_OFFSET		0x0048
-#define OMAP4430_PM_L4PER_DMTIMER4_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0048)
 #define OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET		0x004c
-#define OMAP4430_RM_L4PER_DMTIMER4_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x004c)
 #define OMAP4_PM_L4PER_DMTIMER9_WKDEP_OFFSET		0x0050
-#define OMAP4430_PM_L4PER_DMTIMER9_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0050)
 #define OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET		0x0054
-#define OMAP4430_RM_L4PER_DMTIMER9_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0054)
 #define OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET		0x005c
-#define OMAP4430_RM_L4PER_ELM_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x005c)
 #define OMAP4_PM_L4PER_GPIO2_WKDEP_OFFSET		0x0060
-#define OMAP4430_PM_L4PER_GPIO2_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0060)
 #define OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET		0x0064
-#define OMAP4430_RM_L4PER_GPIO2_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0064)
 #define OMAP4_PM_L4PER_GPIO3_WKDEP_OFFSET		0x0068
-#define OMAP4430_PM_L4PER_GPIO3_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0068)
 #define OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET		0x006c
-#define OMAP4430_RM_L4PER_GPIO3_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x006c)
 #define OMAP4_PM_L4PER_GPIO4_WKDEP_OFFSET		0x0070
-#define OMAP4430_PM_L4PER_GPIO4_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0070)
 #define OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET		0x0074
-#define OMAP4430_RM_L4PER_GPIO4_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0074)
 #define OMAP4_PM_L4PER_GPIO5_WKDEP_OFFSET		0x0078
-#define OMAP4430_PM_L4PER_GPIO5_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0078)
 #define OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET		0x007c
-#define OMAP4430_RM_L4PER_GPIO5_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x007c)
 #define OMAP4_PM_L4PER_GPIO6_WKDEP_OFFSET		0x0080
-#define OMAP4430_PM_L4PER_GPIO6_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0080)
 #define OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET		0x0084
-#define OMAP4430_RM_L4PER_GPIO6_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0084)
 #define OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET		0x008c
-#define OMAP4430_RM_L4PER_HDQ1W_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x008c)
 #define OMAP4_PM_L4PER_HECC1_WKDEP_OFFSET		0x0090
-#define OMAP4430_PM_L4PER_HECC1_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0090)
 #define OMAP4_RM_L4PER_HECC1_CONTEXT_OFFSET		0x0094
-#define OMAP4430_RM_L4PER_HECC1_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0094)
 #define OMAP4_PM_L4PER_HECC2_WKDEP_OFFSET		0x0098
-#define OMAP4430_PM_L4PER_HECC2_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0098)
 #define OMAP4_RM_L4PER_HECC2_CONTEXT_OFFSET		0x009c
-#define OMAP4430_RM_L4PER_HECC2_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x009c)
 #define OMAP4_PM_L4PER_I2C1_WKDEP_OFFSET		0x00a0
-#define OMAP4430_PM_L4PER_I2C1_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00a0)
 #define OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET		0x00a4
-#define OMAP4430_RM_L4PER_I2C1_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00a4)
 #define OMAP4_PM_L4PER_I2C2_WKDEP_OFFSET		0x00a8
-#define OMAP4430_PM_L4PER_I2C2_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00a8)
 #define OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET		0x00ac
-#define OMAP4430_RM_L4PER_I2C2_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00ac)
 #define OMAP4_PM_L4PER_I2C3_WKDEP_OFFSET		0x00b0
-#define OMAP4430_PM_L4PER_I2C3_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00b0)
 #define OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET		0x00b4
-#define OMAP4430_RM_L4PER_I2C3_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00b4)
 #define OMAP4_PM_L4PER_I2C4_WKDEP_OFFSET		0x00b8
-#define OMAP4430_PM_L4PER_I2C4_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00b8)
 #define OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET		0x00bc
-#define OMAP4430_RM_L4PER_I2C4_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00bc)
 #define OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET		0x00c0
-#define OMAP4430_RM_L4PER_L4_PER_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00c0)
 #define OMAP4_PM_L4PER_MCASP2_WKDEP_OFFSET		0x00d0
-#define OMAP4430_PM_L4PER_MCASP2_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00d0)
 #define OMAP4_RM_L4PER_MCASP2_CONTEXT_OFFSET		0x00d4
-#define OMAP4430_RM_L4PER_MCASP2_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00d4)
 #define OMAP4_PM_L4PER_MCASP3_WKDEP_OFFSET		0x00d8
-#define OMAP4430_PM_L4PER_MCASP3_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00d8)
 #define OMAP4_RM_L4PER_MCASP3_CONTEXT_OFFSET		0x00dc
-#define OMAP4430_RM_L4PER_MCASP3_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00dc)
 #define OMAP4_PM_L4PER_MCBSP4_WKDEP_OFFSET		0x00e0
-#define OMAP4430_PM_L4PER_MCBSP4_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00e0)
 #define OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET		0x00e4
-#define OMAP4430_RM_L4PER_MCBSP4_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00e4)
 #define OMAP4_RM_L4PER_MGATE_CONTEXT_OFFSET		0x00ec
-#define OMAP4430_RM_L4PER_MGATE_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00ec)
 #define OMAP4_PM_L4PER_MCSPI1_WKDEP_OFFSET		0x00f0
-#define OMAP4430_PM_L4PER_MCSPI1_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00f0)
 #define OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET		0x00f4
-#define OMAP4430_RM_L4PER_MCSPI1_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00f4)
 #define OMAP4_PM_L4PER_MCSPI2_WKDEP_OFFSET		0x00f8
-#define OMAP4430_PM_L4PER_MCSPI2_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00f8)
 #define OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET		0x00fc
-#define OMAP4430_RM_L4PER_MCSPI2_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00fc)
 #define OMAP4_PM_L4PER_MCSPI3_WKDEP_OFFSET		0x0100
-#define OMAP4430_PM_L4PER_MCSPI3_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0100)
 #define OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET		0x0104
-#define OMAP4430_RM_L4PER_MCSPI3_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0104)
 #define OMAP4_PM_L4PER_MCSPI4_WKDEP_OFFSET		0x0108
-#define OMAP4430_PM_L4PER_MCSPI4_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0108)
 #define OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET		0x010c
-#define OMAP4430_RM_L4PER_MCSPI4_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x010c)
 #define OMAP4_PM_L4PER_MMCSD3_WKDEP_OFFSET		0x0120
-#define OMAP4430_PM_L4PER_MMCSD3_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0120)
 #define OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET		0x0124
-#define OMAP4430_RM_L4PER_MMCSD3_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0124)
 #define OMAP4_PM_L4PER_MMCSD4_WKDEP_OFFSET		0x0128
-#define OMAP4430_PM_L4PER_MMCSD4_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0128)
 #define OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET		0x012c
-#define OMAP4430_RM_L4PER_MMCSD4_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x012c)
 #define OMAP4_RM_L4PER_MSPROHG_CONTEXT_OFFSET		0x0134
-#define OMAP4430_RM_L4PER_MSPROHG_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0134)
 #define OMAP4_PM_L4PER_SLIMBUS2_WKDEP_OFFSET		0x0138
-#define OMAP4430_PM_L4PER_SLIMBUS2_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0138)
 #define OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET		0x013c
-#define OMAP4430_RM_L4PER_SLIMBUS2_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x013c)
 #define OMAP4_PM_L4PER_UART1_WKDEP_OFFSET		0x0140
-#define OMAP4430_PM_L4PER_UART1_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0140)
 #define OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET		0x0144
-#define OMAP4430_RM_L4PER_UART1_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0144)
 #define OMAP4_PM_L4PER_UART2_WKDEP_OFFSET		0x0148
-#define OMAP4430_PM_L4PER_UART2_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0148)
 #define OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET		0x014c
-#define OMAP4430_RM_L4PER_UART2_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x014c)
 #define OMAP4_PM_L4PER_UART3_WKDEP_OFFSET		0x0150
-#define OMAP4430_PM_L4PER_UART3_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0150)
 #define OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET		0x0154
-#define OMAP4430_RM_L4PER_UART3_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0154)
 #define OMAP4_PM_L4PER_UART4_WKDEP_OFFSET		0x0158
-#define OMAP4430_PM_L4PER_UART4_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0158)
 #define OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET		0x015c
-#define OMAP4430_RM_L4PER_UART4_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x015c)
 #define OMAP4_PM_L4PER_MMCSD5_WKDEP_OFFSET		0x0160
-#define OMAP4430_PM_L4PER_MMCSD5_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0160)
 #define OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET		0x0164
-#define OMAP4430_RM_L4PER_MMCSD5_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0164)
 #define OMAP4_PM_L4PER_I2C5_WKDEP_OFFSET		0x0168
-#define OMAP4430_PM_L4PER_I2C5_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0168)
 #define OMAP4_RM_L4PER_I2C5_CONTEXT_OFFSET		0x016c
-#define OMAP4430_RM_L4PER_I2C5_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x016c)
 #define OMAP4_RM_L4SEC_AES1_CONTEXT_OFFSET		0x01a4
-#define OMAP4430_RM_L4SEC_AES1_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01a4)
 #define OMAP4_RM_L4SEC_AES2_CONTEXT_OFFSET		0x01ac
-#define OMAP4430_RM_L4SEC_AES2_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01ac)
 #define OMAP4_RM_L4SEC_DES3DES_CONTEXT_OFFSET		0x01b4
-#define OMAP4430_RM_L4SEC_DES3DES_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01b4)
 #define OMAP4_RM_L4SEC_PKAEIP29_CONTEXT_OFFSET		0x01bc
-#define OMAP4430_RM_L4SEC_PKAEIP29_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01bc)
 #define OMAP4_RM_L4SEC_RNG_CONTEXT_OFFSET		0x01c4
-#define OMAP4430_RM_L4SEC_RNG_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01c4)
 #define OMAP4_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET		0x01cc
-#define OMAP4430_RM_L4SEC_SHA2MD51_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01cc)
 #define OMAP4_RM_L4SEC_CRYPTODMA_CONTEXT_OFFSET		0x01dc
-#define OMAP4430_RM_L4SEC_CRYPTODMA_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01dc)
 
 /* PRM.CEFUSE_PRM register offsets */
 #define OMAP4_PM_CEFUSE_PWRSTCTRL_OFFSET		0x0000
-#define OMAP4430_PM_CEFUSE_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_INST, 0x0000)
 #define OMAP4_PM_CEFUSE_PWRSTST_OFFSET			0x0004
-#define OMAP4430_PM_CEFUSE_PWRSTST			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_INST, 0x0004)
 #define OMAP4_RM_CEFUSE_CEFUSE_CONTEXT_OFFSET		0x0024
-#define OMAP4430_RM_CEFUSE_CEFUSE_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_INST, 0x0024)
 
 /* PRM.WKUP_PRM register offsets */
 #define OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET		0x0024
-#define OMAP4430_RM_WKUP_L4WKUP_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0024)
 #define OMAP4_RM_WKUP_WDT1_CONTEXT_OFFSET		0x002c
-#define OMAP4430_RM_WKUP_WDT1_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x002c)
 #define OMAP4_PM_WKUP_WDT2_WKDEP_OFFSET			0x0030
-#define OMAP4430_PM_WKUP_WDT2_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0030)
 #define OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET		0x0034
-#define OMAP4430_RM_WKUP_WDT2_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0034)
 #define OMAP4_PM_WKUP_GPIO1_WKDEP_OFFSET		0x0038
-#define OMAP4430_PM_WKUP_GPIO1_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0038)
 #define OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET		0x003c
-#define OMAP4430_RM_WKUP_GPIO1_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x003c)
 #define OMAP4_PM_WKUP_TIMER1_WKDEP_OFFSET		0x0040
-#define OMAP4430_PM_WKUP_TIMER1_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0040)
 #define OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET		0x0044
-#define OMAP4430_RM_WKUP_TIMER1_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0044)
 #define OMAP4_PM_WKUP_TIMER12_WKDEP_OFFSET		0x0048
-#define OMAP4430_PM_WKUP_TIMER12_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0048)
 #define OMAP4_RM_WKUP_TIMER12_CONTEXT_OFFSET		0x004c
-#define OMAP4430_RM_WKUP_TIMER12_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x004c)
 #define OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET		0x0054
-#define OMAP4430_RM_WKUP_SYNCTIMER_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0054)
 #define OMAP4_PM_WKUP_USIM_WKDEP_OFFSET			0x0058
-#define OMAP4430_PM_WKUP_USIM_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0058)
 #define OMAP4_RM_WKUP_USIM_CONTEXT_OFFSET		0x005c
-#define OMAP4430_RM_WKUP_USIM_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x005c)
 #define OMAP4_RM_WKUP_SARRAM_CONTEXT_OFFSET		0x0064
-#define OMAP4430_RM_WKUP_SARRAM_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0064)
 #define OMAP4_PM_WKUP_KEYBOARD_WKDEP_OFFSET		0x0078
-#define OMAP4430_PM_WKUP_KEYBOARD_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0078)
 #define OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET		0x007c
-#define OMAP4430_RM_WKUP_KEYBOARD_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x007c)
 #define OMAP4_PM_WKUP_RTC_WKDEP_OFFSET			0x0080
-#define OMAP4430_PM_WKUP_RTC_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0080)
 #define OMAP4_RM_WKUP_RTC_CONTEXT_OFFSET		0x0084
-#define OMAP4430_RM_WKUP_RTC_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0084)
 
 /* PRM.WKUP_CM register offsets */
 #define OMAP4_CM_WKUP_CLKSTCTRL_OFFSET			0x0000
-#define OMAP4430_CM_WKUP_CLKSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0000)
 #define OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET		0x0020
-#define OMAP4430_CM_WKUP_L4WKUP_CLKCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0020)
 #define OMAP4_CM_WKUP_WDT1_CLKCTRL_OFFSET		0x0028
-#define OMAP4430_CM_WKUP_WDT1_CLKCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0028)
 #define OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET		0x0030
-#define OMAP4430_CM_WKUP_WDT2_CLKCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0030)
 #define OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET		0x0038
-#define OMAP4430_CM_WKUP_GPIO1_CLKCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0038)
 #define OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET		0x0040
-#define OMAP4430_CM_WKUP_TIMER1_CLKCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0040)
 #define OMAP4_CM_WKUP_TIMER12_CLKCTRL_OFFSET		0x0048
-#define OMAP4430_CM_WKUP_TIMER12_CLKCTRL		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0048)
 #define OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET		0x0050
-#define OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0050)
 #define OMAP4_CM_WKUP_USIM_CLKCTRL_OFFSET		0x0058
-#define OMAP4430_CM_WKUP_USIM_CLKCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0058)
 #define OMAP4_CM_WKUP_SARRAM_CLKCTRL_OFFSET		0x0060
-#define OMAP4430_CM_WKUP_SARRAM_CLKCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0060)
 #define OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET		0x0078
-#define OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0078)
 #define OMAP4_CM_WKUP_RTC_CLKCTRL_OFFSET		0x0080
-#define OMAP4430_CM_WKUP_RTC_CLKCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0080)
 #define OMAP4_CM_WKUP_BANDGAP_CLKCTRL_OFFSET		0x0088
-#define OMAP4430_CM_WKUP_BANDGAP_CLKCTRL		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0088)
 
 /* PRM.EMU_PRM register offsets */
 #define OMAP4_PM_EMU_PWRSTCTRL_OFFSET			0x0000
-#define OMAP4430_PM_EMU_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_INST, 0x0000)
 #define OMAP4_PM_EMU_PWRSTST_OFFSET			0x0004
-#define OMAP4430_PM_EMU_PWRSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_INST, 0x0004)
 #define OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET		0x0024
-#define OMAP4430_RM_EMU_DEBUGSS_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_INST, 0x0024)
 
 /* PRM.EMU_CM register offsets */
 #define OMAP4_CM_EMU_CLKSTCTRL_OFFSET			0x0000
-#define OMAP4430_CM_EMU_CLKSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_INST, 0x0000)
 #define OMAP4_CM_EMU_DYNAMICDEP_OFFSET			0x0008
-#define OMAP4430_CM_EMU_DYNAMICDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_INST, 0x0008)
 #define OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET		0x0020
-#define OMAP4430_CM_EMU_DEBUGSS_CLKCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_INST, 0x0020)
 
 /* PRM.DEVICE_PRM register offsets */
 #define OMAP4_PRM_RSTCTRL_OFFSET			0x0000
-#define OMAP4430_PRM_RSTCTRL				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0000)
 #define OMAP4_PRM_RSTST_OFFSET				0x0004
-#define OMAP4430_PRM_RSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0004)
 #define OMAP4_PRM_RSTTIME_OFFSET			0x0008
-#define OMAP4430_PRM_RSTTIME				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0008)
 #define OMAP4_PRM_CLKREQCTRL_OFFSET			0x000c
-#define OMAP4430_PRM_CLKREQCTRL				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x000c)
 #define OMAP4_PRM_VOLTCTRL_OFFSET			0x0010
-#define OMAP4430_PRM_VOLTCTRL				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0010)
 #define OMAP4_PRM_PWRREQCTRL_OFFSET			0x0014
-#define OMAP4430_PRM_PWRREQCTRL				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0014)
 #define OMAP4_PRM_PSCON_COUNT_OFFSET			0x0018
-#define OMAP4430_PRM_PSCON_COUNT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0018)
 #define OMAP4_PRM_IO_COUNT_OFFSET			0x001c
-#define OMAP4430_PRM_IO_COUNT				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x001c)
 #define OMAP4_PRM_IO_PMCTRL_OFFSET			0x0020
-#define OMAP4430_PRM_IO_PMCTRL				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0020)
 #define OMAP4_PRM_VOLTSETUP_WARMRESET_OFFSET		0x0024
-#define OMAP4430_PRM_VOLTSETUP_WARMRESET		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0024)
 #define OMAP4_PRM_VOLTSETUP_CORE_OFF_OFFSET		0x0028
-#define OMAP4430_PRM_VOLTSETUP_CORE_OFF			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0028)
 #define OMAP4_PRM_VOLTSETUP_MPU_OFF_OFFSET		0x002c
-#define OMAP4430_PRM_VOLTSETUP_MPU_OFF			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x002c)
 #define OMAP4_PRM_VOLTSETUP_IVA_OFF_OFFSET		0x0030
-#define OMAP4430_PRM_VOLTSETUP_IVA_OFF			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0030)
 #define OMAP4_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET	0x0034
-#define OMAP4430_PRM_VOLTSETUP_CORE_RET_SLEEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0034)
 #define OMAP4_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET	0x0038
-#define OMAP4430_PRM_VOLTSETUP_MPU_RET_SLEEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0038)
 #define OMAP4_PRM_VOLTSETUP_IVA_RET_SLEEP_OFFSET	0x003c
-#define OMAP4430_PRM_VOLTSETUP_IVA_RET_SLEEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x003c)
 #define OMAP4_PRM_VP_CORE_CONFIG_OFFSET			0x0040
-#define OMAP4430_PRM_VP_CORE_CONFIG			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0040)
 #define OMAP4_PRM_VP_CORE_STATUS_OFFSET			0x0044
-#define OMAP4430_PRM_VP_CORE_STATUS			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0044)
 #define OMAP4_PRM_VP_CORE_VLIMITTO_OFFSET		0x0048
-#define OMAP4430_PRM_VP_CORE_VLIMITTO			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0048)
 #define OMAP4_PRM_VP_CORE_VOLTAGE_OFFSET		0x004c
-#define OMAP4430_PRM_VP_CORE_VOLTAGE			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x004c)
 #define OMAP4_PRM_VP_CORE_VSTEPMAX_OFFSET		0x0050
-#define OMAP4430_PRM_VP_CORE_VSTEPMAX			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0050)
 #define OMAP4_PRM_VP_CORE_VSTEPMIN_OFFSET		0x0054
-#define OMAP4430_PRM_VP_CORE_VSTEPMIN			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0054)
 #define OMAP4_PRM_VP_MPU_CONFIG_OFFSET			0x0058
-#define OMAP4430_PRM_VP_MPU_CONFIG			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0058)
 #define OMAP4_PRM_VP_MPU_STATUS_OFFSET			0x005c
-#define OMAP4430_PRM_VP_MPU_STATUS			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x005c)
 #define OMAP4_PRM_VP_MPU_VLIMITTO_OFFSET		0x0060
-#define OMAP4430_PRM_VP_MPU_VLIMITTO			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0060)
 #define OMAP4_PRM_VP_MPU_VOLTAGE_OFFSET			0x0064
-#define OMAP4430_PRM_VP_MPU_VOLTAGE			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0064)
 #define OMAP4_PRM_VP_MPU_VSTEPMAX_OFFSET		0x0068
-#define OMAP4430_PRM_VP_MPU_VSTEPMAX			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0068)
 #define OMAP4_PRM_VP_MPU_VSTEPMIN_OFFSET		0x006c
-#define OMAP4430_PRM_VP_MPU_VSTEPMIN			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x006c)
 #define OMAP4_PRM_VP_IVA_CONFIG_OFFSET			0x0070
-#define OMAP4430_PRM_VP_IVA_CONFIG			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0070)
 #define OMAP4_PRM_VP_IVA_STATUS_OFFSET			0x0074
-#define OMAP4430_PRM_VP_IVA_STATUS			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0074)
 #define OMAP4_PRM_VP_IVA_VLIMITTO_OFFSET		0x0078
-#define OMAP4430_PRM_VP_IVA_VLIMITTO			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0078)
 #define OMAP4_PRM_VP_IVA_VOLTAGE_OFFSET			0x007c
-#define OMAP4430_PRM_VP_IVA_VOLTAGE			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x007c)
 #define OMAP4_PRM_VP_IVA_VSTEPMAX_OFFSET		0x0080
-#define OMAP4430_PRM_VP_IVA_VSTEPMAX			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0080)
 #define OMAP4_PRM_VP_IVA_VSTEPMIN_OFFSET		0x0084
-#define OMAP4430_PRM_VP_IVA_VSTEPMIN			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0084)
 #define OMAP4_PRM_VC_SMPS_SA_OFFSET			0x0088
-#define OMAP4430_PRM_VC_SMPS_SA				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0088)
 #define OMAP4_PRM_VC_VAL_SMPS_RA_VOL_OFFSET		0x008c
-#define OMAP4430_PRM_VC_VAL_SMPS_RA_VOL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x008c)
 #define OMAP4_PRM_VC_VAL_SMPS_RA_CMD_OFFSET		0x0090
-#define OMAP4430_PRM_VC_VAL_SMPS_RA_CMD			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0090)
 #define OMAP4_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET		0x0094
-#define OMAP4430_PRM_VC_VAL_CMD_VDD_CORE_L		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0094)
 #define OMAP4_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET		0x0098
-#define OMAP4430_PRM_VC_VAL_CMD_VDD_MPU_L		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0098)
 #define OMAP4_PRM_VC_VAL_CMD_VDD_IVA_L_OFFSET		0x009c
-#define OMAP4430_PRM_VC_VAL_CMD_VDD_IVA_L		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x009c)
 #define OMAP4_PRM_VC_VAL_BYPASS_OFFSET			0x00a0
-#define OMAP4430_PRM_VC_VAL_BYPASS			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a0)
 #define OMAP4_PRM_VC_CFG_CHANNEL_OFFSET			0x00a4
-#define OMAP4430_PRM_VC_CFG_CHANNEL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a4)
 #define OMAP4_PRM_VC_CFG_I2C_MODE_OFFSET		0x00a8
-#define OMAP4430_PRM_VC_CFG_I2C_MODE			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a8)
 #define OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET			0x00ac
-#define OMAP4430_PRM_VC_CFG_I2C_CLK			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00ac)
 #define OMAP4_PRM_SRAM_COUNT_OFFSET			0x00b0
-#define OMAP4430_PRM_SRAM_COUNT				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00b0)
 #define OMAP4_PRM_SRAM_WKUP_SETUP_OFFSET		0x00b4
-#define OMAP4430_PRM_SRAM_WKUP_SETUP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00b4)
 #define OMAP4_PRM_LDO_SRAM_CORE_SETUP_OFFSET		0x00b8
-#define OMAP4430_PRM_LDO_SRAM_CORE_SETUP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00b8)
 #define OMAP4_PRM_LDO_SRAM_CORE_CTRL_OFFSET		0x00bc
-#define OMAP4430_PRM_LDO_SRAM_CORE_CTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00bc)
 #define OMAP4_PRM_LDO_SRAM_MPU_SETUP_OFFSET		0x00c0
-#define OMAP4430_PRM_LDO_SRAM_MPU_SETUP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00c0)
 #define OMAP4_PRM_LDO_SRAM_MPU_CTRL_OFFSET		0x00c4
-#define OMAP4430_PRM_LDO_SRAM_MPU_CTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00c4)
 #define OMAP4_PRM_LDO_SRAM_IVA_SETUP_OFFSET		0x00c8
-#define OMAP4430_PRM_LDO_SRAM_IVA_SETUP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00c8)
 #define OMAP4_PRM_LDO_SRAM_IVA_CTRL_OFFSET		0x00cc
-#define OMAP4430_PRM_LDO_SRAM_IVA_CTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00cc)
 #define OMAP4_PRM_LDO_ABB_MPU_SETUP_OFFSET		0x00d0
-#define OMAP4430_PRM_LDO_ABB_MPU_SETUP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00d0)
 #define OMAP4_PRM_LDO_ABB_MPU_CTRL_OFFSET		0x00d4
-#define OMAP4430_PRM_LDO_ABB_MPU_CTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00d4)
 #define OMAP4_PRM_LDO_ABB_IVA_SETUP_OFFSET		0x00d8
-#define OMAP4430_PRM_LDO_ABB_IVA_SETUP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00d8)
 #define OMAP4_PRM_LDO_ABB_IVA_CTRL_OFFSET		0x00dc
-#define OMAP4430_PRM_LDO_ABB_IVA_CTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00dc)
 #define OMAP4_PRM_LDO_BANDGAP_SETUP_OFFSET		0x00e0
-#define OMAP4430_PRM_LDO_BANDGAP_SETUP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00e0)
 #define OMAP4_PRM_DEVICE_OFF_CTRL_OFFSET		0x00e4
-#define OMAP4430_PRM_DEVICE_OFF_CTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00e4)
 #define OMAP4_PRM_PHASE1_CNDP_OFFSET			0x00e8
-#define OMAP4430_PRM_PHASE1_CNDP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00e8)
 #define OMAP4_PRM_PHASE2A_CNDP_OFFSET			0x00ec
-#define OMAP4430_PRM_PHASE2A_CNDP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00ec)
 #define OMAP4_PRM_PHASE2B_CNDP_OFFSET			0x00f0
-#define OMAP4430_PRM_PHASE2B_CNDP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f0)
 #define OMAP4_PRM_MODEM_IF_CTRL_OFFSET			0x00f4
-#define OMAP4430_PRM_MODEM_IF_CTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f4)
 #define OMAP4_PRM_VC_ERRST_OFFSET			0x00f8
-#define OMAP4430_PRM_VC_ERRST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f8)
 
 #endif
-- 
1.7.9.5

[PATCH 38/55] ARM: OMAP4: PRM: move parts of prm44xx.h header file to public location

[Tero Kristo]

Parts of this file are needed from both the driver and mach-omap2 board
code.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/cminst44xx.c   |    3 +-
 arch/arm/mach-omap2/powerdomain.c  |    3 +-
 arch/arm/mach-omap2/prm44xx.c      |    2 +-
 arch/arm/mach-omap2/prm44xx.h      |  394 +--------------------------------
 arch/arm/mach-omap2/prm_common.c   |    5 +-
 arch/arm/mach-omap2/prminst44xx.c  |    3 +-
 include/linux/power/omap/prm44xx.h |  420 ++++++++++++++++++++++++++++++++++++
 7 files changed, 432 insertions(+), 398 deletions(-)
 create mode 100644 include/linux/power/omap/prm44xx.h

diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c
index b577a8e..084e5ce 100644
--- a/arch/arm/mach-omap2/cminst44xx.c
+++ b/arch/arm/mach-omap2/cminst44xx.c
@@ -21,13 +21,14 @@
 #include <linux/err.h>
 #include <linux/io.h>
 
+#include "prm.h"
 #include "clockdomain.h"
 #include <linux/power/omap/cm.h>
 #include "cm1_44xx.h"
 #include "cm2_44xx.h"
 #include <linux/power/omap/cm44xx.h>
 #include "prcm44xx.h"
-#include "prm44xx.h"
+#include <linux/power/omap/prm44xx.h>
 #include "prcm_mpu44xx.h"
 #include "prcm-common.h"
 
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index fdb6172..a29d50c 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -25,10 +25,11 @@
 #include <linux/power/omap/cm2xxx_3xxx.h>
 #include "prcm44xx.h"
 #include <linux/power/omap/prm2xxx_3xxx.h>
-#include "prm44xx.h"
+#include <linux/power/omap/prm44xx.h>
 
 #include <asm/cpu.h>
 
+#include "prm.h"
 #include "powerdomain.h"
 #include "clockdomain.h"
 #include "voltage.h"
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index 5033cd3..dff2ffa 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -20,7 +20,7 @@
 
 
 #include "vp.h"
-#include "prm44xx.h"
+#include <linux/power/omap/prm44xx.h>
 #include "prm54xx.h"
 #include "prm7xx.h"
 #include "prcm44xx.h"
diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h
index 7fc277b..1f7a3a6 100644
--- a/arch/arm/mach-omap2/prm44xx.h
+++ b/arch/arm/mach-omap2/prm44xx.h
@@ -28,403 +28,11 @@
 #include "prm44xx_54xx.h"
 #include "prcm-common.h"
 #include "prm.h"
+#include <linux/power/omap/prm44xx.h>
 
 #define OMAP4430_PRM_BASE		0x4a306000
 
 #define OMAP44XX_PRM_REGADDR(inst, reg)				\
 	OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (inst) + (reg))
 
-
-/* PRM instances */
-#define OMAP4430_PRM_OCP_SOCKET_INST	0x0000
-#define OMAP4430_PRM_CKGEN_INST		0x0100
-#define OMAP4430_PRM_MPU_INST		0x0300
-#define OMAP4430_PRM_TESLA_INST		0x0400
-#define OMAP4430_PRM_ABE_INST		0x0500
-#define OMAP4430_PRM_ALWAYS_ON_INST	0x0600
-#define OMAP4430_PRM_CORE_INST		0x0700
-#define OMAP4430_PRM_IVAHD_INST		0x0f00
-#define OMAP4430_PRM_CAM_INST		0x1000
-#define OMAP4430_PRM_DSS_INST		0x1100
-#define OMAP4430_PRM_GFX_INST		0x1200
-#define OMAP4430_PRM_L3INIT_INST	0x1300
-#define OMAP4430_PRM_L4PER_INST		0x1400
-#define OMAP4430_PRM_CEFUSE_INST	0x1600
-#define OMAP4430_PRM_WKUP_INST		0x1700
-#define OMAP4430_PRM_WKUP_CM_INST	0x1800
-#define OMAP4430_PRM_EMU_INST		0x1900
-#define OMAP4430_PRM_EMU_CM_INST	0x1a00
-#define OMAP4430_PRM_DEVICE_INST	0x1b00
-#define OMAP4430_PRM_INSTR_INST		0x1f00
-
-/* PRM clockdomain register offsets (from instance start) */
-#define OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS	0x0000
-#define OMAP4430_PRM_EMU_CM_EMU_CDOFFS		0x0000
-
-/* OMAP4 specific register offsets */
-#define OMAP4_RM_RSTCTRL				0x0000
-#define OMAP4_RM_RSTST					0x0004
-#define OMAP4_RM_RSTTIME				0x0008
-#define OMAP4_PM_PWSTCTRL				0x0000
-#define OMAP4_PM_PWSTST					0x0004
-
-
-/* PRM */
-
-/* PRM.OCP_SOCKET_PRM register offsets */
-#define OMAP4_REVISION_PRM_OFFSET			0x0000
-#define OMAP4_PRM_IRQSTATUS_MPU_OFFSET			0x0010
-#define OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET		0x0014
-#define OMAP4_PRM_IRQENABLE_MPU_OFFSET			0x0018
-#define OMAP4_PRM_IRQENABLE_MPU_2_OFFSET		0x001c
-#define OMAP4_PRM_IRQSTATUS_DUCATI_OFFSET		0x0020
-#define OMAP4_PRM_IRQENABLE_DUCATI_OFFSET		0x0028
-#define OMAP4_PRM_IRQSTATUS_TESLA_OFFSET		0x0030
-#define OMAP4_PRM_IRQENABLE_TESLA_OFFSET		0x0038
-#define OMAP4_CM_PRM_PROFILING_CLKCTRL_OFFSET		0x0040
-
-/* PRM.CKGEN_PRM register offsets */
-#define OMAP4_CM_ABE_DSS_SYS_CLKSEL_OFFSET		0x0000
-#define OMAP4_CM_L4_WKUP_CLKSEL_OFFSET			0x0008
-#define OMAP4_CM_ABE_PLL_REF_CLKSEL_OFFSET		0x000c
-#define OMAP4_CM_SYS_CLKSEL_OFFSET			0x0010
-
-/* PRM.MPU_PRM register offsets */
-#define OMAP4_PM_MPU_PWRSTCTRL_OFFSET			0x0000
-#define OMAP4_PM_MPU_PWRSTST_OFFSET			0x0004
-#define OMAP4_RM_MPU_RSTST_OFFSET			0x0014
-#define OMAP4_RM_MPU_MPU_CONTEXT_OFFSET			0x0024
-
-/* PRM.TESLA_PRM register offsets */
-#define OMAP4_PM_TESLA_PWRSTCTRL_OFFSET			0x0000
-#define OMAP4_PM_TESLA_PWRSTST_OFFSET			0x0004
-#define OMAP4_RM_TESLA_RSTCTRL_OFFSET			0x0010
-#define OMAP4_RM_TESLA_RSTST_OFFSET			0x0014
-#define OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET		0x0024
-
-/* PRM.ABE_PRM register offsets */
-#define OMAP4_PM_ABE_PWRSTCTRL_OFFSET			0x0000
-#define OMAP4_PM_ABE_PWRSTST_OFFSET			0x0004
-#define OMAP4_RM_ABE_AESS_CONTEXT_OFFSET		0x002c
-#define OMAP4_PM_ABE_PDM_WKDEP_OFFSET			0x0030
-#define OMAP4_RM_ABE_PDM_CONTEXT_OFFSET			0x0034
-#define OMAP4_PM_ABE_DMIC_WKDEP_OFFSET			0x0038
-#define OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET		0x003c
-#define OMAP4_PM_ABE_MCASP_WKDEP_OFFSET			0x0040
-#define OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET		0x0044
-#define OMAP4_PM_ABE_MCBSP1_WKDEP_OFFSET		0x0048
-#define OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET		0x004c
-#define OMAP4_PM_ABE_MCBSP2_WKDEP_OFFSET		0x0050
-#define OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET		0x0054
-#define OMAP4_PM_ABE_MCBSP3_WKDEP_OFFSET		0x0058
-#define OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET		0x005c
-#define OMAP4_PM_ABE_SLIMBUS_WKDEP_OFFSET		0x0060
-#define OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET		0x0064
-#define OMAP4_PM_ABE_TIMER5_WKDEP_OFFSET		0x0068
-#define OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET		0x006c
-#define OMAP4_PM_ABE_TIMER6_WKDEP_OFFSET		0x0070
-#define OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET		0x0074
-#define OMAP4_PM_ABE_TIMER7_WKDEP_OFFSET		0x0078
-#define OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET		0x007c
-#define OMAP4_PM_ABE_TIMER8_WKDEP_OFFSET		0x0080
-#define OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET		0x0084
-#define OMAP4_PM_ABE_WDT3_WKDEP_OFFSET			0x0088
-#define OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET		0x008c
-
-/* PRM.ALWAYS_ON_PRM register offsets */
-#define OMAP4_RM_ALWON_MDMINTC_CONTEXT_OFFSET		0x0024
-#define OMAP4_PM_ALWON_SR_MPU_WKDEP_OFFSET		0x0028
-#define OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET		0x002c
-#define OMAP4_PM_ALWON_SR_IVA_WKDEP_OFFSET		0x0030
-#define OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET		0x0034
-#define OMAP4_PM_ALWON_SR_CORE_WKDEP_OFFSET		0x0038
-#define OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET		0x003c
-
-/* PRM.CORE_PRM register offsets */
-#define OMAP4_PM_CORE_PWRSTCTRL_OFFSET			0x0000
-#define OMAP4_PM_CORE_PWRSTST_OFFSET			0x0004
-#define OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET		0x0024
-#define OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET		0x0124
-#define OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET		0x012c
-#define OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET		0x0134
-#define OMAP4_RM_DUCATI_RSTCTRL_OFFSET			0x0210
-#define OMAP4_RM_DUCATI_RSTST_OFFSET			0x0214
-#define OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET		0x0224
-#define OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET		0x0324
-#define OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET		0x0424
-#define OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET		0x042c
-#define OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET		0x0434
-#define OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET		0x043c
-#define OMAP4_RM_MEMIF_DLL_CONTEXT_OFFSET		0x0444
-#define OMAP4_RM_MEMIF_EMIF_H1_CONTEXT_OFFSET		0x0454
-#define OMAP4_RM_MEMIF_EMIF_H2_CONTEXT_OFFSET		0x045c
-#define OMAP4_RM_MEMIF_DLL_H_CONTEXT_OFFSET		0x0464
-#define OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET		0x0524
-#define OMAP4_RM_D2D_MODEM_ICR_CONTEXT_OFFSET		0x052c
-#define OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET		0x0534
-#define OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET		0x0624
-#define OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET		0x062c
-#define OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET		0x0634
-#define OMAP4_RM_L4CFG_SAR_ROM_CONTEXT_OFFSET		0x063c
-#define OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET		0x0724
-#define OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET	0x072c
-#define OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET		0x0744
-
-/* PRM.IVAHD_PRM register offsets */
-#define OMAP4_PM_IVAHD_PWRSTCTRL_OFFSET			0x0000
-#define OMAP4_PM_IVAHD_PWRSTST_OFFSET			0x0004
-#define OMAP4_RM_IVAHD_RSTCTRL_OFFSET			0x0010
-#define OMAP4_RM_IVAHD_RSTST_OFFSET			0x0014
-#define OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET		0x0024
-#define OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET		0x002c
-
-/* PRM.CAM_PRM register offsets */
-#define OMAP4_PM_CAM_PWRSTCTRL_OFFSET			0x0000
-#define OMAP4_PM_CAM_PWRSTST_OFFSET			0x0004
-#define OMAP4_RM_CAM_ISS_CONTEXT_OFFSET			0x0024
-#define OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET		0x002c
-
-/* PRM.DSS_PRM register offsets */
-#define OMAP4_PM_DSS_PWRSTCTRL_OFFSET			0x0000
-#define OMAP4_PM_DSS_PWRSTST_OFFSET			0x0004
-#define OMAP4_PM_DSS_DSS_WKDEP_OFFSET			0x0020
-#define OMAP4_RM_DSS_DSS_CONTEXT_OFFSET			0x0024
-#define OMAP4_RM_DSS_DEISS_CONTEXT_OFFSET		0x002c
-
-/* PRM.GFX_PRM register offsets */
-#define OMAP4_PM_GFX_PWRSTCTRL_OFFSET			0x0000
-#define OMAP4_PM_GFX_PWRSTST_OFFSET			0x0004
-#define OMAP4_RM_GFX_GFX_CONTEXT_OFFSET			0x0024
-
-/* PRM.L3INIT_PRM register offsets */
-#define OMAP4_PM_L3INIT_PWRSTCTRL_OFFSET		0x0000
-#define OMAP4_PM_L3INIT_PWRSTST_OFFSET			0x0004
-#define OMAP4_PM_L3INIT_MMC1_WKDEP_OFFSET		0x0028
-#define OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET		0x002c
-#define OMAP4_PM_L3INIT_MMC2_WKDEP_OFFSET		0x0030
-#define OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET		0x0034
-#define OMAP4_PM_L3INIT_HSI_WKDEP_OFFSET		0x0038
-#define OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET		0x003c
-#define OMAP4_PM_L3INIT_UNIPRO1_WKDEP_OFFSET		0x0040
-#define OMAP4_RM_L3INIT_UNIPRO1_CONTEXT_OFFSET		0x0044
-#define OMAP4_PM_L3INIT_USB_HOST_WKDEP_OFFSET		0x0058
-#define OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET		0x005c
-#define OMAP4_PM_L3INIT_USB_OTG_WKDEP_OFFSET		0x0060
-#define OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET		0x0064
-#define OMAP4_PM_L3INIT_USB_TLL_WKDEP_OFFSET		0x0068
-#define OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET		0x006c
-#define OMAP4_RM_L3INIT_P1500_CONTEXT_OFFSET		0x007c
-#define OMAP4_RM_L3INIT_EMAC_CONTEXT_OFFSET		0x0084
-#define OMAP4_PM_L3INIT_SATA_WKDEP_OFFSET		0x0088
-#define OMAP4_RM_L3INIT_SATA_CONTEXT_OFFSET		0x008c
-#define OMAP4_RM_L3INIT_TPPSS_CONTEXT_OFFSET		0x0094
-#define OMAP4_PM_L3INIT_PCIESS_WKDEP_OFFSET		0x0098
-#define OMAP4_RM_L3INIT_PCIESS_CONTEXT_OFFSET		0x009c
-#define OMAP4_RM_L3INIT_CCPTX_CONTEXT_OFFSET		0x00ac
-#define OMAP4_PM_L3INIT_XHPI_WKDEP_OFFSET		0x00c0
-#define OMAP4_RM_L3INIT_XHPI_CONTEXT_OFFSET		0x00c4
-#define OMAP4_PM_L3INIT_MMC6_WKDEP_OFFSET		0x00c8
-#define OMAP4_RM_L3INIT_MMC6_CONTEXT_OFFSET		0x00cc
-#define OMAP4_PM_L3INIT_USB_HOST_FS_WKDEP_OFFSET	0x00d0
-#define OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET	0x00d4
-#define OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET	0x00e4
-
-/* PRM.L4PER_PRM register offsets */
-#define OMAP4_PM_L4PER_PWRSTCTRL_OFFSET			0x0000
-#define OMAP4_PM_L4PER_PWRSTST_OFFSET			0x0004
-#define OMAP4_RM_L4PER_ADC_CONTEXT_OFFSET		0x0024
-#define OMAP4_PM_L4PER_DMTIMER10_WKDEP_OFFSET		0x0028
-#define OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET		0x002c
-#define OMAP4_PM_L4PER_DMTIMER11_WKDEP_OFFSET		0x0030
-#define OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET		0x0034
-#define OMAP4_PM_L4PER_DMTIMER2_WKDEP_OFFSET		0x0038
-#define OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET		0x003c
-#define OMAP4_PM_L4PER_DMTIMER3_WKDEP_OFFSET		0x0040
-#define OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET		0x0044
-#define OMAP4_PM_L4PER_DMTIMER4_WKDEP_OFFSET		0x0048
-#define OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET		0x004c
-#define OMAP4_PM_L4PER_DMTIMER9_WKDEP_OFFSET		0x0050
-#define OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET		0x0054
-#define OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET		0x005c
-#define OMAP4_PM_L4PER_GPIO2_WKDEP_OFFSET		0x0060
-#define OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET		0x0064
-#define OMAP4_PM_L4PER_GPIO3_WKDEP_OFFSET		0x0068
-#define OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET		0x006c
-#define OMAP4_PM_L4PER_GPIO4_WKDEP_OFFSET		0x0070
-#define OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET		0x0074
-#define OMAP4_PM_L4PER_GPIO5_WKDEP_OFFSET		0x0078
-#define OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET		0x007c
-#define OMAP4_PM_L4PER_GPIO6_WKDEP_OFFSET		0x0080
-#define OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET		0x0084
-#define OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET		0x008c
-#define OMAP4_PM_L4PER_HECC1_WKDEP_OFFSET		0x0090
-#define OMAP4_RM_L4PER_HECC1_CONTEXT_OFFSET		0x0094
-#define OMAP4_PM_L4PER_HECC2_WKDEP_OFFSET		0x0098
-#define OMAP4_RM_L4PER_HECC2_CONTEXT_OFFSET		0x009c
-#define OMAP4_PM_L4PER_I2C1_WKDEP_OFFSET		0x00a0
-#define OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET		0x00a4
-#define OMAP4_PM_L4PER_I2C2_WKDEP_OFFSET		0x00a8
-#define OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET		0x00ac
-#define OMAP4_PM_L4PER_I2C3_WKDEP_OFFSET		0x00b0
-#define OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET		0x00b4
-#define OMAP4_PM_L4PER_I2C4_WKDEP_OFFSET		0x00b8
-#define OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET		0x00bc
-#define OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET		0x00c0
-#define OMAP4_PM_L4PER_MCASP2_WKDEP_OFFSET		0x00d0
-#define OMAP4_RM_L4PER_MCASP2_CONTEXT_OFFSET		0x00d4
-#define OMAP4_PM_L4PER_MCASP3_WKDEP_OFFSET		0x00d8
-#define OMAP4_RM_L4PER_MCASP3_CONTEXT_OFFSET		0x00dc
-#define OMAP4_PM_L4PER_MCBSP4_WKDEP_OFFSET		0x00e0
-#define OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET		0x00e4
-#define OMAP4_RM_L4PER_MGATE_CONTEXT_OFFSET		0x00ec
-#define OMAP4_PM_L4PER_MCSPI1_WKDEP_OFFSET		0x00f0
-#define OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET		0x00f4
-#define OMAP4_PM_L4PER_MCSPI2_WKDEP_OFFSET		0x00f8
-#define OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET		0x00fc
-#define OMAP4_PM_L4PER_MCSPI3_WKDEP_OFFSET		0x0100
-#define OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET		0x0104
-#define OMAP4_PM_L4PER_MCSPI4_WKDEP_OFFSET		0x0108
-#define OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET		0x010c
-#define OMAP4_PM_L4PER_MMCSD3_WKDEP_OFFSET		0x0120
-#define OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET		0x0124
-#define OMAP4_PM_L4PER_MMCSD4_WKDEP_OFFSET		0x0128
-#define OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET		0x012c
-#define OMAP4_RM_L4PER_MSPROHG_CONTEXT_OFFSET		0x0134
-#define OMAP4_PM_L4PER_SLIMBUS2_WKDEP_OFFSET		0x0138
-#define OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET		0x013c
-#define OMAP4_PM_L4PER_UART1_WKDEP_OFFSET		0x0140
-#define OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET		0x0144
-#define OMAP4_PM_L4PER_UART2_WKDEP_OFFSET		0x0148
-#define OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET		0x014c
-#define OMAP4_PM_L4PER_UART3_WKDEP_OFFSET		0x0150
-#define OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET		0x0154
-#define OMAP4_PM_L4PER_UART4_WKDEP_OFFSET		0x0158
-#define OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET		0x015c
-#define OMAP4_PM_L4PER_MMCSD5_WKDEP_OFFSET		0x0160
-#define OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET		0x0164
-#define OMAP4_PM_L4PER_I2C5_WKDEP_OFFSET		0x0168
-#define OMAP4_RM_L4PER_I2C5_CONTEXT_OFFSET		0x016c
-#define OMAP4_RM_L4SEC_AES1_CONTEXT_OFFSET		0x01a4
-#define OMAP4_RM_L4SEC_AES2_CONTEXT_OFFSET		0x01ac
-#define OMAP4_RM_L4SEC_DES3DES_CONTEXT_OFFSET		0x01b4
-#define OMAP4_RM_L4SEC_PKAEIP29_CONTEXT_OFFSET		0x01bc
-#define OMAP4_RM_L4SEC_RNG_CONTEXT_OFFSET		0x01c4
-#define OMAP4_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET		0x01cc
-#define OMAP4_RM_L4SEC_CRYPTODMA_CONTEXT_OFFSET		0x01dc
-
-/* PRM.CEFUSE_PRM register offsets */
-#define OMAP4_PM_CEFUSE_PWRSTCTRL_OFFSET		0x0000
-#define OMAP4_PM_CEFUSE_PWRSTST_OFFSET			0x0004
-#define OMAP4_RM_CEFUSE_CEFUSE_CONTEXT_OFFSET		0x0024
-
-/* PRM.WKUP_PRM register offsets */
-#define OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET		0x0024
-#define OMAP4_RM_WKUP_WDT1_CONTEXT_OFFSET		0x002c
-#define OMAP4_PM_WKUP_WDT2_WKDEP_OFFSET			0x0030
-#define OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET		0x0034
-#define OMAP4_PM_WKUP_GPIO1_WKDEP_OFFSET		0x0038
-#define OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET		0x003c
-#define OMAP4_PM_WKUP_TIMER1_WKDEP_OFFSET		0x0040
-#define OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET		0x0044
-#define OMAP4_PM_WKUP_TIMER12_WKDEP_OFFSET		0x0048
-#define OMAP4_RM_WKUP_TIMER12_CONTEXT_OFFSET		0x004c
-#define OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET		0x0054
-#define OMAP4_PM_WKUP_USIM_WKDEP_OFFSET			0x0058
-#define OMAP4_RM_WKUP_USIM_CONTEXT_OFFSET		0x005c
-#define OMAP4_RM_WKUP_SARRAM_CONTEXT_OFFSET		0x0064
-#define OMAP4_PM_WKUP_KEYBOARD_WKDEP_OFFSET		0x0078
-#define OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET		0x007c
-#define OMAP4_PM_WKUP_RTC_WKDEP_OFFSET			0x0080
-#define OMAP4_RM_WKUP_RTC_CONTEXT_OFFSET		0x0084
-
-/* PRM.WKUP_CM register offsets */
-#define OMAP4_CM_WKUP_CLKSTCTRL_OFFSET			0x0000
-#define OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET		0x0020
-#define OMAP4_CM_WKUP_WDT1_CLKCTRL_OFFSET		0x0028
-#define OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET		0x0030
-#define OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET		0x0038
-#define OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET		0x0040
-#define OMAP4_CM_WKUP_TIMER12_CLKCTRL_OFFSET		0x0048
-#define OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET		0x0050
-#define OMAP4_CM_WKUP_USIM_CLKCTRL_OFFSET		0x0058
-#define OMAP4_CM_WKUP_SARRAM_CLKCTRL_OFFSET		0x0060
-#define OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET		0x0078
-#define OMAP4_CM_WKUP_RTC_CLKCTRL_OFFSET		0x0080
-#define OMAP4_CM_WKUP_BANDGAP_CLKCTRL_OFFSET		0x0088
-
-/* PRM.EMU_PRM register offsets */
-#define OMAP4_PM_EMU_PWRSTCTRL_OFFSET			0x0000
-#define OMAP4_PM_EMU_PWRSTST_OFFSET			0x0004
-#define OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET		0x0024
-
-/* PRM.EMU_CM register offsets */
-#define OMAP4_CM_EMU_CLKSTCTRL_OFFSET			0x0000
-#define OMAP4_CM_EMU_DYNAMICDEP_OFFSET			0x0008
-#define OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET		0x0020
-
-/* PRM.DEVICE_PRM register offsets */
-#define OMAP4_PRM_RSTCTRL_OFFSET			0x0000
-#define OMAP4_PRM_RSTST_OFFSET				0x0004
-#define OMAP4_PRM_RSTTIME_OFFSET			0x0008
-#define OMAP4_PRM_CLKREQCTRL_OFFSET			0x000c
-#define OMAP4_PRM_VOLTCTRL_OFFSET			0x0010
-#define OMAP4_PRM_PWRREQCTRL_OFFSET			0x0014
-#define OMAP4_PRM_PSCON_COUNT_OFFSET			0x0018
-#define OMAP4_PRM_IO_COUNT_OFFSET			0x001c
-#define OMAP4_PRM_IO_PMCTRL_OFFSET			0x0020
-#define OMAP4_PRM_VOLTSETUP_WARMRESET_OFFSET		0x0024
-#define OMAP4_PRM_VOLTSETUP_CORE_OFF_OFFSET		0x0028
-#define OMAP4_PRM_VOLTSETUP_MPU_OFF_OFFSET		0x002c
-#define OMAP4_PRM_VOLTSETUP_IVA_OFF_OFFSET		0x0030
-#define OMAP4_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET	0x0034
-#define OMAP4_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET	0x0038
-#define OMAP4_PRM_VOLTSETUP_IVA_RET_SLEEP_OFFSET	0x003c
-#define OMAP4_PRM_VP_CORE_CONFIG_OFFSET			0x0040
-#define OMAP4_PRM_VP_CORE_STATUS_OFFSET			0x0044
-#define OMAP4_PRM_VP_CORE_VLIMITTO_OFFSET		0x0048
-#define OMAP4_PRM_VP_CORE_VOLTAGE_OFFSET		0x004c
-#define OMAP4_PRM_VP_CORE_VSTEPMAX_OFFSET		0x0050
-#define OMAP4_PRM_VP_CORE_VSTEPMIN_OFFSET		0x0054
-#define OMAP4_PRM_VP_MPU_CONFIG_OFFSET			0x0058
-#define OMAP4_PRM_VP_MPU_STATUS_OFFSET			0x005c
-#define OMAP4_PRM_VP_MPU_VLIMITTO_OFFSET		0x0060
-#define OMAP4_PRM_VP_MPU_VOLTAGE_OFFSET			0x0064
-#define OMAP4_PRM_VP_MPU_VSTEPMAX_OFFSET		0x0068
-#define OMAP4_PRM_VP_MPU_VSTEPMIN_OFFSET		0x006c
-#define OMAP4_PRM_VP_IVA_CONFIG_OFFSET			0x0070
-#define OMAP4_PRM_VP_IVA_STATUS_OFFSET			0x0074
-#define OMAP4_PRM_VP_IVA_VLIMITTO_OFFSET		0x0078
-#define OMAP4_PRM_VP_IVA_VOLTAGE_OFFSET			0x007c
-#define OMAP4_PRM_VP_IVA_VSTEPMAX_OFFSET		0x0080
-#define OMAP4_PRM_VP_IVA_VSTEPMIN_OFFSET		0x0084
-#define OMAP4_PRM_VC_SMPS_SA_OFFSET			0x0088
-#define OMAP4_PRM_VC_VAL_SMPS_RA_VOL_OFFSET		0x008c
-#define OMAP4_PRM_VC_VAL_SMPS_RA_CMD_OFFSET		0x0090
-#define OMAP4_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET		0x0094
-#define OMAP4_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET		0x0098
-#define OMAP4_PRM_VC_VAL_CMD_VDD_IVA_L_OFFSET		0x009c
-#define OMAP4_PRM_VC_VAL_BYPASS_OFFSET			0x00a0
-#define OMAP4_PRM_VC_CFG_CHANNEL_OFFSET			0x00a4
-#define OMAP4_PRM_VC_CFG_I2C_MODE_OFFSET		0x00a8
-#define OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET			0x00ac
-#define OMAP4_PRM_SRAM_COUNT_OFFSET			0x00b0
-#define OMAP4_PRM_SRAM_WKUP_SETUP_OFFSET		0x00b4
-#define OMAP4_PRM_LDO_SRAM_CORE_SETUP_OFFSET		0x00b8
-#define OMAP4_PRM_LDO_SRAM_CORE_CTRL_OFFSET		0x00bc
-#define OMAP4_PRM_LDO_SRAM_MPU_SETUP_OFFSET		0x00c0
-#define OMAP4_PRM_LDO_SRAM_MPU_CTRL_OFFSET		0x00c4
-#define OMAP4_PRM_LDO_SRAM_IVA_SETUP_OFFSET		0x00c8
-#define OMAP4_PRM_LDO_SRAM_IVA_CTRL_OFFSET		0x00cc
-#define OMAP4_PRM_LDO_ABB_MPU_SETUP_OFFSET		0x00d0
-#define OMAP4_PRM_LDO_ABB_MPU_CTRL_OFFSET		0x00d4
-#define OMAP4_PRM_LDO_ABB_IVA_SETUP_OFFSET		0x00d8
-#define OMAP4_PRM_LDO_ABB_IVA_CTRL_OFFSET		0x00dc
-#define OMAP4_PRM_LDO_BANDGAP_SETUP_OFFSET		0x00e0
-#define OMAP4_PRM_DEVICE_OFF_CTRL_OFFSET		0x00e4
-#define OMAP4_PRM_PHASE1_CNDP_OFFSET			0x00e8
-#define OMAP4_PRM_PHASE2A_CNDP_OFFSET			0x00ec
-#define OMAP4_PRM_PHASE2B_CNDP_OFFSET			0x00f0
-#define OMAP4_PRM_MODEM_IF_CTRL_OFFSET			0x00f4
-#define OMAP4_PRM_VC_ERRST_OFFSET			0x00f8
-
 #endif
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index 40e94e7..653862b 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -31,7 +31,10 @@
 #include <linux/power/omap/prm2xxx_3xxx.h>
 #include <linux/power/omap/prm2xxx.h>
 #include <linux/power/omap/prm3xxx.h>
-#include "prm44xx.h"
+#include <linux/power/omap/prm44xx.h>
+
+#include "prm.h"
+#include "prcm-common.h"
 
 /*
  * OMAP_PRCM_MAX_NR_PENDING_REG: maximum number of PRM_IRQ*_MPU regs
diff --git a/arch/arm/mach-omap2/prminst44xx.c b/arch/arm/mach-omap2/prminst44xx.c
index 74349e1..f029cb1 100644
--- a/arch/arm/mach-omap2/prminst44xx.c
+++ b/arch/arm/mach-omap2/prminst44xx.c
@@ -16,8 +16,9 @@
 #include <linux/err.h>
 #include <linux/io.h>
 
+#include "prm.h"
 #include "prcm-common.h"
-#include "prm44xx.h"
+#include <linux/power/omap/prm44xx.h>
 #include "prm54xx.h"
 #include "prm7xx.h"
 #include "prminst44xx.h"
diff --git a/include/linux/power/omap/prm44xx.h b/include/linux/power/omap/prm44xx.h
new file mode 100644
index 0000000..e5cd9f3
--- /dev/null
+++ b/include/linux/power/omap/prm44xx.h
@@ -0,0 +1,420 @@
+/*
+ * OMAP44xx PRM instance offset macros
+ *
+ * Copyright (C) 2009-2011 Texas Instruments, Inc.
+ * Copyright (C) 2009-2010 Nokia Corporation
+ *
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX",
+ *     or "OMAP4430".
+ */
+
+#ifndef __LINUX_POWER_OMAP_PRM44XX_H
+#define __LINUX_POWER_OMAP_PRM44XX_H
+
+/* PRM instances */
+#define OMAP4430_PRM_OCP_SOCKET_INST	0x0000
+#define OMAP4430_PRM_CKGEN_INST		0x0100
+#define OMAP4430_PRM_MPU_INST		0x0300
+#define OMAP4430_PRM_TESLA_INST		0x0400
+#define OMAP4430_PRM_ABE_INST		0x0500
+#define OMAP4430_PRM_ALWAYS_ON_INST	0x0600
+#define OMAP4430_PRM_CORE_INST		0x0700
+#define OMAP4430_PRM_IVAHD_INST		0x0f00
+#define OMAP4430_PRM_CAM_INST		0x1000
+#define OMAP4430_PRM_DSS_INST		0x1100
+#define OMAP4430_PRM_GFX_INST		0x1200
+#define OMAP4430_PRM_L3INIT_INST	0x1300
+#define OMAP4430_PRM_L4PER_INST		0x1400
+#define OMAP4430_PRM_CEFUSE_INST	0x1600
+#define OMAP4430_PRM_WKUP_INST		0x1700
+#define OMAP4430_PRM_WKUP_CM_INST	0x1800
+#define OMAP4430_PRM_EMU_INST		0x1900
+#define OMAP4430_PRM_EMU_CM_INST	0x1a00
+#define OMAP4430_PRM_DEVICE_INST	0x1b00
+#define OMAP4430_PRM_INSTR_INST		0x1f00
+
+/* PRM clockdomain register offsets (from instance start) */
+#define OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS	0x0000
+#define OMAP4430_PRM_EMU_CM_EMU_CDOFFS		0x0000
+
+/* OMAP4 specific register offsets */
+#define OMAP4_RM_RSTCTRL				0x0000
+#define OMAP4_RM_RSTST					0x0004
+#define OMAP4_RM_RSTTIME				0x0008
+#define OMAP4_PM_PWSTCTRL				0x0000
+#define OMAP4_PM_PWSTST					0x0004
+
+
+/* PRM */
+
+/* PRM.OCP_SOCKET_PRM register offsets */
+#define OMAP4_REVISION_PRM_OFFSET			0x0000
+#define OMAP4_PRM_IRQSTATUS_MPU_OFFSET			0x0010
+#define OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET		0x0014
+#define OMAP4_PRM_IRQENABLE_MPU_OFFSET			0x0018
+#define OMAP4_PRM_IRQENABLE_MPU_2_OFFSET		0x001c
+#define OMAP4_PRM_IRQSTATUS_DUCATI_OFFSET		0x0020
+#define OMAP4_PRM_IRQENABLE_DUCATI_OFFSET		0x0028
+#define OMAP4_PRM_IRQSTATUS_TESLA_OFFSET		0x0030
+#define OMAP4_PRM_IRQENABLE_TESLA_OFFSET		0x0038
+#define OMAP4_CM_PRM_PROFILING_CLKCTRL_OFFSET		0x0040
+
+/* PRM.CKGEN_PRM register offsets */
+#define OMAP4_CM_ABE_DSS_SYS_CLKSEL_OFFSET		0x0000
+#define OMAP4_CM_L4_WKUP_CLKSEL_OFFSET			0x0008
+#define OMAP4_CM_ABE_PLL_REF_CLKSEL_OFFSET		0x000c
+#define OMAP4_CM_SYS_CLKSEL_OFFSET			0x0010
+
+/* PRM.MPU_PRM register offsets */
+#define OMAP4_PM_MPU_PWRSTCTRL_OFFSET			0x0000
+#define OMAP4_PM_MPU_PWRSTST_OFFSET			0x0004
+#define OMAP4_RM_MPU_RSTST_OFFSET			0x0014
+#define OMAP4_RM_MPU_MPU_CONTEXT_OFFSET			0x0024
+
+/* PRM.TESLA_PRM register offsets */
+#define OMAP4_PM_TESLA_PWRSTCTRL_OFFSET			0x0000
+#define OMAP4_PM_TESLA_PWRSTST_OFFSET			0x0004
+#define OMAP4_RM_TESLA_RSTCTRL_OFFSET			0x0010
+#define OMAP4_RM_TESLA_RSTST_OFFSET			0x0014
+#define OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET		0x0024
+
+/* PRM.ABE_PRM register offsets */
+#define OMAP4_PM_ABE_PWRSTCTRL_OFFSET			0x0000
+#define OMAP4_PM_ABE_PWRSTST_OFFSET			0x0004
+#define OMAP4_RM_ABE_AESS_CONTEXT_OFFSET		0x002c
+#define OMAP4_PM_ABE_PDM_WKDEP_OFFSET			0x0030
+#define OMAP4_RM_ABE_PDM_CONTEXT_OFFSET			0x0034
+#define OMAP4_PM_ABE_DMIC_WKDEP_OFFSET			0x0038
+#define OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET		0x003c
+#define OMAP4_PM_ABE_MCASP_WKDEP_OFFSET			0x0040
+#define OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET		0x0044
+#define OMAP4_PM_ABE_MCBSP1_WKDEP_OFFSET		0x0048
+#define OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET		0x004c
+#define OMAP4_PM_ABE_MCBSP2_WKDEP_OFFSET		0x0050
+#define OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET		0x0054
+#define OMAP4_PM_ABE_MCBSP3_WKDEP_OFFSET		0x0058
+#define OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET		0x005c
+#define OMAP4_PM_ABE_SLIMBUS_WKDEP_OFFSET		0x0060
+#define OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET		0x0064
+#define OMAP4_PM_ABE_TIMER5_WKDEP_OFFSET		0x0068
+#define OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET		0x006c
+#define OMAP4_PM_ABE_TIMER6_WKDEP_OFFSET		0x0070
+#define OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET		0x0074
+#define OMAP4_PM_ABE_TIMER7_WKDEP_OFFSET		0x0078
+#define OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET		0x007c
+#define OMAP4_PM_ABE_TIMER8_WKDEP_OFFSET		0x0080
+#define OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET		0x0084
+#define OMAP4_PM_ABE_WDT3_WKDEP_OFFSET			0x0088
+#define OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET		0x008c
+
+/* PRM.ALWAYS_ON_PRM register offsets */
+#define OMAP4_RM_ALWON_MDMINTC_CONTEXT_OFFSET		0x0024
+#define OMAP4_PM_ALWON_SR_MPU_WKDEP_OFFSET		0x0028
+#define OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET		0x002c
+#define OMAP4_PM_ALWON_SR_IVA_WKDEP_OFFSET		0x0030
+#define OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET		0x0034
+#define OMAP4_PM_ALWON_SR_CORE_WKDEP_OFFSET		0x0038
+#define OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET		0x003c
+
+/* PRM.CORE_PRM register offsets */
+#define OMAP4_PM_CORE_PWRSTCTRL_OFFSET			0x0000
+#define OMAP4_PM_CORE_PWRSTST_OFFSET			0x0004
+#define OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET		0x0024
+#define OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET		0x0124
+#define OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET		0x012c
+#define OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET		0x0134
+#define OMAP4_RM_DUCATI_RSTCTRL_OFFSET			0x0210
+#define OMAP4_RM_DUCATI_RSTST_OFFSET			0x0214
+#define OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET		0x0224
+#define OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET		0x0324
+#define OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET		0x0424
+#define OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET		0x042c
+#define OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET		0x0434
+#define OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET		0x043c
+#define OMAP4_RM_MEMIF_DLL_CONTEXT_OFFSET		0x0444
+#define OMAP4_RM_MEMIF_EMIF_H1_CONTEXT_OFFSET		0x0454
+#define OMAP4_RM_MEMIF_EMIF_H2_CONTEXT_OFFSET		0x045c
+#define OMAP4_RM_MEMIF_DLL_H_CONTEXT_OFFSET		0x0464
+#define OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET		0x0524
+#define OMAP4_RM_D2D_MODEM_ICR_CONTEXT_OFFSET		0x052c
+#define OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET		0x0534
+#define OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET		0x0624
+#define OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET		0x062c
+#define OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET		0x0634
+#define OMAP4_RM_L4CFG_SAR_ROM_CONTEXT_OFFSET		0x063c
+#define OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET		0x0724
+#define OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET	0x072c
+#define OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET		0x0744
+
+/* PRM.IVAHD_PRM register offsets */
+#define OMAP4_PM_IVAHD_PWRSTCTRL_OFFSET			0x0000
+#define OMAP4_PM_IVAHD_PWRSTST_OFFSET			0x0004
+#define OMAP4_RM_IVAHD_RSTCTRL_OFFSET			0x0010
+#define OMAP4_RM_IVAHD_RSTST_OFFSET			0x0014
+#define OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET		0x0024
+#define OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET		0x002c
+
+/* PRM.CAM_PRM register offsets */
+#define OMAP4_PM_CAM_PWRSTCTRL_OFFSET			0x0000
+#define OMAP4_PM_CAM_PWRSTST_OFFSET			0x0004
+#define OMAP4_RM_CAM_ISS_CONTEXT_OFFSET			0x0024
+#define OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET		0x002c
+
+/* PRM.DSS_PRM register offsets */
+#define OMAP4_PM_DSS_PWRSTCTRL_OFFSET			0x0000
+#define OMAP4_PM_DSS_PWRSTST_OFFSET			0x0004
+#define OMAP4_PM_DSS_DSS_WKDEP_OFFSET			0x0020
+#define OMAP4_RM_DSS_DSS_CONTEXT_OFFSET			0x0024
+#define OMAP4_RM_DSS_DEISS_CONTEXT_OFFSET		0x002c
+
+/* PRM.GFX_PRM register offsets */
+#define OMAP4_PM_GFX_PWRSTCTRL_OFFSET			0x0000
+#define OMAP4_PM_GFX_PWRSTST_OFFSET			0x0004
+#define OMAP4_RM_GFX_GFX_CONTEXT_OFFSET			0x0024
+
+/* PRM.L3INIT_PRM register offsets */
+#define OMAP4_PM_L3INIT_PWRSTCTRL_OFFSET		0x0000
+#define OMAP4_PM_L3INIT_PWRSTST_OFFSET			0x0004
+#define OMAP4_PM_L3INIT_MMC1_WKDEP_OFFSET		0x0028
+#define OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET		0x002c
+#define OMAP4_PM_L3INIT_MMC2_WKDEP_OFFSET		0x0030
+#define OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET		0x0034
+#define OMAP4_PM_L3INIT_HSI_WKDEP_OFFSET		0x0038
+#define OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET		0x003c
+#define OMAP4_PM_L3INIT_UNIPRO1_WKDEP_OFFSET		0x0040
+#define OMAP4_RM_L3INIT_UNIPRO1_CONTEXT_OFFSET		0x0044
+#define OMAP4_PM_L3INIT_USB_HOST_WKDEP_OFFSET		0x0058
+#define OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET		0x005c
+#define OMAP4_PM_L3INIT_USB_OTG_WKDEP_OFFSET		0x0060
+#define OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET		0x0064
+#define OMAP4_PM_L3INIT_USB_TLL_WKDEP_OFFSET		0x0068
+#define OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET		0x006c
+#define OMAP4_RM_L3INIT_P1500_CONTEXT_OFFSET		0x007c
+#define OMAP4_RM_L3INIT_EMAC_CONTEXT_OFFSET		0x0084
+#define OMAP4_PM_L3INIT_SATA_WKDEP_OFFSET		0x0088
+#define OMAP4_RM_L3INIT_SATA_CONTEXT_OFFSET		0x008c
+#define OMAP4_RM_L3INIT_TPPSS_CONTEXT_OFFSET		0x0094
+#define OMAP4_PM_L3INIT_PCIESS_WKDEP_OFFSET		0x0098
+#define OMAP4_RM_L3INIT_PCIESS_CONTEXT_OFFSET		0x009c
+#define OMAP4_RM_L3INIT_CCPTX_CONTEXT_OFFSET		0x00ac
+#define OMAP4_PM_L3INIT_XHPI_WKDEP_OFFSET		0x00c0
+#define OMAP4_RM_L3INIT_XHPI_CONTEXT_OFFSET		0x00c4
+#define OMAP4_PM_L3INIT_MMC6_WKDEP_OFFSET		0x00c8
+#define OMAP4_RM_L3INIT_MMC6_CONTEXT_OFFSET		0x00cc
+#define OMAP4_PM_L3INIT_USB_HOST_FS_WKDEP_OFFSET	0x00d0
+#define OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET	0x00d4
+#define OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET	0x00e4
+
+/* PRM.L4PER_PRM register offsets */
+#define OMAP4_PM_L4PER_PWRSTCTRL_OFFSET			0x0000
+#define OMAP4_PM_L4PER_PWRSTST_OFFSET			0x0004
+#define OMAP4_RM_L4PER_ADC_CONTEXT_OFFSET		0x0024
+#define OMAP4_PM_L4PER_DMTIMER10_WKDEP_OFFSET		0x0028
+#define OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET		0x002c
+#define OMAP4_PM_L4PER_DMTIMER11_WKDEP_OFFSET		0x0030
+#define OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET		0x0034
+#define OMAP4_PM_L4PER_DMTIMER2_WKDEP_OFFSET		0x0038
+#define OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET		0x003c
+#define OMAP4_PM_L4PER_DMTIMER3_WKDEP_OFFSET		0x0040
+#define OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET		0x0044
+#define OMAP4_PM_L4PER_DMTIMER4_WKDEP_OFFSET		0x0048
+#define OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET		0x004c
+#define OMAP4_PM_L4PER_DMTIMER9_WKDEP_OFFSET		0x0050
+#define OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET		0x0054
+#define OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET		0x005c
+#define OMAP4_PM_L4PER_GPIO2_WKDEP_OFFSET		0x0060
+#define OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET		0x0064
+#define OMAP4_PM_L4PER_GPIO3_WKDEP_OFFSET		0x0068
+#define OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET		0x006c
+#define OMAP4_PM_L4PER_GPIO4_WKDEP_OFFSET		0x0070
+#define OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET		0x0074
+#define OMAP4_PM_L4PER_GPIO5_WKDEP_OFFSET		0x0078
+#define OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET		0x007c
+#define OMAP4_PM_L4PER_GPIO6_WKDEP_OFFSET		0x0080
+#define OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET		0x0084
+#define OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET		0x008c
+#define OMAP4_PM_L4PER_HECC1_WKDEP_OFFSET		0x0090
+#define OMAP4_RM_L4PER_HECC1_CONTEXT_OFFSET		0x0094
+#define OMAP4_PM_L4PER_HECC2_WKDEP_OFFSET		0x0098
+#define OMAP4_RM_L4PER_HECC2_CONTEXT_OFFSET		0x009c
+#define OMAP4_PM_L4PER_I2C1_WKDEP_OFFSET		0x00a0
+#define OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET		0x00a4
+#define OMAP4_PM_L4PER_I2C2_WKDEP_OFFSET		0x00a8
+#define OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET		0x00ac
+#define OMAP4_PM_L4PER_I2C3_WKDEP_OFFSET		0x00b0
+#define OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET		0x00b4
+#define OMAP4_PM_L4PER_I2C4_WKDEP_OFFSET		0x00b8
+#define OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET		0x00bc
+#define OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET		0x00c0
+#define OMAP4_PM_L4PER_MCASP2_WKDEP_OFFSET		0x00d0
+#define OMAP4_RM_L4PER_MCASP2_CONTEXT_OFFSET		0x00d4
+#define OMAP4_PM_L4PER_MCASP3_WKDEP_OFFSET		0x00d8
+#define OMAP4_RM_L4PER_MCASP3_CONTEXT_OFFSET		0x00dc
+#define OMAP4_PM_L4PER_MCBSP4_WKDEP_OFFSET		0x00e0
+#define OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET		0x00e4
+#define OMAP4_RM_L4PER_MGATE_CONTEXT_OFFSET		0x00ec
+#define OMAP4_PM_L4PER_MCSPI1_WKDEP_OFFSET		0x00f0
+#define OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET		0x00f4
+#define OMAP4_PM_L4PER_MCSPI2_WKDEP_OFFSET		0x00f8
+#define OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET		0x00fc
+#define OMAP4_PM_L4PER_MCSPI3_WKDEP_OFFSET		0x0100
+#define OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET		0x0104
+#define OMAP4_PM_L4PER_MCSPI4_WKDEP_OFFSET		0x0108
+#define OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET		0x010c
+#define OMAP4_PM_L4PER_MMCSD3_WKDEP_OFFSET		0x0120
+#define OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET		0x0124
+#define OMAP4_PM_L4PER_MMCSD4_WKDEP_OFFSET		0x0128
+#define OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET		0x012c
+#define OMAP4_RM_L4PER_MSPROHG_CONTEXT_OFFSET		0x0134
+#define OMAP4_PM_L4PER_SLIMBUS2_WKDEP_OFFSET		0x0138
+#define OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET		0x013c
+#define OMAP4_PM_L4PER_UART1_WKDEP_OFFSET		0x0140
+#define OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET		0x0144
+#define OMAP4_PM_L4PER_UART2_WKDEP_OFFSET		0x0148
+#define OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET		0x014c
+#define OMAP4_PM_L4PER_UART3_WKDEP_OFFSET		0x0150
+#define OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET		0x0154
+#define OMAP4_PM_L4PER_UART4_WKDEP_OFFSET		0x0158
+#define OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET		0x015c
+#define OMAP4_PM_L4PER_MMCSD5_WKDEP_OFFSET		0x0160
+#define OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET		0x0164
+#define OMAP4_PM_L4PER_I2C5_WKDEP_OFFSET		0x0168
+#define OMAP4_RM_L4PER_I2C5_CONTEXT_OFFSET		0x016c
+#define OMAP4_RM_L4SEC_AES1_CONTEXT_OFFSET		0x01a4
+#define OMAP4_RM_L4SEC_AES2_CONTEXT_OFFSET		0x01ac
+#define OMAP4_RM_L4SEC_DES3DES_CONTEXT_OFFSET		0x01b4
+#define OMAP4_RM_L4SEC_PKAEIP29_CONTEXT_OFFSET		0x01bc
+#define OMAP4_RM_L4SEC_RNG_CONTEXT_OFFSET		0x01c4
+#define OMAP4_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET		0x01cc
+#define OMAP4_RM_L4SEC_CRYPTODMA_CONTEXT_OFFSET		0x01dc
+
+/* PRM.CEFUSE_PRM register offsets */
+#define OMAP4_PM_CEFUSE_PWRSTCTRL_OFFSET		0x0000
+#define OMAP4_PM_CEFUSE_PWRSTST_OFFSET			0x0004
+#define OMAP4_RM_CEFUSE_CEFUSE_CONTEXT_OFFSET		0x0024
+
+/* PRM.WKUP_PRM register offsets */
+#define OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET		0x0024
+#define OMAP4_RM_WKUP_WDT1_CONTEXT_OFFSET		0x002c
+#define OMAP4_PM_WKUP_WDT2_WKDEP_OFFSET			0x0030
+#define OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET		0x0034
+#define OMAP4_PM_WKUP_GPIO1_WKDEP_OFFSET		0x0038
+#define OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET		0x003c
+#define OMAP4_PM_WKUP_TIMER1_WKDEP_OFFSET		0x0040
+#define OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET		0x0044
+#define OMAP4_PM_WKUP_TIMER12_WKDEP_OFFSET		0x0048
+#define OMAP4_RM_WKUP_TIMER12_CONTEXT_OFFSET		0x004c
+#define OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET		0x0054
+#define OMAP4_PM_WKUP_USIM_WKDEP_OFFSET			0x0058
+#define OMAP4_RM_WKUP_USIM_CONTEXT_OFFSET		0x005c
+#define OMAP4_RM_WKUP_SARRAM_CONTEXT_OFFSET		0x0064
+#define OMAP4_PM_WKUP_KEYBOARD_WKDEP_OFFSET		0x0078
+#define OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET		0x007c
+#define OMAP4_PM_WKUP_RTC_WKDEP_OFFSET			0x0080
+#define OMAP4_RM_WKUP_RTC_CONTEXT_OFFSET		0x0084
+
+/* PRM.WKUP_CM register offsets */
+#define OMAP4_CM_WKUP_CLKSTCTRL_OFFSET			0x0000
+#define OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET		0x0020
+#define OMAP4_CM_WKUP_WDT1_CLKCTRL_OFFSET		0x0028
+#define OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET		0x0030
+#define OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET		0x0038
+#define OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET		0x0040
+#define OMAP4_CM_WKUP_TIMER12_CLKCTRL_OFFSET		0x0048
+#define OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET		0x0050
+#define OMAP4_CM_WKUP_USIM_CLKCTRL_OFFSET		0x0058
+#define OMAP4_CM_WKUP_SARRAM_CLKCTRL_OFFSET		0x0060
+#define OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET		0x0078
+#define OMAP4_CM_WKUP_RTC_CLKCTRL_OFFSET		0x0080
+#define OMAP4_CM_WKUP_BANDGAP_CLKCTRL_OFFSET		0x0088
+
+/* PRM.EMU_PRM register offsets */
+#define OMAP4_PM_EMU_PWRSTCTRL_OFFSET			0x0000
+#define OMAP4_PM_EMU_PWRSTST_OFFSET			0x0004
+#define OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET		0x0024
+
+/* PRM.EMU_CM register offsets */
+#define OMAP4_CM_EMU_CLKSTCTRL_OFFSET			0x0000
+#define OMAP4_CM_EMU_DYNAMICDEP_OFFSET			0x0008
+#define OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET		0x0020
+
+/* PRM.DEVICE_PRM register offsets */
+#define OMAP4_PRM_RSTCTRL_OFFSET			0x0000
+#define OMAP4_PRM_RSTST_OFFSET				0x0004
+#define OMAP4_PRM_RSTTIME_OFFSET			0x0008
+#define OMAP4_PRM_CLKREQCTRL_OFFSET			0x000c
+#define OMAP4_PRM_VOLTCTRL_OFFSET			0x0010
+#define OMAP4_PRM_PWRREQCTRL_OFFSET			0x0014
+#define OMAP4_PRM_PSCON_COUNT_OFFSET			0x0018
+#define OMAP4_PRM_IO_COUNT_OFFSET			0x001c
+#define OMAP4_PRM_IO_PMCTRL_OFFSET			0x0020
+#define OMAP4_PRM_VOLTSETUP_WARMRESET_OFFSET		0x0024
+#define OMAP4_PRM_VOLTSETUP_CORE_OFF_OFFSET		0x0028
+#define OMAP4_PRM_VOLTSETUP_MPU_OFF_OFFSET		0x002c
+#define OMAP4_PRM_VOLTSETUP_IVA_OFF_OFFSET		0x0030
+#define OMAP4_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET	0x0034
+#define OMAP4_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET	0x0038
+#define OMAP4_PRM_VOLTSETUP_IVA_RET_SLEEP_OFFSET	0x003c
+#define OMAP4_PRM_VP_CORE_CONFIG_OFFSET			0x0040
+#define OMAP4_PRM_VP_CORE_STATUS_OFFSET			0x0044
+#define OMAP4_PRM_VP_CORE_VLIMITTO_OFFSET		0x0048
+#define OMAP4_PRM_VP_CORE_VOLTAGE_OFFSET		0x004c
+#define OMAP4_PRM_VP_CORE_VSTEPMAX_OFFSET		0x0050
+#define OMAP4_PRM_VP_CORE_VSTEPMIN_OFFSET		0x0054
+#define OMAP4_PRM_VP_MPU_CONFIG_OFFSET			0x0058
+#define OMAP4_PRM_VP_MPU_STATUS_OFFSET			0x005c
+#define OMAP4_PRM_VP_MPU_VLIMITTO_OFFSET		0x0060
+#define OMAP4_PRM_VP_MPU_VOLTAGE_OFFSET			0x0064
+#define OMAP4_PRM_VP_MPU_VSTEPMAX_OFFSET		0x0068
+#define OMAP4_PRM_VP_MPU_VSTEPMIN_OFFSET		0x006c
+#define OMAP4_PRM_VP_IVA_CONFIG_OFFSET			0x0070
+#define OMAP4_PRM_VP_IVA_STATUS_OFFSET			0x0074
+#define OMAP4_PRM_VP_IVA_VLIMITTO_OFFSET		0x0078
+#define OMAP4_PRM_VP_IVA_VOLTAGE_OFFSET			0x007c
+#define OMAP4_PRM_VP_IVA_VSTEPMAX_OFFSET		0x0080
+#define OMAP4_PRM_VP_IVA_VSTEPMIN_OFFSET		0x0084
+#define OMAP4_PRM_VC_SMPS_SA_OFFSET			0x0088
+#define OMAP4_PRM_VC_VAL_SMPS_RA_VOL_OFFSET		0x008c
+#define OMAP4_PRM_VC_VAL_SMPS_RA_CMD_OFFSET		0x0090
+#define OMAP4_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET		0x0094
+#define OMAP4_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET		0x0098
+#define OMAP4_PRM_VC_VAL_CMD_VDD_IVA_L_OFFSET		0x009c
+#define OMAP4_PRM_VC_VAL_BYPASS_OFFSET			0x00a0
+#define OMAP4_PRM_VC_CFG_CHANNEL_OFFSET			0x00a4
+#define OMAP4_PRM_VC_CFG_I2C_MODE_OFFSET		0x00a8
+#define OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET			0x00ac
+#define OMAP4_PRM_SRAM_COUNT_OFFSET			0x00b0
+#define OMAP4_PRM_SRAM_WKUP_SETUP_OFFSET		0x00b4
+#define OMAP4_PRM_LDO_SRAM_CORE_SETUP_OFFSET		0x00b8
+#define OMAP4_PRM_LDO_SRAM_CORE_CTRL_OFFSET		0x00bc
+#define OMAP4_PRM_LDO_SRAM_MPU_SETUP_OFFSET		0x00c0
+#define OMAP4_PRM_LDO_SRAM_MPU_CTRL_OFFSET		0x00c4
+#define OMAP4_PRM_LDO_SRAM_IVA_SETUP_OFFSET		0x00c8
+#define OMAP4_PRM_LDO_SRAM_IVA_CTRL_OFFSET		0x00cc
+#define OMAP4_PRM_LDO_ABB_MPU_SETUP_OFFSET		0x00d0
+#define OMAP4_PRM_LDO_ABB_MPU_CTRL_OFFSET		0x00d4
+#define OMAP4_PRM_LDO_ABB_IVA_SETUP_OFFSET		0x00d8
+#define OMAP4_PRM_LDO_ABB_IVA_CTRL_OFFSET		0x00dc
+#define OMAP4_PRM_LDO_BANDGAP_SETUP_OFFSET		0x00e0
+#define OMAP4_PRM_DEVICE_OFF_CTRL_OFFSET		0x00e4
+#define OMAP4_PRM_PHASE1_CNDP_OFFSET			0x00e8
+#define OMAP4_PRM_PHASE2A_CNDP_OFFSET			0x00ec
+#define OMAP4_PRM_PHASE2B_CNDP_OFFSET			0x00f0
+#define OMAP4_PRM_MODEM_IF_CTRL_OFFSET			0x00f4
+#define OMAP4_PRM_VC_ERRST_OFFSET			0x00f8
+
+#endif
-- 
1.7.9.5

[PATCH 39/55] ARM: OMAP5: PRM: remove direct register declaration macros

[Tero Kristo]

None of these are currently used, so cleanup.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/prm54xx.h |   18 ------------------
 1 file changed, 18 deletions(-)

diff --git a/arch/arm/mach-omap2/prm54xx.h b/arch/arm/mach-omap2/prm54xx.h
index e441101..3f1b383 100644
--- a/arch/arm/mach-omap2/prm54xx.h
+++ b/arch/arm/mach-omap2/prm54xx.h
@@ -69,7 +69,6 @@
 #define OMAP54XX_PRM_IRQSTATUS_DSP_OFFSET			0x0030
 #define OMAP54XX_PRM_IRQENABLE_DSP_OFFSET			0x0038
 #define OMAP54XX_CM_PRM_PROFILING_CLKCTRL_OFFSET		0x0040
-#define OMAP54XX_CM_PRM_PROFILING_CLKCTRL			OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_OCP_SOCKET_INST, 0x0040)
 #define OMAP54XX_PRM_DEBUG_OUT_OFFSET				0x0084
 #define OMAP54XX_PRM_DEBUG_TRANS_CFG_OFFSET			0x0090
 #define OMAP54XX_PRM_DEBUG_OFF_TRANS_OFFSET			0x0094
@@ -80,13 +79,9 @@
 
 /* PRM.CKGEN_PRM register offsets */
 #define OMAP54XX_CM_CLKSEL_ABE_DSS_SYS_OFFSET			0x0000
-#define OMAP54XX_CM_CLKSEL_ABE_DSS_SYS				OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_CKGEN_INST, 0x0000)
 #define OMAP54XX_CM_CLKSEL_WKUPAON_OFFSET			0x0008
-#define OMAP54XX_CM_CLKSEL_WKUPAON				OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_CKGEN_INST, 0x0008)
 #define OMAP54XX_CM_CLKSEL_ABE_PLL_REF_OFFSET			0x000c
-#define OMAP54XX_CM_CLKSEL_ABE_PLL_REF				OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_CKGEN_INST, 0x000c)
 #define OMAP54XX_CM_CLKSEL_SYS_OFFSET				0x0010
-#define OMAP54XX_CM_CLKSEL_SYS					OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_CKGEN_INST, 0x0010)
 
 /* PRM.MPU_PRM register offsets */
 #define OMAP54XX_PM_MPU_PWRSTCTRL_OFFSET			0x0000
@@ -314,27 +309,16 @@
 /* PRM.WKUPAON_CM register offsets */
 #define OMAP54XX_CM_WKUPAON_CLKSTCTRL_OFFSET			0x0000
 #define OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET		0x0020
-#define OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL			OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0020)
 #define OMAP54XX_CM_WKUPAON_WD_TIMER1_CLKCTRL_OFFSET		0x0028
-#define OMAP54XX_CM_WKUPAON_WD_TIMER1_CLKCTRL			OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0028)
 #define OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET		0x0030
-#define OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL			OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0030)
 #define OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET		0x0038
-#define OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL			OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0038)
 #define OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET		0x0040
-#define OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL			OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0040)
 #define OMAP54XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET		0x0048
-#define OMAP54XX_CM_WKUPAON_TIMER12_CLKCTRL			OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0048)
 #define OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET		0x0050
-#define OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL			OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0050)
 #define OMAP54XX_CM_WKUPAON_SAR_RAM_CLKCTRL_OFFSET		0x0060
-#define OMAP54XX_CM_WKUPAON_SAR_RAM_CLKCTRL			OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0060)
 #define OMAP54XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET			0x0078
-#define OMAP54XX_CM_WKUPAON_KBD_CLKCTRL				OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0078)
 #define OMAP54XX_CM_WKUPAON_SCRM_CLKCTRL_OFFSET			0x0090
-#define OMAP54XX_CM_WKUPAON_SCRM_CLKCTRL			OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0090)
 #define OMAP54XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL_OFFSET		0x0098
-#define OMAP54XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL			OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0098)
 
 /* PRM.EMU_PRM register offsets */
 #define OMAP54XX_PM_EMU_PWRSTCTRL_OFFSET			0x0000
@@ -345,9 +329,7 @@
 #define OMAP54XX_CM_EMU_CLKSTCTRL_OFFSET			0x0000
 #define OMAP54XX_CM_EMU_DYNAMICDEP_OFFSET			0x0008
 #define OMAP54XX_CM_EMU_DEBUGSS_CLKCTRL_OFFSET			0x0020
-#define OMAP54XX_CM_EMU_DEBUGSS_CLKCTRL				OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_EMU_CM_INST, 0x0020)
 #define OMAP54XX_CM_EMU_MPU_EMU_DBG_CLKCTRL_OFFSET		0x0028
-#define OMAP54XX_CM_EMU_MPU_EMU_DBG_CLKCTRL			OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_EMU_CM_INST, 0x0028)
 
 /* PRM.DEVICE_PRM register offsets */
 #define OMAP54XX_PRM_RSTCTRL_OFFSET				0x0000
-- 
1.7.9.5

[PATCH 40/55] ARM: OMAP5: PRM: move parts of prm54xx.h header file to public location

[Tero Kristo]

Parts of this file are needed by both the driver and mach-omap2 board
code.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/prm44xx.c      |    2 +-
 arch/arm/mach-omap2/prm54xx.h      |  371 +---------------------------------
 arch/arm/mach-omap2/prminst44xx.c  |    2 +-
 include/linux/power/omap/prm54xx.h |  393 ++++++++++++++++++++++++++++++++++++
 4 files changed, 396 insertions(+), 372 deletions(-)
 create mode 100644 include/linux/power/omap/prm54xx.h

diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index dff2ffa..97b7ab2 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -21,7 +21,7 @@
 
 #include "vp.h"
 #include <linux/power/omap/prm44xx.h>
-#include "prm54xx.h"
+#include <linux/power/omap/prm54xx.h>
 #include "prm7xx.h"
 #include "prcm44xx.h"
 #include "prminst44xx_private.h"
diff --git a/arch/arm/mach-omap2/prm54xx.h b/arch/arm/mach-omap2/prm54xx.h
index 3f1b383..64d0859 100644
--- a/arch/arm/mach-omap2/prm54xx.h
+++ b/arch/arm/mach-omap2/prm54xx.h
@@ -24,380 +24,11 @@
 #include "prm44xx_54xx.h"
 #include "prcm-common.h"
 #include "prm.h"
+#include <linux/power/omap/prm54xx.h>
 
 #define OMAP54XX_PRM_BASE		0x4ae06000
 
 #define OMAP54XX_PRM_REGADDR(inst, reg)				\
 	OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE + (inst) + (reg))
 
-
-/* PRM instances */
-#define OMAP54XX_PRM_OCP_SOCKET_INST	0x0000
-#define OMAP54XX_PRM_CKGEN_INST		0x0100
-#define OMAP54XX_PRM_MPU_INST		0x0300
-#define OMAP54XX_PRM_DSP_INST		0x0400
-#define OMAP54XX_PRM_ABE_INST		0x0500
-#define OMAP54XX_PRM_COREAON_INST	0x0600
-#define OMAP54XX_PRM_CORE_INST		0x0700
-#define OMAP54XX_PRM_IVA_INST		0x1200
-#define OMAP54XX_PRM_CAM_INST		0x1300
-#define OMAP54XX_PRM_DSS_INST		0x1400
-#define OMAP54XX_PRM_GPU_INST		0x1500
-#define OMAP54XX_PRM_L3INIT_INST	0x1600
-#define OMAP54XX_PRM_CUSTEFUSE_INST	0x1700
-#define OMAP54XX_PRM_WKUPAON_INST	0x1800
-#define OMAP54XX_PRM_WKUPAON_CM_INST	0x1900
-#define OMAP54XX_PRM_EMU_INST		0x1a00
-#define OMAP54XX_PRM_EMU_CM_INST	0x1b00
-#define OMAP54XX_PRM_DEVICE_INST	0x1c00
-#define OMAP54XX_PRM_INSTR_INST		0x1f00
-
-/* PRM clockdomain register offsets (from instance start) */
-#define OMAP54XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS	0x0000
-#define OMAP54XX_PRM_EMU_CM_EMU_CDOFFS		0x0000
-
-/* PRM */
-
-/* PRM.OCP_SOCKET_PRM register offsets */
-#define OMAP54XX_REVISION_PRM_OFFSET				0x0000
-#define OMAP54XX_PRM_IRQSTATUS_MPU_OFFSET			0x0010
-#define OMAP54XX_PRM_IRQSTATUS_MPU_2_OFFSET			0x0014
-#define OMAP54XX_PRM_IRQENABLE_MPU_OFFSET			0x0018
-#define OMAP54XX_PRM_IRQENABLE_MPU_2_OFFSET			0x001c
-#define OMAP54XX_PRM_IRQSTATUS_IPU_OFFSET			0x0020
-#define OMAP54XX_PRM_IRQENABLE_IPU_OFFSET			0x0028
-#define OMAP54XX_PRM_IRQSTATUS_DSP_OFFSET			0x0030
-#define OMAP54XX_PRM_IRQENABLE_DSP_OFFSET			0x0038
-#define OMAP54XX_CM_PRM_PROFILING_CLKCTRL_OFFSET		0x0040
-#define OMAP54XX_PRM_DEBUG_OUT_OFFSET				0x0084
-#define OMAP54XX_PRM_DEBUG_TRANS_CFG_OFFSET			0x0090
-#define OMAP54XX_PRM_DEBUG_OFF_TRANS_OFFSET			0x0094
-#define OMAP54XX_PRM_DEBUG_CORE_RET_TRANS_OFFSET		0x0098
-#define OMAP54XX_PRM_DEBUG_MPU_RET_TRANS_OFFSET			0x009c
-#define OMAP54XX_PRM_DEBUG_MM_RET_TRANS_OFFSET			0x00a0
-#define OMAP54XX_PRM_DEBUG_WKUPAON_FD_TRANS_OFFSET		0x00a4
-
-/* PRM.CKGEN_PRM register offsets */
-#define OMAP54XX_CM_CLKSEL_ABE_DSS_SYS_OFFSET			0x0000
-#define OMAP54XX_CM_CLKSEL_WKUPAON_OFFSET			0x0008
-#define OMAP54XX_CM_CLKSEL_ABE_PLL_REF_OFFSET			0x000c
-#define OMAP54XX_CM_CLKSEL_SYS_OFFSET				0x0010
-
-/* PRM.MPU_PRM register offsets */
-#define OMAP54XX_PM_MPU_PWRSTCTRL_OFFSET			0x0000
-#define OMAP54XX_PM_MPU_PWRSTST_OFFSET				0x0004
-#define OMAP54XX_RM_MPU_MPU_CONTEXT_OFFSET			0x0024
-
-/* PRM.DSP_PRM register offsets */
-#define OMAP54XX_PM_DSP_PWRSTCTRL_OFFSET			0x0000
-#define OMAP54XX_PM_DSP_PWRSTST_OFFSET				0x0004
-#define OMAP54XX_RM_DSP_RSTCTRL_OFFSET				0x0010
-#define OMAP54XX_RM_DSP_RSTST_OFFSET				0x0014
-#define OMAP54XX_RM_DSP_DSP_CONTEXT_OFFSET			0x0024
-
-/* PRM.ABE_PRM register offsets */
-#define OMAP54XX_PM_ABE_PWRSTCTRL_OFFSET			0x0000
-#define OMAP54XX_PM_ABE_PWRSTST_OFFSET				0x0004
-#define OMAP54XX_RM_ABE_AESS_CONTEXT_OFFSET			0x002c
-#define OMAP54XX_PM_ABE_MCPDM_WKDEP_OFFSET			0x0030
-#define OMAP54XX_RM_ABE_MCPDM_CONTEXT_OFFSET			0x0034
-#define OMAP54XX_PM_ABE_DMIC_WKDEP_OFFSET			0x0038
-#define OMAP54XX_RM_ABE_DMIC_CONTEXT_OFFSET			0x003c
-#define OMAP54XX_PM_ABE_MCASP_WKDEP_OFFSET			0x0040
-#define OMAP54XX_RM_ABE_MCASP_CONTEXT_OFFSET			0x0044
-#define OMAP54XX_PM_ABE_MCBSP1_WKDEP_OFFSET			0x0048
-#define OMAP54XX_RM_ABE_MCBSP1_CONTEXT_OFFSET			0x004c
-#define OMAP54XX_PM_ABE_MCBSP2_WKDEP_OFFSET			0x0050
-#define OMAP54XX_RM_ABE_MCBSP2_CONTEXT_OFFSET			0x0054
-#define OMAP54XX_PM_ABE_MCBSP3_WKDEP_OFFSET			0x0058
-#define OMAP54XX_RM_ABE_MCBSP3_CONTEXT_OFFSET			0x005c
-#define OMAP54XX_PM_ABE_SLIMBUS1_WKDEP_OFFSET			0x0060
-#define OMAP54XX_RM_ABE_SLIMBUS1_CONTEXT_OFFSET			0x0064
-#define OMAP54XX_PM_ABE_TIMER5_WKDEP_OFFSET			0x0068
-#define OMAP54XX_RM_ABE_TIMER5_CONTEXT_OFFSET			0x006c
-#define OMAP54XX_PM_ABE_TIMER6_WKDEP_OFFSET			0x0070
-#define OMAP54XX_RM_ABE_TIMER6_CONTEXT_OFFSET			0x0074
-#define OMAP54XX_PM_ABE_TIMER7_WKDEP_OFFSET			0x0078
-#define OMAP54XX_RM_ABE_TIMER7_CONTEXT_OFFSET			0x007c
-#define OMAP54XX_PM_ABE_TIMER8_WKDEP_OFFSET			0x0080
-#define OMAP54XX_RM_ABE_TIMER8_CONTEXT_OFFSET			0x0084
-#define OMAP54XX_PM_ABE_WD_TIMER3_WKDEP_OFFSET			0x0088
-#define OMAP54XX_RM_ABE_WD_TIMER3_CONTEXT_OFFSET		0x008c
-
-/* PRM.COREAON_PRM register offsets */
-#define OMAP54XX_PM_COREAON_SMARTREFLEX_MPU_WKDEP_OFFSET	0x0028
-#define OMAP54XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET	0x002c
-#define OMAP54XX_PM_COREAON_SMARTREFLEX_MM_WKDEP_OFFSET		0x0030
-#define OMAP54XX_RM_COREAON_SMARTREFLEX_MM_CONTEXT_OFFSET	0x0034
-#define OMAP54XX_PM_COREAON_SMARTREFLEX_CORE_WKDEP_OFFSET	0x0038
-#define OMAP54XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET	0x003c
-
-/* PRM.CORE_PRM register offsets */
-#define OMAP54XX_PM_CORE_PWRSTCTRL_OFFSET			0x0000
-#define OMAP54XX_PM_CORE_PWRSTST_OFFSET				0x0004
-#define OMAP54XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET		0x0024
-#define OMAP54XX_RM_L3MAIN2_L3_MAIN_2_CONTEXT_OFFSET		0x0124
-#define OMAP54XX_RM_L3MAIN2_GPMC_CONTEXT_OFFSET			0x012c
-#define OMAP54XX_RM_L3MAIN2_OCMC_RAM_CONTEXT_OFFSET		0x0134
-#define OMAP54XX_RM_IPU_RSTCTRL_OFFSET				0x0210
-#define OMAP54XX_RM_IPU_RSTST_OFFSET				0x0214
-#define OMAP54XX_RM_IPU_IPU_CONTEXT_OFFSET			0x0224
-#define OMAP54XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET		0x0324
-#define OMAP54XX_RM_EMIF_DMM_CONTEXT_OFFSET			0x0424
-#define OMAP54XX_RM_EMIF_EMIF_OCP_FW_CONTEXT_OFFSET		0x042c
-#define OMAP54XX_RM_EMIF_EMIF1_CONTEXT_OFFSET			0x0434
-#define OMAP54XX_RM_EMIF_EMIF2_CONTEXT_OFFSET			0x043c
-#define OMAP54XX_RM_EMIF_EMIF_DLL_CONTEXT_OFFSET		0x0444
-#define OMAP54XX_RM_C2C_C2C_CONTEXT_OFFSET			0x0524
-#define OMAP54XX_RM_C2C_MODEM_ICR_CONTEXT_OFFSET		0x052c
-#define OMAP54XX_RM_C2C_C2C_OCP_FW_CONTEXT_OFFSET		0x0534
-#define OMAP54XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET			0x0624
-#define OMAP54XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET		0x062c
-#define OMAP54XX_RM_L4CFG_MAILBOX_CONTEXT_OFFSET		0x0634
-#define OMAP54XX_RM_L4CFG_SAR_ROM_CONTEXT_OFFSET		0x063c
-#define OMAP54XX_RM_L4CFG_OCP2SCP2_CONTEXT_OFFSET		0x0644
-#define OMAP54XX_RM_L3INSTR_L3_MAIN_3_CONTEXT_OFFSET		0x0724
-#define OMAP54XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET		0x072c
-#define OMAP54XX_RM_L3INSTR_OCP_WP_NOC_CONTEXT_OFFSET		0x0744
-#define OMAP54XX_RM_MIPIEXT_LLI_CONTEXT_OFFSET			0x0824
-#define OMAP54XX_RM_MIPIEXT_LLI_OCP_FW_CONTEXT_OFFSET		0x082c
-#define OMAP54XX_RM_MIPIEXT_MPHY_CONTEXT_OFFSET			0x0834
-#define OMAP54XX_PM_L4PER_TIMER10_WKDEP_OFFSET			0x0928
-#define OMAP54XX_RM_L4PER_TIMER10_CONTEXT_OFFSET		0x092c
-#define OMAP54XX_PM_L4PER_TIMER11_WKDEP_OFFSET			0x0930
-#define OMAP54XX_RM_L4PER_TIMER11_CONTEXT_OFFSET		0x0934
-#define OMAP54XX_PM_L4PER_TIMER2_WKDEP_OFFSET			0x0938
-#define OMAP54XX_RM_L4PER_TIMER2_CONTEXT_OFFSET			0x093c
-#define OMAP54XX_PM_L4PER_TIMER3_WKDEP_OFFSET			0x0940
-#define OMAP54XX_RM_L4PER_TIMER3_CONTEXT_OFFSET			0x0944
-#define OMAP54XX_PM_L4PER_TIMER4_WKDEP_OFFSET			0x0948
-#define OMAP54XX_RM_L4PER_TIMER4_CONTEXT_OFFSET			0x094c
-#define OMAP54XX_PM_L4PER_TIMER9_WKDEP_OFFSET			0x0950
-#define OMAP54XX_RM_L4PER_TIMER9_CONTEXT_OFFSET			0x0954
-#define OMAP54XX_RM_L4PER_ELM_CONTEXT_OFFSET			0x095c
-#define OMAP54XX_PM_L4PER_GPIO2_WKDEP_OFFSET			0x0960
-#define OMAP54XX_RM_L4PER_GPIO2_CONTEXT_OFFSET			0x0964
-#define OMAP54XX_PM_L4PER_GPIO3_WKDEP_OFFSET			0x0968
-#define OMAP54XX_RM_L4PER_GPIO3_CONTEXT_OFFSET			0x096c
-#define OMAP54XX_PM_L4PER_GPIO4_WKDEP_OFFSET			0x0970
-#define OMAP54XX_RM_L4PER_GPIO4_CONTEXT_OFFSET			0x0974
-#define OMAP54XX_PM_L4PER_GPIO5_WKDEP_OFFSET			0x0978
-#define OMAP54XX_RM_L4PER_GPIO5_CONTEXT_OFFSET			0x097c
-#define OMAP54XX_PM_L4PER_GPIO6_WKDEP_OFFSET			0x0980
-#define OMAP54XX_RM_L4PER_GPIO6_CONTEXT_OFFSET			0x0984
-#define OMAP54XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET			0x098c
-#define OMAP54XX_PM_L4PER_I2C1_WKDEP_OFFSET			0x09a0
-#define OMAP54XX_RM_L4PER_I2C1_CONTEXT_OFFSET			0x09a4
-#define OMAP54XX_PM_L4PER_I2C2_WKDEP_OFFSET			0x09a8
-#define OMAP54XX_RM_L4PER_I2C2_CONTEXT_OFFSET			0x09ac
-#define OMAP54XX_PM_L4PER_I2C3_WKDEP_OFFSET			0x09b0
-#define OMAP54XX_RM_L4PER_I2C3_CONTEXT_OFFSET			0x09b4
-#define OMAP54XX_PM_L4PER_I2C4_WKDEP_OFFSET			0x09b8
-#define OMAP54XX_RM_L4PER_I2C4_CONTEXT_OFFSET			0x09bc
-#define OMAP54XX_RM_L4PER_L4_PER_CONTEXT_OFFSET			0x09c0
-#define OMAP54XX_PM_L4PER_MCSPI1_WKDEP_OFFSET			0x09f0
-#define OMAP54XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET			0x09f4
-#define OMAP54XX_PM_L4PER_MCSPI2_WKDEP_OFFSET			0x09f8
-#define OMAP54XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET			0x09fc
-#define OMAP54XX_PM_L4PER_MCSPI3_WKDEP_OFFSET			0x0a00
-#define OMAP54XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET			0x0a04
-#define OMAP54XX_PM_L4PER_MCSPI4_WKDEP_OFFSET			0x0a08
-#define OMAP54XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET			0x0a0c
-#define OMAP54XX_PM_L4PER_GPIO7_WKDEP_OFFSET			0x0a10
-#define OMAP54XX_RM_L4PER_GPIO7_CONTEXT_OFFSET			0x0a14
-#define OMAP54XX_PM_L4PER_GPIO8_WKDEP_OFFSET			0x0a18
-#define OMAP54XX_RM_L4PER_GPIO8_CONTEXT_OFFSET			0x0a1c
-#define OMAP54XX_PM_L4PER_MMC3_WKDEP_OFFSET			0x0a20
-#define OMAP54XX_RM_L4PER_MMC3_CONTEXT_OFFSET			0x0a24
-#define OMAP54XX_PM_L4PER_MMC4_WKDEP_OFFSET			0x0a28
-#define OMAP54XX_RM_L4PER_MMC4_CONTEXT_OFFSET			0x0a2c
-#define OMAP54XX_PM_L4PER_UART1_WKDEP_OFFSET			0x0a40
-#define OMAP54XX_RM_L4PER_UART1_CONTEXT_OFFSET			0x0a44
-#define OMAP54XX_PM_L4PER_UART2_WKDEP_OFFSET			0x0a48
-#define OMAP54XX_RM_L4PER_UART2_CONTEXT_OFFSET			0x0a4c
-#define OMAP54XX_PM_L4PER_UART3_WKDEP_OFFSET			0x0a50
-#define OMAP54XX_RM_L4PER_UART3_CONTEXT_OFFSET			0x0a54
-#define OMAP54XX_RM_L4PER_UART4_CONTEXT_OFFSET			0x0a58
-#define OMAP54XX_PM_L4PER_UART4_WKDEP_OFFSET			0x0a5c
-#define OMAP54XX_PM_L4PER_MMC5_WKDEP_OFFSET			0x0a60
-#define OMAP54XX_RM_L4PER_MMC5_CONTEXT_OFFSET			0x0a64
-#define OMAP54XX_PM_L4PER_I2C5_WKDEP_OFFSET			0x0a68
-#define OMAP54XX_RM_L4PER_I2C5_CONTEXT_OFFSET			0x0a6c
-#define OMAP54XX_PM_L4PER_UART5_WKDEP_OFFSET			0x0a70
-#define OMAP54XX_RM_L4PER_UART5_CONTEXT_OFFSET			0x0a74
-#define OMAP54XX_PM_L4PER_UART6_WKDEP_OFFSET			0x0a78
-#define OMAP54XX_RM_L4PER_UART6_CONTEXT_OFFSET			0x0a7c
-#define OMAP54XX_RM_L4SEC_AES1_CONTEXT_OFFSET			0x0aa4
-#define OMAP54XX_RM_L4SEC_AES2_CONTEXT_OFFSET			0x0aac
-#define OMAP54XX_RM_L4SEC_DES3DES_CONTEXT_OFFSET		0x0ab4
-#define OMAP54XX_RM_L4SEC_FPKA_CONTEXT_OFFSET			0x0abc
-#define OMAP54XX_RM_L4SEC_RNG_CONTEXT_OFFSET			0x0ac4
-#define OMAP54XX_RM_L4SEC_SHA2MD5_CONTEXT_OFFSET		0x0acc
-#define OMAP54XX_RM_L4SEC_DMA_CRYPTO_CONTEXT_OFFSET		0x0adc
-
-/* PRM.IVA_PRM register offsets */
-#define OMAP54XX_PM_IVA_PWRSTCTRL_OFFSET			0x0000
-#define OMAP54XX_PM_IVA_PWRSTST_OFFSET				0x0004
-#define OMAP54XX_RM_IVA_RSTCTRL_OFFSET				0x0010
-#define OMAP54XX_RM_IVA_RSTST_OFFSET				0x0014
-#define OMAP54XX_RM_IVA_IVA_CONTEXT_OFFSET			0x0024
-#define OMAP54XX_RM_IVA_SL2_CONTEXT_OFFSET			0x002c
-
-/* PRM.CAM_PRM register offsets */
-#define OMAP54XX_PM_CAM_PWRSTCTRL_OFFSET			0x0000
-#define OMAP54XX_PM_CAM_PWRSTST_OFFSET				0x0004
-#define OMAP54XX_RM_CAM_ISS_CONTEXT_OFFSET			0x0024
-#define OMAP54XX_RM_CAM_FDIF_CONTEXT_OFFSET			0x002c
-#define OMAP54XX_RM_CAM_CAL_CONTEXT_OFFSET			0x0034
-
-/* PRM.DSS_PRM register offsets */
-#define OMAP54XX_PM_DSS_PWRSTCTRL_OFFSET			0x0000
-#define OMAP54XX_PM_DSS_PWRSTST_OFFSET				0x0004
-#define OMAP54XX_PM_DSS_DSS_WKDEP_OFFSET			0x0020
-#define OMAP54XX_RM_DSS_DSS_CONTEXT_OFFSET			0x0024
-#define OMAP54XX_RM_DSS_BB2D_CONTEXT_OFFSET			0x0034
-
-/* PRM.GPU_PRM register offsets */
-#define OMAP54XX_PM_GPU_PWRSTCTRL_OFFSET			0x0000
-#define OMAP54XX_PM_GPU_PWRSTST_OFFSET				0x0004
-#define OMAP54XX_RM_GPU_GPU_CONTEXT_OFFSET			0x0024
-
-/* PRM.L3INIT_PRM register offsets */
-#define OMAP54XX_PM_L3INIT_PWRSTCTRL_OFFSET			0x0000
-#define OMAP54XX_PM_L3INIT_PWRSTST_OFFSET			0x0004
-#define OMAP54XX_PM_L3INIT_MMC1_WKDEP_OFFSET			0x0028
-#define OMAP54XX_RM_L3INIT_MMC1_CONTEXT_OFFSET			0x002c
-#define OMAP54XX_PM_L3INIT_MMC2_WKDEP_OFFSET			0x0030
-#define OMAP54XX_RM_L3INIT_MMC2_CONTEXT_OFFSET			0x0034
-#define OMAP54XX_PM_L3INIT_HSI_WKDEP_OFFSET			0x0038
-#define OMAP54XX_RM_L3INIT_HSI_CONTEXT_OFFSET			0x003c
-#define OMAP54XX_PM_L3INIT_UNIPRO2_WKDEP_OFFSET			0x0040
-#define OMAP54XX_RM_L3INIT_UNIPRO2_CONTEXT_OFFSET		0x0044
-#define OMAP54XX_PM_L3INIT_USB_HOST_HS_WKDEP_OFFSET		0x0058
-#define OMAP54XX_RM_L3INIT_USB_HOST_HS_CONTEXT_OFFSET		0x005c
-#define OMAP54XX_PM_L3INIT_USB_TLL_HS_WKDEP_OFFSET		0x0068
-#define OMAP54XX_RM_L3INIT_USB_TLL_HS_CONTEXT_OFFSET		0x006c
-#define OMAP54XX_RM_L3INIT_IEEE1500_2_OCP_CONTEXT_OFFSET	0x007c
-#define OMAP54XX_PM_L3INIT_SATA_WKDEP_OFFSET			0x0088
-#define OMAP54XX_RM_L3INIT_SATA_CONTEXT_OFFSET			0x008c
-#define OMAP54XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET		0x00e4
-#define OMAP54XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET		0x00ec
-#define OMAP54XX_PM_L3INIT_USB_OTG_SS_WKDEP_OFFSET		0x00f0
-#define OMAP54XX_RM_L3INIT_USB_OTG_SS_CONTEXT_OFFSET		0x00f4
-
-/* PRM.CUSTEFUSE_PRM register offsets */
-#define OMAP54XX_PM_CUSTEFUSE_PWRSTCTRL_OFFSET			0x0000
-#define OMAP54XX_PM_CUSTEFUSE_PWRSTST_OFFSET			0x0004
-#define OMAP54XX_RM_CUSTEFUSE_EFUSE_CTRL_CUST_CONTEXT_OFFSET	0x0024
-
-/* PRM.WKUPAON_PRM register offsets */
-#define OMAP54XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET		0x0024
-#define OMAP54XX_RM_WKUPAON_WD_TIMER1_CONTEXT_OFFSET		0x002c
-#define OMAP54XX_PM_WKUPAON_WD_TIMER2_WKDEP_OFFSET		0x0030
-#define OMAP54XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET		0x0034
-#define OMAP54XX_PM_WKUPAON_GPIO1_WKDEP_OFFSET			0x0038
-#define OMAP54XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET		0x003c
-#define OMAP54XX_PM_WKUPAON_TIMER1_WKDEP_OFFSET			0x0040
-#define OMAP54XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET		0x0044
-#define OMAP54XX_PM_WKUPAON_TIMER12_WKDEP_OFFSET		0x0048
-#define OMAP54XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET		0x004c
-#define OMAP54XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET		0x0054
-#define OMAP54XX_RM_WKUPAON_SAR_RAM_CONTEXT_OFFSET		0x0064
-#define OMAP54XX_PM_WKUPAON_KBD_WKDEP_OFFSET			0x0078
-#define OMAP54XX_RM_WKUPAON_KBD_CONTEXT_OFFSET			0x007c
-
-/* PRM.WKUPAON_CM register offsets */
-#define OMAP54XX_CM_WKUPAON_CLKSTCTRL_OFFSET			0x0000
-#define OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET		0x0020
-#define OMAP54XX_CM_WKUPAON_WD_TIMER1_CLKCTRL_OFFSET		0x0028
-#define OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET		0x0030
-#define OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET		0x0038
-#define OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET		0x0040
-#define OMAP54XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET		0x0048
-#define OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET		0x0050
-#define OMAP54XX_CM_WKUPAON_SAR_RAM_CLKCTRL_OFFSET		0x0060
-#define OMAP54XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET			0x0078
-#define OMAP54XX_CM_WKUPAON_SCRM_CLKCTRL_OFFSET			0x0090
-#define OMAP54XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL_OFFSET		0x0098
-
-/* PRM.EMU_PRM register offsets */
-#define OMAP54XX_PM_EMU_PWRSTCTRL_OFFSET			0x0000
-#define OMAP54XX_PM_EMU_PWRSTST_OFFSET				0x0004
-#define OMAP54XX_RM_EMU_DEBUGSS_CONTEXT_OFFSET			0x0024
-
-/* PRM.EMU_CM register offsets */
-#define OMAP54XX_CM_EMU_CLKSTCTRL_OFFSET			0x0000
-#define OMAP54XX_CM_EMU_DYNAMICDEP_OFFSET			0x0008
-#define OMAP54XX_CM_EMU_DEBUGSS_CLKCTRL_OFFSET			0x0020
-#define OMAP54XX_CM_EMU_MPU_EMU_DBG_CLKCTRL_OFFSET		0x0028
-
-/* PRM.DEVICE_PRM register offsets */
-#define OMAP54XX_PRM_RSTCTRL_OFFSET				0x0000
-#define OMAP54XX_PRM_RSTST_OFFSET				0x0004
-#define OMAP54XX_PRM_RSTTIME_OFFSET				0x0008
-#define OMAP54XX_PRM_CLKREQCTRL_OFFSET				0x000c
-#define OMAP54XX_PRM_VOLTCTRL_OFFSET				0x0010
-#define OMAP54XX_PRM_PWRREQCTRL_OFFSET				0x0014
-#define OMAP54XX_PRM_PSCON_COUNT_OFFSET				0x0018
-#define OMAP54XX_PRM_IO_COUNT_OFFSET				0x001c
-#define OMAP54XX_PRM_IO_PMCTRL_OFFSET				0x0020
-#define OMAP54XX_PRM_VOLTSETUP_WARMRESET_OFFSET			0x0024
-#define OMAP54XX_PRM_VOLTSETUP_CORE_OFF_OFFSET			0x0028
-#define OMAP54XX_PRM_VOLTSETUP_MPU_OFF_OFFSET			0x002c
-#define OMAP54XX_PRM_VOLTSETUP_MM_OFF_OFFSET			0x0030
-#define OMAP54XX_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET		0x0034
-#define OMAP54XX_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET		0x0038
-#define OMAP54XX_PRM_VOLTSETUP_MM_RET_SLEEP_OFFSET		0x003c
-#define OMAP54XX_PRM_VP_CORE_CONFIG_OFFSET			0x0040
-#define OMAP54XX_PRM_VP_CORE_STATUS_OFFSET			0x0044
-#define OMAP54XX_PRM_VP_CORE_VLIMITTO_OFFSET			0x0048
-#define OMAP54XX_PRM_VP_CORE_VOLTAGE_OFFSET			0x004c
-#define OMAP54XX_PRM_VP_CORE_VSTEPMAX_OFFSET			0x0050
-#define OMAP54XX_PRM_VP_CORE_VSTEPMIN_OFFSET			0x0054
-#define OMAP54XX_PRM_VP_MPU_CONFIG_OFFSET			0x0058
-#define OMAP54XX_PRM_VP_MPU_STATUS_OFFSET			0x005c
-#define OMAP54XX_PRM_VP_MPU_VLIMITTO_OFFSET			0x0060
-#define OMAP54XX_PRM_VP_MPU_VOLTAGE_OFFSET			0x0064
-#define OMAP54XX_PRM_VP_MPU_VSTEPMAX_OFFSET			0x0068
-#define OMAP54XX_PRM_VP_MPU_VSTEPMIN_OFFSET			0x006c
-#define OMAP54XX_PRM_VP_MM_CONFIG_OFFSET			0x0070
-#define OMAP54XX_PRM_VP_MM_STATUS_OFFSET			0x0074
-#define OMAP54XX_PRM_VP_MM_VLIMITTO_OFFSET			0x0078
-#define OMAP54XX_PRM_VP_MM_VOLTAGE_OFFSET			0x007c
-#define OMAP54XX_PRM_VP_MM_VSTEPMAX_OFFSET			0x0080
-#define OMAP54XX_PRM_VP_MM_VSTEPMIN_OFFSET			0x0084
-#define OMAP54XX_PRM_VC_SMPS_CORE_CONFIG_OFFSET			0x0088
-#define OMAP54XX_PRM_VC_SMPS_MM_CONFIG_OFFSET			0x008c
-#define OMAP54XX_PRM_VC_SMPS_MPU_CONFIG_OFFSET			0x0090
-#define OMAP54XX_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET		0x0094
-#define OMAP54XX_PRM_VC_VAL_CMD_VDD_MM_L_OFFSET			0x0098
-#define OMAP54XX_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET		0x009c
-#define OMAP54XX_PRM_VC_VAL_BYPASS_OFFSET			0x00a0
-#define OMAP54XX_PRM_VC_CORE_ERRST_OFFSET			0x00a4
-#define OMAP54XX_PRM_VC_MM_ERRST_OFFSET				0x00a8
-#define OMAP54XX_PRM_VC_MPU_ERRST_OFFSET			0x00ac
-#define OMAP54XX_PRM_VC_BYPASS_ERRST_OFFSET			0x00b0
-#define OMAP54XX_PRM_VC_CFG_I2C_MODE_OFFSET			0x00b4
-#define OMAP54XX_PRM_VC_CFG_I2C_CLK_OFFSET			0x00b8
-#define OMAP54XX_PRM_SRAM_COUNT_OFFSET				0x00bc
-#define OMAP54XX_PRM_SRAM_WKUP_SETUP_OFFSET			0x00c0
-#define OMAP54XX_PRM_SLDO_CORE_SETUP_OFFSET			0x00c4
-#define OMAP54XX_PRM_SLDO_CORE_CTRL_OFFSET			0x00c8
-#define OMAP54XX_PRM_SLDO_MPU_SETUP_OFFSET			0x00cc
-#define OMAP54XX_PRM_SLDO_MPU_CTRL_OFFSET			0x00d0
-#define OMAP54XX_PRM_SLDO_MM_SETUP_OFFSET			0x00d4
-#define OMAP54XX_PRM_SLDO_MM_CTRL_OFFSET			0x00d8
-#define OMAP54XX_PRM_ABBLDO_MPU_SETUP_OFFSET			0x00dc
-#define OMAP54XX_PRM_ABBLDO_MPU_CTRL_OFFSET			0x00e0
-#define OMAP54XX_PRM_ABBLDO_MM_SETUP_OFFSET			0x00e4
-#define OMAP54XX_PRM_ABBLDO_MM_CTRL_OFFSET			0x00e8
-#define OMAP54XX_PRM_BANDGAP_SETUP_OFFSET			0x00ec
-#define OMAP54XX_PRM_DEVICE_OFF_CTRL_OFFSET			0x00f0
-#define OMAP54XX_PRM_PHASE1_CNDP_OFFSET				0x00f4
-#define OMAP54XX_PRM_PHASE2A_CNDP_OFFSET			0x00f8
-#define OMAP54XX_PRM_PHASE2B_CNDP_OFFSET			0x00fc
-#define OMAP54XX_PRM_MODEM_IF_CTRL_OFFSET			0x0100
-#define OMAP54XX_PRM_VOLTST_MPU_OFFSET				0x0110
-#define OMAP54XX_PRM_VOLTST_MM_OFFSET				0x0114
-
 #endif
diff --git a/arch/arm/mach-omap2/prminst44xx.c b/arch/arm/mach-omap2/prminst44xx.c
index f029cb1..f330766 100644
--- a/arch/arm/mach-omap2/prminst44xx.c
+++ b/arch/arm/mach-omap2/prminst44xx.c
@@ -19,7 +19,7 @@
 #include "prm.h"
 #include "prcm-common.h"
 #include <linux/power/omap/prm44xx.h>
-#include "prm54xx.h"
+#include <linux/power/omap/prm54xx.h>
 #include "prm7xx.h"
 #include "prminst44xx.h"
 #include "prcm44xx.h"
diff --git a/include/linux/power/omap/prm54xx.h b/include/linux/power/omap/prm54xx.h
new file mode 100644
index 0000000..61484c9
--- /dev/null
+++ b/include/linux/power/omap/prm54xx.h
@@ -0,0 +1,393 @@
+/*
+ * OMAP54xx PRM instance offset macros
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __LINUX_POWER_OMAP_PRM54XX_H
+#define __LINUX_POWER_OMAP_PRM54XX_H
+
+/* PRM instances */
+#define OMAP54XX_PRM_OCP_SOCKET_INST	0x0000
+#define OMAP54XX_PRM_CKGEN_INST		0x0100
+#define OMAP54XX_PRM_MPU_INST		0x0300
+#define OMAP54XX_PRM_DSP_INST		0x0400
+#define OMAP54XX_PRM_ABE_INST		0x0500
+#define OMAP54XX_PRM_COREAON_INST	0x0600
+#define OMAP54XX_PRM_CORE_INST		0x0700
+#define OMAP54XX_PRM_IVA_INST		0x1200
+#define OMAP54XX_PRM_CAM_INST		0x1300
+#define OMAP54XX_PRM_DSS_INST		0x1400
+#define OMAP54XX_PRM_GPU_INST		0x1500
+#define OMAP54XX_PRM_L3INIT_INST	0x1600
+#define OMAP54XX_PRM_CUSTEFUSE_INST	0x1700
+#define OMAP54XX_PRM_WKUPAON_INST	0x1800
+#define OMAP54XX_PRM_WKUPAON_CM_INST	0x1900
+#define OMAP54XX_PRM_EMU_INST		0x1a00
+#define OMAP54XX_PRM_EMU_CM_INST	0x1b00
+#define OMAP54XX_PRM_DEVICE_INST	0x1c00
+#define OMAP54XX_PRM_INSTR_INST		0x1f00
+
+/* PRM clockdomain register offsets (from instance start) */
+#define OMAP54XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS	0x0000
+#define OMAP54XX_PRM_EMU_CM_EMU_CDOFFS		0x0000
+
+/* PRM */
+
+/* PRM.OCP_SOCKET_PRM register offsets */
+#define OMAP54XX_REVISION_PRM_OFFSET				0x0000
+#define OMAP54XX_PRM_IRQSTATUS_MPU_OFFSET			0x0010
+#define OMAP54XX_PRM_IRQSTATUS_MPU_2_OFFSET			0x0014
+#define OMAP54XX_PRM_IRQENABLE_MPU_OFFSET			0x0018
+#define OMAP54XX_PRM_IRQENABLE_MPU_2_OFFSET			0x001c
+#define OMAP54XX_PRM_IRQSTATUS_IPU_OFFSET			0x0020
+#define OMAP54XX_PRM_IRQENABLE_IPU_OFFSET			0x0028
+#define OMAP54XX_PRM_IRQSTATUS_DSP_OFFSET			0x0030
+#define OMAP54XX_PRM_IRQENABLE_DSP_OFFSET			0x0038
+#define OMAP54XX_CM_PRM_PROFILING_CLKCTRL_OFFSET		0x0040
+#define OMAP54XX_PRM_DEBUG_OUT_OFFSET				0x0084
+#define OMAP54XX_PRM_DEBUG_TRANS_CFG_OFFSET			0x0090
+#define OMAP54XX_PRM_DEBUG_OFF_TRANS_OFFSET			0x0094
+#define OMAP54XX_PRM_DEBUG_CORE_RET_TRANS_OFFSET		0x0098
+#define OMAP54XX_PRM_DEBUG_MPU_RET_TRANS_OFFSET			0x009c
+#define OMAP54XX_PRM_DEBUG_MM_RET_TRANS_OFFSET			0x00a0
+#define OMAP54XX_PRM_DEBUG_WKUPAON_FD_TRANS_OFFSET		0x00a4
+
+/* PRM.CKGEN_PRM register offsets */
+#define OMAP54XX_CM_CLKSEL_ABE_DSS_SYS_OFFSET			0x0000
+#define OMAP54XX_CM_CLKSEL_WKUPAON_OFFSET			0x0008
+#define OMAP54XX_CM_CLKSEL_ABE_PLL_REF_OFFSET			0x000c
+#define OMAP54XX_CM_CLKSEL_SYS_OFFSET				0x0010
+
+/* PRM.MPU_PRM register offsets */
+#define OMAP54XX_PM_MPU_PWRSTCTRL_OFFSET			0x0000
+#define OMAP54XX_PM_MPU_PWRSTST_OFFSET				0x0004
+#define OMAP54XX_RM_MPU_MPU_CONTEXT_OFFSET			0x0024
+
+/* PRM.DSP_PRM register offsets */
+#define OMAP54XX_PM_DSP_PWRSTCTRL_OFFSET			0x0000
+#define OMAP54XX_PM_DSP_PWRSTST_OFFSET				0x0004
+#define OMAP54XX_RM_DSP_RSTCTRL_OFFSET				0x0010
+#define OMAP54XX_RM_DSP_RSTST_OFFSET				0x0014
+#define OMAP54XX_RM_DSP_DSP_CONTEXT_OFFSET			0x0024
+
+/* PRM.ABE_PRM register offsets */
+#define OMAP54XX_PM_ABE_PWRSTCTRL_OFFSET			0x0000
+#define OMAP54XX_PM_ABE_PWRSTST_OFFSET				0x0004
+#define OMAP54XX_RM_ABE_AESS_CONTEXT_OFFSET			0x002c
+#define OMAP54XX_PM_ABE_MCPDM_WKDEP_OFFSET			0x0030
+#define OMAP54XX_RM_ABE_MCPDM_CONTEXT_OFFSET			0x0034
+#define OMAP54XX_PM_ABE_DMIC_WKDEP_OFFSET			0x0038
+#define OMAP54XX_RM_ABE_DMIC_CONTEXT_OFFSET			0x003c
+#define OMAP54XX_PM_ABE_MCASP_WKDEP_OFFSET			0x0040
+#define OMAP54XX_RM_ABE_MCASP_CONTEXT_OFFSET			0x0044
+#define OMAP54XX_PM_ABE_MCBSP1_WKDEP_OFFSET			0x0048
+#define OMAP54XX_RM_ABE_MCBSP1_CONTEXT_OFFSET			0x004c
+#define OMAP54XX_PM_ABE_MCBSP2_WKDEP_OFFSET			0x0050
+#define OMAP54XX_RM_ABE_MCBSP2_CONTEXT_OFFSET			0x0054
+#define OMAP54XX_PM_ABE_MCBSP3_WKDEP_OFFSET			0x0058
+#define OMAP54XX_RM_ABE_MCBSP3_CONTEXT_OFFSET			0x005c
+#define OMAP54XX_PM_ABE_SLIMBUS1_WKDEP_OFFSET			0x0060
+#define OMAP54XX_RM_ABE_SLIMBUS1_CONTEXT_OFFSET			0x0064
+#define OMAP54XX_PM_ABE_TIMER5_WKDEP_OFFSET			0x0068
+#define OMAP54XX_RM_ABE_TIMER5_CONTEXT_OFFSET			0x006c
+#define OMAP54XX_PM_ABE_TIMER6_WKDEP_OFFSET			0x0070
+#define OMAP54XX_RM_ABE_TIMER6_CONTEXT_OFFSET			0x0074
+#define OMAP54XX_PM_ABE_TIMER7_WKDEP_OFFSET			0x0078
+#define OMAP54XX_RM_ABE_TIMER7_CONTEXT_OFFSET			0x007c
+#define OMAP54XX_PM_ABE_TIMER8_WKDEP_OFFSET			0x0080
+#define OMAP54XX_RM_ABE_TIMER8_CONTEXT_OFFSET			0x0084
+#define OMAP54XX_PM_ABE_WD_TIMER3_WKDEP_OFFSET			0x0088
+#define OMAP54XX_RM_ABE_WD_TIMER3_CONTEXT_OFFSET		0x008c
+
+/* PRM.COREAON_PRM register offsets */
+#define OMAP54XX_PM_COREAON_SMARTREFLEX_MPU_WKDEP_OFFSET	0x0028
+#define OMAP54XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET	0x002c
+#define OMAP54XX_PM_COREAON_SMARTREFLEX_MM_WKDEP_OFFSET		0x0030
+#define OMAP54XX_RM_COREAON_SMARTREFLEX_MM_CONTEXT_OFFSET	0x0034
+#define OMAP54XX_PM_COREAON_SMARTREFLEX_CORE_WKDEP_OFFSET	0x0038
+#define OMAP54XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET	0x003c
+
+/* PRM.CORE_PRM register offsets */
+#define OMAP54XX_PM_CORE_PWRSTCTRL_OFFSET			0x0000
+#define OMAP54XX_PM_CORE_PWRSTST_OFFSET				0x0004
+#define OMAP54XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET		0x0024
+#define OMAP54XX_RM_L3MAIN2_L3_MAIN_2_CONTEXT_OFFSET		0x0124
+#define OMAP54XX_RM_L3MAIN2_GPMC_CONTEXT_OFFSET			0x012c
+#define OMAP54XX_RM_L3MAIN2_OCMC_RAM_CONTEXT_OFFSET		0x0134
+#define OMAP54XX_RM_IPU_RSTCTRL_OFFSET				0x0210
+#define OMAP54XX_RM_IPU_RSTST_OFFSET				0x0214
+#define OMAP54XX_RM_IPU_IPU_CONTEXT_OFFSET			0x0224
+#define OMAP54XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET		0x0324
+#define OMAP54XX_RM_EMIF_DMM_CONTEXT_OFFSET			0x0424
+#define OMAP54XX_RM_EMIF_EMIF_OCP_FW_CONTEXT_OFFSET		0x042c
+#define OMAP54XX_RM_EMIF_EMIF1_CONTEXT_OFFSET			0x0434
+#define OMAP54XX_RM_EMIF_EMIF2_CONTEXT_OFFSET			0x043c
+#define OMAP54XX_RM_EMIF_EMIF_DLL_CONTEXT_OFFSET		0x0444
+#define OMAP54XX_RM_C2C_C2C_CONTEXT_OFFSET			0x0524
+#define OMAP54XX_RM_C2C_MODEM_ICR_CONTEXT_OFFSET		0x052c
+#define OMAP54XX_RM_C2C_C2C_OCP_FW_CONTEXT_OFFSET		0x0534
+#define OMAP54XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET			0x0624
+#define OMAP54XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET		0x062c
+#define OMAP54XX_RM_L4CFG_MAILBOX_CONTEXT_OFFSET		0x0634
+#define OMAP54XX_RM_L4CFG_SAR_ROM_CONTEXT_OFFSET		0x063c
+#define OMAP54XX_RM_L4CFG_OCP2SCP2_CONTEXT_OFFSET		0x0644
+#define OMAP54XX_RM_L3INSTR_L3_MAIN_3_CONTEXT_OFFSET		0x0724
+#define OMAP54XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET		0x072c
+#define OMAP54XX_RM_L3INSTR_OCP_WP_NOC_CONTEXT_OFFSET		0x0744
+#define OMAP54XX_RM_MIPIEXT_LLI_CONTEXT_OFFSET			0x0824
+#define OMAP54XX_RM_MIPIEXT_LLI_OCP_FW_CONTEXT_OFFSET		0x082c
+#define OMAP54XX_RM_MIPIEXT_MPHY_CONTEXT_OFFSET			0x0834
+#define OMAP54XX_PM_L4PER_TIMER10_WKDEP_OFFSET			0x0928
+#define OMAP54XX_RM_L4PER_TIMER10_CONTEXT_OFFSET		0x092c
+#define OMAP54XX_PM_L4PER_TIMER11_WKDEP_OFFSET			0x0930
+#define OMAP54XX_RM_L4PER_TIMER11_CONTEXT_OFFSET		0x0934
+#define OMAP54XX_PM_L4PER_TIMER2_WKDEP_OFFSET			0x0938
+#define OMAP54XX_RM_L4PER_TIMER2_CONTEXT_OFFSET			0x093c
+#define OMAP54XX_PM_L4PER_TIMER3_WKDEP_OFFSET			0x0940
+#define OMAP54XX_RM_L4PER_TIMER3_CONTEXT_OFFSET			0x0944
+#define OMAP54XX_PM_L4PER_TIMER4_WKDEP_OFFSET			0x0948
+#define OMAP54XX_RM_L4PER_TIMER4_CONTEXT_OFFSET			0x094c
+#define OMAP54XX_PM_L4PER_TIMER9_WKDEP_OFFSET			0x0950
+#define OMAP54XX_RM_L4PER_TIMER9_CONTEXT_OFFSET			0x0954
+#define OMAP54XX_RM_L4PER_ELM_CONTEXT_OFFSET			0x095c
+#define OMAP54XX_PM_L4PER_GPIO2_WKDEP_OFFSET			0x0960
+#define OMAP54XX_RM_L4PER_GPIO2_CONTEXT_OFFSET			0x0964
+#define OMAP54XX_PM_L4PER_GPIO3_WKDEP_OFFSET			0x0968
+#define OMAP54XX_RM_L4PER_GPIO3_CONTEXT_OFFSET			0x096c
+#define OMAP54XX_PM_L4PER_GPIO4_WKDEP_OFFSET			0x0970
+#define OMAP54XX_RM_L4PER_GPIO4_CONTEXT_OFFSET			0x0974
+#define OMAP54XX_PM_L4PER_GPIO5_WKDEP_OFFSET			0x0978
+#define OMAP54XX_RM_L4PER_GPIO5_CONTEXT_OFFSET			0x097c
+#define OMAP54XX_PM_L4PER_GPIO6_WKDEP_OFFSET			0x0980
+#define OMAP54XX_RM_L4PER_GPIO6_CONTEXT_OFFSET			0x0984
+#define OMAP54XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET			0x098c
+#define OMAP54XX_PM_L4PER_I2C1_WKDEP_OFFSET			0x09a0
+#define OMAP54XX_RM_L4PER_I2C1_CONTEXT_OFFSET			0x09a4
+#define OMAP54XX_PM_L4PER_I2C2_WKDEP_OFFSET			0x09a8
+#define OMAP54XX_RM_L4PER_I2C2_CONTEXT_OFFSET			0x09ac
+#define OMAP54XX_PM_L4PER_I2C3_WKDEP_OFFSET			0x09b0
+#define OMAP54XX_RM_L4PER_I2C3_CONTEXT_OFFSET			0x09b4
+#define OMAP54XX_PM_L4PER_I2C4_WKDEP_OFFSET			0x09b8
+#define OMAP54XX_RM_L4PER_I2C4_CONTEXT_OFFSET			0x09bc
+#define OMAP54XX_RM_L4PER_L4_PER_CONTEXT_OFFSET			0x09c0
+#define OMAP54XX_PM_L4PER_MCSPI1_WKDEP_OFFSET			0x09f0
+#define OMAP54XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET			0x09f4
+#define OMAP54XX_PM_L4PER_MCSPI2_WKDEP_OFFSET			0x09f8
+#define OMAP54XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET			0x09fc
+#define OMAP54XX_PM_L4PER_MCSPI3_WKDEP_OFFSET			0x0a00
+#define OMAP54XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET			0x0a04
+#define OMAP54XX_PM_L4PER_MCSPI4_WKDEP_OFFSET			0x0a08
+#define OMAP54XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET			0x0a0c
+#define OMAP54XX_PM_L4PER_GPIO7_WKDEP_OFFSET			0x0a10
+#define OMAP54XX_RM_L4PER_GPIO7_CONTEXT_OFFSET			0x0a14
+#define OMAP54XX_PM_L4PER_GPIO8_WKDEP_OFFSET			0x0a18
+#define OMAP54XX_RM_L4PER_GPIO8_CONTEXT_OFFSET			0x0a1c
+#define OMAP54XX_PM_L4PER_MMC3_WKDEP_OFFSET			0x0a20
+#define OMAP54XX_RM_L4PER_MMC3_CONTEXT_OFFSET			0x0a24
+#define OMAP54XX_PM_L4PER_MMC4_WKDEP_OFFSET			0x0a28
+#define OMAP54XX_RM_L4PER_MMC4_CONTEXT_OFFSET			0x0a2c
+#define OMAP54XX_PM_L4PER_UART1_WKDEP_OFFSET			0x0a40
+#define OMAP54XX_RM_L4PER_UART1_CONTEXT_OFFSET			0x0a44
+#define OMAP54XX_PM_L4PER_UART2_WKDEP_OFFSET			0x0a48
+#define OMAP54XX_RM_L4PER_UART2_CONTEXT_OFFSET			0x0a4c
+#define OMAP54XX_PM_L4PER_UART3_WKDEP_OFFSET			0x0a50
+#define OMAP54XX_RM_L4PER_UART3_CONTEXT_OFFSET			0x0a54
+#define OMAP54XX_RM_L4PER_UART4_CONTEXT_OFFSET			0x0a58
+#define OMAP54XX_PM_L4PER_UART4_WKDEP_OFFSET			0x0a5c
+#define OMAP54XX_PM_L4PER_MMC5_WKDEP_OFFSET			0x0a60
+#define OMAP54XX_RM_L4PER_MMC5_CONTEXT_OFFSET			0x0a64
+#define OMAP54XX_PM_L4PER_I2C5_WKDEP_OFFSET			0x0a68
+#define OMAP54XX_RM_L4PER_I2C5_CONTEXT_OFFSET			0x0a6c
+#define OMAP54XX_PM_L4PER_UART5_WKDEP_OFFSET			0x0a70
+#define OMAP54XX_RM_L4PER_UART5_CONTEXT_OFFSET			0x0a74
+#define OMAP54XX_PM_L4PER_UART6_WKDEP_OFFSET			0x0a78
+#define OMAP54XX_RM_L4PER_UART6_CONTEXT_OFFSET			0x0a7c
+#define OMAP54XX_RM_L4SEC_AES1_CONTEXT_OFFSET			0x0aa4
+#define OMAP54XX_RM_L4SEC_AES2_CONTEXT_OFFSET			0x0aac
+#define OMAP54XX_RM_L4SEC_DES3DES_CONTEXT_OFFSET		0x0ab4
+#define OMAP54XX_RM_L4SEC_FPKA_CONTEXT_OFFSET			0x0abc
+#define OMAP54XX_RM_L4SEC_RNG_CONTEXT_OFFSET			0x0ac4
+#define OMAP54XX_RM_L4SEC_SHA2MD5_CONTEXT_OFFSET		0x0acc
+#define OMAP54XX_RM_L4SEC_DMA_CRYPTO_CONTEXT_OFFSET		0x0adc
+
+/* PRM.IVA_PRM register offsets */
+#define OMAP54XX_PM_IVA_PWRSTCTRL_OFFSET			0x0000
+#define OMAP54XX_PM_IVA_PWRSTST_OFFSET				0x0004
+#define OMAP54XX_RM_IVA_RSTCTRL_OFFSET				0x0010
+#define OMAP54XX_RM_IVA_RSTST_OFFSET				0x0014
+#define OMAP54XX_RM_IVA_IVA_CONTEXT_OFFSET			0x0024
+#define OMAP54XX_RM_IVA_SL2_CONTEXT_OFFSET			0x002c
+
+/* PRM.CAM_PRM register offsets */
+#define OMAP54XX_PM_CAM_PWRSTCTRL_OFFSET			0x0000
+#define OMAP54XX_PM_CAM_PWRSTST_OFFSET				0x0004
+#define OMAP54XX_RM_CAM_ISS_CONTEXT_OFFSET			0x0024
+#define OMAP54XX_RM_CAM_FDIF_CONTEXT_OFFSET			0x002c
+#define OMAP54XX_RM_CAM_CAL_CONTEXT_OFFSET			0x0034
+
+/* PRM.DSS_PRM register offsets */
+#define OMAP54XX_PM_DSS_PWRSTCTRL_OFFSET			0x0000
+#define OMAP54XX_PM_DSS_PWRSTST_OFFSET				0x0004
+#define OMAP54XX_PM_DSS_DSS_WKDEP_OFFSET			0x0020
+#define OMAP54XX_RM_DSS_DSS_CONTEXT_OFFSET			0x0024
+#define OMAP54XX_RM_DSS_BB2D_CONTEXT_OFFSET			0x0034
+
+/* PRM.GPU_PRM register offsets */
+#define OMAP54XX_PM_GPU_PWRSTCTRL_OFFSET			0x0000
+#define OMAP54XX_PM_GPU_PWRSTST_OFFSET				0x0004
+#define OMAP54XX_RM_GPU_GPU_CONTEXT_OFFSET			0x0024
+
+/* PRM.L3INIT_PRM register offsets */
+#define OMAP54XX_PM_L3INIT_PWRSTCTRL_OFFSET			0x0000
+#define OMAP54XX_PM_L3INIT_PWRSTST_OFFSET			0x0004
+#define OMAP54XX_PM_L3INIT_MMC1_WKDEP_OFFSET			0x0028
+#define OMAP54XX_RM_L3INIT_MMC1_CONTEXT_OFFSET			0x002c
+#define OMAP54XX_PM_L3INIT_MMC2_WKDEP_OFFSET			0x0030
+#define OMAP54XX_RM_L3INIT_MMC2_CONTEXT_OFFSET			0x0034
+#define OMAP54XX_PM_L3INIT_HSI_WKDEP_OFFSET			0x0038
+#define OMAP54XX_RM_L3INIT_HSI_CONTEXT_OFFSET			0x003c
+#define OMAP54XX_PM_L3INIT_UNIPRO2_WKDEP_OFFSET			0x0040
+#define OMAP54XX_RM_L3INIT_UNIPRO2_CONTEXT_OFFSET		0x0044
+#define OMAP54XX_PM_L3INIT_USB_HOST_HS_WKDEP_OFFSET		0x0058
+#define OMAP54XX_RM_L3INIT_USB_HOST_HS_CONTEXT_OFFSET		0x005c
+#define OMAP54XX_PM_L3INIT_USB_TLL_HS_WKDEP_OFFSET		0x0068
+#define OMAP54XX_RM_L3INIT_USB_TLL_HS_CONTEXT_OFFSET		0x006c
+#define OMAP54XX_RM_L3INIT_IEEE1500_2_OCP_CONTEXT_OFFSET	0x007c
+#define OMAP54XX_PM_L3INIT_SATA_WKDEP_OFFSET			0x0088
+#define OMAP54XX_RM_L3INIT_SATA_CONTEXT_OFFSET			0x008c
+#define OMAP54XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET		0x00e4
+#define OMAP54XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET		0x00ec
+#define OMAP54XX_PM_L3INIT_USB_OTG_SS_WKDEP_OFFSET		0x00f0
+#define OMAP54XX_RM_L3INIT_USB_OTG_SS_CONTEXT_OFFSET		0x00f4
+
+/* PRM.CUSTEFUSE_PRM register offsets */
+#define OMAP54XX_PM_CUSTEFUSE_PWRSTCTRL_OFFSET			0x0000
+#define OMAP54XX_PM_CUSTEFUSE_PWRSTST_OFFSET			0x0004
+#define OMAP54XX_RM_CUSTEFUSE_EFUSE_CTRL_CUST_CONTEXT_OFFSET	0x0024
+
+/* PRM.WKUPAON_PRM register offsets */
+#define OMAP54XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET		0x0024
+#define OMAP54XX_RM_WKUPAON_WD_TIMER1_CONTEXT_OFFSET		0x002c
+#define OMAP54XX_PM_WKUPAON_WD_TIMER2_WKDEP_OFFSET		0x0030
+#define OMAP54XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET		0x0034
+#define OMAP54XX_PM_WKUPAON_GPIO1_WKDEP_OFFSET			0x0038
+#define OMAP54XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET		0x003c
+#define OMAP54XX_PM_WKUPAON_TIMER1_WKDEP_OFFSET			0x0040
+#define OMAP54XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET		0x0044
+#define OMAP54XX_PM_WKUPAON_TIMER12_WKDEP_OFFSET		0x0048
+#define OMAP54XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET		0x004c
+#define OMAP54XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET		0x0054
+#define OMAP54XX_RM_WKUPAON_SAR_RAM_CONTEXT_OFFSET		0x0064
+#define OMAP54XX_PM_WKUPAON_KBD_WKDEP_OFFSET			0x0078
+#define OMAP54XX_RM_WKUPAON_KBD_CONTEXT_OFFSET			0x007c
+
+/* PRM.WKUPAON_CM register offsets */
+#define OMAP54XX_CM_WKUPAON_CLKSTCTRL_OFFSET			0x0000
+#define OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET		0x0020
+#define OMAP54XX_CM_WKUPAON_WD_TIMER1_CLKCTRL_OFFSET		0x0028
+#define OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET		0x0030
+#define OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET		0x0038
+#define OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET		0x0040
+#define OMAP54XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET		0x0048
+#define OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET		0x0050
+#define OMAP54XX_CM_WKUPAON_SAR_RAM_CLKCTRL_OFFSET		0x0060
+#define OMAP54XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET			0x0078
+#define OMAP54XX_CM_WKUPAON_SCRM_CLKCTRL_OFFSET			0x0090
+#define OMAP54XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL_OFFSET		0x0098
+
+/* PRM.EMU_PRM register offsets */
+#define OMAP54XX_PM_EMU_PWRSTCTRL_OFFSET			0x0000
+#define OMAP54XX_PM_EMU_PWRSTST_OFFSET				0x0004
+#define OMAP54XX_RM_EMU_DEBUGSS_CONTEXT_OFFSET			0x0024
+
+/* PRM.EMU_CM register offsets */
+#define OMAP54XX_CM_EMU_CLKSTCTRL_OFFSET			0x0000
+#define OMAP54XX_CM_EMU_DYNAMICDEP_OFFSET			0x0008
+#define OMAP54XX_CM_EMU_DEBUGSS_CLKCTRL_OFFSET			0x0020
+#define OMAP54XX_CM_EMU_MPU_EMU_DBG_CLKCTRL_OFFSET		0x0028
+
+/* PRM.DEVICE_PRM register offsets */
+#define OMAP54XX_PRM_RSTCTRL_OFFSET				0x0000
+#define OMAP54XX_PRM_RSTST_OFFSET				0x0004
+#define OMAP54XX_PRM_RSTTIME_OFFSET				0x0008
+#define OMAP54XX_PRM_CLKREQCTRL_OFFSET				0x000c
+#define OMAP54XX_PRM_VOLTCTRL_OFFSET				0x0010
+#define OMAP54XX_PRM_PWRREQCTRL_OFFSET				0x0014
+#define OMAP54XX_PRM_PSCON_COUNT_OFFSET				0x0018
+#define OMAP54XX_PRM_IO_COUNT_OFFSET				0x001c
+#define OMAP54XX_PRM_IO_PMCTRL_OFFSET				0x0020
+#define OMAP54XX_PRM_VOLTSETUP_WARMRESET_OFFSET			0x0024
+#define OMAP54XX_PRM_VOLTSETUP_CORE_OFF_OFFSET			0x0028
+#define OMAP54XX_PRM_VOLTSETUP_MPU_OFF_OFFSET			0x002c
+#define OMAP54XX_PRM_VOLTSETUP_MM_OFF_OFFSET			0x0030
+#define OMAP54XX_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET		0x0034
+#define OMAP54XX_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET		0x0038
+#define OMAP54XX_PRM_VOLTSETUP_MM_RET_SLEEP_OFFSET		0x003c
+#define OMAP54XX_PRM_VP_CORE_CONFIG_OFFSET			0x0040
+#define OMAP54XX_PRM_VP_CORE_STATUS_OFFSET			0x0044
+#define OMAP54XX_PRM_VP_CORE_VLIMITTO_OFFSET			0x0048
+#define OMAP54XX_PRM_VP_CORE_VOLTAGE_OFFSET			0x004c
+#define OMAP54XX_PRM_VP_CORE_VSTEPMAX_OFFSET			0x0050
+#define OMAP54XX_PRM_VP_CORE_VSTEPMIN_OFFSET			0x0054
+#define OMAP54XX_PRM_VP_MPU_CONFIG_OFFSET			0x0058
+#define OMAP54XX_PRM_VP_MPU_STATUS_OFFSET			0x005c
+#define OMAP54XX_PRM_VP_MPU_VLIMITTO_OFFSET			0x0060
+#define OMAP54XX_PRM_VP_MPU_VOLTAGE_OFFSET			0x0064
+#define OMAP54XX_PRM_VP_MPU_VSTEPMAX_OFFSET			0x0068
+#define OMAP54XX_PRM_VP_MPU_VSTEPMIN_OFFSET			0x006c
+#define OMAP54XX_PRM_VP_MM_CONFIG_OFFSET			0x0070
+#define OMAP54XX_PRM_VP_MM_STATUS_OFFSET			0x0074
+#define OMAP54XX_PRM_VP_MM_VLIMITTO_OFFSET			0x0078
+#define OMAP54XX_PRM_VP_MM_VOLTAGE_OFFSET			0x007c
+#define OMAP54XX_PRM_VP_MM_VSTEPMAX_OFFSET			0x0080
+#define OMAP54XX_PRM_VP_MM_VSTEPMIN_OFFSET			0x0084
+#define OMAP54XX_PRM_VC_SMPS_CORE_CONFIG_OFFSET			0x0088
+#define OMAP54XX_PRM_VC_SMPS_MM_CONFIG_OFFSET			0x008c
+#define OMAP54XX_PRM_VC_SMPS_MPU_CONFIG_OFFSET			0x0090
+#define OMAP54XX_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET		0x0094
+#define OMAP54XX_PRM_VC_VAL_CMD_VDD_MM_L_OFFSET			0x0098
+#define OMAP54XX_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET		0x009c
+#define OMAP54XX_PRM_VC_VAL_BYPASS_OFFSET			0x00a0
+#define OMAP54XX_PRM_VC_CORE_ERRST_OFFSET			0x00a4
+#define OMAP54XX_PRM_VC_MM_ERRST_OFFSET				0x00a8
+#define OMAP54XX_PRM_VC_MPU_ERRST_OFFSET			0x00ac
+#define OMAP54XX_PRM_VC_BYPASS_ERRST_OFFSET			0x00b0
+#define OMAP54XX_PRM_VC_CFG_I2C_MODE_OFFSET			0x00b4
+#define OMAP54XX_PRM_VC_CFG_I2C_CLK_OFFSET			0x00b8
+#define OMAP54XX_PRM_SRAM_COUNT_OFFSET				0x00bc
+#define OMAP54XX_PRM_SRAM_WKUP_SETUP_OFFSET			0x00c0
+#define OMAP54XX_PRM_SLDO_CORE_SETUP_OFFSET			0x00c4
+#define OMAP54XX_PRM_SLDO_CORE_CTRL_OFFSET			0x00c8
+#define OMAP54XX_PRM_SLDO_MPU_SETUP_OFFSET			0x00cc
+#define OMAP54XX_PRM_SLDO_MPU_CTRL_OFFSET			0x00d0
+#define OMAP54XX_PRM_SLDO_MM_SETUP_OFFSET			0x00d4
+#define OMAP54XX_PRM_SLDO_MM_CTRL_OFFSET			0x00d8
+#define OMAP54XX_PRM_ABBLDO_MPU_SETUP_OFFSET			0x00dc
+#define OMAP54XX_PRM_ABBLDO_MPU_CTRL_OFFSET			0x00e0
+#define OMAP54XX_PRM_ABBLDO_MM_SETUP_OFFSET			0x00e4
+#define OMAP54XX_PRM_ABBLDO_MM_CTRL_OFFSET			0x00e8
+#define OMAP54XX_PRM_BANDGAP_SETUP_OFFSET			0x00ec
+#define OMAP54XX_PRM_DEVICE_OFF_CTRL_OFFSET			0x00f0
+#define OMAP54XX_PRM_PHASE1_CNDP_OFFSET				0x00f4
+#define OMAP54XX_PRM_PHASE2A_CNDP_OFFSET			0x00f8
+#define OMAP54XX_PRM_PHASE2B_CNDP_OFFSET			0x00fc
+#define OMAP54XX_PRM_MODEM_IF_CTRL_OFFSET			0x0100
+#define OMAP54XX_PRM_VOLTST_MPU_OFFSET				0x0110
+#define OMAP54XX_PRM_VOLTST_MM_OFFSET				0x0114
+
+#endif
-- 
1.7.9.5

[PATCH 41/55] ARM: DRA7: PRM: remove direct register declaration macros

[Tero Kristo]

None of these are currently used, so cleanup.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/prm7xx.h |   77 ------------------------------------------
 1 file changed, 77 deletions(-)

diff --git a/arch/arm/mach-omap2/prm7xx.h b/arch/arm/mach-omap2/prm7xx.h
index d92a840..b971af5 100644
--- a/arch/arm/mach-omap2/prm7xx.h
+++ b/arch/arm/mach-omap2/prm7xx.h
@@ -78,7 +78,6 @@
 #define DRA7XX_PRM_IRQSTATUS_DSP1_OFFSET			0x0030
 #define DRA7XX_PRM_IRQENABLE_DSP1_OFFSET			0x0038
 #define DRA7XX_CM_PRM_PROFILING_CLKCTRL_OFFSET			0x0040
-#define DRA7XX_CM_PRM_PROFILING_CLKCTRL				DRA7XX_PRM_REGADDR(DRA7XX_PRM_OCP_SOCKET_INST, 0x0040)
 #define DRA7XX_PRM_IRQENABLE_DSP2_OFFSET			0x0044
 #define DRA7XX_PRM_IRQENABLE_EVE1_OFFSET			0x0048
 #define DRA7XX_PRM_IRQENABLE_EVE2_OFFSET			0x004c
@@ -98,113 +97,59 @@
 
 /* PRM.CKGEN_PRM register offsets */
 #define DRA7XX_CM_CLKSEL_SYSCLK1_OFFSET				0x0000
-#define DRA7XX_CM_CLKSEL_SYSCLK1				DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0000)
 #define DRA7XX_CM_CLKSEL_WKUPAON_OFFSET				0x0008
-#define DRA7XX_CM_CLKSEL_WKUPAON				DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0008)
 #define DRA7XX_CM_CLKSEL_ABE_PLL_REF_OFFSET			0x000c
-#define DRA7XX_CM_CLKSEL_ABE_PLL_REF				DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x000c)
 #define DRA7XX_CM_CLKSEL_SYS_OFFSET				0x0010
-#define DRA7XX_CM_CLKSEL_SYS					DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0010)
 #define DRA7XX_CM_CLKSEL_ABE_PLL_BYPAS_OFFSET			0x0014
-#define DRA7XX_CM_CLKSEL_ABE_PLL_BYPAS				DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0014)
 #define DRA7XX_CM_CLKSEL_ABE_PLL_SYS_OFFSET			0x0018
-#define DRA7XX_CM_CLKSEL_ABE_PLL_SYS				DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0018)
 #define DRA7XX_CM_CLKSEL_ABE_24M_OFFSET				0x001c
-#define DRA7XX_CM_CLKSEL_ABE_24M				DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x001c)
 #define DRA7XX_CM_CLKSEL_ABE_SYS_OFFSET				0x0020
-#define DRA7XX_CM_CLKSEL_ABE_SYS				DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0020)
 #define DRA7XX_CM_CLKSEL_HDMI_MCASP_AUX_OFFSET			0x0024
-#define DRA7XX_CM_CLKSEL_HDMI_MCASP_AUX				DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0024)
 #define DRA7XX_CM_CLKSEL_HDMI_TIMER_OFFSET			0x0028
-#define DRA7XX_CM_CLKSEL_HDMI_TIMER				DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0028)
 #define DRA7XX_CM_CLKSEL_MCASP_SYS_OFFSET			0x002c
-#define DRA7XX_CM_CLKSEL_MCASP_SYS				DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x002c)
 #define DRA7XX_CM_CLKSEL_MLBP_MCASP_OFFSET			0x0030
-#define DRA7XX_CM_CLKSEL_MLBP_MCASP				DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0030)
 #define DRA7XX_CM_CLKSEL_MLB_MCASP_OFFSET			0x0034
-#define DRA7XX_CM_CLKSEL_MLB_MCASP				DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0034)
 #define DRA7XX_CM_CLKSEL_PER_ABE_X1_GFCLK_MCASP_AUX_OFFSET	0x0038
-#define DRA7XX_CM_CLKSEL_PER_ABE_X1_GFCLK_MCASP_AUX		DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0038)
 #define DRA7XX_CM_CLKSEL_SYS_CLK1_32K_OFFSET			0x0040
-#define DRA7XX_CM_CLKSEL_SYS_CLK1_32K				DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0040)
 #define DRA7XX_CM_CLKSEL_TIMER_SYS_OFFSET			0x0044
-#define DRA7XX_CM_CLKSEL_TIMER_SYS				DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0044)
 #define DRA7XX_CM_CLKSEL_VIDEO1_MCASP_AUX_OFFSET		0x0048
-#define DRA7XX_CM_CLKSEL_VIDEO1_MCASP_AUX			DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0048)
 #define DRA7XX_CM_CLKSEL_VIDEO1_TIMER_OFFSET			0x004c
-#define DRA7XX_CM_CLKSEL_VIDEO1_TIMER				DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x004c)
 #define DRA7XX_CM_CLKSEL_VIDEO2_MCASP_AUX_OFFSET		0x0050
-#define DRA7XX_CM_CLKSEL_VIDEO2_MCASP_AUX			DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0050)
 #define DRA7XX_CM_CLKSEL_VIDEO2_TIMER_OFFSET			0x0054
-#define DRA7XX_CM_CLKSEL_VIDEO2_TIMER				DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0054)
 #define DRA7XX_CM_CLKSEL_CLKOUTMUX0_OFFSET			0x0058
-#define DRA7XX_CM_CLKSEL_CLKOUTMUX0				DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0058)
 #define DRA7XX_CM_CLKSEL_CLKOUTMUX1_OFFSET			0x005c
-#define DRA7XX_CM_CLKSEL_CLKOUTMUX1				DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x005c)
 #define DRA7XX_CM_CLKSEL_CLKOUTMUX2_OFFSET			0x0060
-#define DRA7XX_CM_CLKSEL_CLKOUTMUX2				DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0060)
 #define DRA7XX_CM_CLKSEL_HDMI_PLL_SYS_OFFSET			0x0064
-#define DRA7XX_CM_CLKSEL_HDMI_PLL_SYS				DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0064)
 #define DRA7XX_CM_CLKSEL_VIDEO1_PLL_SYS_OFFSET			0x0068
-#define DRA7XX_CM_CLKSEL_VIDEO1_PLL_SYS				DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0068)
 #define DRA7XX_CM_CLKSEL_VIDEO2_PLL_SYS_OFFSET			0x006c
-#define DRA7XX_CM_CLKSEL_VIDEO2_PLL_SYS				DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x006c)
 #define DRA7XX_CM_CLKSEL_ABE_CLK_DIV_OFFSET			0x0070
-#define DRA7XX_CM_CLKSEL_ABE_CLK_DIV				DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0070)
 #define DRA7XX_CM_CLKSEL_ABE_GICLK_DIV_OFFSET			0x0074
-#define DRA7XX_CM_CLKSEL_ABE_GICLK_DIV				DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0074)
 #define DRA7XX_CM_CLKSEL_AESS_FCLK_DIV_OFFSET			0x0078
-#define DRA7XX_CM_CLKSEL_AESS_FCLK_DIV				DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0078)
 #define DRA7XX_CM_CLKSEL_EVE_CLK_OFFSET				0x0080
-#define DRA7XX_CM_CLKSEL_EVE_CLK				DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0080)
 #define DRA7XX_CM_CLKSEL_USB_OTG_CLK_CLKOUTMUX_OFFSET		0x0084
-#define DRA7XX_CM_CLKSEL_USB_OTG_CLK_CLKOUTMUX			DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0084)
 #define DRA7XX_CM_CLKSEL_CORE_DPLL_OUT_CLK_CLKOUTMUX_OFFSET	0x0088
-#define DRA7XX_CM_CLKSEL_CORE_DPLL_OUT_CLK_CLKOUTMUX		DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0088)
 #define DRA7XX_CM_CLKSEL_DSP_GFCLK_CLKOUTMUX_OFFSET		0x008c
-#define DRA7XX_CM_CLKSEL_DSP_GFCLK_CLKOUTMUX			DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x008c)
 #define DRA7XX_CM_CLKSEL_EMIF_PHY_GCLK_CLKOUTMUX_OFFSET		0x0090
-#define DRA7XX_CM_CLKSEL_EMIF_PHY_GCLK_CLKOUTMUX		DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0090)
 #define DRA7XX_CM_CLKSEL_EMU_CLK_CLKOUTMUX_OFFSET		0x0094
-#define DRA7XX_CM_CLKSEL_EMU_CLK_CLKOUTMUX			DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0094)
 #define DRA7XX_CM_CLKSEL_FUNC_96M_AON_CLK_CLKOUTMUX_OFFSET	0x0098
-#define DRA7XX_CM_CLKSEL_FUNC_96M_AON_CLK_CLKOUTMUX		DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0098)
 #define DRA7XX_CM_CLKSEL_GMAC_250M_CLK_CLKOUTMUX_OFFSET		0x009c
-#define DRA7XX_CM_CLKSEL_GMAC_250M_CLK_CLKOUTMUX		DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x009c)
 #define DRA7XX_CM_CLKSEL_GPU_GCLK_CLKOUTMUX_OFFSET		0x00a0
-#define DRA7XX_CM_CLKSEL_GPU_GCLK_CLKOUTMUX			DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00a0)
 #define DRA7XX_CM_CLKSEL_HDMI_CLK_CLKOUTMUX_OFFSET		0x00a4
-#define DRA7XX_CM_CLKSEL_HDMI_CLK_CLKOUTMUX			DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00a4)
 #define DRA7XX_CM_CLKSEL_IVA_GCLK_CLKOUTMUX_OFFSET		0x00a8
-#define DRA7XX_CM_CLKSEL_IVA_GCLK_CLKOUTMUX			DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00a8)
 #define DRA7XX_CM_CLKSEL_L3INIT_480M_GFCLK_CLKOUTMUX_OFFSET	0x00ac
-#define DRA7XX_CM_CLKSEL_L3INIT_480M_GFCLK_CLKOUTMUX		DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00ac)
 #define DRA7XX_CM_CLKSEL_MPU_GCLK_CLKOUTMUX_OFFSET		0x00b0
-#define DRA7XX_CM_CLKSEL_MPU_GCLK_CLKOUTMUX			DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00b0)
 #define DRA7XX_CM_CLKSEL_PCIE1_CLK_CLKOUTMUX_OFFSET		0x00b4
-#define DRA7XX_CM_CLKSEL_PCIE1_CLK_CLKOUTMUX			DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00b4)
 #define DRA7XX_CM_CLKSEL_PCIE2_CLK_CLKOUTMUX_OFFSET		0x00b8
-#define DRA7XX_CM_CLKSEL_PCIE2_CLK_CLKOUTMUX			DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00b8)
 #define DRA7XX_CM_CLKSEL_PER_ABE_X1_CLK_CLKOUTMUX_OFFSET	0x00bc
-#define DRA7XX_CM_CLKSEL_PER_ABE_X1_CLK_CLKOUTMUX		DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00bc)
 #define DRA7XX_CM_CLKSEL_SATA_CLK_CLKOUTMUX_OFFSET		0x00c0
-#define DRA7XX_CM_CLKSEL_SATA_CLK_CLKOUTMUX			DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00c0)
 #define DRA7XX_CM_CLKSEL_SECURE_32K_CLK_CLKOUTMUX_OFFSET	0x00c4
-#define DRA7XX_CM_CLKSEL_SECURE_32K_CLK_CLKOUTMUX		DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00c4)
 #define DRA7XX_CM_CLKSEL_SYS_CLK1_CLKOUTMUX_OFFSET		0x00c8
-#define DRA7XX_CM_CLKSEL_SYS_CLK1_CLKOUTMUX			DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00c8)
 #define DRA7XX_CM_CLKSEL_SYS_CLK2_CLKOUTMUX_OFFSET		0x00cc
-#define DRA7XX_CM_CLKSEL_SYS_CLK2_CLKOUTMUX			DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00cc)
 #define DRA7XX_CM_CLKSEL_VIDEO1_CLK_CLKOUTMUX_OFFSET		0x00d0
-#define DRA7XX_CM_CLKSEL_VIDEO1_CLK_CLKOUTMUX			DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00d0)
 #define DRA7XX_CM_CLKSEL_VIDEO2_CLK_CLKOUTMUX_OFFSET		0x00d4
-#define DRA7XX_CM_CLKSEL_VIDEO2_CLK_CLKOUTMUX			DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00d4)
 #define DRA7XX_CM_CLKSEL_ABE_LP_CLK_OFFSET			0x00d8
-#define DRA7XX_CM_CLKSEL_ABE_LP_CLK				DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00d8)
 #define DRA7XX_CM_CLKSEL_ADC_GFCLK_OFFSET			0x00dc
-#define DRA7XX_CM_CLKSEL_ADC_GFCLK				DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00dc)
 #define DRA7XX_CM_CLKSEL_EVE_GFCLK_CLKOUTMUX_OFFSET		0x00e0
-#define DRA7XX_CM_CLKSEL_EVE_GFCLK_CLKOUTMUX			DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00e0)
 
 /* PRM.MPU_PRM register offsets */
 #define DRA7XX_PM_MPU_PWRSTCTRL_OFFSET				0x0000
@@ -527,45 +472,25 @@
 /* PRM.WKUPAON_CM register offsets */
 #define DRA7XX_CM_WKUPAON_CLKSTCTRL_OFFSET			0x0000
 #define DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET		0x0020
-#define DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL			DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0020)
 #define DRA7XX_CM_WKUPAON_WD_TIMER1_CLKCTRL_OFFSET		0x0028
-#define DRA7XX_CM_WKUPAON_WD_TIMER1_CLKCTRL			DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0028)
 #define DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET		0x0030
-#define DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL			DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0030)
 #define DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET			0x0038
-#define DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL				DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0038)
 #define DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET			0x0040
-#define DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL			DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0040)
 #define DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET		0x0048
-#define DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL			DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0048)
 #define DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET		0x0050
-#define DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL			DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0050)
 #define DRA7XX_CM_WKUPAON_SAR_RAM_CLKCTRL_OFFSET		0x0060
-#define DRA7XX_CM_WKUPAON_SAR_RAM_CLKCTRL			DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0060)
 #define DRA7XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET			0x0078
-#define DRA7XX_CM_WKUPAON_KBD_CLKCTRL				DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0078)
 #define DRA7XX_CM_WKUPAON_UART10_CLKCTRL_OFFSET			0x0080
-#define DRA7XX_CM_WKUPAON_UART10_CLKCTRL			DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0080)
 #define DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET			0x0088
-#define DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL				DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0088)
 #define DRA7XX_CM_WKUPAON_SCRM_CLKCTRL_OFFSET			0x0090
-#define DRA7XX_CM_WKUPAON_SCRM_CLKCTRL				DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0090)
 #define DRA7XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL_OFFSET		0x0098
-#define DRA7XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL			DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0098)
 #define DRA7XX_CM_WKUPAON_ADC_CLKCTRL_OFFSET			0x00a0
-#define DRA7XX_CM_WKUPAON_ADC_CLKCTRL				DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00a0)
 #define DRA7XX_CM_WKUPAON_SPARE_SAFETY1_CLKCTRL_OFFSET		0x00b0
-#define DRA7XX_CM_WKUPAON_SPARE_SAFETY1_CLKCTRL			DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00b0)
 #define DRA7XX_CM_WKUPAON_SPARE_SAFETY2_CLKCTRL_OFFSET		0x00b8
-#define DRA7XX_CM_WKUPAON_SPARE_SAFETY2_CLKCTRL			DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00b8)
 #define DRA7XX_CM_WKUPAON_SPARE_SAFETY3_CLKCTRL_OFFSET		0x00c0
-#define DRA7XX_CM_WKUPAON_SPARE_SAFETY3_CLKCTRL			DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00c0)
 #define DRA7XX_CM_WKUPAON_SPARE_SAFETY4_CLKCTRL_OFFSET		0x00c8
-#define DRA7XX_CM_WKUPAON_SPARE_SAFETY4_CLKCTRL			DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00c8)
 #define DRA7XX_CM_WKUPAON_SPARE_UNKNOWN2_CLKCTRL_OFFSET		0x00d0
-#define DRA7XX_CM_WKUPAON_SPARE_UNKNOWN2_CLKCTRL		DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00d0)
 #define DRA7XX_CM_WKUPAON_SPARE_UNKNOWN3_CLKCTRL_OFFSET		0x00d8
-#define DRA7XX_CM_WKUPAON_SPARE_UNKNOWN3_CLKCTRL		DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00d8)
 
 /* PRM.EMU_PRM register offsets */
 #define DRA7XX_PM_EMU_PWRSTCTRL_OFFSET				0x0000
@@ -575,10 +500,8 @@
 /* PRM.EMU_CM register offsets */
 #define DRA7XX_CM_EMU_CLKSTCTRL_OFFSET				0x0000
 #define DRA7XX_CM_EMU_DEBUGSS_CLKCTRL_OFFSET			0x0004
-#define DRA7XX_CM_EMU_DEBUGSS_CLKCTRL				DRA7XX_PRM_REGADDR(DRA7XX_PRM_EMU_CM_INST, 0x0004)
 #define DRA7XX_CM_EMU_DYNAMICDEP_OFFSET				0x0008
 #define DRA7XX_CM_EMU_MPU_EMU_DBG_CLKCTRL_OFFSET		0x000c
-#define DRA7XX_CM_EMU_MPU_EMU_DBG_CLKCTRL			DRA7XX_PRM_REGADDR(DRA7XX_PRM_EMU_CM_INST, 0x000c)
 
 /* PRM.DSP2_PRM register offsets */
 #define DRA7XX_PM_DSP2_PWRSTCTRL_OFFSET				0x0000
-- 
1.7.9.5

[PATCH 42/55] ARM: DRA7: PRM: move parts of prm7xx.h header file to public location

[Tero Kristo]

Parts of this file are needed by both the driver and mach-omap2 board
code.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/prm44xx.c     |    5 +-
 arch/arm/mach-omap2/prm7xx.h      |  568 +----------------------------------
 arch/arm/mach-omap2/prminst44xx.c |    2 +-
 include/linux/power/omap/prm7xx.h |  591 +++++++++++++++++++++++++++++++++++++
 4 files changed, 597 insertions(+), 569 deletions(-)
 create mode 100644 include/linux/power/omap/prm7xx.h

diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index 97b7ab2..a80e8b5 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -22,10 +22,13 @@
 #include "vp.h"
 #include <linux/power/omap/prm44xx.h>
 #include <linux/power/omap/prm54xx.h>
-#include "prm7xx.h"
+#include <linux/power/omap/prm7xx.h>
 #include "prcm44xx.h"
 #include "prminst44xx_private.h"
 #include "powerdomain.h"
+#include "prm.h"
+#include "prcm-common.h"
+#include "prm44xx_54xx.h"
 
 #define OMAP4430_GLOBAL_COLD_RST_SHIFT			0
 #define OMAP4430_GLOBAL_WARM_SW_RST_SHIFT		1
diff --git a/arch/arm/mach-omap2/prm7xx.h b/arch/arm/mach-omap2/prm7xx.h
index b971af5..c6dc341 100644
--- a/arch/arm/mach-omap2/prm7xx.h
+++ b/arch/arm/mach-omap2/prm7xx.h
@@ -25,577 +25,11 @@
 #include "prm44xx_54xx.h"
 #include "prcm-common.h"
 #include "prm.h"
+#include <linux/power/omap/prm7xx.h>
 
 #define DRA7XX_PRM_BASE		0x4ae06000
 
 #define DRA7XX_PRM_REGADDR(inst, reg)				\
 	OMAP2_L4_IO_ADDRESS(DRA7XX_PRM_BASE + (inst) + (reg))
 
-
-/* PRM instances */
-#define DRA7XX_PRM_OCP_SOCKET_INST	0x0000
-#define DRA7XX_PRM_CKGEN_INST		0x0100
-#define DRA7XX_PRM_MPU_INST		0x0300
-#define DRA7XX_PRM_DSP1_INST		0x0400
-#define DRA7XX_PRM_IPU_INST		0x0500
-#define DRA7XX_PRM_COREAON_INST		0x0628
-#define DRA7XX_PRM_CORE_INST		0x0700
-#define DRA7XX_PRM_IVA_INST		0x0f00
-#define DRA7XX_PRM_CAM_INST		0x1000
-#define DRA7XX_PRM_DSS_INST		0x1100
-#define DRA7XX_PRM_GPU_INST		0x1200
-#define DRA7XX_PRM_L3INIT_INST		0x1300
-#define DRA7XX_PRM_L4PER_INST		0x1400
-#define DRA7XX_PRM_CUSTEFUSE_INST	0x1600
-#define DRA7XX_PRM_WKUPAON_INST		0x1724
-#define DRA7XX_PRM_WKUPAON_CM_INST	0x1800
-#define DRA7XX_PRM_EMU_INST		0x1900
-#define DRA7XX_PRM_EMU_CM_INST		0x1a00
-#define DRA7XX_PRM_DSP2_INST		0x1b00
-#define DRA7XX_PRM_EVE1_INST		0x1b40
-#define DRA7XX_PRM_EVE2_INST		0x1b80
-#define DRA7XX_PRM_EVE3_INST		0x1bc0
-#define DRA7XX_PRM_EVE4_INST		0x1c00
-#define DRA7XX_PRM_RTC_INST		0x1c60
-#define DRA7XX_PRM_VPE_INST		0x1c80
-#define DRA7XX_PRM_DEVICE_INST		0x1d00
-#define DRA7XX_PRM_INSTR_INST		0x1f00
-
-/* PRM clockdomain register offsets (from instance start) */
-#define DRA7XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS	0x0000
-#define DRA7XX_PRM_EMU_CM_EMU_CDOFFS		0x0000
-
-/* PRM */
-
-/* PRM.OCP_SOCKET_PRM register offsets */
-#define DRA7XX_REVISION_PRM_OFFSET				0x0000
-#define DRA7XX_PRM_IRQSTATUS_MPU_OFFSET				0x0010
-#define DRA7XX_PRM_IRQSTATUS_MPU_2_OFFSET			0x0014
-#define DRA7XX_PRM_IRQENABLE_MPU_OFFSET				0x0018
-#define DRA7XX_PRM_IRQENABLE_MPU_2_OFFSET			0x001c
-#define DRA7XX_PRM_IRQSTATUS_IPU2_OFFSET			0x0020
-#define DRA7XX_PRM_IRQENABLE_IPU2_OFFSET			0x0028
-#define DRA7XX_PRM_IRQSTATUS_DSP1_OFFSET			0x0030
-#define DRA7XX_PRM_IRQENABLE_DSP1_OFFSET			0x0038
-#define DRA7XX_CM_PRM_PROFILING_CLKCTRL_OFFSET			0x0040
-#define DRA7XX_PRM_IRQENABLE_DSP2_OFFSET			0x0044
-#define DRA7XX_PRM_IRQENABLE_EVE1_OFFSET			0x0048
-#define DRA7XX_PRM_IRQENABLE_EVE2_OFFSET			0x004c
-#define DRA7XX_PRM_IRQENABLE_EVE3_OFFSET			0x0050
-#define DRA7XX_PRM_IRQENABLE_EVE4_OFFSET			0x0054
-#define DRA7XX_PRM_IRQENABLE_IPU1_OFFSET			0x0058
-#define DRA7XX_PRM_IRQSTATUS_DSP2_OFFSET			0x005c
-#define DRA7XX_PRM_IRQSTATUS_EVE1_OFFSET			0x0060
-#define DRA7XX_PRM_IRQSTATUS_EVE2_OFFSET			0x0064
-#define DRA7XX_PRM_IRQSTATUS_EVE3_OFFSET			0x0068
-#define DRA7XX_PRM_IRQSTATUS_EVE4_OFFSET			0x006c
-#define DRA7XX_PRM_IRQSTATUS_IPU1_OFFSET			0x0070
-#define DRA7XX_PRM_DEBUG_CFG1_OFFSET				0x00e4
-#define DRA7XX_PRM_DEBUG_CFG2_OFFSET				0x00e8
-#define DRA7XX_PRM_DEBUG_CFG3_OFFSET				0x00ec
-#define DRA7XX_PRM_DEBUG_OUT_OFFSET				0x00f4
-
-/* PRM.CKGEN_PRM register offsets */
-#define DRA7XX_CM_CLKSEL_SYSCLK1_OFFSET				0x0000
-#define DRA7XX_CM_CLKSEL_WKUPAON_OFFSET				0x0008
-#define DRA7XX_CM_CLKSEL_ABE_PLL_REF_OFFSET			0x000c
-#define DRA7XX_CM_CLKSEL_SYS_OFFSET				0x0010
-#define DRA7XX_CM_CLKSEL_ABE_PLL_BYPAS_OFFSET			0x0014
-#define DRA7XX_CM_CLKSEL_ABE_PLL_SYS_OFFSET			0x0018
-#define DRA7XX_CM_CLKSEL_ABE_24M_OFFSET				0x001c
-#define DRA7XX_CM_CLKSEL_ABE_SYS_OFFSET				0x0020
-#define DRA7XX_CM_CLKSEL_HDMI_MCASP_AUX_OFFSET			0x0024
-#define DRA7XX_CM_CLKSEL_HDMI_TIMER_OFFSET			0x0028
-#define DRA7XX_CM_CLKSEL_MCASP_SYS_OFFSET			0x002c
-#define DRA7XX_CM_CLKSEL_MLBP_MCASP_OFFSET			0x0030
-#define DRA7XX_CM_CLKSEL_MLB_MCASP_OFFSET			0x0034
-#define DRA7XX_CM_CLKSEL_PER_ABE_X1_GFCLK_MCASP_AUX_OFFSET	0x0038
-#define DRA7XX_CM_CLKSEL_SYS_CLK1_32K_OFFSET			0x0040
-#define DRA7XX_CM_CLKSEL_TIMER_SYS_OFFSET			0x0044
-#define DRA7XX_CM_CLKSEL_VIDEO1_MCASP_AUX_OFFSET		0x0048
-#define DRA7XX_CM_CLKSEL_VIDEO1_TIMER_OFFSET			0x004c
-#define DRA7XX_CM_CLKSEL_VIDEO2_MCASP_AUX_OFFSET		0x0050
-#define DRA7XX_CM_CLKSEL_VIDEO2_TIMER_OFFSET			0x0054
-#define DRA7XX_CM_CLKSEL_CLKOUTMUX0_OFFSET			0x0058
-#define DRA7XX_CM_CLKSEL_CLKOUTMUX1_OFFSET			0x005c
-#define DRA7XX_CM_CLKSEL_CLKOUTMUX2_OFFSET			0x0060
-#define DRA7XX_CM_CLKSEL_HDMI_PLL_SYS_OFFSET			0x0064
-#define DRA7XX_CM_CLKSEL_VIDEO1_PLL_SYS_OFFSET			0x0068
-#define DRA7XX_CM_CLKSEL_VIDEO2_PLL_SYS_OFFSET			0x006c
-#define DRA7XX_CM_CLKSEL_ABE_CLK_DIV_OFFSET			0x0070
-#define DRA7XX_CM_CLKSEL_ABE_GICLK_DIV_OFFSET			0x0074
-#define DRA7XX_CM_CLKSEL_AESS_FCLK_DIV_OFFSET			0x0078
-#define DRA7XX_CM_CLKSEL_EVE_CLK_OFFSET				0x0080
-#define DRA7XX_CM_CLKSEL_USB_OTG_CLK_CLKOUTMUX_OFFSET		0x0084
-#define DRA7XX_CM_CLKSEL_CORE_DPLL_OUT_CLK_CLKOUTMUX_OFFSET	0x0088
-#define DRA7XX_CM_CLKSEL_DSP_GFCLK_CLKOUTMUX_OFFSET		0x008c
-#define DRA7XX_CM_CLKSEL_EMIF_PHY_GCLK_CLKOUTMUX_OFFSET		0x0090
-#define DRA7XX_CM_CLKSEL_EMU_CLK_CLKOUTMUX_OFFSET		0x0094
-#define DRA7XX_CM_CLKSEL_FUNC_96M_AON_CLK_CLKOUTMUX_OFFSET	0x0098
-#define DRA7XX_CM_CLKSEL_GMAC_250M_CLK_CLKOUTMUX_OFFSET		0x009c
-#define DRA7XX_CM_CLKSEL_GPU_GCLK_CLKOUTMUX_OFFSET		0x00a0
-#define DRA7XX_CM_CLKSEL_HDMI_CLK_CLKOUTMUX_OFFSET		0x00a4
-#define DRA7XX_CM_CLKSEL_IVA_GCLK_CLKOUTMUX_OFFSET		0x00a8
-#define DRA7XX_CM_CLKSEL_L3INIT_480M_GFCLK_CLKOUTMUX_OFFSET	0x00ac
-#define DRA7XX_CM_CLKSEL_MPU_GCLK_CLKOUTMUX_OFFSET		0x00b0
-#define DRA7XX_CM_CLKSEL_PCIE1_CLK_CLKOUTMUX_OFFSET		0x00b4
-#define DRA7XX_CM_CLKSEL_PCIE2_CLK_CLKOUTMUX_OFFSET		0x00b8
-#define DRA7XX_CM_CLKSEL_PER_ABE_X1_CLK_CLKOUTMUX_OFFSET	0x00bc
-#define DRA7XX_CM_CLKSEL_SATA_CLK_CLKOUTMUX_OFFSET		0x00c0
-#define DRA7XX_CM_CLKSEL_SECURE_32K_CLK_CLKOUTMUX_OFFSET	0x00c4
-#define DRA7XX_CM_CLKSEL_SYS_CLK1_CLKOUTMUX_OFFSET		0x00c8
-#define DRA7XX_CM_CLKSEL_SYS_CLK2_CLKOUTMUX_OFFSET		0x00cc
-#define DRA7XX_CM_CLKSEL_VIDEO1_CLK_CLKOUTMUX_OFFSET		0x00d0
-#define DRA7XX_CM_CLKSEL_VIDEO2_CLK_CLKOUTMUX_OFFSET		0x00d4
-#define DRA7XX_CM_CLKSEL_ABE_LP_CLK_OFFSET			0x00d8
-#define DRA7XX_CM_CLKSEL_ADC_GFCLK_OFFSET			0x00dc
-#define DRA7XX_CM_CLKSEL_EVE_GFCLK_CLKOUTMUX_OFFSET		0x00e0
-
-/* PRM.MPU_PRM register offsets */
-#define DRA7XX_PM_MPU_PWRSTCTRL_OFFSET				0x0000
-#define DRA7XX_PM_MPU_PWRSTST_OFFSET				0x0004
-#define DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET			0x0024
-
-/* PRM.DSP1_PRM register offsets */
-#define DRA7XX_PM_DSP1_PWRSTCTRL_OFFSET				0x0000
-#define DRA7XX_PM_DSP1_PWRSTST_OFFSET				0x0004
-#define DRA7XX_RM_DSP1_RSTCTRL_OFFSET				0x0010
-#define DRA7XX_RM_DSP1_RSTST_OFFSET				0x0014
-#define DRA7XX_RM_DSP1_DSP1_CONTEXT_OFFSET			0x0024
-
-/* PRM.IPU_PRM register offsets */
-#define DRA7XX_PM_IPU_PWRSTCTRL_OFFSET				0x0000
-#define DRA7XX_PM_IPU_PWRSTST_OFFSET				0x0004
-#define DRA7XX_RM_IPU1_RSTCTRL_OFFSET				0x0010
-#define DRA7XX_RM_IPU1_RSTST_OFFSET				0x0014
-#define DRA7XX_RM_IPU1_IPU1_CONTEXT_OFFSET			0x0024
-#define DRA7XX_PM_IPU_MCASP1_WKDEP_OFFSET			0x0050
-#define DRA7XX_RM_IPU_MCASP1_CONTEXT_OFFSET			0x0054
-#define DRA7XX_PM_IPU_TIMER5_WKDEP_OFFSET			0x0058
-#define DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET			0x005c
-#define DRA7XX_PM_IPU_TIMER6_WKDEP_OFFSET			0x0060
-#define DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET			0x0064
-#define DRA7XX_PM_IPU_TIMER7_WKDEP_OFFSET			0x0068
-#define DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET			0x006c
-#define DRA7XX_PM_IPU_TIMER8_WKDEP_OFFSET			0x0070
-#define DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET			0x0074
-#define DRA7XX_PM_IPU_I2C5_WKDEP_OFFSET				0x0078
-#define DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET			0x007c
-#define DRA7XX_PM_IPU_UART6_WKDEP_OFFSET			0x0080
-#define DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET			0x0084
-
-/* PRM.COREAON_PRM register offsets */
-#define DRA7XX_PM_COREAON_SMARTREFLEX_MPU_WKDEP_OFFSET		0x0000
-#define DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET	0x0004
-#define DRA7XX_PM_COREAON_SMARTREFLEX_CORE_WKDEP_OFFSET		0x0010
-#define DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET	0x0014
-#define DRA7XX_PM_COREAON_SMARTREFLEX_GPU_WKDEP_OFFSET		0x0030
-#define DRA7XX_RM_COREAON_SMARTREFLEX_GPU_CONTEXT_OFFSET	0x0034
-#define DRA7XX_PM_COREAON_SMARTREFLEX_DSPEVE_WKDEP_OFFSET	0x0040
-#define DRA7XX_RM_COREAON_SMARTREFLEX_DSPEVE_CONTEXT_OFFSET	0x0044
-#define DRA7XX_PM_COREAON_SMARTREFLEX_IVAHD_WKDEP_OFFSET	0x0050
-#define DRA7XX_RM_COREAON_SMARTREFLEX_IVAHD_CONTEXT_OFFSET	0x0054
-#define DRA7XX_RM_COREAON_DUMMY_MODULE1_CONTEXT_OFFSET		0x0084
-#define DRA7XX_RM_COREAON_DUMMY_MODULE2_CONTEXT_OFFSET		0x0094
-#define DRA7XX_RM_COREAON_DUMMY_MODULE3_CONTEXT_OFFSET		0x00a4
-#define DRA7XX_RM_COREAON_DUMMY_MODULE4_CONTEXT_OFFSET		0x00b4
-
-/* PRM.CORE_PRM register offsets */
-#define DRA7XX_PM_CORE_PWRSTCTRL_OFFSET				0x0000
-#define DRA7XX_PM_CORE_PWRSTST_OFFSET				0x0004
-#define DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET		0x0024
-#define DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET			0x002c
-#define DRA7XX_RM_L3MAIN1_MMU_EDMA_CONTEXT_OFFSET		0x0034
-#define DRA7XX_PM_L3MAIN1_OCMC_RAM1_WKDEP_OFFSET		0x0050
-#define DRA7XX_RM_L3MAIN1_OCMC_RAM1_CONTEXT_OFFSET		0x0054
-#define DRA7XX_PM_L3MAIN1_OCMC_RAM2_WKDEP_OFFSET		0x0058
-#define DRA7XX_RM_L3MAIN1_OCMC_RAM2_CONTEXT_OFFSET		0x005c
-#define DRA7XX_PM_L3MAIN1_OCMC_RAM3_WKDEP_OFFSET		0x0060
-#define DRA7XX_RM_L3MAIN1_OCMC_RAM3_CONTEXT_OFFSET		0x0064
-#define DRA7XX_RM_L3MAIN1_OCMC_ROM_CONTEXT_OFFSET		0x006c
-#define DRA7XX_PM_L3MAIN1_TPCC_WKDEP_OFFSET			0x0070
-#define DRA7XX_RM_L3MAIN1_TPCC_CONTEXT_OFFSET			0x0074
-#define DRA7XX_PM_L3MAIN1_TPTC1_WKDEP_OFFSET			0x0078
-#define DRA7XX_RM_L3MAIN1_TPTC1_CONTEXT_OFFSET			0x007c
-#define DRA7XX_PM_L3MAIN1_TPTC2_WKDEP_OFFSET			0x0080
-#define DRA7XX_RM_L3MAIN1_TPTC2_CONTEXT_OFFSET			0x0084
-#define DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET			0x008c
-#define DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET			0x0094
-#define DRA7XX_RM_L3MAIN1_SPARE_CME_CONTEXT_OFFSET		0x009c
-#define DRA7XX_RM_L3MAIN1_SPARE_HDMI_CONTEXT_OFFSET		0x00a4
-#define DRA7XX_RM_L3MAIN1_SPARE_ICM_CONTEXT_OFFSET		0x00ac
-#define DRA7XX_RM_L3MAIN1_SPARE_IVA2_CONTEXT_OFFSET		0x00b4
-#define DRA7XX_RM_L3MAIN1_SPARE_SATA2_CONTEXT_OFFSET		0x00bc
-#define DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN4_CONTEXT_OFFSET		0x00c4
-#define DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN5_CONTEXT_OFFSET		0x00cc
-#define DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN6_CONTEXT_OFFSET		0x00d4
-#define DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL1_CONTEXT_OFFSET	0x00dc
-#define DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL2_CONTEXT_OFFSET	0x00f4
-#define DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL3_CONTEXT_OFFSET	0x00fc
-#define DRA7XX_RM_IPU2_RSTCTRL_OFFSET				0x0210
-#define DRA7XX_RM_IPU2_RSTST_OFFSET				0x0214
-#define DRA7XX_RM_IPU2_IPU2_CONTEXT_OFFSET			0x0224
-#define DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET			0x0324
-#define DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET			0x0424
-#define DRA7XX_RM_EMIF_EMIF_OCP_FW_CONTEXT_OFFSET		0x042c
-#define DRA7XX_RM_EMIF_EMIF1_CONTEXT_OFFSET			0x0434
-#define DRA7XX_RM_EMIF_EMIF2_CONTEXT_OFFSET			0x043c
-#define DRA7XX_RM_EMIF_EMIF_DLL_CONTEXT_OFFSET			0x0444
-#define DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET			0x0524
-#define DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET			0x0624
-#define DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET			0x062c
-#define DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET			0x0634
-#define DRA7XX_RM_L4CFG_SAR_ROM_CONTEXT_OFFSET			0x063c
-#define DRA7XX_RM_L4CFG_OCP2SCP2_CONTEXT_OFFSET			0x0644
-#define DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET			0x064c
-#define DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET			0x0654
-#define DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET			0x065c
-#define DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET			0x0664
-#define DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET			0x066c
-#define DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET			0x0674
-#define DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET			0x067c
-#define DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET			0x0684
-#define DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET		0x068c
-#define DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET		0x0694
-#define DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET		0x069c
-#define DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET		0x06a4
-#define DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_RTC_CONTEXT_OFFSET	0x06ac
-#define DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CONTEXT_OFFSET	0x06b4
-#define DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_WKUP_CONTEXT_OFFSET	0x06bc
-#define DRA7XX_RM_L4CFG_IO_DELAY_BLOCK_CONTEXT_OFFSET		0x06c4
-#define DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET		0x0724
-#define DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET		0x072c
-#define DRA7XX_RM_L3INSTR_OCP_WP_NOC_CONTEXT_OFFSET		0x0744
-
-/* PRM.IVA_PRM register offsets */
-#define DRA7XX_PM_IVA_PWRSTCTRL_OFFSET				0x0000
-#define DRA7XX_PM_IVA_PWRSTST_OFFSET				0x0004
-#define DRA7XX_RM_IVA_RSTCTRL_OFFSET				0x0010
-#define DRA7XX_RM_IVA_RSTST_OFFSET				0x0014
-#define DRA7XX_RM_IVA_IVA_CONTEXT_OFFSET			0x0024
-#define DRA7XX_RM_IVA_SL2_CONTEXT_OFFSET			0x002c
-
-/* PRM.CAM_PRM register offsets */
-#define DRA7XX_PM_CAM_PWRSTCTRL_OFFSET				0x0000
-#define DRA7XX_PM_CAM_PWRSTST_OFFSET				0x0004
-#define DRA7XX_PM_CAM_VIP1_WKDEP_OFFSET				0x0020
-#define DRA7XX_RM_CAM_VIP1_CONTEXT_OFFSET			0x0024
-#define DRA7XX_PM_CAM_VIP2_WKDEP_OFFSET				0x0028
-#define DRA7XX_RM_CAM_VIP2_CONTEXT_OFFSET			0x002c
-#define DRA7XX_PM_CAM_VIP3_WKDEP_OFFSET				0x0030
-#define DRA7XX_RM_CAM_VIP3_CONTEXT_OFFSET			0x0034
-#define DRA7XX_RM_CAM_LVDSRX_CONTEXT_OFFSET			0x003c
-#define DRA7XX_RM_CAM_CSI1_CONTEXT_OFFSET			0x0044
-#define DRA7XX_RM_CAM_CSI2_CONTEXT_OFFSET			0x004c
-
-/* PRM.DSS_PRM register offsets */
-#define DRA7XX_PM_DSS_PWRSTCTRL_OFFSET				0x0000
-#define DRA7XX_PM_DSS_PWRSTST_OFFSET				0x0004
-#define DRA7XX_PM_DSS_DSS_WKDEP_OFFSET				0x0020
-#define DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET			0x0024
-#define DRA7XX_PM_DSS_DSS2_WKDEP_OFFSET				0x0028
-#define DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET			0x0034
-#define DRA7XX_RM_DSS_SDVENC_CONTEXT_OFFSET			0x003c
-
-/* PRM.GPU_PRM register offsets */
-#define DRA7XX_PM_GPU_PWRSTCTRL_OFFSET				0x0000
-#define DRA7XX_PM_GPU_PWRSTST_OFFSET				0x0004
-#define DRA7XX_RM_GPU_GPU_CONTEXT_OFFSET			0x0024
-
-/* PRM.L3INIT_PRM register offsets */
-#define DRA7XX_PM_L3INIT_PWRSTCTRL_OFFSET			0x0000
-#define DRA7XX_PM_L3INIT_PWRSTST_OFFSET				0x0004
-#define DRA7XX_PM_L3INIT_MMC1_WKDEP_OFFSET			0x0028
-#define DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET			0x002c
-#define DRA7XX_PM_L3INIT_MMC2_WKDEP_OFFSET			0x0030
-#define DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET			0x0034
-#define DRA7XX_PM_L3INIT_USB_OTG_SS2_WKDEP_OFFSET		0x0040
-#define DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET		0x0044
-#define DRA7XX_PM_L3INIT_USB_OTG_SS3_WKDEP_OFFSET		0x0048
-#define DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET		0x004c
-#define DRA7XX_PM_L3INIT_USB_OTG_SS4_WKDEP_OFFSET		0x0050
-#define DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET		0x0054
-#define DRA7XX_RM_L3INIT_MLB_SS_CONTEXT_OFFSET			0x005c
-#define DRA7XX_RM_L3INIT_IEEE1500_2_OCP_CONTEXT_OFFSET		0x007c
-#define DRA7XX_PM_L3INIT_SATA_WKDEP_OFFSET			0x0088
-#define DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET			0x008c
-#define DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET			0x00d4
-#define DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET		0x00e4
-#define DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET		0x00ec
-#define DRA7XX_PM_L3INIT_USB_OTG_SS1_WKDEP_OFFSET		0x00f0
-#define DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET		0x00f4
-
-/* PRM.L4PER_PRM register offsets */
-#define DRA7XX_PM_L4PER_PWRSTCTRL_OFFSET			0x0000
-#define DRA7XX_PM_L4PER_PWRSTST_OFFSET				0x0004
-#define DRA7XX_RM_L4PER2_L4PER2_CONTEXT_OFFSET			0x000c
-#define DRA7XX_RM_L4PER3_L4PER3_CONTEXT_OFFSET			0x0014
-#define DRA7XX_RM_L4PER2_PRUSS1_CONTEXT_OFFSET			0x001c
-#define DRA7XX_RM_L4PER2_PRUSS2_CONTEXT_OFFSET			0x0024
-#define DRA7XX_PM_L4PER_TIMER10_WKDEP_OFFSET			0x0028
-#define DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET			0x002c
-#define DRA7XX_PM_L4PER_TIMER11_WKDEP_OFFSET			0x0030
-#define DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET			0x0034
-#define DRA7XX_PM_L4PER_TIMER2_WKDEP_OFFSET			0x0038
-#define DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET			0x003c
-#define DRA7XX_PM_L4PER_TIMER3_WKDEP_OFFSET			0x0040
-#define DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET			0x0044
-#define DRA7XX_PM_L4PER_TIMER4_WKDEP_OFFSET			0x0048
-#define DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET			0x004c
-#define DRA7XX_PM_L4PER_TIMER9_WKDEP_OFFSET			0x0050
-#define DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET			0x0054
-#define DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET			0x005c
-#define DRA7XX_PM_L4PER_GPIO2_WKDEP_OFFSET			0x0060
-#define DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET			0x0064
-#define DRA7XX_PM_L4PER_GPIO3_WKDEP_OFFSET			0x0068
-#define DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET			0x006c
-#define DRA7XX_PM_L4PER_GPIO4_WKDEP_OFFSET			0x0070
-#define DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET			0x0074
-#define DRA7XX_PM_L4PER_GPIO5_WKDEP_OFFSET			0x0078
-#define DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET			0x007c
-#define DRA7XX_PM_L4PER_GPIO6_WKDEP_OFFSET			0x0080
-#define DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET			0x0084
-#define DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET			0x008c
-#define DRA7XX_RM_L4PER2_PWMSS2_CONTEXT_OFFSET			0x0094
-#define DRA7XX_RM_L4PER2_PWMSS3_CONTEXT_OFFSET			0x009c
-#define DRA7XX_PM_L4PER_I2C1_WKDEP_OFFSET			0x00a0
-#define DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET			0x00a4
-#define DRA7XX_PM_L4PER_I2C2_WKDEP_OFFSET			0x00a8
-#define DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET			0x00ac
-#define DRA7XX_PM_L4PER_I2C3_WKDEP_OFFSET			0x00b0
-#define DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET			0x00b4
-#define DRA7XX_PM_L4PER_I2C4_WKDEP_OFFSET			0x00b8
-#define DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET			0x00bc
-#define DRA7XX_RM_L4PER_L4PER1_CONTEXT_OFFSET			0x00c0
-#define DRA7XX_RM_L4PER2_PWMSS1_CONTEXT_OFFSET			0x00c4
-#define DRA7XX_PM_L4PER_TIMER13_WKDEP_OFFSET			0x00c8
-#define DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET			0x00cc
-#define DRA7XX_PM_L4PER_TIMER14_WKDEP_OFFSET			0x00d0
-#define DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET			0x00d4
-#define DRA7XX_PM_L4PER_TIMER15_WKDEP_OFFSET			0x00d8
-#define DRA7XX_RM_L4PER3_TIMER15_CONTEXT_OFFSET			0x00dc
-#define DRA7XX_PM_L4PER_MCSPI1_WKDEP_OFFSET			0x00f0
-#define DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET			0x00f4
-#define DRA7XX_PM_L4PER_MCSPI2_WKDEP_OFFSET			0x00f8
-#define DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET			0x00fc
-#define DRA7XX_PM_L4PER_MCSPI3_WKDEP_OFFSET			0x0100
-#define DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET			0x0104
-#define DRA7XX_PM_L4PER_MCSPI4_WKDEP_OFFSET			0x0108
-#define DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET			0x010c
-#define DRA7XX_PM_L4PER_GPIO7_WKDEP_OFFSET			0x0110
-#define DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET			0x0114
-#define DRA7XX_PM_L4PER_GPIO8_WKDEP_OFFSET			0x0118
-#define DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET			0x011c
-#define DRA7XX_PM_L4PER_MMC3_WKDEP_OFFSET			0x0120
-#define DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET			0x0124
-#define DRA7XX_PM_L4PER_MMC4_WKDEP_OFFSET			0x0128
-#define DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET			0x012c
-#define DRA7XX_PM_L4PER_TIMER16_WKDEP_OFFSET			0x0130
-#define DRA7XX_RM_L4PER3_TIMER16_CONTEXT_OFFSET			0x0134
-#define DRA7XX_PM_L4PER2_QSPI_WKDEP_OFFSET			0x0138
-#define DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET			0x013c
-#define DRA7XX_PM_L4PER_UART1_WKDEP_OFFSET			0x0140
-#define DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET			0x0144
-#define DRA7XX_PM_L4PER_UART2_WKDEP_OFFSET			0x0148
-#define DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET			0x014c
-#define DRA7XX_PM_L4PER_UART3_WKDEP_OFFSET			0x0150
-#define DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET			0x0154
-#define DRA7XX_PM_L4PER_UART4_WKDEP_OFFSET			0x0158
-#define DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET			0x015c
-#define DRA7XX_PM_L4PER2_MCASP2_WKDEP_OFFSET			0x0160
-#define DRA7XX_RM_L4PER2_MCASP2_CONTEXT_OFFSET			0x0164
-#define DRA7XX_PM_L4PER2_MCASP3_WKDEP_OFFSET			0x0168
-#define DRA7XX_RM_L4PER2_MCASP3_CONTEXT_OFFSET			0x016c
-#define DRA7XX_PM_L4PER_UART5_WKDEP_OFFSET			0x0170
-#define DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET			0x0174
-#define DRA7XX_PM_L4PER2_MCASP5_WKDEP_OFFSET			0x0178
-#define DRA7XX_RM_L4PER2_MCASP5_CONTEXT_OFFSET			0x017c
-#define DRA7XX_PM_L4PER2_MCASP6_WKDEP_OFFSET			0x0180
-#define DRA7XX_RM_L4PER2_MCASP6_CONTEXT_OFFSET			0x0184
-#define DRA7XX_PM_L4PER2_MCASP7_WKDEP_OFFSET			0x0188
-#define DRA7XX_RM_L4PER2_MCASP7_CONTEXT_OFFSET			0x018c
-#define DRA7XX_PM_L4PER2_MCASP8_WKDEP_OFFSET			0x0190
-#define DRA7XX_RM_L4PER2_MCASP8_CONTEXT_OFFSET			0x0194
-#define DRA7XX_PM_L4PER2_MCASP4_WKDEP_OFFSET			0x0198
-#define DRA7XX_RM_L4PER2_MCASP4_CONTEXT_OFFSET			0x019c
-#define DRA7XX_RM_L4SEC_AES1_CONTEXT_OFFSET			0x01a4
-#define DRA7XX_RM_L4SEC_AES2_CONTEXT_OFFSET			0x01ac
-#define DRA7XX_RM_L4SEC_DES3DES_CONTEXT_OFFSET			0x01b4
-#define DRA7XX_RM_L4SEC_FPKA_CONTEXT_OFFSET			0x01bc
-#define DRA7XX_RM_L4SEC_RNG_CONTEXT_OFFSET			0x01c4
-#define DRA7XX_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET			0x01cc
-#define DRA7XX_PM_L4PER2_UART7_WKDEP_OFFSET			0x01d0
-#define DRA7XX_RM_L4PER2_UART7_CONTEXT_OFFSET			0x01d4
-#define DRA7XX_RM_L4SEC_DMA_CRYPTO_CONTEXT_OFFSET		0x01dc
-#define DRA7XX_PM_L4PER2_UART8_WKDEP_OFFSET			0x01e0
-#define DRA7XX_RM_L4PER2_UART8_CONTEXT_OFFSET			0x01e4
-#define DRA7XX_PM_L4PER2_UART9_WKDEP_OFFSET			0x01e8
-#define DRA7XX_RM_L4PER2_UART9_CONTEXT_OFFSET			0x01ec
-#define DRA7XX_PM_L4PER2_DCAN2_WKDEP_OFFSET			0x01f0
-#define DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET			0x01f4
-#define DRA7XX_RM_L4SEC_SHA2MD52_CONTEXT_OFFSET			0x01fc
-
-/* PRM.CUSTEFUSE_PRM register offsets */
-#define DRA7XX_PM_CUSTEFUSE_PWRSTCTRL_OFFSET			0x0000
-#define DRA7XX_PM_CUSTEFUSE_PWRSTST_OFFSET			0x0004
-#define DRA7XX_RM_CUSTEFUSE_EFUSE_CTRL_CUST_CONTEXT_OFFSET	0x0024
-
-/* PRM.WKUPAON_PRM register offsets */
-#define DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET		0x0000
-#define DRA7XX_PM_WKUPAON_WD_TIMER1_WKDEP_OFFSET		0x0004
-#define DRA7XX_RM_WKUPAON_WD_TIMER1_CONTEXT_OFFSET		0x0008
-#define DRA7XX_PM_WKUPAON_WD_TIMER2_WKDEP_OFFSET		0x000c
-#define DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET		0x0010
-#define DRA7XX_PM_WKUPAON_GPIO1_WKDEP_OFFSET			0x0014
-#define DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET			0x0018
-#define DRA7XX_PM_WKUPAON_TIMER1_WKDEP_OFFSET			0x001c
-#define DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET			0x0020
-#define DRA7XX_PM_WKUPAON_TIMER12_WKDEP_OFFSET			0x0024
-#define DRA7XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET		0x0028
-#define DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET		0x0030
-#define DRA7XX_RM_WKUPAON_SAR_RAM_CONTEXT_OFFSET		0x0040
-#define DRA7XX_PM_WKUPAON_KBD_WKDEP_OFFSET			0x0054
-#define DRA7XX_RM_WKUPAON_KBD_CONTEXT_OFFSET			0x0058
-#define DRA7XX_PM_WKUPAON_UART10_WKDEP_OFFSET			0x005c
-#define DRA7XX_RM_WKUPAON_UART10_CONTEXT_OFFSET			0x0060
-#define DRA7XX_PM_WKUPAON_DCAN1_WKDEP_OFFSET			0x0064
-#define DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET			0x0068
-#define DRA7XX_PM_WKUPAON_ADC_WKDEP_OFFSET				0x007c
-#define DRA7XX_RM_WKUPAON_ADC_CONTEXT_OFFSET			0x0080
-#define DRA7XX_RM_WKUPAON_SPARE_SAFETY1_CONTEXT_OFFSET		0x0090
-#define DRA7XX_RM_WKUPAON_SPARE_SAFETY2_CONTEXT_OFFSET		0x0098
-#define DRA7XX_RM_WKUPAON_SPARE_SAFETY3_CONTEXT_OFFSET		0x00a0
-#define DRA7XX_RM_WKUPAON_SPARE_SAFETY4_CONTEXT_OFFSET		0x00a8
-#define DRA7XX_RM_WKUPAON_SPARE_UNKNOWN2_CONTEXT_OFFSET		0x00b0
-#define DRA7XX_RM_WKUPAON_SPARE_UNKNOWN3_CONTEXT_OFFSET		0x00b8
-
-/* PRM.WKUPAON_CM register offsets */
-#define DRA7XX_CM_WKUPAON_CLKSTCTRL_OFFSET			0x0000
-#define DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET		0x0020
-#define DRA7XX_CM_WKUPAON_WD_TIMER1_CLKCTRL_OFFSET		0x0028
-#define DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET		0x0030
-#define DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET			0x0038
-#define DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET			0x0040
-#define DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET		0x0048
-#define DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET		0x0050
-#define DRA7XX_CM_WKUPAON_SAR_RAM_CLKCTRL_OFFSET		0x0060
-#define DRA7XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET			0x0078
-#define DRA7XX_CM_WKUPAON_UART10_CLKCTRL_OFFSET			0x0080
-#define DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET			0x0088
-#define DRA7XX_CM_WKUPAON_SCRM_CLKCTRL_OFFSET			0x0090
-#define DRA7XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL_OFFSET		0x0098
-#define DRA7XX_CM_WKUPAON_ADC_CLKCTRL_OFFSET			0x00a0
-#define DRA7XX_CM_WKUPAON_SPARE_SAFETY1_CLKCTRL_OFFSET		0x00b0
-#define DRA7XX_CM_WKUPAON_SPARE_SAFETY2_CLKCTRL_OFFSET		0x00b8
-#define DRA7XX_CM_WKUPAON_SPARE_SAFETY3_CLKCTRL_OFFSET		0x00c0
-#define DRA7XX_CM_WKUPAON_SPARE_SAFETY4_CLKCTRL_OFFSET		0x00c8
-#define DRA7XX_CM_WKUPAON_SPARE_UNKNOWN2_CLKCTRL_OFFSET		0x00d0
-#define DRA7XX_CM_WKUPAON_SPARE_UNKNOWN3_CLKCTRL_OFFSET		0x00d8
-
-/* PRM.EMU_PRM register offsets */
-#define DRA7XX_PM_EMU_PWRSTCTRL_OFFSET				0x0000
-#define DRA7XX_PM_EMU_PWRSTST_OFFSET				0x0004
-#define DRA7XX_RM_EMU_DEBUGSS_CONTEXT_OFFSET			0x0024
-
-/* PRM.EMU_CM register offsets */
-#define DRA7XX_CM_EMU_CLKSTCTRL_OFFSET				0x0000
-#define DRA7XX_CM_EMU_DEBUGSS_CLKCTRL_OFFSET			0x0004
-#define DRA7XX_CM_EMU_DYNAMICDEP_OFFSET				0x0008
-#define DRA7XX_CM_EMU_MPU_EMU_DBG_CLKCTRL_OFFSET		0x000c
-
-/* PRM.DSP2_PRM register offsets */
-#define DRA7XX_PM_DSP2_PWRSTCTRL_OFFSET				0x0000
-#define DRA7XX_PM_DSP2_PWRSTST_OFFSET				0x0004
-#define DRA7XX_RM_DSP2_RSTCTRL_OFFSET				0x0010
-#define DRA7XX_RM_DSP2_RSTST_OFFSET				0x0014
-#define DRA7XX_RM_DSP2_DSP2_CONTEXT_OFFSET			0x0024
-
-/* PRM.EVE1_PRM register offsets */
-#define DRA7XX_PM_EVE1_PWRSTCTRL_OFFSET				0x0000
-#define DRA7XX_PM_EVE1_PWRSTST_OFFSET				0x0004
-#define DRA7XX_RM_EVE1_RSTCTRL_OFFSET				0x0010
-#define DRA7XX_RM_EVE1_RSTST_OFFSET				0x0014
-#define DRA7XX_PM_EVE1_EVE1_WKDEP_OFFSET			0x0020
-#define DRA7XX_RM_EVE1_EVE1_CONTEXT_OFFSET			0x0024
-
-/* PRM.EVE2_PRM register offsets */
-#define DRA7XX_PM_EVE2_PWRSTCTRL_OFFSET				0x0000
-#define DRA7XX_PM_EVE2_PWRSTST_OFFSET				0x0004
-#define DRA7XX_RM_EVE2_RSTCTRL_OFFSET				0x0010
-#define DRA7XX_RM_EVE2_RSTST_OFFSET				0x0014
-#define DRA7XX_PM_EVE2_EVE2_WKDEP_OFFSET			0x0020
-#define DRA7XX_RM_EVE2_EVE2_CONTEXT_OFFSET			0x0024
-
-/* PRM.EVE3_PRM register offsets */
-#define DRA7XX_PM_EVE3_PWRSTCTRL_OFFSET				0x0000
-#define DRA7XX_PM_EVE3_PWRSTST_OFFSET				0x0004
-#define DRA7XX_RM_EVE3_RSTCTRL_OFFSET				0x0010
-#define DRA7XX_RM_EVE3_RSTST_OFFSET				0x0014
-#define DRA7XX_PM_EVE3_EVE3_WKDEP_OFFSET			0x0020
-#define DRA7XX_RM_EVE3_EVE3_CONTEXT_OFFSET			0x0024
-
-/* PRM.EVE4_PRM register offsets */
-#define DRA7XX_PM_EVE4_PWRSTCTRL_OFFSET				0x0000
-#define DRA7XX_PM_EVE4_PWRSTST_OFFSET				0x0004
-#define DRA7XX_RM_EVE4_RSTCTRL_OFFSET				0x0010
-#define DRA7XX_RM_EVE4_RSTST_OFFSET				0x0014
-#define DRA7XX_PM_EVE4_EVE4_WKDEP_OFFSET			0x0020
-#define DRA7XX_RM_EVE4_EVE4_CONTEXT_OFFSET			0x0024
-
-/* PRM.RTC_PRM register offsets */
-#define DRA7XX_PM_RTC_RTCSS_WKDEP_OFFSET			0x0000
-#define DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET			0x0004
-
-/* PRM.VPE_PRM register offsets */
-#define DRA7XX_PM_VPE_PWRSTCTRL_OFFSET				0x0000
-#define DRA7XX_PM_VPE_PWRSTST_OFFSET				0x0004
-#define DRA7XX_PM_VPE_VPE_WKDEP_OFFSET				0x0020
-#define DRA7XX_RM_VPE_VPE_CONTEXT_OFFSET			0x0024
-
-/* PRM.DEVICE_PRM register offsets */
-#define DRA7XX_PRM_RSTCTRL_OFFSET				0x0000
-#define DRA7XX_PRM_RSTST_OFFSET					0x0004
-#define DRA7XX_PRM_RSTTIME_OFFSET				0x0008
-#define DRA7XX_PRM_CLKREQCTRL_OFFSET				0x000c
-#define DRA7XX_PRM_VOLTCTRL_OFFSET				0x0010
-#define DRA7XX_PRM_PWRREQCTRL_OFFSET				0x0014
-#define DRA7XX_PRM_PSCON_COUNT_OFFSET				0x0018
-#define DRA7XX_PRM_IO_COUNT_OFFSET				0x001c
-#define DRA7XX_PRM_IO_PMCTRL_OFFSET				0x0020
-#define DRA7XX_PRM_VOLTSETUP_WARMRESET_OFFSET			0x0024
-#define DRA7XX_PRM_VOLTSETUP_CORE_OFF_OFFSET			0x0028
-#define DRA7XX_PRM_VOLTSETUP_MPU_OFF_OFFSET			0x002c
-#define DRA7XX_PRM_VOLTSETUP_MM_OFF_OFFSET			0x0030
-#define DRA7XX_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET		0x0034
-#define DRA7XX_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET		0x0038
-#define DRA7XX_PRM_VOLTSETUP_MM_RET_SLEEP_OFFSET		0x003c
-#define DRA7XX_PRM_SRAM_COUNT_OFFSET				0x00bc
-#define DRA7XX_PRM_SRAM_WKUP_SETUP_OFFSET			0x00c0
-#define DRA7XX_PRM_SLDO_CORE_SETUP_OFFSET			0x00c4
-#define DRA7XX_PRM_SLDO_CORE_CTRL_OFFSET			0x00c8
-#define DRA7XX_PRM_SLDO_MPU_SETUP_OFFSET			0x00cc
-#define DRA7XX_PRM_SLDO_MPU_CTRL_OFFSET				0x00d0
-#define DRA7XX_PRM_SLDO_GPU_SETUP_OFFSET			0x00d4
-#define DRA7XX_PRM_SLDO_GPU_CTRL_OFFSET				0x00d8
-#define DRA7XX_PRM_ABBLDO_MPU_SETUP_OFFSET			0x00dc
-#define DRA7XX_PRM_ABBLDO_MPU_CTRL_OFFSET			0x00e0
-#define DRA7XX_PRM_ABBLDO_GPU_SETUP_OFFSET			0x00e4
-#define DRA7XX_PRM_ABBLDO_GPU_CTRL_OFFSET			0x00e8
-#define DRA7XX_PRM_BANDGAP_SETUP_OFFSET				0x00ec
-#define DRA7XX_PRM_DEVICE_OFF_CTRL_OFFSET			0x00f0
-#define DRA7XX_PRM_PHASE1_CNDP_OFFSET				0x00f4
-#define DRA7XX_PRM_PHASE2A_CNDP_OFFSET				0x00f8
-#define DRA7XX_PRM_PHASE2B_CNDP_OFFSET				0x00fc
-#define DRA7XX_PRM_MODEM_IF_CTRL_OFFSET				0x0100
-#define DRA7XX_PRM_VOLTST_MPU_OFFSET				0x0110
-#define DRA7XX_PRM_VOLTST_MM_OFFSET				0x0114
-#define DRA7XX_PRM_SLDO_DSPEVE_SETUP_OFFSET			0x0118
-#define DRA7XX_PRM_SLDO_IVA_SETUP_OFFSET			0x011c
-#define DRA7XX_PRM_ABBLDO_DSPEVE_CTRL_OFFSET			0x0120
-#define DRA7XX_PRM_ABBLDO_IVA_CTRL_OFFSET			0x0124
-#define DRA7XX_PRM_SLDO_DSPEVE_CTRL_OFFSET			0x0128
-#define DRA7XX_PRM_SLDO_IVA_CTRL_OFFSET				0x012c
-#define DRA7XX_PRM_ABBLDO_DSPEVE_SETUP_OFFSET			0x0130
-#define DRA7XX_PRM_ABBLDO_IVA_SETUP_OFFSET			0x0134
-
 #endif
diff --git a/arch/arm/mach-omap2/prminst44xx.c b/arch/arm/mach-omap2/prminst44xx.c
index f330766..feb508f 100644
--- a/arch/arm/mach-omap2/prminst44xx.c
+++ b/arch/arm/mach-omap2/prminst44xx.c
@@ -20,7 +20,7 @@
 #include "prcm-common.h"
 #include <linux/power/omap/prm44xx.h>
 #include <linux/power/omap/prm54xx.h>
-#include "prm7xx.h"
+#include <linux/power/omap/prm7xx.h>
 #include "prminst44xx.h"
 #include "prcm44xx.h"
 #include "prcm_mpu44xx.h"
diff --git a/include/linux/power/omap/prm7xx.h b/include/linux/power/omap/prm7xx.h
new file mode 100644
index 0000000..a2d49ba
--- /dev/null
+++ b/include/linux/power/omap/prm7xx.h
@@ -0,0 +1,591 @@
+/*
+ * DRA7xx PRM instance offset macros
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Generated by code originally written by:
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __LINUX_POWER_OMAP_PRM7XX_H
+#define __LINUX_POWER_OMAP_PRM7XX_H
+
+/* PRM instances */
+#define DRA7XX_PRM_OCP_SOCKET_INST	0x0000
+#define DRA7XX_PRM_CKGEN_INST		0x0100
+#define DRA7XX_PRM_MPU_INST		0x0300
+#define DRA7XX_PRM_DSP1_INST		0x0400
+#define DRA7XX_PRM_IPU_INST		0x0500
+#define DRA7XX_PRM_COREAON_INST		0x0628
+#define DRA7XX_PRM_CORE_INST		0x0700
+#define DRA7XX_PRM_IVA_INST		0x0f00
+#define DRA7XX_PRM_CAM_INST		0x1000
+#define DRA7XX_PRM_DSS_INST		0x1100
+#define DRA7XX_PRM_GPU_INST		0x1200
+#define DRA7XX_PRM_L3INIT_INST		0x1300
+#define DRA7XX_PRM_L4PER_INST		0x1400
+#define DRA7XX_PRM_CUSTEFUSE_INST	0x1600
+#define DRA7XX_PRM_WKUPAON_INST		0x1724
+#define DRA7XX_PRM_WKUPAON_CM_INST	0x1800
+#define DRA7XX_PRM_EMU_INST		0x1900
+#define DRA7XX_PRM_EMU_CM_INST		0x1a00
+#define DRA7XX_PRM_DSP2_INST		0x1b00
+#define DRA7XX_PRM_EVE1_INST		0x1b40
+#define DRA7XX_PRM_EVE2_INST		0x1b80
+#define DRA7XX_PRM_EVE3_INST		0x1bc0
+#define DRA7XX_PRM_EVE4_INST		0x1c00
+#define DRA7XX_PRM_RTC_INST		0x1c60
+#define DRA7XX_PRM_VPE_INST		0x1c80
+#define DRA7XX_PRM_DEVICE_INST		0x1d00
+#define DRA7XX_PRM_INSTR_INST		0x1f00
+
+/* PRM clockdomain register offsets (from instance start) */
+#define DRA7XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS	0x0000
+#define DRA7XX_PRM_EMU_CM_EMU_CDOFFS		0x0000
+
+/* PRM */
+
+/* PRM.OCP_SOCKET_PRM register offsets */
+#define DRA7XX_REVISION_PRM_OFFSET				0x0000
+#define DRA7XX_PRM_IRQSTATUS_MPU_OFFSET				0x0010
+#define DRA7XX_PRM_IRQSTATUS_MPU_2_OFFSET			0x0014
+#define DRA7XX_PRM_IRQENABLE_MPU_OFFSET				0x0018
+#define DRA7XX_PRM_IRQENABLE_MPU_2_OFFSET			0x001c
+#define DRA7XX_PRM_IRQSTATUS_IPU2_OFFSET			0x0020
+#define DRA7XX_PRM_IRQENABLE_IPU2_OFFSET			0x0028
+#define DRA7XX_PRM_IRQSTATUS_DSP1_OFFSET			0x0030
+#define DRA7XX_PRM_IRQENABLE_DSP1_OFFSET			0x0038
+#define DRA7XX_CM_PRM_PROFILING_CLKCTRL_OFFSET			0x0040
+#define DRA7XX_PRM_IRQENABLE_DSP2_OFFSET			0x0044
+#define DRA7XX_PRM_IRQENABLE_EVE1_OFFSET			0x0048
+#define DRA7XX_PRM_IRQENABLE_EVE2_OFFSET			0x004c
+#define DRA7XX_PRM_IRQENABLE_EVE3_OFFSET			0x0050
+#define DRA7XX_PRM_IRQENABLE_EVE4_OFFSET			0x0054
+#define DRA7XX_PRM_IRQENABLE_IPU1_OFFSET			0x0058
+#define DRA7XX_PRM_IRQSTATUS_DSP2_OFFSET			0x005c
+#define DRA7XX_PRM_IRQSTATUS_EVE1_OFFSET			0x0060
+#define DRA7XX_PRM_IRQSTATUS_EVE2_OFFSET			0x0064
+#define DRA7XX_PRM_IRQSTATUS_EVE3_OFFSET			0x0068
+#define DRA7XX_PRM_IRQSTATUS_EVE4_OFFSET			0x006c
+#define DRA7XX_PRM_IRQSTATUS_IPU1_OFFSET			0x0070
+#define DRA7XX_PRM_DEBUG_CFG1_OFFSET				0x00e4
+#define DRA7XX_PRM_DEBUG_CFG2_OFFSET				0x00e8
+#define DRA7XX_PRM_DEBUG_CFG3_OFFSET				0x00ec
+#define DRA7XX_PRM_DEBUG_OUT_OFFSET				0x00f4
+
+/* PRM.CKGEN_PRM register offsets */
+#define DRA7XX_CM_CLKSEL_SYSCLK1_OFFSET				0x0000
+#define DRA7XX_CM_CLKSEL_WKUPAON_OFFSET				0x0008
+#define DRA7XX_CM_CLKSEL_ABE_PLL_REF_OFFSET			0x000c
+#define DRA7XX_CM_CLKSEL_SYS_OFFSET				0x0010
+#define DRA7XX_CM_CLKSEL_ABE_PLL_BYPAS_OFFSET			0x0014
+#define DRA7XX_CM_CLKSEL_ABE_PLL_SYS_OFFSET			0x0018
+#define DRA7XX_CM_CLKSEL_ABE_24M_OFFSET				0x001c
+#define DRA7XX_CM_CLKSEL_ABE_SYS_OFFSET				0x0020
+#define DRA7XX_CM_CLKSEL_HDMI_MCASP_AUX_OFFSET			0x0024
+#define DRA7XX_CM_CLKSEL_HDMI_TIMER_OFFSET			0x0028
+#define DRA7XX_CM_CLKSEL_MCASP_SYS_OFFSET			0x002c
+#define DRA7XX_CM_CLKSEL_MLBP_MCASP_OFFSET			0x0030
+#define DRA7XX_CM_CLKSEL_MLB_MCASP_OFFSET			0x0034
+#define DRA7XX_CM_CLKSEL_PER_ABE_X1_GFCLK_MCASP_AUX_OFFSET	0x0038
+#define DRA7XX_CM_CLKSEL_SYS_CLK1_32K_OFFSET			0x0040
+#define DRA7XX_CM_CLKSEL_TIMER_SYS_OFFSET			0x0044
+#define DRA7XX_CM_CLKSEL_VIDEO1_MCASP_AUX_OFFSET		0x0048
+#define DRA7XX_CM_CLKSEL_VIDEO1_TIMER_OFFSET			0x004c
+#define DRA7XX_CM_CLKSEL_VIDEO2_MCASP_AUX_OFFSET		0x0050
+#define DRA7XX_CM_CLKSEL_VIDEO2_TIMER_OFFSET			0x0054
+#define DRA7XX_CM_CLKSEL_CLKOUTMUX0_OFFSET			0x0058
+#define DRA7XX_CM_CLKSEL_CLKOUTMUX1_OFFSET			0x005c
+#define DRA7XX_CM_CLKSEL_CLKOUTMUX2_OFFSET			0x0060
+#define DRA7XX_CM_CLKSEL_HDMI_PLL_SYS_OFFSET			0x0064
+#define DRA7XX_CM_CLKSEL_VIDEO1_PLL_SYS_OFFSET			0x0068
+#define DRA7XX_CM_CLKSEL_VIDEO2_PLL_SYS_OFFSET			0x006c
+#define DRA7XX_CM_CLKSEL_ABE_CLK_DIV_OFFSET			0x0070
+#define DRA7XX_CM_CLKSEL_ABE_GICLK_DIV_OFFSET			0x0074
+#define DRA7XX_CM_CLKSEL_AESS_FCLK_DIV_OFFSET			0x0078
+#define DRA7XX_CM_CLKSEL_EVE_CLK_OFFSET				0x0080
+#define DRA7XX_CM_CLKSEL_USB_OTG_CLK_CLKOUTMUX_OFFSET		0x0084
+#define DRA7XX_CM_CLKSEL_CORE_DPLL_OUT_CLK_CLKOUTMUX_OFFSET	0x0088
+#define DRA7XX_CM_CLKSEL_DSP_GFCLK_CLKOUTMUX_OFFSET		0x008c
+#define DRA7XX_CM_CLKSEL_EMIF_PHY_GCLK_CLKOUTMUX_OFFSET		0x0090
+#define DRA7XX_CM_CLKSEL_EMU_CLK_CLKOUTMUX_OFFSET		0x0094
+#define DRA7XX_CM_CLKSEL_FUNC_96M_AON_CLK_CLKOUTMUX_OFFSET	0x0098
+#define DRA7XX_CM_CLKSEL_GMAC_250M_CLK_CLKOUTMUX_OFFSET		0x009c
+#define DRA7XX_CM_CLKSEL_GPU_GCLK_CLKOUTMUX_OFFSET		0x00a0
+#define DRA7XX_CM_CLKSEL_HDMI_CLK_CLKOUTMUX_OFFSET		0x00a4
+#define DRA7XX_CM_CLKSEL_IVA_GCLK_CLKOUTMUX_OFFSET		0x00a8
+#define DRA7XX_CM_CLKSEL_L3INIT_480M_GFCLK_CLKOUTMUX_OFFSET	0x00ac
+#define DRA7XX_CM_CLKSEL_MPU_GCLK_CLKOUTMUX_OFFSET		0x00b0
+#define DRA7XX_CM_CLKSEL_PCIE1_CLK_CLKOUTMUX_OFFSET		0x00b4
+#define DRA7XX_CM_CLKSEL_PCIE2_CLK_CLKOUTMUX_OFFSET		0x00b8
+#define DRA7XX_CM_CLKSEL_PER_ABE_X1_CLK_CLKOUTMUX_OFFSET	0x00bc
+#define DRA7XX_CM_CLKSEL_SATA_CLK_CLKOUTMUX_OFFSET		0x00c0
+#define DRA7XX_CM_CLKSEL_SECURE_32K_CLK_CLKOUTMUX_OFFSET	0x00c4
+#define DRA7XX_CM_CLKSEL_SYS_CLK1_CLKOUTMUX_OFFSET		0x00c8
+#define DRA7XX_CM_CLKSEL_SYS_CLK2_CLKOUTMUX_OFFSET		0x00cc
+#define DRA7XX_CM_CLKSEL_VIDEO1_CLK_CLKOUTMUX_OFFSET		0x00d0
+#define DRA7XX_CM_CLKSEL_VIDEO2_CLK_CLKOUTMUX_OFFSET		0x00d4
+#define DRA7XX_CM_CLKSEL_ABE_LP_CLK_OFFSET			0x00d8
+#define DRA7XX_CM_CLKSEL_ADC_GFCLK_OFFSET			0x00dc
+#define DRA7XX_CM_CLKSEL_EVE_GFCLK_CLKOUTMUX_OFFSET		0x00e0
+
+/* PRM.MPU_PRM register offsets */
+#define DRA7XX_PM_MPU_PWRSTCTRL_OFFSET				0x0000
+#define DRA7XX_PM_MPU_PWRSTST_OFFSET				0x0004
+#define DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET			0x0024
+
+/* PRM.DSP1_PRM register offsets */
+#define DRA7XX_PM_DSP1_PWRSTCTRL_OFFSET				0x0000
+#define DRA7XX_PM_DSP1_PWRSTST_OFFSET				0x0004
+#define DRA7XX_RM_DSP1_RSTCTRL_OFFSET				0x0010
+#define DRA7XX_RM_DSP1_RSTST_OFFSET				0x0014
+#define DRA7XX_RM_DSP1_DSP1_CONTEXT_OFFSET			0x0024
+
+/* PRM.IPU_PRM register offsets */
+#define DRA7XX_PM_IPU_PWRSTCTRL_OFFSET				0x0000
+#define DRA7XX_PM_IPU_PWRSTST_OFFSET				0x0004
+#define DRA7XX_RM_IPU1_RSTCTRL_OFFSET				0x0010
+#define DRA7XX_RM_IPU1_RSTST_OFFSET				0x0014
+#define DRA7XX_RM_IPU1_IPU1_CONTEXT_OFFSET			0x0024
+#define DRA7XX_PM_IPU_MCASP1_WKDEP_OFFSET			0x0050
+#define DRA7XX_RM_IPU_MCASP1_CONTEXT_OFFSET			0x0054
+#define DRA7XX_PM_IPU_TIMER5_WKDEP_OFFSET			0x0058
+#define DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET			0x005c
+#define DRA7XX_PM_IPU_TIMER6_WKDEP_OFFSET			0x0060
+#define DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET			0x0064
+#define DRA7XX_PM_IPU_TIMER7_WKDEP_OFFSET			0x0068
+#define DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET			0x006c
+#define DRA7XX_PM_IPU_TIMER8_WKDEP_OFFSET			0x0070
+#define DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET			0x0074
+#define DRA7XX_PM_IPU_I2C5_WKDEP_OFFSET				0x0078
+#define DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET			0x007c
+#define DRA7XX_PM_IPU_UART6_WKDEP_OFFSET			0x0080
+#define DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET			0x0084
+
+/* PRM.COREAON_PRM register offsets */
+#define DRA7XX_PM_COREAON_SMARTREFLEX_MPU_WKDEP_OFFSET		0x0000
+#define DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET	0x0004
+#define DRA7XX_PM_COREAON_SMARTREFLEX_CORE_WKDEP_OFFSET		0x0010
+#define DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET	0x0014
+#define DRA7XX_PM_COREAON_SMARTREFLEX_GPU_WKDEP_OFFSET		0x0030
+#define DRA7XX_RM_COREAON_SMARTREFLEX_GPU_CONTEXT_OFFSET	0x0034
+#define DRA7XX_PM_COREAON_SMARTREFLEX_DSPEVE_WKDEP_OFFSET	0x0040
+#define DRA7XX_RM_COREAON_SMARTREFLEX_DSPEVE_CONTEXT_OFFSET	0x0044
+#define DRA7XX_PM_COREAON_SMARTREFLEX_IVAHD_WKDEP_OFFSET	0x0050
+#define DRA7XX_RM_COREAON_SMARTREFLEX_IVAHD_CONTEXT_OFFSET	0x0054
+#define DRA7XX_RM_COREAON_DUMMY_MODULE1_CONTEXT_OFFSET		0x0084
+#define DRA7XX_RM_COREAON_DUMMY_MODULE2_CONTEXT_OFFSET		0x0094
+#define DRA7XX_RM_COREAON_DUMMY_MODULE3_CONTEXT_OFFSET		0x00a4
+#define DRA7XX_RM_COREAON_DUMMY_MODULE4_CONTEXT_OFFSET		0x00b4
+
+/* PRM.CORE_PRM register offsets */
+#define DRA7XX_PM_CORE_PWRSTCTRL_OFFSET				0x0000
+#define DRA7XX_PM_CORE_PWRSTST_OFFSET				0x0004
+#define DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET		0x0024
+#define DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET			0x002c
+#define DRA7XX_RM_L3MAIN1_MMU_EDMA_CONTEXT_OFFSET		0x0034
+#define DRA7XX_PM_L3MAIN1_OCMC_RAM1_WKDEP_OFFSET		0x0050
+#define DRA7XX_RM_L3MAIN1_OCMC_RAM1_CONTEXT_OFFSET		0x0054
+#define DRA7XX_PM_L3MAIN1_OCMC_RAM2_WKDEP_OFFSET		0x0058
+#define DRA7XX_RM_L3MAIN1_OCMC_RAM2_CONTEXT_OFFSET		0x005c
+#define DRA7XX_PM_L3MAIN1_OCMC_RAM3_WKDEP_OFFSET		0x0060
+#define DRA7XX_RM_L3MAIN1_OCMC_RAM3_CONTEXT_OFFSET		0x0064
+#define DRA7XX_RM_L3MAIN1_OCMC_ROM_CONTEXT_OFFSET		0x006c
+#define DRA7XX_PM_L3MAIN1_TPCC_WKDEP_OFFSET			0x0070
+#define DRA7XX_RM_L3MAIN1_TPCC_CONTEXT_OFFSET			0x0074
+#define DRA7XX_PM_L3MAIN1_TPTC1_WKDEP_OFFSET			0x0078
+#define DRA7XX_RM_L3MAIN1_TPTC1_CONTEXT_OFFSET			0x007c
+#define DRA7XX_PM_L3MAIN1_TPTC2_WKDEP_OFFSET			0x0080
+#define DRA7XX_RM_L3MAIN1_TPTC2_CONTEXT_OFFSET			0x0084
+#define DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET			0x008c
+#define DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET			0x0094
+#define DRA7XX_RM_L3MAIN1_SPARE_CME_CONTEXT_OFFSET		0x009c
+#define DRA7XX_RM_L3MAIN1_SPARE_HDMI_CONTEXT_OFFSET		0x00a4
+#define DRA7XX_RM_L3MAIN1_SPARE_ICM_CONTEXT_OFFSET		0x00ac
+#define DRA7XX_RM_L3MAIN1_SPARE_IVA2_CONTEXT_OFFSET		0x00b4
+#define DRA7XX_RM_L3MAIN1_SPARE_SATA2_CONTEXT_OFFSET		0x00bc
+#define DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN4_CONTEXT_OFFSET		0x00c4
+#define DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN5_CONTEXT_OFFSET		0x00cc
+#define DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN6_CONTEXT_OFFSET		0x00d4
+#define DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL1_CONTEXT_OFFSET	0x00dc
+#define DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL2_CONTEXT_OFFSET	0x00f4
+#define DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL3_CONTEXT_OFFSET	0x00fc
+#define DRA7XX_RM_IPU2_RSTCTRL_OFFSET				0x0210
+#define DRA7XX_RM_IPU2_RSTST_OFFSET				0x0214
+#define DRA7XX_RM_IPU2_IPU2_CONTEXT_OFFSET			0x0224
+#define DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET			0x0324
+#define DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET			0x0424
+#define DRA7XX_RM_EMIF_EMIF_OCP_FW_CONTEXT_OFFSET		0x042c
+#define DRA7XX_RM_EMIF_EMIF1_CONTEXT_OFFSET			0x0434
+#define DRA7XX_RM_EMIF_EMIF2_CONTEXT_OFFSET			0x043c
+#define DRA7XX_RM_EMIF_EMIF_DLL_CONTEXT_OFFSET			0x0444
+#define DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET			0x0524
+#define DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET			0x0624
+#define DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET			0x062c
+#define DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET			0x0634
+#define DRA7XX_RM_L4CFG_SAR_ROM_CONTEXT_OFFSET			0x063c
+#define DRA7XX_RM_L4CFG_OCP2SCP2_CONTEXT_OFFSET			0x0644
+#define DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET			0x064c
+#define DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET			0x0654
+#define DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET			0x065c
+#define DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET			0x0664
+#define DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET			0x066c
+#define DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET			0x0674
+#define DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET			0x067c
+#define DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET			0x0684
+#define DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET		0x068c
+#define DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET		0x0694
+#define DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET		0x069c
+#define DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET		0x06a4
+#define DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_RTC_CONTEXT_OFFSET	0x06ac
+#define DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CONTEXT_OFFSET	0x06b4
+#define DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_WKUP_CONTEXT_OFFSET	0x06bc
+#define DRA7XX_RM_L4CFG_IO_DELAY_BLOCK_CONTEXT_OFFSET		0x06c4
+#define DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET		0x0724
+#define DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET		0x072c
+#define DRA7XX_RM_L3INSTR_OCP_WP_NOC_CONTEXT_OFFSET		0x0744
+
+/* PRM.IVA_PRM register offsets */
+#define DRA7XX_PM_IVA_PWRSTCTRL_OFFSET				0x0000
+#define DRA7XX_PM_IVA_PWRSTST_OFFSET				0x0004
+#define DRA7XX_RM_IVA_RSTCTRL_OFFSET				0x0010
+#define DRA7XX_RM_IVA_RSTST_OFFSET				0x0014
+#define DRA7XX_RM_IVA_IVA_CONTEXT_OFFSET			0x0024
+#define DRA7XX_RM_IVA_SL2_CONTEXT_OFFSET			0x002c
+
+/* PRM.CAM_PRM register offsets */
+#define DRA7XX_PM_CAM_PWRSTCTRL_OFFSET				0x0000
+#define DRA7XX_PM_CAM_PWRSTST_OFFSET				0x0004
+#define DRA7XX_PM_CAM_VIP1_WKDEP_OFFSET				0x0020
+#define DRA7XX_RM_CAM_VIP1_CONTEXT_OFFSET			0x0024
+#define DRA7XX_PM_CAM_VIP2_WKDEP_OFFSET				0x0028
+#define DRA7XX_RM_CAM_VIP2_CONTEXT_OFFSET			0x002c
+#define DRA7XX_PM_CAM_VIP3_WKDEP_OFFSET				0x0030
+#define DRA7XX_RM_CAM_VIP3_CONTEXT_OFFSET			0x0034
+#define DRA7XX_RM_CAM_LVDSRX_CONTEXT_OFFSET			0x003c
+#define DRA7XX_RM_CAM_CSI1_CONTEXT_OFFSET			0x0044
+#define DRA7XX_RM_CAM_CSI2_CONTEXT_OFFSET			0x004c
+
+/* PRM.DSS_PRM register offsets */
+#define DRA7XX_PM_DSS_PWRSTCTRL_OFFSET				0x0000
+#define DRA7XX_PM_DSS_PWRSTST_OFFSET				0x0004
+#define DRA7XX_PM_DSS_DSS_WKDEP_OFFSET				0x0020
+#define DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET			0x0024
+#define DRA7XX_PM_DSS_DSS2_WKDEP_OFFSET				0x0028
+#define DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET			0x0034
+#define DRA7XX_RM_DSS_SDVENC_CONTEXT_OFFSET			0x003c
+
+/* PRM.GPU_PRM register offsets */
+#define DRA7XX_PM_GPU_PWRSTCTRL_OFFSET				0x0000
+#define DRA7XX_PM_GPU_PWRSTST_OFFSET				0x0004
+#define DRA7XX_RM_GPU_GPU_CONTEXT_OFFSET			0x0024
+
+/* PRM.L3INIT_PRM register offsets */
+#define DRA7XX_PM_L3INIT_PWRSTCTRL_OFFSET			0x0000
+#define DRA7XX_PM_L3INIT_PWRSTST_OFFSET				0x0004
+#define DRA7XX_PM_L3INIT_MMC1_WKDEP_OFFSET			0x0028
+#define DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET			0x002c
+#define DRA7XX_PM_L3INIT_MMC2_WKDEP_OFFSET			0x0030
+#define DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET			0x0034
+#define DRA7XX_PM_L3INIT_USB_OTG_SS2_WKDEP_OFFSET		0x0040
+#define DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET		0x0044
+#define DRA7XX_PM_L3INIT_USB_OTG_SS3_WKDEP_OFFSET		0x0048
+#define DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET		0x004c
+#define DRA7XX_PM_L3INIT_USB_OTG_SS4_WKDEP_OFFSET		0x0050
+#define DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET		0x0054
+#define DRA7XX_RM_L3INIT_MLB_SS_CONTEXT_OFFSET			0x005c
+#define DRA7XX_RM_L3INIT_IEEE1500_2_OCP_CONTEXT_OFFSET		0x007c
+#define DRA7XX_PM_L3INIT_SATA_WKDEP_OFFSET			0x0088
+#define DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET			0x008c
+#define DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET			0x00d4
+#define DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET		0x00e4
+#define DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET		0x00ec
+#define DRA7XX_PM_L3INIT_USB_OTG_SS1_WKDEP_OFFSET		0x00f0
+#define DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET		0x00f4
+
+/* PRM.L4PER_PRM register offsets */
+#define DRA7XX_PM_L4PER_PWRSTCTRL_OFFSET			0x0000
+#define DRA7XX_PM_L4PER_PWRSTST_OFFSET				0x0004
+#define DRA7XX_RM_L4PER2_L4PER2_CONTEXT_OFFSET			0x000c
+#define DRA7XX_RM_L4PER3_L4PER3_CONTEXT_OFFSET			0x0014
+#define DRA7XX_RM_L4PER2_PRUSS1_CONTEXT_OFFSET			0x001c
+#define DRA7XX_RM_L4PER2_PRUSS2_CONTEXT_OFFSET			0x0024
+#define DRA7XX_PM_L4PER_TIMER10_WKDEP_OFFSET			0x0028
+#define DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET			0x002c
+#define DRA7XX_PM_L4PER_TIMER11_WKDEP_OFFSET			0x0030
+#define DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET			0x0034
+#define DRA7XX_PM_L4PER_TIMER2_WKDEP_OFFSET			0x0038
+#define DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET			0x003c
+#define DRA7XX_PM_L4PER_TIMER3_WKDEP_OFFSET			0x0040
+#define DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET			0x0044
+#define DRA7XX_PM_L4PER_TIMER4_WKDEP_OFFSET			0x0048
+#define DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET			0x004c
+#define DRA7XX_PM_L4PER_TIMER9_WKDEP_OFFSET			0x0050
+#define DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET			0x0054
+#define DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET			0x005c
+#define DRA7XX_PM_L4PER_GPIO2_WKDEP_OFFSET			0x0060
+#define DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET			0x0064
+#define DRA7XX_PM_L4PER_GPIO3_WKDEP_OFFSET			0x0068
+#define DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET			0x006c
+#define DRA7XX_PM_L4PER_GPIO4_WKDEP_OFFSET			0x0070
+#define DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET			0x0074
+#define DRA7XX_PM_L4PER_GPIO5_WKDEP_OFFSET			0x0078
+#define DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET			0x007c
+#define DRA7XX_PM_L4PER_GPIO6_WKDEP_OFFSET			0x0080
+#define DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET			0x0084
+#define DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET			0x008c
+#define DRA7XX_RM_L4PER2_PWMSS2_CONTEXT_OFFSET			0x0094
+#define DRA7XX_RM_L4PER2_PWMSS3_CONTEXT_OFFSET			0x009c
+#define DRA7XX_PM_L4PER_I2C1_WKDEP_OFFSET			0x00a0
+#define DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET			0x00a4
+#define DRA7XX_PM_L4PER_I2C2_WKDEP_OFFSET			0x00a8
+#define DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET			0x00ac
+#define DRA7XX_PM_L4PER_I2C3_WKDEP_OFFSET			0x00b0
+#define DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET			0x00b4
+#define DRA7XX_PM_L4PER_I2C4_WKDEP_OFFSET			0x00b8
+#define DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET			0x00bc
+#define DRA7XX_RM_L4PER_L4PER1_CONTEXT_OFFSET			0x00c0
+#define DRA7XX_RM_L4PER2_PWMSS1_CONTEXT_OFFSET			0x00c4
+#define DRA7XX_PM_L4PER_TIMER13_WKDEP_OFFSET			0x00c8
+#define DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET			0x00cc
+#define DRA7XX_PM_L4PER_TIMER14_WKDEP_OFFSET			0x00d0
+#define DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET			0x00d4
+#define DRA7XX_PM_L4PER_TIMER15_WKDEP_OFFSET			0x00d8
+#define DRA7XX_RM_L4PER3_TIMER15_CONTEXT_OFFSET			0x00dc
+#define DRA7XX_PM_L4PER_MCSPI1_WKDEP_OFFSET			0x00f0
+#define DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET			0x00f4
+#define DRA7XX_PM_L4PER_MCSPI2_WKDEP_OFFSET			0x00f8
+#define DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET			0x00fc
+#define DRA7XX_PM_L4PER_MCSPI3_WKDEP_OFFSET			0x0100
+#define DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET			0x0104
+#define DRA7XX_PM_L4PER_MCSPI4_WKDEP_OFFSET			0x0108
+#define DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET			0x010c
+#define DRA7XX_PM_L4PER_GPIO7_WKDEP_OFFSET			0x0110
+#define DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET			0x0114
+#define DRA7XX_PM_L4PER_GPIO8_WKDEP_OFFSET			0x0118
+#define DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET			0x011c
+#define DRA7XX_PM_L4PER_MMC3_WKDEP_OFFSET			0x0120
+#define DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET			0x0124
+#define DRA7XX_PM_L4PER_MMC4_WKDEP_OFFSET			0x0128
+#define DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET			0x012c
+#define DRA7XX_PM_L4PER_TIMER16_WKDEP_OFFSET			0x0130
+#define DRA7XX_RM_L4PER3_TIMER16_CONTEXT_OFFSET			0x0134
+#define DRA7XX_PM_L4PER2_QSPI_WKDEP_OFFSET			0x0138
+#define DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET			0x013c
+#define DRA7XX_PM_L4PER_UART1_WKDEP_OFFSET			0x0140
+#define DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET			0x0144
+#define DRA7XX_PM_L4PER_UART2_WKDEP_OFFSET			0x0148
+#define DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET			0x014c
+#define DRA7XX_PM_L4PER_UART3_WKDEP_OFFSET			0x0150
+#define DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET			0x0154
+#define DRA7XX_PM_L4PER_UART4_WKDEP_OFFSET			0x0158
+#define DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET			0x015c
+#define DRA7XX_PM_L4PER2_MCASP2_WKDEP_OFFSET			0x0160
+#define DRA7XX_RM_L4PER2_MCASP2_CONTEXT_OFFSET			0x0164
+#define DRA7XX_PM_L4PER2_MCASP3_WKDEP_OFFSET			0x0168
+#define DRA7XX_RM_L4PER2_MCASP3_CONTEXT_OFFSET			0x016c
+#define DRA7XX_PM_L4PER_UART5_WKDEP_OFFSET			0x0170
+#define DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET			0x0174
+#define DRA7XX_PM_L4PER2_MCASP5_WKDEP_OFFSET			0x0178
+#define DRA7XX_RM_L4PER2_MCASP5_CONTEXT_OFFSET			0x017c
+#define DRA7XX_PM_L4PER2_MCASP6_WKDEP_OFFSET			0x0180
+#define DRA7XX_RM_L4PER2_MCASP6_CONTEXT_OFFSET			0x0184
+#define DRA7XX_PM_L4PER2_MCASP7_WKDEP_OFFSET			0x0188
+#define DRA7XX_RM_L4PER2_MCASP7_CONTEXT_OFFSET			0x018c
+#define DRA7XX_PM_L4PER2_MCASP8_WKDEP_OFFSET			0x0190
+#define DRA7XX_RM_L4PER2_MCASP8_CONTEXT_OFFSET			0x0194
+#define DRA7XX_PM_L4PER2_MCASP4_WKDEP_OFFSET			0x0198
+#define DRA7XX_RM_L4PER2_MCASP4_CONTEXT_OFFSET			0x019c
+#define DRA7XX_RM_L4SEC_AES1_CONTEXT_OFFSET			0x01a4
+#define DRA7XX_RM_L4SEC_AES2_CONTEXT_OFFSET			0x01ac
+#define DRA7XX_RM_L4SEC_DES3DES_CONTEXT_OFFSET			0x01b4
+#define DRA7XX_RM_L4SEC_FPKA_CONTEXT_OFFSET			0x01bc
+#define DRA7XX_RM_L4SEC_RNG_CONTEXT_OFFSET			0x01c4
+#define DRA7XX_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET			0x01cc
+#define DRA7XX_PM_L4PER2_UART7_WKDEP_OFFSET			0x01d0
+#define DRA7XX_RM_L4PER2_UART7_CONTEXT_OFFSET			0x01d4
+#define DRA7XX_RM_L4SEC_DMA_CRYPTO_CONTEXT_OFFSET		0x01dc
+#define DRA7XX_PM_L4PER2_UART8_WKDEP_OFFSET			0x01e0
+#define DRA7XX_RM_L4PER2_UART8_CONTEXT_OFFSET			0x01e4
+#define DRA7XX_PM_L4PER2_UART9_WKDEP_OFFSET			0x01e8
+#define DRA7XX_RM_L4PER2_UART9_CONTEXT_OFFSET			0x01ec
+#define DRA7XX_PM_L4PER2_DCAN2_WKDEP_OFFSET			0x01f0
+#define DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET			0x01f4
+#define DRA7XX_RM_L4SEC_SHA2MD52_CONTEXT_OFFSET			0x01fc
+
+/* PRM.CUSTEFUSE_PRM register offsets */
+#define DRA7XX_PM_CUSTEFUSE_PWRSTCTRL_OFFSET			0x0000
+#define DRA7XX_PM_CUSTEFUSE_PWRSTST_OFFSET			0x0004
+#define DRA7XX_RM_CUSTEFUSE_EFUSE_CTRL_CUST_CONTEXT_OFFSET	0x0024
+
+/* PRM.WKUPAON_PRM register offsets */
+#define DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET		0x0000
+#define DRA7XX_PM_WKUPAON_WD_TIMER1_WKDEP_OFFSET		0x0004
+#define DRA7XX_RM_WKUPAON_WD_TIMER1_CONTEXT_OFFSET		0x0008
+#define DRA7XX_PM_WKUPAON_WD_TIMER2_WKDEP_OFFSET		0x000c
+#define DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET		0x0010
+#define DRA7XX_PM_WKUPAON_GPIO1_WKDEP_OFFSET			0x0014
+#define DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET			0x0018
+#define DRA7XX_PM_WKUPAON_TIMER1_WKDEP_OFFSET			0x001c
+#define DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET			0x0020
+#define DRA7XX_PM_WKUPAON_TIMER12_WKDEP_OFFSET			0x0024
+#define DRA7XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET		0x0028
+#define DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET		0x0030
+#define DRA7XX_RM_WKUPAON_SAR_RAM_CONTEXT_OFFSET		0x0040
+#define DRA7XX_PM_WKUPAON_KBD_WKDEP_OFFSET			0x0054
+#define DRA7XX_RM_WKUPAON_KBD_CONTEXT_OFFSET			0x0058
+#define DRA7XX_PM_WKUPAON_UART10_WKDEP_OFFSET			0x005c
+#define DRA7XX_RM_WKUPAON_UART10_CONTEXT_OFFSET			0x0060
+#define DRA7XX_PM_WKUPAON_DCAN1_WKDEP_OFFSET			0x0064
+#define DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET			0x0068
+#define DRA7XX_PM_WKUPAON_ADC_WKDEP_OFFSET				0x007c
+#define DRA7XX_RM_WKUPAON_ADC_CONTEXT_OFFSET			0x0080
+#define DRA7XX_RM_WKUPAON_SPARE_SAFETY1_CONTEXT_OFFSET		0x0090
+#define DRA7XX_RM_WKUPAON_SPARE_SAFETY2_CONTEXT_OFFSET		0x0098
+#define DRA7XX_RM_WKUPAON_SPARE_SAFETY3_CONTEXT_OFFSET		0x00a0
+#define DRA7XX_RM_WKUPAON_SPARE_SAFETY4_CONTEXT_OFFSET		0x00a8
+#define DRA7XX_RM_WKUPAON_SPARE_UNKNOWN2_CONTEXT_OFFSET		0x00b0
+#define DRA7XX_RM_WKUPAON_SPARE_UNKNOWN3_CONTEXT_OFFSET		0x00b8
+
+/* PRM.WKUPAON_CM register offsets */
+#define DRA7XX_CM_WKUPAON_CLKSTCTRL_OFFSET			0x0000
+#define DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET		0x0020
+#define DRA7XX_CM_WKUPAON_WD_TIMER1_CLKCTRL_OFFSET		0x0028
+#define DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET		0x0030
+#define DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET			0x0038
+#define DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET			0x0040
+#define DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET		0x0048
+#define DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET		0x0050
+#define DRA7XX_CM_WKUPAON_SAR_RAM_CLKCTRL_OFFSET		0x0060
+#define DRA7XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET			0x0078
+#define DRA7XX_CM_WKUPAON_UART10_CLKCTRL_OFFSET			0x0080
+#define DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET			0x0088
+#define DRA7XX_CM_WKUPAON_SCRM_CLKCTRL_OFFSET			0x0090
+#define DRA7XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL_OFFSET		0x0098
+#define DRA7XX_CM_WKUPAON_ADC_CLKCTRL_OFFSET			0x00a0
+#define DRA7XX_CM_WKUPAON_SPARE_SAFETY1_CLKCTRL_OFFSET		0x00b0
+#define DRA7XX_CM_WKUPAON_SPARE_SAFETY2_CLKCTRL_OFFSET		0x00b8
+#define DRA7XX_CM_WKUPAON_SPARE_SAFETY3_CLKCTRL_OFFSET		0x00c0
+#define DRA7XX_CM_WKUPAON_SPARE_SAFETY4_CLKCTRL_OFFSET		0x00c8
+#define DRA7XX_CM_WKUPAON_SPARE_UNKNOWN2_CLKCTRL_OFFSET		0x00d0
+#define DRA7XX_CM_WKUPAON_SPARE_UNKNOWN3_CLKCTRL_OFFSET		0x00d8
+
+/* PRM.EMU_PRM register offsets */
+#define DRA7XX_PM_EMU_PWRSTCTRL_OFFSET				0x0000
+#define DRA7XX_PM_EMU_PWRSTST_OFFSET				0x0004
+#define DRA7XX_RM_EMU_DEBUGSS_CONTEXT_OFFSET			0x0024
+
+/* PRM.EMU_CM register offsets */
+#define DRA7XX_CM_EMU_CLKSTCTRL_OFFSET				0x0000
+#define DRA7XX_CM_EMU_DEBUGSS_CLKCTRL_OFFSET			0x0004
+#define DRA7XX_CM_EMU_DYNAMICDEP_OFFSET				0x0008
+#define DRA7XX_CM_EMU_MPU_EMU_DBG_CLKCTRL_OFFSET		0x000c
+
+/* PRM.DSP2_PRM register offsets */
+#define DRA7XX_PM_DSP2_PWRSTCTRL_OFFSET				0x0000
+#define DRA7XX_PM_DSP2_PWRSTST_OFFSET				0x0004
+#define DRA7XX_RM_DSP2_RSTCTRL_OFFSET				0x0010
+#define DRA7XX_RM_DSP2_RSTST_OFFSET				0x0014
+#define DRA7XX_RM_DSP2_DSP2_CONTEXT_OFFSET			0x0024
+
+/* PRM.EVE1_PRM register offsets */
+#define DRA7XX_PM_EVE1_PWRSTCTRL_OFFSET				0x0000
+#define DRA7XX_PM_EVE1_PWRSTST_OFFSET				0x0004
+#define DRA7XX_RM_EVE1_RSTCTRL_OFFSET				0x0010
+#define DRA7XX_RM_EVE1_RSTST_OFFSET				0x0014
+#define DRA7XX_PM_EVE1_EVE1_WKDEP_OFFSET			0x0020
+#define DRA7XX_RM_EVE1_EVE1_CONTEXT_OFFSET			0x0024
+
+/* PRM.EVE2_PRM register offsets */
+#define DRA7XX_PM_EVE2_PWRSTCTRL_OFFSET				0x0000
+#define DRA7XX_PM_EVE2_PWRSTST_OFFSET				0x0004
+#define DRA7XX_RM_EVE2_RSTCTRL_OFFSET				0x0010
+#define DRA7XX_RM_EVE2_RSTST_OFFSET				0x0014
+#define DRA7XX_PM_EVE2_EVE2_WKDEP_OFFSET			0x0020
+#define DRA7XX_RM_EVE2_EVE2_CONTEXT_OFFSET			0x0024
+
+/* PRM.EVE3_PRM register offsets */
+#define DRA7XX_PM_EVE3_PWRSTCTRL_OFFSET				0x0000
+#define DRA7XX_PM_EVE3_PWRSTST_OFFSET				0x0004
+#define DRA7XX_RM_EVE3_RSTCTRL_OFFSET				0x0010
+#define DRA7XX_RM_EVE3_RSTST_OFFSET				0x0014
+#define DRA7XX_PM_EVE3_EVE3_WKDEP_OFFSET			0x0020
+#define DRA7XX_RM_EVE3_EVE3_CONTEXT_OFFSET			0x0024
+
+/* PRM.EVE4_PRM register offsets */
+#define DRA7XX_PM_EVE4_PWRSTCTRL_OFFSET				0x0000
+#define DRA7XX_PM_EVE4_PWRSTST_OFFSET				0x0004
+#define DRA7XX_RM_EVE4_RSTCTRL_OFFSET				0x0010
+#define DRA7XX_RM_EVE4_RSTST_OFFSET				0x0014
+#define DRA7XX_PM_EVE4_EVE4_WKDEP_OFFSET			0x0020
+#define DRA7XX_RM_EVE4_EVE4_CONTEXT_OFFSET			0x0024
+
+/* PRM.RTC_PRM register offsets */
+#define DRA7XX_PM_RTC_RTCSS_WKDEP_OFFSET			0x0000
+#define DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET			0x0004
+
+/* PRM.VPE_PRM register offsets */
+#define DRA7XX_PM_VPE_PWRSTCTRL_OFFSET				0x0000
+#define DRA7XX_PM_VPE_PWRSTST_OFFSET				0x0004
+#define DRA7XX_PM_VPE_VPE_WKDEP_OFFSET				0x0020
+#define DRA7XX_RM_VPE_VPE_CONTEXT_OFFSET			0x0024
+
+/* PRM.DEVICE_PRM register offsets */
+#define DRA7XX_PRM_RSTCTRL_OFFSET				0x0000
+#define DRA7XX_PRM_RSTST_OFFSET					0x0004
+#define DRA7XX_PRM_RSTTIME_OFFSET				0x0008
+#define DRA7XX_PRM_CLKREQCTRL_OFFSET				0x000c
+#define DRA7XX_PRM_VOLTCTRL_OFFSET				0x0010
+#define DRA7XX_PRM_PWRREQCTRL_OFFSET				0x0014
+#define DRA7XX_PRM_PSCON_COUNT_OFFSET				0x0018
+#define DRA7XX_PRM_IO_COUNT_OFFSET				0x001c
+#define DRA7XX_PRM_IO_PMCTRL_OFFSET				0x0020
+#define DRA7XX_PRM_VOLTSETUP_WARMRESET_OFFSET			0x0024
+#define DRA7XX_PRM_VOLTSETUP_CORE_OFF_OFFSET			0x0028
+#define DRA7XX_PRM_VOLTSETUP_MPU_OFF_OFFSET			0x002c
+#define DRA7XX_PRM_VOLTSETUP_MM_OFF_OFFSET			0x0030
+#define DRA7XX_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET		0x0034
+#define DRA7XX_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET		0x0038
+#define DRA7XX_PRM_VOLTSETUP_MM_RET_SLEEP_OFFSET		0x003c
+#define DRA7XX_PRM_SRAM_COUNT_OFFSET				0x00bc
+#define DRA7XX_PRM_SRAM_WKUP_SETUP_OFFSET			0x00c0
+#define DRA7XX_PRM_SLDO_CORE_SETUP_OFFSET			0x00c4
+#define DRA7XX_PRM_SLDO_CORE_CTRL_OFFSET			0x00c8
+#define DRA7XX_PRM_SLDO_MPU_SETUP_OFFSET			0x00cc
+#define DRA7XX_PRM_SLDO_MPU_CTRL_OFFSET				0x00d0
+#define DRA7XX_PRM_SLDO_GPU_SETUP_OFFSET			0x00d4
+#define DRA7XX_PRM_SLDO_GPU_CTRL_OFFSET				0x00d8
+#define DRA7XX_PRM_ABBLDO_MPU_SETUP_OFFSET			0x00dc
+#define DRA7XX_PRM_ABBLDO_MPU_CTRL_OFFSET			0x00e0
+#define DRA7XX_PRM_ABBLDO_GPU_SETUP_OFFSET			0x00e4
+#define DRA7XX_PRM_ABBLDO_GPU_CTRL_OFFSET			0x00e8
+#define DRA7XX_PRM_BANDGAP_SETUP_OFFSET				0x00ec
+#define DRA7XX_PRM_DEVICE_OFF_CTRL_OFFSET			0x00f0
+#define DRA7XX_PRM_PHASE1_CNDP_OFFSET				0x00f4
+#define DRA7XX_PRM_PHASE2A_CNDP_OFFSET				0x00f8
+#define DRA7XX_PRM_PHASE2B_CNDP_OFFSET				0x00fc
+#define DRA7XX_PRM_MODEM_IF_CTRL_OFFSET				0x0100
+#define DRA7XX_PRM_VOLTST_MPU_OFFSET				0x0110
+#define DRA7XX_PRM_VOLTST_MM_OFFSET				0x0114
+#define DRA7XX_PRM_SLDO_DSPEVE_SETUP_OFFSET			0x0118
+#define DRA7XX_PRM_SLDO_IVA_SETUP_OFFSET			0x011c
+#define DRA7XX_PRM_ABBLDO_DSPEVE_CTRL_OFFSET			0x0120
+#define DRA7XX_PRM_ABBLDO_IVA_CTRL_OFFSET			0x0124
+#define DRA7XX_PRM_SLDO_DSPEVE_CTRL_OFFSET			0x0128
+#define DRA7XX_PRM_SLDO_IVA_CTRL_OFFSET				0x012c
+#define DRA7XX_PRM_ABBLDO_DSPEVE_SETUP_OFFSET			0x0130
+#define DRA7XX_PRM_ABBLDO_IVA_SETUP_OFFSET			0x0134
+
+#endif
-- 
1.7.9.5

[PATCH 43/55] ARM: OMAP4: PRM: get rid of prminst44xx.h header file

[Tero Kristo]

Only contains a few function prototypes, so move these to the public
prm44xx.h header and remove the now unnecessary prminst44xx.h.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/io.c                      |    1 -
 arch/arm/mach-omap2/omap-mpuss-lowpower.c     |    1 -
 arch/arm/mach-omap2/omap4-common.c            |    1 -
 arch/arm/mach-omap2/omap4-restart.c           |    2 +-
 arch/arm/mach-omap2/omap_hwmod.c              |    1 -
 arch/arm/mach-omap2/prminst44xx.c             |    1 -
 arch/arm/mach-omap2/prminst44xx.h             |   27 -------------------------
 arch/arm/mach-omap2/prminst44xx_private.h     |    2 +-
 arch/arm/mach-omap2/voltage.c                 |    1 -
 arch/arm/mach-omap2/voltagedomains44xx_data.c |    1 -
 include/linux/power/omap/prm44xx.h            |   12 +++++++++++
 11 files changed, 14 insertions(+), 36 deletions(-)
 delete mode 100644 arch/arm/mach-omap2/prminst44xx.h

diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index ed677bb..96d498f 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -48,7 +48,6 @@
 #include "prm.h"
 #include <linux/power/omap/cm.h>
 #include "prcm_mpu44xx.h"
-#include "prminst44xx.h"
 #include <linux/power/omap/cm44xx.h>
 #include "prm2xxx.h"
 #include "prm3xxx.h"
diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
index 4b1b059..50127e1 100644
--- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
+++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
@@ -57,7 +57,6 @@
 #include "omap4-sar-layout.h"
 #include "pm.h"
 #include "prcm_mpu44xx.h"
-#include "prminst44xx.h"
 #include "prcm44xx.h"
 #include "prm44xx.h"
 #include "prm-regbits-44xx.h"
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index 6cd3f37..54e054a 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -35,7 +35,6 @@
 #include "iomap.h"
 #include "common.h"
 #include "mmc.h"
-#include "prminst44xx.h"
 #include "prcm_mpu44xx.h"
 #include "omap4-sar-layout.h"
 #include "omap-secure.h"
diff --git a/arch/arm/mach-omap2/omap4-restart.c b/arch/arm/mach-omap2/omap4-restart.c
index 41dfd7d..f0102d1 100644
--- a/arch/arm/mach-omap2/omap4-restart.c
+++ b/arch/arm/mach-omap2/omap4-restart.c
@@ -9,7 +9,7 @@
 
 #include <linux/types.h>
 #include <linux/reboot.h>
-#include "prminst44xx.h"
+#include <linux/power/omap/prm44xx.h>
 
 /**
  * omap44xx_restart - trigger a software restart of the SoC
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 4576f0b..096c43d 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -159,7 +159,6 @@
 #include "prm3xxx.h"
 #include "prm44xx.h"
 #include "prm33xx.h"
-#include "prminst44xx.h"
 #include "mux.h"
 #include "pm.h"
 
diff --git a/arch/arm/mach-omap2/prminst44xx.c b/arch/arm/mach-omap2/prminst44xx.c
index feb508f..01f6b15 100644
--- a/arch/arm/mach-omap2/prminst44xx.c
+++ b/arch/arm/mach-omap2/prminst44xx.c
@@ -21,7 +21,6 @@
 #include <linux/power/omap/prm44xx.h>
 #include <linux/power/omap/prm54xx.h>
 #include <linux/power/omap/prm7xx.h>
-#include "prminst44xx.h"
 #include "prcm44xx.h"
 #include "prcm_mpu44xx.h"
 
diff --git a/arch/arm/mach-omap2/prminst44xx.h b/arch/arm/mach-omap2/prminst44xx.h
deleted file mode 100644
index fec8f18..0000000
--- a/arch/arm/mach-omap2/prminst44xx.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * OMAP4 Power/Reset Management (PRM) function prototypes
- *
- * Copyright (C) 2010 Nokia Corporation
- * Copyright (C) 2011 Texas Instruments, Inc.
- * Paul Walmsley
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __ARCH_ASM_MACH_OMAP2_PRMINST44XX_H
-#define __ARCH_ASM_MACH_OMAP2_PRMINST44XX_H
-
-extern void omap4_prminst_global_warm_sw_reset(void);
-
-extern int omap4_prminst_is_hardreset_asserted(u8 shift, u8 part, s16 inst,
-					       u16 rstctrl_offs);
-extern int omap4_prminst_assert_hardreset(u8 shift, u8 part, s16 inst,
-					  u16 rstctrl_offs);
-extern int omap4_prminst_deassert_hardreset(u8 shift, u8 part, s16 inst,
-					    u16 rstctrl_offs);
-void omap4_prminst_mpuss_clear_prev_logic_pwrst(void);
-
-extern void omap_prm_base_init(void);
-
-#endif
diff --git a/arch/arm/mach-omap2/prminst44xx_private.h b/arch/arm/mach-omap2/prminst44xx_private.h
index 59a6e55..5db33b7 100644
--- a/arch/arm/mach-omap2/prminst44xx_private.h
+++ b/arch/arm/mach-omap2/prminst44xx_private.h
@@ -12,7 +12,7 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_PRMINST44XX_PRIVATE_H
 #define __ARCH_ARM_MACH_OMAP2_PRMINST44XX_PRIVATE_H
 
-#include "prminst44xx.h"
+#include <linux/power/omap/prm44xx.h>
 
 /*
  * In an ideal world, we would not export these low-level functions,
diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
index 3ac8fe1..78f5a68 100644
--- a/arch/arm/mach-omap2/voltage.c
+++ b/arch/arm/mach-omap2/voltage.c
@@ -33,7 +33,6 @@
 #include "prm-regbits-44xx.h"
 #include "prm44xx.h"
 #include "prcm44xx.h"
-#include "prminst44xx.h"
 #include "control.h"
 
 #include "voltage.h"
diff --git a/arch/arm/mach-omap2/voltagedomains44xx_data.c b/arch/arm/mach-omap2/voltagedomains44xx_data.c
index 48b22a0..479b412 100644
--- a/arch/arm/mach-omap2/voltagedomains44xx_data.c
+++ b/arch/arm/mach-omap2/voltagedomains44xx_data.c
@@ -26,7 +26,6 @@
 #include "prm-regbits-44xx.h"
 #include "prm44xx.h"
 #include "prcm44xx.h"
-#include "prminst44xx.h"
 #include "voltage.h"
 #include "omap_opp_data.h"
 #include "vc.h"
diff --git a/include/linux/power/omap/prm44xx.h b/include/linux/power/omap/prm44xx.h
index e5cd9f3..3c5852e 100644
--- a/include/linux/power/omap/prm44xx.h
+++ b/include/linux/power/omap/prm44xx.h
@@ -417,4 +417,16 @@
 #define OMAP4_PRM_MODEM_IF_CTRL_OFFSET			0x00f4
 #define OMAP4_PRM_VC_ERRST_OFFSET			0x00f8
 
+#ifndef __ASSEMBLER__
+void omap4_prminst_global_warm_sw_reset(void);
+int omap4_prminst_is_hardreset_asserted(u8 shift, u8 part, s16 inst,
+					u16 rstctrl_offs);
+int omap4_prminst_assert_hardreset(u8 shift, u8 part, s16 inst,
+				   u16 rstctrl_offs);
+int omap4_prminst_deassert_hardreset(u8 shift, u8 part, s16 inst,
+				     u16 rstctrl_offs);
+void omap4_prminst_mpuss_clear_prev_logic_pwrst(void);
+void omap_prm_base_init(void);
+#endif
+
 #endif
-- 
1.7.9.5

[PATCH 44/55] ARM: OMAP4: PRM: make omap4_prm_read/write_inst_reg calls static

[Tero Kristo]

These are not (and should not be) used by anybody outside the PRM
driver itself.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/prm44xx.c      |    6 +++---
 arch/arm/mach-omap2/prm44xx_54xx.h |    4 ----
 2 files changed, 3 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index a80e8b5..f1f3e78 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -115,19 +115,19 @@ static struct prm_reset_src_map omap44xx_prm_reset_src_map[] = {
 /* PRM low-level functions */
 
 /* Read a register in a CM/PRM instance in the PRM module */
-u32 omap4_prm_read_inst_reg(s16 inst, u16 reg)
+static u32 omap4_prm_read_inst_reg(s16 inst, u16 reg)
 {
 	return __raw_readl(prm_base + inst + reg);
 }
 
 /* Write into a register in a CM/PRM instance in the PRM module */
-void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 reg)
+static void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 reg)
 {
 	__raw_writel(val, prm_base + inst + reg);
 }
 
 /* Read-modify-write a register in a PRM module. Caller must lock */
-u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg)
+static u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg)
 {
 	u32 v;
 
diff --git a/arch/arm/mach-omap2/prm44xx_54xx.h b/arch/arm/mach-omap2/prm44xx_54xx.h
index 73734b2..4b36d3d 100644
--- a/arch/arm/mach-omap2/prm44xx_54xx.h
+++ b/arch/arm/mach-omap2/prm44xx_54xx.h
@@ -26,10 +26,6 @@
 /* Function prototypes */
 #ifndef __ASSEMBLER__
 
-extern u32 omap4_prm_read_inst_reg(s16 inst, u16 idx);
-extern void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 idx);
-extern u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
-
 /* OMAP4/OMAP5-specific VP functions */
 u32 omap4_prm_vp_check_txdone(u8 vp_id);
 void omap4_prm_vp_clear_txdone(u8 vp_id);
-- 
1.7.9.5

[PATCH 45/55] ARM: OMAP4: PRM: move prm44xx_54xx.h header to public location

[Tero Kristo]

This file needs to be accessible from the PRCM core and mach-omap2 board
support code.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/prm44xx.c           |    2 +-
 arch/arm/mach-omap2/prm44xx.h           |    2 +-
 arch/arm/mach-omap2/prm44xx_54xx.h      |   61 -------------------------------
 arch/arm/mach-omap2/prm54xx.h           |    2 +-
 arch/arm/mach-omap2/prm7xx.h            |    2 +-
 include/linux/power/omap/prm44xx_54xx.h |   61 +++++++++++++++++++++++++++++++
 6 files changed, 65 insertions(+), 65 deletions(-)
 delete mode 100644 arch/arm/mach-omap2/prm44xx_54xx.h
 create mode 100644 include/linux/power/omap/prm44xx_54xx.h

diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index f1f3e78..7cbb35f 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -28,7 +28,7 @@
 #include "powerdomain.h"
 #include "prm.h"
 #include "prcm-common.h"
-#include "prm44xx_54xx.h"
+#include <linux/power/omap/prm44xx_54xx.h>
 
 #define OMAP4430_GLOBAL_COLD_RST_SHIFT			0
 #define OMAP4430_GLOBAL_WARM_SW_RST_SHIFT		1
diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h
index 1f7a3a6..52585e1 100644
--- a/arch/arm/mach-omap2/prm44xx.h
+++ b/arch/arm/mach-omap2/prm44xx.h
@@ -25,7 +25,7 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_PRM44XX_H
 #define __ARCH_ARM_MACH_OMAP2_PRM44XX_H
 
-#include "prm44xx_54xx.h"
+#include <linux/power/omap/prm44xx_54xx.h>
 #include "prcm-common.h"
 #include "prm.h"
 #include <linux/power/omap/prm44xx.h>
diff --git a/arch/arm/mach-omap2/prm44xx_54xx.h b/arch/arm/mach-omap2/prm44xx_54xx.h
deleted file mode 100644
index 4b36d3d..0000000
--- a/arch/arm/mach-omap2/prm44xx_54xx.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * OMAP44xx and 54xx PRM common functions
- *
- * Copyright (C) 2009-2013 Texas Instruments, Inc.
- * Copyright (C) 2009-2010 Nokia Corporation
- *
- * Paul Walmsley (paul@pwsan.com)
- * Rajendra Nayak (rnayak@ti.com)
- * Benoit Cousson (b-cousson@ti.com)
- *
- * This file is automatically generated from the OMAP hardware databases.
- * We respectfully ask that any modifications to this file be coordinated
- * with the public linux-omap@vger.kernel.org mailing list and the
- * authors above to ensure that the autogeneration scripts are kept
- * up-to-date with the file contents.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef __ARCH_ARM_MACH_OMAP2_PRM44XX_54XX_H
-#define __ARCH_ARM_MACH_OMAP2_PRM44XX_54XX_H
-
-/* Function prototypes */
-#ifndef __ASSEMBLER__
-
-/* OMAP4/OMAP5-specific VP functions */
-u32 omap4_prm_vp_check_txdone(u8 vp_id);
-void omap4_prm_vp_clear_txdone(u8 vp_id);
-
-/*
- * OMAP4/OMAP5 access functions for voltage controller (VC) and
- * voltage proccessor (VP) in the PRM.
- */
-extern u32 omap4_prm_vcvp_read(u8 offset);
-extern void omap4_prm_vcvp_write(u32 val, u8 offset);
-extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
-
-#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
-	defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM43XX)
-void omap44xx_prm_reconfigure_io_chain(void);
-#else
-static inline void omap44xx_prm_reconfigure_io_chain(void)
-{
-}
-#endif
-
-/* PRM interrupt-related functions */
-extern void omap44xx_prm_read_pending_irqs(unsigned long *events);
-extern void omap44xx_prm_ocp_barrier(void);
-extern void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask);
-extern void omap44xx_prm_restore_irqen(u32 *saved_mask);
-
-int __init omap44xx_prm_init(u16 cpu_type);
-extern u32 omap44xx_prm_get_reset_sources(void);
-
-#endif
-
-#endif
diff --git a/arch/arm/mach-omap2/prm54xx.h b/arch/arm/mach-omap2/prm54xx.h
index 64d0859..34a0835 100644
--- a/arch/arm/mach-omap2/prm54xx.h
+++ b/arch/arm/mach-omap2/prm54xx.h
@@ -21,7 +21,7 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_PRM54XX_H
 #define __ARCH_ARM_MACH_OMAP2_PRM54XX_H
 
-#include "prm44xx_54xx.h"
+#include <linux/power/omap/prm44xx_54xx.h>
 #include "prcm-common.h"
 #include "prm.h"
 #include <linux/power/omap/prm54xx.h>
diff --git a/arch/arm/mach-omap2/prm7xx.h b/arch/arm/mach-omap2/prm7xx.h
index c6dc341..2637d62 100644
--- a/arch/arm/mach-omap2/prm7xx.h
+++ b/arch/arm/mach-omap2/prm7xx.h
@@ -22,7 +22,7 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_PRM7XX_H
 #define __ARCH_ARM_MACH_OMAP2_PRM7XX_H
 
-#include "prm44xx_54xx.h"
+#include <linux/power/omap/prm44xx_54xx.h>
 #include "prcm-common.h"
 #include "prm.h"
 #include <linux/power/omap/prm7xx.h>
diff --git a/include/linux/power/omap/prm44xx_54xx.h b/include/linux/power/omap/prm44xx_54xx.h
new file mode 100644
index 0000000..b6d6d65
--- /dev/null
+++ b/include/linux/power/omap/prm44xx_54xx.h
@@ -0,0 +1,61 @@
+/*
+ * OMAP44xx and 54xx PRM common functions
+ *
+ * Copyright (C) 2009-2013 Texas Instruments, Inc.
+ * Copyright (C) 2009-2010 Nokia Corporation
+ *
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __LINUX_POWER_OMAP_PRM44XX_54XX_H
+#define __LINUX_POWER_OMAP_PRM44XX_54XX_H
+
+/* Function prototypes */
+#ifndef __ASSEMBLER__
+
+/* OMAP4/OMAP5-specific VP functions */
+u32 omap4_prm_vp_check_txdone(u8 vp_id);
+void omap4_prm_vp_clear_txdone(u8 vp_id);
+
+/*
+ * OMAP4/OMAP5 access functions for voltage controller (VC) and
+ * voltage proccessor (VP) in the PRM.
+ */
+u32 omap4_prm_vcvp_read(u8 offset);
+void omap4_prm_vcvp_write(u32 val, u8 offset);
+u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
+
+#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
+	defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM43XX)
+void omap44xx_prm_reconfigure_io_chain(void);
+#else
+static inline void omap44xx_prm_reconfigure_io_chain(void)
+{
+}
+#endif
+
+/* PRM interrupt-related functions */
+void omap44xx_prm_read_pending_irqs(unsigned long *events);
+void omap44xx_prm_ocp_barrier(void);
+void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask);
+void omap44xx_prm_restore_irqen(u32 *saved_mask);
+
+int __init omap44xx_prm_init(u16 cpu_type);
+u32 omap44xx_prm_get_reset_sources(void);
+
+#endif
+
+#endif
-- 
1.7.9.5

[PATCH 46/55] ARM: OMAP3+: VP: move OMAP*_VP_VDD_*_ID definitions to prm public headers

[Tero Kristo]

vp.h is not publicly available, however the PRM driver requires access to
these so moved to prm public headers.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/prm3xxx.c      |    1 -
 arch/arm/mach-omap2/prm44xx.c      |    1 -
 arch/arm/mach-omap2/vp.h           |    9 ---------
 include/linux/power/omap/prm3xxx.h |    3 +++
 include/linux/power/omap/prm44xx.h |    4 ++++
 5 files changed, 7 insertions(+), 11 deletions(-)

diff --git a/arch/arm/mach-omap2/prm3xxx.c b/arch/arm/mach-omap2/prm3xxx.c
index 93f87e1..e7d409c 100644
--- a/arch/arm/mach-omap2/prm3xxx.c
+++ b/arch/arm/mach-omap2/prm3xxx.c
@@ -18,7 +18,6 @@
 #include <linux/io.h>
 #include <linux/irq.h>
 
-#include "vp.h"
 #include "powerdomain.h"
 #include <linux/power/omap/prm3xxx.h>
 #include "prm2xxx_3xxx_private.h"
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index 7cbb35f..2b25710 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -19,7 +19,6 @@
 #include <linux/io.h>
 
 
-#include "vp.h"
 #include <linux/power/omap/prm44xx.h>
 #include <linux/power/omap/prm54xx.h>
 #include <linux/power/omap/prm7xx.h>
diff --git a/arch/arm/mach-omap2/vp.h b/arch/arm/mach-omap2/vp.h
index 0fdf7080..7e08296 100644
--- a/arch/arm/mach-omap2/vp.h
+++ b/arch/arm/mach-omap2/vp.h
@@ -21,15 +21,6 @@
 
 struct voltagedomain;
 
-/*
- * Voltage Processor (VP) identifiers
- */
-#define OMAP3_VP_VDD_MPU_ID 0
-#define OMAP3_VP_VDD_CORE_ID 1
-#define OMAP4_VP_VDD_CORE_ID 0
-#define OMAP4_VP_VDD_IVA_ID 1
-#define OMAP4_VP_VDD_MPU_ID 2
-
 /* XXX document */
 #define VP_IDLE_TIMEOUT		200
 #define VP_TRANXDONE_TIMEOUT	300
diff --git a/include/linux/power/omap/prm3xxx.h b/include/linux/power/omap/prm3xxx.h
index 3bdc372..af39ebd 100644
--- a/include/linux/power/omap/prm3xxx.h
+++ b/include/linux/power/omap/prm3xxx.h
@@ -18,6 +18,9 @@
 
 #include <linux/power/omap/prm2xxx_3xxx.h>
 
+#define OMAP3_VP_VDD_MPU_ID	0
+#define OMAP3_VP_VDD_CORE_ID	1
+
 /*
  * OMAP3-specific global PRM registers
  * Use __raw_{read,write}l() with these registers.
diff --git a/include/linux/power/omap/prm44xx.h b/include/linux/power/omap/prm44xx.h
index 3c5852e..9395c0d 100644
--- a/include/linux/power/omap/prm44xx.h
+++ b/include/linux/power/omap/prm44xx.h
@@ -25,6 +25,10 @@
 #ifndef __LINUX_POWER_OMAP_PRM44XX_H
 #define __LINUX_POWER_OMAP_PRM44XX_H
 
+#define OMAP4_VP_VDD_CORE_ID	0
+#define OMAP4_VP_VDD_IVA_ID	1
+#define OMAP4_VP_VDD_MPU_ID	2
+
 /* PRM instances */
 #define OMAP4430_PRM_OCP_SOCKET_INST	0x0000
 #define OMAP4430_PRM_CKGEN_INST		0x0100
-- 
1.7.9.5

[PATCH 47/55] ARM: OMAP2+: PRM: move prcm-common.h header to public location

[Tero Kristo]

This file needs to be accessible from the PRCM core and mach-omap2 board
support code.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/cm2xxx.c                     |    2 +-
 arch/arm/mach-omap2/cm2xxx.h                     |    2 +-
 arch/arm/mach-omap2/cm33xx.c                     |    2 +-
 arch/arm/mach-omap2/cm3xxx.c                     |    2 +-
 arch/arm/mach-omap2/cm3xxx.h                     |    2 +-
 arch/arm/mach-omap2/cm_common.c                  |    2 +-
 arch/arm/mach-omap2/cminst44xx.c                 |    2 +-
 arch/arm/mach-omap2/pm.c                         |    2 +-
 arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c |    2 +-
 arch/arm/mach-omap2/powerdomains2xxx_data.c      |    2 +-
 arch/arm/mach-omap2/powerdomains33xx_data.c      |    2 +-
 arch/arm/mach-omap2/powerdomains3xxx_data.c      |    2 +-
 arch/arm/mach-omap2/powerdomains43xx_data.c      |    2 +-
 arch/arm/mach-omap2/powerdomains44xx_data.c      |    2 +-
 arch/arm/mach-omap2/powerdomains54xx_data.c      |    2 +-
 arch/arm/mach-omap2/powerdomains7xx_data.c       |    2 +-
 arch/arm/mach-omap2/prcm-common.h                |  537 ----------------------
 arch/arm/mach-omap2/prm.h                        |    2 +-
 arch/arm/mach-omap2/prm2xxx.h                    |    2 +-
 arch/arm/mach-omap2/prm2xxx_3xxx_private.h       |    2 +-
 arch/arm/mach-omap2/prm33xx.h                    |    2 +-
 arch/arm/mach-omap2/prm3xxx.h                    |    2 +-
 arch/arm/mach-omap2/prm44xx.c                    |    2 +-
 arch/arm/mach-omap2/prm44xx.h                    |    2 +-
 arch/arm/mach-omap2/prm54xx.h                    |    2 +-
 arch/arm/mach-omap2/prm7xx.h                     |    2 +-
 arch/arm/mach-omap2/prm_common.c                 |    2 +-
 arch/arm/mach-omap2/prminst44xx.c                |    2 +-
 include/linux/power/omap/prcm-common.h           |  536 +++++++++++++++++++++
 29 files changed, 563 insertions(+), 564 deletions(-)
 delete mode 100644 arch/arm/mach-omap2/prcm-common.h
 create mode 100644 include/linux/power/omap/prcm-common.h

diff --git a/arch/arm/mach-omap2/cm2xxx.c b/arch/arm/mach-omap2/cm2xxx.c
index 2385498..f7365c7 100644
--- a/arch/arm/mach-omap2/cm2xxx.c
+++ b/arch/arm/mach-omap2/cm2xxx.c
@@ -23,7 +23,7 @@
 #include "cm2xxx_3xxx_private.h"
 #include <linux/power/omap/cm2xxx.h>
 #include "clockdomain.h"
-#include "prcm-common.h"
+#include <linux/power/omap/prcm-common.h>
 #include <linux/power/omap/prm2xxx_3xxx.h>
 
 /* CM_AUTOIDLE_PLL.AUTO_* bit values for DPLLs */
diff --git a/arch/arm/mach-omap2/cm2xxx.h b/arch/arm/mach-omap2/cm2xxx.h
index 80e9892..169541e 100644
--- a/arch/arm/mach-omap2/cm2xxx.h
+++ b/arch/arm/mach-omap2/cm2xxx.h
@@ -16,7 +16,7 @@
 #ifndef __ARCH_ASM_MACH_OMAP2_CM2XXX_H
 #define __ARCH_ASM_MACH_OMAP2_CM2XXX_H
 
-#include "prcm-common.h"
+#include <linux/power/omap/prcm-common.h>
 #include <linux/power/omap/cm2xxx_3xxx.h>
 #include <linux/power/omap/cm2xxx.h>
 
diff --git a/arch/arm/mach-omap2/cm33xx.c b/arch/arm/mach-omap2/cm33xx.c
index 43e4f26..1f68cde 100644
--- a/arch/arm/mach-omap2/cm33xx.c
+++ b/arch/arm/mach-omap2/cm33xx.c
@@ -26,7 +26,7 @@
 #include <linux/power/omap/cm.h>
 #include <linux/power/omap/cm33xx.h>
 #include <linux/power/omap/prm33xx.h>
-#include "prcm-common.h"
+#include <linux/power/omap/prcm-common.h>
 
 #define AM33XX_MODULEMODE_SHIFT			0
 #define AM33XX_MODULEMODE_MASK			(0x3 << 0)
diff --git a/arch/arm/mach-omap2/cm3xxx.c b/arch/arm/mach-omap2/cm3xxx.c
index a80cd3e..01c69f2 100644
--- a/arch/arm/mach-omap2/cm3xxx.c
+++ b/arch/arm/mach-omap2/cm3xxx.c
@@ -23,7 +23,7 @@
 #include "cm2xxx_3xxx_private.h"
 #include <linux/power/omap/cm3xxx.h>
 #include "clockdomain.h"
-#include "prcm-common.h"
+#include <linux/power/omap/prcm-common.h>
 
 #define OMAP34XX_CLKSTCTRL_DISABLE_AUTO		0x0
 #define OMAP34XX_CLKSTCTRL_FORCE_SLEEP		0x1
diff --git a/arch/arm/mach-omap2/cm3xxx.h b/arch/arm/mach-omap2/cm3xxx.h
index 5fdc14c..23846ff 100644
--- a/arch/arm/mach-omap2/cm3xxx.h
+++ b/arch/arm/mach-omap2/cm3xxx.h
@@ -16,7 +16,7 @@
 #ifndef __ARCH_ASM_MACH_OMAP2_CM3XXX_H
 #define __ARCH_ASM_MACH_OMAP2_CM3XXX_H
 
-#include "prcm-common.h"
+#include <linux/power/omap/prcm-common.h>
 #include <linux/power/omap/cm2xxx_3xxx.h>
 #include <linux/power/omap/cm3xxx.h>
 
diff --git a/arch/arm/mach-omap2/cm_common.c b/arch/arm/mach-omap2/cm_common.c
index 3843f1f..0a21fa9 100644
--- a/arch/arm/mach-omap2/cm_common.c
+++ b/arch/arm/mach-omap2/cm_common.c
@@ -19,7 +19,7 @@
 #include <linux/power/omap/cm2xxx.h>
 #include <linux/power/omap/cm3xxx.h>
 #include <linux/power/omap/cm.h>
-#include "prcm-common.h"
+#include <linux/power/omap/prcm-common.h>
 
 /*
  * cm_ll_data: function pointers to SoC-specific implementations of
diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c
index 084e5ce..5ebd8e3 100644
--- a/arch/arm/mach-omap2/cminst44xx.c
+++ b/arch/arm/mach-omap2/cminst44xx.c
@@ -30,7 +30,7 @@
 #include "prcm44xx.h"
 #include <linux/power/omap/prm44xx.h>
 #include "prcm_mpu44xx.h"
-#include "prcm-common.h"
+#include <linux/power/omap/prcm-common.h>
 
 #define OMAP4430_IDLEST_SHIFT		16
 #define OMAP4430_IDLEST_MASK		(0x3 << 16)
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index e1b4141..f464aed 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -25,7 +25,7 @@
 #include "common.h"
 
 #include "soc.h"
-#include "prcm-common.h"
+#include <linux/power/omap/prcm-common.h>
 #include "voltage.h"
 #include "powerdomain.h"
 #include "clockdomain.h"
diff --git a/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c b/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c
index 7b946f1..57abec8 100644
--- a/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c
+++ b/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c
@@ -33,7 +33,7 @@
 
 #include "powerdomain.h"
 
-#include "prcm-common.h"
+#include <linux/power/omap/prcm-common.h>
 #include "prm.h"
 
 /* OMAP2/3-common powerdomains */
diff --git a/arch/arm/mach-omap2/powerdomains2xxx_data.c b/arch/arm/mach-omap2/powerdomains2xxx_data.c
index 266bd96..9506c0e 100644
--- a/arch/arm/mach-omap2/powerdomains2xxx_data.c
+++ b/arch/arm/mach-omap2/powerdomains2xxx_data.c
@@ -18,7 +18,7 @@
 #include "powerdomain.h"
 #include "powerdomains2xxx_3xxx_data.h"
 
-#include "prcm-common.h"
+#include <linux/power/omap/prcm-common.h>
 #include <linux/power/omap/prm2xxx_3xxx.h>
 #include "prm-regbits-24xx.h"
 
diff --git a/arch/arm/mach-omap2/powerdomains33xx_data.c b/arch/arm/mach-omap2/powerdomains33xx_data.c
index 869adb8..0a7a5ca 100644
--- a/arch/arm/mach-omap2/powerdomains33xx_data.c
+++ b/arch/arm/mach-omap2/powerdomains33xx_data.c
@@ -17,7 +17,7 @@
 #include <linux/init.h>
 
 #include "powerdomain.h"
-#include "prcm-common.h"
+#include <linux/power/omap/prcm-common.h>
 #include "prm-regbits-33xx.h"
 #include "prm33xx.h"
 
diff --git a/arch/arm/mach-omap2/powerdomains3xxx_data.c b/arch/arm/mach-omap2/powerdomains3xxx_data.c
index 7ba44db..be12876 100644
--- a/arch/arm/mach-omap2/powerdomains3xxx_data.c
+++ b/arch/arm/mach-omap2/powerdomains3xxx_data.c
@@ -18,7 +18,7 @@
 #include "soc.h"
 #include "powerdomain.h"
 #include "powerdomains2xxx_3xxx_data.h"
-#include "prcm-common.h"
+#include <linux/power/omap/prcm-common.h>
 #include <linux/power/omap/prm2xxx_3xxx.h>
 #include "prm-regbits-34xx.h"
 #include <linux/power/omap/cm2xxx_3xxx.h>
diff --git a/arch/arm/mach-omap2/powerdomains43xx_data.c b/arch/arm/mach-omap2/powerdomains43xx_data.c
index 95fee54..b99eac7 100644
--- a/arch/arm/mach-omap2/powerdomains43xx_data.c
+++ b/arch/arm/mach-omap2/powerdomains43xx_data.c
@@ -13,7 +13,7 @@
 
 #include "powerdomain.h"
 
-#include "prcm-common.h"
+#include <linux/power/omap/prcm-common.h>
 #include "prcm44xx.h"
 #include "prcm43xx.h"
 
diff --git a/arch/arm/mach-omap2/powerdomains44xx_data.c b/arch/arm/mach-omap2/powerdomains44xx_data.c
index 704664c..ea1ffc1 100644
--- a/arch/arm/mach-omap2/powerdomains44xx_data.c
+++ b/arch/arm/mach-omap2/powerdomains44xx_data.c
@@ -24,7 +24,7 @@
 
 #include "powerdomain.h"
 
-#include "prcm-common.h"
+#include <linux/power/omap/prcm-common.h>
 #include "prcm44xx.h"
 #include "prm-regbits-44xx.h"
 #include "prm44xx.h"
diff --git a/arch/arm/mach-omap2/powerdomains54xx_data.c b/arch/arm/mach-omap2/powerdomains54xx_data.c
index ce1d752..b4a815b 100644
--- a/arch/arm/mach-omap2/powerdomains54xx_data.c
+++ b/arch/arm/mach-omap2/powerdomains54xx_data.c
@@ -23,7 +23,7 @@
 
 #include "powerdomain.h"
 
-#include "prcm-common.h"
+#include <linux/power/omap/prcm-common.h>
 #include "prcm44xx.h"
 #include "prm54xx.h"
 #include "prcm_mpu54xx.h"
diff --git a/arch/arm/mach-omap2/powerdomains7xx_data.c b/arch/arm/mach-omap2/powerdomains7xx_data.c
index 48151d1..cf33ef6 100644
--- a/arch/arm/mach-omap2/powerdomains7xx_data.c
+++ b/arch/arm/mach-omap2/powerdomains7xx_data.c
@@ -25,7 +25,7 @@
 
 #include "powerdomain.h"
 
-#include "prcm-common.h"
+#include <linux/power/omap/prcm-common.h>
 #include "prcm44xx.h"
 #include "prm7xx.h"
 #include "prcm_mpu7xx.h"
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
deleted file mode 100644
index 1a05d04..0000000
--- a/arch/arm/mach-omap2/prcm-common.h
+++ /dev/null
@@ -1,537 +0,0 @@
-#ifndef __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H
-#define __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H
-
-/*
- * OMAP2/3 PRCM base and module definitions
- *
- * Copyright (C) 2007-2009, 2011 Texas Instruments, Inc.
- * Copyright (C) 2007-2009 Nokia Corporation
- *
- * Written by Paul Walmsley
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-/* Module offsets from both CM_BASE & PRM_BASE */
-
-/*
- * Offsets that are the same on 24xx and 34xx
- *
- * Technically, in terms of the TRM, OCP_MOD is 34xx only; PLL_MOD is
- * CCR_MOD on 3430; and GFX_MOD only exists < 3430ES2.
- */
-#define OCP_MOD						0x000
-#define MPU_MOD						0x100
-#define CORE_MOD					0x200
-#define GFX_MOD						0x300
-#define WKUP_MOD					0x400
-#define PLL_MOD						0x500
-
-
-/* Chip-specific module offsets */
-#define OMAP24XX_GR_MOD					OCP_MOD
-#define OMAP24XX_DSP_MOD				0x800
-
-#define OMAP2430_MDM_MOD				0xc00
-
-/* IVA2 module is < base on 3430 */
-#define OMAP3430_IVA2_MOD				-0x800
-#define OMAP3430ES2_SGX_MOD				GFX_MOD
-#define OMAP3430_CCR_MOD				PLL_MOD
-#define OMAP3430_DSS_MOD				0x600
-#define OMAP3430_CAM_MOD				0x700
-#define OMAP3430_PER_MOD				0x800
-#define OMAP3430_EMU_MOD				0x900
-#define OMAP3430_GR_MOD					0xa00
-#define OMAP3430_NEON_MOD				0xb00
-#define OMAP3430ES2_USBHOST_MOD				0xc00
-
-/*
- * TI81XX PRM module offsets
- */
-#define TI81XX_PRM_DEVICE_MOD			0x0000
-#define TI816X_PRM_ACTIVE_MOD			0x0a00
-#define TI81XX_PRM_DEFAULT_MOD			0x0b00
-#define TI816X_PRM_IVAHD0_MOD			0x0c00
-#define TI816X_PRM_IVAHD1_MOD			0x0d00
-#define TI816X_PRM_IVAHD2_MOD			0x0e00
-#define TI816X_PRM_SGX_MOD				0x0f00
-#define TI81XX_PRM_ALWON_MOD			0x1800
-
-/* 24XX register bits shared between CM & PRM registers */
-
-/* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
-#define OMAP2420_EN_MMC_SHIFT				26
-#define OMAP2420_EN_MMC_MASK				(1 << 26)
-#define OMAP24XX_EN_UART2_SHIFT				22
-#define OMAP24XX_EN_UART2_MASK				(1 << 22)
-#define OMAP24XX_EN_UART1_SHIFT				21
-#define OMAP24XX_EN_UART1_MASK				(1 << 21)
-#define OMAP24XX_EN_MCSPI2_SHIFT			18
-#define OMAP24XX_EN_MCSPI2_MASK				(1 << 18)
-#define OMAP24XX_EN_MCSPI1_SHIFT			17
-#define OMAP24XX_EN_MCSPI1_MASK				(1 << 17)
-#define OMAP24XX_EN_MCBSP2_SHIFT			16
-#define OMAP24XX_EN_MCBSP2_MASK				(1 << 16)
-#define OMAP24XX_EN_MCBSP1_SHIFT			15
-#define OMAP24XX_EN_MCBSP1_MASK				(1 << 15)
-#define OMAP24XX_EN_GPT12_SHIFT				14
-#define OMAP24XX_EN_GPT12_MASK				(1 << 14)
-#define OMAP24XX_EN_GPT11_SHIFT				13
-#define OMAP24XX_EN_GPT11_MASK				(1 << 13)
-#define OMAP24XX_EN_GPT10_SHIFT				12
-#define OMAP24XX_EN_GPT10_MASK				(1 << 12)
-#define OMAP24XX_EN_GPT9_SHIFT				11
-#define OMAP24XX_EN_GPT9_MASK				(1 << 11)
-#define OMAP24XX_EN_GPT8_SHIFT				10
-#define OMAP24XX_EN_GPT8_MASK				(1 << 10)
-#define OMAP24XX_EN_GPT7_SHIFT				9
-#define OMAP24XX_EN_GPT7_MASK				(1 << 9)
-#define OMAP24XX_EN_GPT6_SHIFT				8
-#define OMAP24XX_EN_GPT6_MASK				(1 << 8)
-#define OMAP24XX_EN_GPT5_SHIFT				7
-#define OMAP24XX_EN_GPT5_MASK				(1 << 7)
-#define OMAP24XX_EN_GPT4_SHIFT				6
-#define OMAP24XX_EN_GPT4_MASK				(1 << 6)
-#define OMAP24XX_EN_GPT3_SHIFT				5
-#define OMAP24XX_EN_GPT3_MASK				(1 << 5)
-#define OMAP24XX_EN_GPT2_SHIFT				4
-#define OMAP24XX_EN_GPT2_MASK				(1 << 4)
-#define OMAP2420_EN_VLYNQ_SHIFT				3
-#define OMAP2420_EN_VLYNQ_MASK				(1 << 3)
-
-/* CM_FCLKEN2_CORE, CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
-#define OMAP2430_EN_GPIO5_SHIFT				10
-#define OMAP2430_EN_GPIO5_MASK				(1 << 10)
-#define OMAP2430_EN_MCSPI3_SHIFT			9
-#define OMAP2430_EN_MCSPI3_MASK				(1 << 9)
-#define OMAP2430_EN_MMCHS2_SHIFT			8
-#define OMAP2430_EN_MMCHS2_MASK				(1 << 8)
-#define OMAP2430_EN_MMCHS1_SHIFT			7
-#define OMAP2430_EN_MMCHS1_MASK				(1 << 7)
-#define OMAP24XX_EN_UART3_SHIFT				2
-#define OMAP24XX_EN_UART3_MASK				(1 << 2)
-#define OMAP24XX_EN_USB_SHIFT				0
-#define OMAP24XX_EN_USB_MASK				(1 << 0)
-
-/* CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
-#define OMAP2430_EN_MDM_INTC_SHIFT			11
-#define OMAP2430_EN_MDM_INTC_MASK			(1 << 11)
-#define OMAP2430_EN_USBHS_SHIFT				6
-#define OMAP2430_EN_USBHS_MASK				(1 << 6)
-#define OMAP24XX_EN_GPMC_SHIFT				1
-#define OMAP24XX_EN_GPMC_MASK				(1 << 1)
-
-/* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */
-#define OMAP2420_ST_MMC_SHIFT				26
-#define OMAP2420_ST_MMC_MASK				(1 << 26)
-#define OMAP24XX_ST_UART2_SHIFT				22
-#define OMAP24XX_ST_UART2_MASK				(1 << 22)
-#define OMAP24XX_ST_UART1_SHIFT				21
-#define OMAP24XX_ST_UART1_MASK				(1 << 21)
-#define OMAP24XX_ST_MCSPI2_SHIFT			18
-#define OMAP24XX_ST_MCSPI2_MASK				(1 << 18)
-#define OMAP24XX_ST_MCSPI1_SHIFT			17
-#define OMAP24XX_ST_MCSPI1_MASK				(1 << 17)
-#define OMAP24XX_ST_MCBSP2_SHIFT			16
-#define OMAP24XX_ST_MCBSP2_MASK				(1 << 16)
-#define OMAP24XX_ST_MCBSP1_SHIFT			15
-#define OMAP24XX_ST_MCBSP1_MASK				(1 << 15)
-#define OMAP24XX_ST_GPT12_SHIFT				14
-#define OMAP24XX_ST_GPT12_MASK				(1 << 14)
-#define OMAP24XX_ST_GPT11_SHIFT				13
-#define OMAP24XX_ST_GPT11_MASK				(1 << 13)
-#define OMAP24XX_ST_GPT10_SHIFT				12
-#define OMAP24XX_ST_GPT10_MASK				(1 << 12)
-#define OMAP24XX_ST_GPT9_SHIFT				11
-#define OMAP24XX_ST_GPT9_MASK				(1 << 11)
-#define OMAP24XX_ST_GPT8_SHIFT				10
-#define OMAP24XX_ST_GPT8_MASK				(1 << 10)
-#define OMAP24XX_ST_GPT7_SHIFT				9
-#define OMAP24XX_ST_GPT7_MASK				(1 << 9)
-#define OMAP24XX_ST_GPT6_SHIFT				8
-#define OMAP24XX_ST_GPT6_MASK				(1 << 8)
-#define OMAP24XX_ST_GPT5_SHIFT				7
-#define OMAP24XX_ST_GPT5_MASK				(1 << 7)
-#define OMAP24XX_ST_GPT4_SHIFT				6
-#define OMAP24XX_ST_GPT4_MASK				(1 << 6)
-#define OMAP24XX_ST_GPT3_SHIFT				5
-#define OMAP24XX_ST_GPT3_MASK				(1 << 5)
-#define OMAP24XX_ST_GPT2_SHIFT				4
-#define OMAP24XX_ST_GPT2_MASK				(1 << 4)
-#define OMAP2420_ST_VLYNQ_SHIFT				3
-#define OMAP2420_ST_VLYNQ_MASK				(1 << 3)
-
-/* CM_IDLEST2_CORE, PM_WKST2_CORE shared bits */
-#define OMAP2430_ST_MDM_INTC_SHIFT			11
-#define OMAP2430_ST_MDM_INTC_MASK			(1 << 11)
-#define OMAP2430_ST_GPIO5_SHIFT				10
-#define OMAP2430_ST_GPIO5_MASK				(1 << 10)
-#define OMAP2430_ST_MCSPI3_SHIFT			9
-#define OMAP2430_ST_MCSPI3_MASK				(1 << 9)
-#define OMAP2430_ST_MMCHS2_SHIFT			8
-#define OMAP2430_ST_MMCHS2_MASK				(1 << 8)
-#define OMAP2430_ST_MMCHS1_SHIFT			7
-#define OMAP2430_ST_MMCHS1_MASK				(1 << 7)
-#define OMAP2430_ST_USBHS_SHIFT				6
-#define OMAP2430_ST_USBHS_MASK				(1 << 6)
-#define OMAP24XX_ST_UART3_SHIFT				2
-#define OMAP24XX_ST_UART3_MASK				(1 << 2)
-#define OMAP24XX_ST_USB_SHIFT				0
-#define OMAP24XX_ST_USB_MASK				(1 << 0)
-
-/* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
-#define OMAP24XX_EN_GPIOS_SHIFT				2
-#define OMAP24XX_EN_GPIOS_MASK				(1 << 2)
-#define OMAP24XX_EN_GPT1_SHIFT				0
-#define OMAP24XX_EN_GPT1_MASK				(1 << 0)
-
-/* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */
-#define OMAP24XX_ST_GPIOS_SHIFT				2
-#define OMAP24XX_ST_GPIOS_MASK				(1 << 2)
-#define OMAP24XX_ST_32KSYNC_SHIFT			1
-#define OMAP24XX_ST_32KSYNC_MASK			(1 << 1)
-#define OMAP24XX_ST_GPT1_SHIFT				0
-#define OMAP24XX_ST_GPT1_MASK				(1 << 0)
-
-/* CM_IDLEST_MDM and PM_WKST_MDM shared bits */
-#define OMAP2430_ST_MDM_SHIFT				0
-#define OMAP2430_ST_MDM_MASK				(1 << 0)
-
-
-/* 3430 register bits shared between CM & PRM registers */
-
-/* CM_REVISION, PRM_REVISION shared bits */
-#define OMAP3430_REV_SHIFT				0
-#define OMAP3430_REV_MASK				(0xff << 0)
-
-/* CM_SYSCONFIG, PRM_SYSCONFIG shared bits */
-#define OMAP3430_AUTOIDLE_MASK				(1 << 0)
-
-/* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
-#define OMAP3430_EN_MMC3_MASK				(1 << 30)
-#define OMAP3430_EN_MMC3_SHIFT				30
-#define OMAP3430_EN_MMC2_MASK				(1 << 25)
-#define OMAP3430_EN_MMC2_SHIFT				25
-#define OMAP3430_EN_MMC1_MASK				(1 << 24)
-#define OMAP3430_EN_MMC1_SHIFT				24
-#define AM35XX_EN_UART4_MASK				(1 << 23)
-#define AM35XX_EN_UART4_SHIFT				23
-#define OMAP3430_EN_MCSPI4_MASK				(1 << 21)
-#define OMAP3430_EN_MCSPI4_SHIFT			21
-#define OMAP3430_EN_MCSPI3_MASK				(1 << 20)
-#define OMAP3430_EN_MCSPI3_SHIFT			20
-#define OMAP3430_EN_MCSPI2_MASK				(1 << 19)
-#define OMAP3430_EN_MCSPI2_SHIFT			19
-#define OMAP3430_EN_MCSPI1_MASK				(1 << 18)
-#define OMAP3430_EN_MCSPI1_SHIFT			18
-#define OMAP3430_EN_I2C3_MASK				(1 << 17)
-#define OMAP3430_EN_I2C3_SHIFT				17
-#define OMAP3430_EN_I2C2_MASK				(1 << 16)
-#define OMAP3430_EN_I2C2_SHIFT				16
-#define OMAP3430_EN_I2C1_MASK				(1 << 15)
-#define OMAP3430_EN_I2C1_SHIFT				15
-#define OMAP3430_EN_UART2_MASK				(1 << 14)
-#define OMAP3430_EN_UART2_SHIFT				14
-#define OMAP3430_EN_UART1_MASK				(1 << 13)
-#define OMAP3430_EN_UART1_SHIFT				13
-#define OMAP3430_EN_GPT11_MASK				(1 << 12)
-#define OMAP3430_EN_GPT11_SHIFT				12
-#define OMAP3430_EN_GPT10_MASK				(1 << 11)
-#define OMAP3430_EN_GPT10_SHIFT				11
-#define OMAP3430_EN_MCBSP5_MASK				(1 << 10)
-#define OMAP3430_EN_MCBSP5_SHIFT			10
-#define OMAP3430_EN_MCBSP1_MASK				(1 << 9)
-#define OMAP3430_EN_MCBSP1_SHIFT			9
-#define OMAP3430_EN_FSHOSTUSB_MASK			(1 << 5)
-#define OMAP3430_EN_FSHOSTUSB_SHIFT			5
-#define OMAP3430_EN_D2D_MASK				(1 << 3)
-#define OMAP3430_EN_D2D_SHIFT				3
-
-/* CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
-#define OMAP3430_EN_HSOTGUSB_MASK			(1 << 4)
-#define OMAP3430_EN_HSOTGUSB_SHIFT			4
-
-/* PM_WKST1_CORE, CM_IDLEST1_CORE shared bits */
-#define OMAP3430_ST_MMC3_SHIFT				30
-#define OMAP3430_ST_MMC3_MASK				(1 << 30)
-#define OMAP3430_ST_MMC2_SHIFT				25
-#define OMAP3430_ST_MMC2_MASK				(1 << 25)
-#define OMAP3430_ST_MMC1_SHIFT				24
-#define OMAP3430_ST_MMC1_MASK				(1 << 24)
-#define OMAP3430_ST_MCSPI4_SHIFT			21
-#define OMAP3430_ST_MCSPI4_MASK				(1 << 21)
-#define OMAP3430_ST_MCSPI3_SHIFT			20
-#define OMAP3430_ST_MCSPI3_MASK				(1 << 20)
-#define OMAP3430_ST_MCSPI2_SHIFT			19
-#define OMAP3430_ST_MCSPI2_MASK				(1 << 19)
-#define OMAP3430_ST_MCSPI1_SHIFT			18
-#define OMAP3430_ST_MCSPI1_MASK				(1 << 18)
-#define OMAP3430_ST_I2C3_SHIFT				17
-#define OMAP3430_ST_I2C3_MASK				(1 << 17)
-#define OMAP3430_ST_I2C2_SHIFT				16
-#define OMAP3430_ST_I2C2_MASK				(1 << 16)
-#define OMAP3430_ST_I2C1_SHIFT				15
-#define OMAP3430_ST_I2C1_MASK				(1 << 15)
-#define OMAP3430_ST_UART2_SHIFT				14
-#define OMAP3430_ST_UART2_MASK				(1 << 14)
-#define OMAP3430_ST_UART1_SHIFT				13
-#define OMAP3430_ST_UART1_MASK				(1 << 13)
-#define OMAP3430_ST_GPT11_SHIFT				12
-#define OMAP3430_ST_GPT11_MASK				(1 << 12)
-#define OMAP3430_ST_GPT10_SHIFT				11
-#define OMAP3430_ST_GPT10_MASK				(1 << 11)
-#define OMAP3430_ST_MCBSP5_SHIFT			10
-#define OMAP3430_ST_MCBSP5_MASK				(1 << 10)
-#define OMAP3430_ST_MCBSP1_SHIFT			9
-#define OMAP3430_ST_MCBSP1_MASK				(1 << 9)
-#define OMAP3430ES1_ST_FSHOSTUSB_SHIFT			5
-#define OMAP3430ES1_ST_FSHOSTUSB_MASK			(1 << 5)
-#define OMAP3430ES1_ST_HSOTGUSB_SHIFT			4
-#define OMAP3430ES1_ST_HSOTGUSB_MASK			(1 << 4)
-#define OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT		5
-#define OMAP3430ES2_ST_HSOTGUSB_IDLE_MASK		(1 << 5)
-#define OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT		4
-#define OMAP3430ES2_ST_HSOTGUSB_STDBY_MASK		(1 << 4)
-#define OMAP3430_ST_D2D_SHIFT				3
-#define OMAP3430_ST_D2D_MASK				(1 << 3)
-
-/* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
-#define OMAP3430_EN_GPIO1_MASK				(1 << 3)
-#define OMAP3430_EN_GPIO1_SHIFT				3
-#define OMAP3430_EN_GPT12_MASK				(1 << 1)
-#define OMAP3430_EN_GPT12_SHIFT				1
-#define OMAP3430_EN_GPT1_MASK				(1 << 0)
-#define OMAP3430_EN_GPT1_SHIFT				0
-
-/* CM_FCLKEN_WKUP, PM_WKEN_WKUP shared bits */
-#define OMAP3430_EN_SR2_MASK				(1 << 7)
-#define OMAP3430_EN_SR2_SHIFT				7
-#define OMAP3430_EN_SR1_MASK				(1 << 6)
-#define OMAP3430_EN_SR1_SHIFT				6
-
-/* CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
-#define OMAP3430_EN_GPT12_MASK				(1 << 1)
-#define OMAP3430_EN_GPT12_SHIFT				1
-
-/* CM_IDLEST_WKUP, PM_WKST_WKUP shared bits */
-#define OMAP3430_ST_SR2_SHIFT				7
-#define OMAP3430_ST_SR2_MASK				(1 << 7)
-#define OMAP3430_ST_SR1_SHIFT				6
-#define OMAP3430_ST_SR1_MASK				(1 << 6)
-#define OMAP3430_ST_GPIO1_SHIFT				3
-#define OMAP3430_ST_GPIO1_MASK				(1 << 3)
-#define OMAP3430_ST_32KSYNC_SHIFT			2
-#define OMAP3430_ST_32KSYNC_MASK			(1 << 2)
-#define OMAP3430_ST_GPT12_SHIFT				1
-#define OMAP3430_ST_GPT12_MASK				(1 << 1)
-#define OMAP3430_ST_GPT1_SHIFT				0
-#define OMAP3430_ST_GPT1_MASK				(1 << 0)
-
-/*
- * CM_SLEEPDEP_GFX, CM_SLEEPDEP_DSS, CM_SLEEPDEP_CAM,
- * CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_GFX,
- * PM_WKDEP_DSS, PM_WKDEP_CAM, PM_WKDEP_PER, PM_WKDEP_NEON shared bits
- */
-#define OMAP3430_EN_MPU_MASK				(1 << 1)
-#define OMAP3430_EN_MPU_SHIFT				1
-
-/* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER shared bits */
-
-#define OMAP3630_EN_UART4_MASK				(1 << 18)
-#define OMAP3630_EN_UART4_SHIFT				18
-#define OMAP3430_EN_GPIO6_MASK				(1 << 17)
-#define OMAP3430_EN_GPIO6_SHIFT				17
-#define OMAP3430_EN_GPIO5_MASK				(1 << 16)
-#define OMAP3430_EN_GPIO5_SHIFT				16
-#define OMAP3430_EN_GPIO4_MASK				(1 << 15)
-#define OMAP3430_EN_GPIO4_SHIFT				15
-#define OMAP3430_EN_GPIO3_MASK				(1 << 14)
-#define OMAP3430_EN_GPIO3_SHIFT				14
-#define OMAP3430_EN_GPIO2_MASK				(1 << 13)
-#define OMAP3430_EN_GPIO2_SHIFT				13
-#define OMAP3430_EN_UART3_MASK				(1 << 11)
-#define OMAP3430_EN_UART3_SHIFT				11
-#define OMAP3430_EN_GPT9_MASK				(1 << 10)
-#define OMAP3430_EN_GPT9_SHIFT				10
-#define OMAP3430_EN_GPT8_MASK				(1 << 9)
-#define OMAP3430_EN_GPT8_SHIFT				9
-#define OMAP3430_EN_GPT7_MASK				(1 << 8)
-#define OMAP3430_EN_GPT7_SHIFT				8
-#define OMAP3430_EN_GPT6_MASK				(1 << 7)
-#define OMAP3430_EN_GPT6_SHIFT				7
-#define OMAP3430_EN_GPT5_MASK				(1 << 6)
-#define OMAP3430_EN_GPT5_SHIFT				6
-#define OMAP3430_EN_GPT4_MASK				(1 << 5)
-#define OMAP3430_EN_GPT4_SHIFT				5
-#define OMAP3430_EN_GPT3_MASK				(1 << 4)
-#define OMAP3430_EN_GPT3_SHIFT				4
-#define OMAP3430_EN_GPT2_MASK				(1 << 3)
-#define OMAP3430_EN_GPT2_SHIFT				3
-
-/* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER, PM_WKST_PER shared bits */
-/* XXX Possible TI documentation bug: should the PM_WKST_PER EN_* bits
- * be ST_* bits instead? */
-#define OMAP3430_EN_MCBSP4_MASK				(1 << 2)
-#define OMAP3430_EN_MCBSP4_SHIFT			2
-#define OMAP3430_EN_MCBSP3_MASK				(1 << 1)
-#define OMAP3430_EN_MCBSP3_SHIFT			1
-#define OMAP3430_EN_MCBSP2_MASK				(1 << 0)
-#define OMAP3430_EN_MCBSP2_SHIFT			0
-
-/* CM_IDLEST_PER, PM_WKST_PER shared bits */
-#define OMAP3630_ST_UART4_SHIFT				18
-#define OMAP3630_ST_UART4_MASK				(1 << 18)
-#define OMAP3430_ST_GPIO6_SHIFT				17
-#define OMAP3430_ST_GPIO6_MASK				(1 << 17)
-#define OMAP3430_ST_GPIO5_SHIFT				16
-#define OMAP3430_ST_GPIO5_MASK				(1 << 16)
-#define OMAP3430_ST_GPIO4_SHIFT				15
-#define OMAP3430_ST_GPIO4_MASK				(1 << 15)
-#define OMAP3430_ST_GPIO3_SHIFT				14
-#define OMAP3430_ST_GPIO3_MASK				(1 << 14)
-#define OMAP3430_ST_GPIO2_SHIFT				13
-#define OMAP3430_ST_GPIO2_MASK				(1 << 13)
-#define OMAP3430_ST_UART3_SHIFT				11
-#define OMAP3430_ST_UART3_MASK				(1 << 11)
-#define OMAP3430_ST_GPT9_SHIFT				10
-#define OMAP3430_ST_GPT9_MASK				(1 << 10)
-#define OMAP3430_ST_GPT8_SHIFT				9
-#define OMAP3430_ST_GPT8_MASK				(1 << 9)
-#define OMAP3430_ST_GPT7_SHIFT				8
-#define OMAP3430_ST_GPT7_MASK				(1 << 8)
-#define OMAP3430_ST_GPT6_SHIFT				7
-#define OMAP3430_ST_GPT6_MASK				(1 << 7)
-#define OMAP3430_ST_GPT5_SHIFT				6
-#define OMAP3430_ST_GPT5_MASK				(1 << 6)
-#define OMAP3430_ST_GPT4_SHIFT				5
-#define OMAP3430_ST_GPT4_MASK				(1 << 5)
-#define OMAP3430_ST_GPT3_SHIFT				4
-#define OMAP3430_ST_GPT3_MASK				(1 << 4)
-#define OMAP3430_ST_GPT2_SHIFT				3
-#define OMAP3430_ST_GPT2_MASK				(1 << 3)
-
-/* CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_MPU, PM_WKDEP_PER shared bits */
-#define OMAP3430_EN_CORE_SHIFT				0
-#define OMAP3430_EN_CORE_MASK				(1 << 0)
-
-
-
-/*
- * Maximum time(us) it takes to output the signal WUCLKOUT of the last
- * pad of the I/O ring after asserting WUCLKIN high.  Tero measured
- * the actual time at 7 to 8 microseconds on OMAP3 and 2 to 4
- * microseconds on OMAP4, so this timeout may be too high.
- */
-#define MAX_IOPAD_LATCH_TIME			100
-# ifndef __ASSEMBLER__
-
-#include <linux/delay.h>
-
-/**
- * omap_test_timeout - busy-loop, testing a condition
- * @cond: condition to test until it evaluates to true
- * @timeout: maximum number of microseconds in the timeout
- * @index: loop index (integer)
- *
- * Loop waiting for @cond to become true or until at least @timeout
- * microseconds have passed.  To use, define some integer @index in the
- * calling code.  After running, if @index == @timeout, then the loop has
- * timed out.
- */
-#define omap_test_timeout(cond, timeout, index)			\
-({								\
-	for (index = 0; index < timeout; index++) {		\
-		if (cond)					\
-			break;					\
-		udelay(1);					\
-	}							\
-})
-
-/**
- * struct omap_prcm_irq - describes a PRCM interrupt bit
- * @name: a short name describing the interrupt type, e.g. "wkup" or "io"
- * @offset: the bit shift of the interrupt inside the IRQ{ENABLE,STATUS} regs
- * @priority: should this interrupt be handled before @priority=false IRQs?
- *
- * Describes interrupt bits inside the PRM_IRQ{ENABLE,STATUS}_MPU* registers.
- * On systems with multiple PRM MPU IRQ registers, the bitfields read from
- * the registers are concatenated, so @offset could be > 31 on these systems -
- * see omap_prm_irq_handler() for more details.  I/O ring interrupts should
- * have @priority set to true.
- */
-struct omap_prcm_irq {
-	const char *name;
-	unsigned int offset;
-	bool priority;
-};
-
-/**
- * struct omap_prcm_irq_setup - PRCM interrupt controller details
- * @ack: PRM register offset for the first PRM_IRQSTATUS_MPU register
- * @mask: PRM register offset for the first PRM_IRQENABLE_MPU register
- * @nr_regs: number of PRM_IRQ{STATUS,ENABLE}_MPU* registers
- * @nr_irqs: number of entries in the @irqs array
- * @irqs: ptr to an array of PRCM interrupt bits (see @nr_irqs)
- * @irq: MPU IRQ asserted when a PRCM interrupt arrives
- * @read_pending_irqs: fn ptr to determine if any PRCM IRQs are pending
- * @ocp_barrier: fn ptr to force buffered PRM writes to complete
- * @save_and_clear_irqen: fn ptr to save and clear IRQENABLE regs
- * @restore_irqen: fn ptr to save and clear IRQENABLE regs
- * @reconfigure_io_chain: fn ptr to reconfigure IO chain
- * @saved_mask: IRQENABLE regs are saved here during suspend
- * @priority_mask: 1 bit per IRQ, set to 1 if omap_prcm_irq.priority = true
- * @base_irq: base dynamic IRQ number, returned from irq_alloc_descs() in init
- * @suspended: set to true after Linux suspend code has called our ->prepare()
- * @suspend_save_flag: set to true after IRQ masks have been saved and disabled
- *
- * @saved_mask, @priority_mask, @base_irq, @suspended, and
- * @suspend_save_flag are populated dynamically, and are not to be
- * specified in static initializers.
- */
-struct omap_prcm_irq_setup {
-	u16 ack;
-	u16 mask;
-	u8 nr_regs;
-	u8 nr_irqs;
-	const struct omap_prcm_irq *irqs;
-	int irq;
-	void (*read_pending_irqs)(unsigned long *events);
-	void (*ocp_barrier)(void);
-	void (*save_and_clear_irqen)(u32 *saved_mask);
-	void (*restore_irqen)(u32 *saved_mask);
-	void (*reconfigure_io_chain)(void);
-	u32 *saved_mask;
-	u32 *priority_mask;
-	int base_irq;
-	bool suspended;
-	bool suspend_save_flag;
-};
-
-/* OMAP_PRCM_IRQ: convenience macro for creating struct omap_prcm_irq records */
-#define OMAP_PRCM_IRQ(_name, _offset, _priority) {	\
-	.name = _name,					\
-	.offset = _offset,				\
-	.priority = _priority				\
-	}
-
-struct of_device_id;
-
-extern void __iomem *clk_memmaps[];
-
-extern void omap_prcm_irq_cleanup(void);
-extern int omap_prcm_register_chain_handler(
-	struct omap_prcm_irq_setup *irq_setup);
-extern int omap_prcm_event_to_irq(const char *event);
-extern void omap_prcm_irq_prepare(void);
-extern void omap_prcm_irq_complete(void);
-void omap_pcs_legacy_init(int irq, void (*rearm)(void));
-int of_prcm_module_init(struct of_device_id *match_table);
-int of_cm_init(void);
-
-# endif
-
-#endif
-
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index 8caa7af..6a02cf3 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -13,7 +13,7 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_PRM_H
 #define __ARCH_ARM_MACH_OMAP2_PRM_H
 
-#include "prcm-common.h"
+#include <linux/power/omap/prcm-common.h>
 
 # ifndef __ASSEMBLER__
 extern void __iomem *prm_base;
diff --git a/arch/arm/mach-omap2/prm2xxx.h b/arch/arm/mach-omap2/prm2xxx.h
index feeaf00..b86486b 100644
--- a/arch/arm/mach-omap2/prm2xxx.h
+++ b/arch/arm/mach-omap2/prm2xxx.h
@@ -16,7 +16,7 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_PRM2XXX_H
 #define __ARCH_ARM_MACH_OMAP2_PRM2XXX_H
 
-#include "prcm-common.h"
+#include <linux/power/omap/prcm-common.h>
 #include "prm.h"
 #include <linux/power/omap/prm2xxx.h>
 #include <linux/power/omap/prm2xxx_3xxx.h>
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx_private.h b/arch/arm/mach-omap2/prm2xxx_3xxx_private.h
index ebd6a09..c02a267 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx_private.h
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx_private.h
@@ -16,7 +16,7 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_PRM2XXX_3XXX_PRIVATE_H
 #define __ARCH_ARM_MACH_OMAP2_PRM2XXX_3XXX_PRIVATE_H
 
-#include "prcm-common.h"
+#include <linux/power/omap/prcm-common.h>
 #include "prm.h"
 #include <linux/power/omap/prm2xxx_3xxx.h>
 
diff --git a/arch/arm/mach-omap2/prm33xx.h b/arch/arm/mach-omap2/prm33xx.h
index 7825b1c..598ba48 100644
--- a/arch/arm/mach-omap2/prm33xx.h
+++ b/arch/arm/mach-omap2/prm33xx.h
@@ -16,7 +16,7 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_PRM33XX_H
 #define __ARCH_ARM_MACH_OMAP2_PRM33XX_H
 
-#include "prcm-common.h"
+#include <linux/power/omap/prcm-common.h>
 #include "prm.h"
 #include <linux/power/omap/prm33xx.h>
 
diff --git a/arch/arm/mach-omap2/prm3xxx.h b/arch/arm/mach-omap2/prm3xxx.h
index 6c06fce..693b5ad 100644
--- a/arch/arm/mach-omap2/prm3xxx.h
+++ b/arch/arm/mach-omap2/prm3xxx.h
@@ -16,7 +16,7 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_PRM3XXX_H
 #define __ARCH_ARM_MACH_OMAP2_PRM3XXX_H
 
-#include "prcm-common.h"
+#include <linux/power/omap/prcm-common.h>
 #include "prm.h"
 #include <linux/power/omap/prm2xxx_3xxx.h>
 #include <linux/power/omap/prm3xxx.h>
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index 2b25710..705509a 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -26,7 +26,7 @@
 #include "prminst44xx_private.h"
 #include "powerdomain.h"
 #include "prm.h"
-#include "prcm-common.h"
+#include <linux/power/omap/prcm-common.h>
 #include <linux/power/omap/prm44xx_54xx.h>
 
 #define OMAP4430_GLOBAL_COLD_RST_SHIFT			0
diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h
index 52585e1..b7066fd 100644
--- a/arch/arm/mach-omap2/prm44xx.h
+++ b/arch/arm/mach-omap2/prm44xx.h
@@ -26,7 +26,7 @@
 #define __ARCH_ARM_MACH_OMAP2_PRM44XX_H
 
 #include <linux/power/omap/prm44xx_54xx.h>
-#include "prcm-common.h"
+#include <linux/power/omap/prcm-common.h>
 #include "prm.h"
 #include <linux/power/omap/prm44xx.h>
 
diff --git a/arch/arm/mach-omap2/prm54xx.h b/arch/arm/mach-omap2/prm54xx.h
index 34a0835..250c2d5 100644
--- a/arch/arm/mach-omap2/prm54xx.h
+++ b/arch/arm/mach-omap2/prm54xx.h
@@ -22,7 +22,7 @@
 #define __ARCH_ARM_MACH_OMAP2_PRM54XX_H
 
 #include <linux/power/omap/prm44xx_54xx.h>
-#include "prcm-common.h"
+#include <linux/power/omap/prcm-common.h>
 #include "prm.h"
 #include <linux/power/omap/prm54xx.h>
 
diff --git a/arch/arm/mach-omap2/prm7xx.h b/arch/arm/mach-omap2/prm7xx.h
index 2637d62..6e84906 100644
--- a/arch/arm/mach-omap2/prm7xx.h
+++ b/arch/arm/mach-omap2/prm7xx.h
@@ -23,7 +23,7 @@
 #define __ARCH_ARM_MACH_OMAP2_PRM7XX_H
 
 #include <linux/power/omap/prm44xx_54xx.h>
-#include "prcm-common.h"
+#include <linux/power/omap/prcm-common.h>
 #include "prm.h"
 #include <linux/power/omap/prm7xx.h>
 
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index 653862b..acdd0f1 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -34,7 +34,7 @@
 #include <linux/power/omap/prm44xx.h>
 
 #include "prm.h"
-#include "prcm-common.h"
+#include <linux/power/omap/prcm-common.h>
 
 /*
  * OMAP_PRCM_MAX_NR_PENDING_REG: maximum number of PRM_IRQ*_MPU regs
diff --git a/arch/arm/mach-omap2/prminst44xx.c b/arch/arm/mach-omap2/prminst44xx.c
index 01f6b15..50c660d 100644
--- a/arch/arm/mach-omap2/prminst44xx.c
+++ b/arch/arm/mach-omap2/prminst44xx.c
@@ -17,7 +17,7 @@
 #include <linux/io.h>
 
 #include "prm.h"
-#include "prcm-common.h"
+#include <linux/power/omap/prcm-common.h>
 #include <linux/power/omap/prm44xx.h>
 #include <linux/power/omap/prm54xx.h>
 #include <linux/power/omap/prm7xx.h>
diff --git a/include/linux/power/omap/prcm-common.h b/include/linux/power/omap/prcm-common.h
new file mode 100644
index 0000000..67143a2
--- /dev/null
+++ b/include/linux/power/omap/prcm-common.h
@@ -0,0 +1,535 @@
+/*
+ * OMAP2/3 PRCM base and module definitions
+ *
+ * Copyright (C) 2007-2009, 2011 Texas Instruments, Inc.
+ * Copyright (C) 2007-2009 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __LINUX_POWER_OMAP_PRCM_COMMON_H
+#define __LINUX_POWER_OMAP_PRCM_COMMON_H
+
+/* Module offsets from both CM_BASE & PRM_BASE */
+
+/*
+ * Offsets that are the same on 24xx and 34xx
+ *
+ * Technically, in terms of the TRM, OCP_MOD is 34xx only; PLL_MOD is
+ * CCR_MOD on 3430; and GFX_MOD only exists < 3430ES2.
+ */
+#define OCP_MOD						0x000
+#define MPU_MOD						0x100
+#define CORE_MOD					0x200
+#define GFX_MOD						0x300
+#define WKUP_MOD					0x400
+#define PLL_MOD						0x500
+
+
+/* Chip-specific module offsets */
+#define OMAP24XX_GR_MOD					OCP_MOD
+#define OMAP24XX_DSP_MOD				0x800
+
+#define OMAP2430_MDM_MOD				0xc00
+
+/* IVA2 module is < base on 3430 */
+#define OMAP3430_IVA2_MOD				-0x800
+#define OMAP3430ES2_SGX_MOD				GFX_MOD
+#define OMAP3430_CCR_MOD				PLL_MOD
+#define OMAP3430_DSS_MOD				0x600
+#define OMAP3430_CAM_MOD				0x700
+#define OMAP3430_PER_MOD				0x800
+#define OMAP3430_EMU_MOD				0x900
+#define OMAP3430_GR_MOD					0xa00
+#define OMAP3430_NEON_MOD				0xb00
+#define OMAP3430ES2_USBHOST_MOD				0xc00
+
+/*
+ * TI81XX PRM module offsets
+ */
+#define TI81XX_PRM_DEVICE_MOD			0x0000
+#define TI816X_PRM_ACTIVE_MOD			0x0a00
+#define TI81XX_PRM_DEFAULT_MOD			0x0b00
+#define TI816X_PRM_IVAHD0_MOD			0x0c00
+#define TI816X_PRM_IVAHD1_MOD			0x0d00
+#define TI816X_PRM_IVAHD2_MOD			0x0e00
+#define TI816X_PRM_SGX_MOD				0x0f00
+#define TI81XX_PRM_ALWON_MOD			0x1800
+
+/* 24XX register bits shared between CM & PRM registers */
+
+/* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
+#define OMAP2420_EN_MMC_SHIFT				26
+#define OMAP2420_EN_MMC_MASK				(1 << 26)
+#define OMAP24XX_EN_UART2_SHIFT				22
+#define OMAP24XX_EN_UART2_MASK				(1 << 22)
+#define OMAP24XX_EN_UART1_SHIFT				21
+#define OMAP24XX_EN_UART1_MASK				(1 << 21)
+#define OMAP24XX_EN_MCSPI2_SHIFT			18
+#define OMAP24XX_EN_MCSPI2_MASK				(1 << 18)
+#define OMAP24XX_EN_MCSPI1_SHIFT			17
+#define OMAP24XX_EN_MCSPI1_MASK				(1 << 17)
+#define OMAP24XX_EN_MCBSP2_SHIFT			16
+#define OMAP24XX_EN_MCBSP2_MASK				(1 << 16)
+#define OMAP24XX_EN_MCBSP1_SHIFT			15
+#define OMAP24XX_EN_MCBSP1_MASK				(1 << 15)
+#define OMAP24XX_EN_GPT12_SHIFT				14
+#define OMAP24XX_EN_GPT12_MASK				(1 << 14)
+#define OMAP24XX_EN_GPT11_SHIFT				13
+#define OMAP24XX_EN_GPT11_MASK				(1 << 13)
+#define OMAP24XX_EN_GPT10_SHIFT				12
+#define OMAP24XX_EN_GPT10_MASK				(1 << 12)
+#define OMAP24XX_EN_GPT9_SHIFT				11
+#define OMAP24XX_EN_GPT9_MASK				(1 << 11)
+#define OMAP24XX_EN_GPT8_SHIFT				10
+#define OMAP24XX_EN_GPT8_MASK				(1 << 10)
+#define OMAP24XX_EN_GPT7_SHIFT				9
+#define OMAP24XX_EN_GPT7_MASK				(1 << 9)
+#define OMAP24XX_EN_GPT6_SHIFT				8
+#define OMAP24XX_EN_GPT6_MASK				(1 << 8)
+#define OMAP24XX_EN_GPT5_SHIFT				7
+#define OMAP24XX_EN_GPT5_MASK				(1 << 7)
+#define OMAP24XX_EN_GPT4_SHIFT				6
+#define OMAP24XX_EN_GPT4_MASK				(1 << 6)
+#define OMAP24XX_EN_GPT3_SHIFT				5
+#define OMAP24XX_EN_GPT3_MASK				(1 << 5)
+#define OMAP24XX_EN_GPT2_SHIFT				4
+#define OMAP24XX_EN_GPT2_MASK				(1 << 4)
+#define OMAP2420_EN_VLYNQ_SHIFT				3
+#define OMAP2420_EN_VLYNQ_MASK				(1 << 3)
+
+/* CM_FCLKEN2_CORE, CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
+#define OMAP2430_EN_GPIO5_SHIFT				10
+#define OMAP2430_EN_GPIO5_MASK				(1 << 10)
+#define OMAP2430_EN_MCSPI3_SHIFT			9
+#define OMAP2430_EN_MCSPI3_MASK				(1 << 9)
+#define OMAP2430_EN_MMCHS2_SHIFT			8
+#define OMAP2430_EN_MMCHS2_MASK				(1 << 8)
+#define OMAP2430_EN_MMCHS1_SHIFT			7
+#define OMAP2430_EN_MMCHS1_MASK				(1 << 7)
+#define OMAP24XX_EN_UART3_SHIFT				2
+#define OMAP24XX_EN_UART3_MASK				(1 << 2)
+#define OMAP24XX_EN_USB_SHIFT				0
+#define OMAP24XX_EN_USB_MASK				(1 << 0)
+
+/* CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
+#define OMAP2430_EN_MDM_INTC_SHIFT			11
+#define OMAP2430_EN_MDM_INTC_MASK			(1 << 11)
+#define OMAP2430_EN_USBHS_SHIFT				6
+#define OMAP2430_EN_USBHS_MASK				(1 << 6)
+#define OMAP24XX_EN_GPMC_SHIFT				1
+#define OMAP24XX_EN_GPMC_MASK				(1 << 1)
+
+/* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */
+#define OMAP2420_ST_MMC_SHIFT				26
+#define OMAP2420_ST_MMC_MASK				(1 << 26)
+#define OMAP24XX_ST_UART2_SHIFT				22
+#define OMAP24XX_ST_UART2_MASK				(1 << 22)
+#define OMAP24XX_ST_UART1_SHIFT				21
+#define OMAP24XX_ST_UART1_MASK				(1 << 21)
+#define OMAP24XX_ST_MCSPI2_SHIFT			18
+#define OMAP24XX_ST_MCSPI2_MASK				(1 << 18)
+#define OMAP24XX_ST_MCSPI1_SHIFT			17
+#define OMAP24XX_ST_MCSPI1_MASK				(1 << 17)
+#define OMAP24XX_ST_MCBSP2_SHIFT			16
+#define OMAP24XX_ST_MCBSP2_MASK				(1 << 16)
+#define OMAP24XX_ST_MCBSP1_SHIFT			15
+#define OMAP24XX_ST_MCBSP1_MASK				(1 << 15)
+#define OMAP24XX_ST_GPT12_SHIFT				14
+#define OMAP24XX_ST_GPT12_MASK				(1 << 14)
+#define OMAP24XX_ST_GPT11_SHIFT				13
+#define OMAP24XX_ST_GPT11_MASK				(1 << 13)
+#define OMAP24XX_ST_GPT10_SHIFT				12
+#define OMAP24XX_ST_GPT10_MASK				(1 << 12)
+#define OMAP24XX_ST_GPT9_SHIFT				11
+#define OMAP24XX_ST_GPT9_MASK				(1 << 11)
+#define OMAP24XX_ST_GPT8_SHIFT				10
+#define OMAP24XX_ST_GPT8_MASK				(1 << 10)
+#define OMAP24XX_ST_GPT7_SHIFT				9
+#define OMAP24XX_ST_GPT7_MASK				(1 << 9)
+#define OMAP24XX_ST_GPT6_SHIFT				8
+#define OMAP24XX_ST_GPT6_MASK				(1 << 8)
+#define OMAP24XX_ST_GPT5_SHIFT				7
+#define OMAP24XX_ST_GPT5_MASK				(1 << 7)
+#define OMAP24XX_ST_GPT4_SHIFT				6
+#define OMAP24XX_ST_GPT4_MASK				(1 << 6)
+#define OMAP24XX_ST_GPT3_SHIFT				5
+#define OMAP24XX_ST_GPT3_MASK				(1 << 5)
+#define OMAP24XX_ST_GPT2_SHIFT				4
+#define OMAP24XX_ST_GPT2_MASK				(1 << 4)
+#define OMAP2420_ST_VLYNQ_SHIFT				3
+#define OMAP2420_ST_VLYNQ_MASK				(1 << 3)
+
+/* CM_IDLEST2_CORE, PM_WKST2_CORE shared bits */
+#define OMAP2430_ST_MDM_INTC_SHIFT			11
+#define OMAP2430_ST_MDM_INTC_MASK			(1 << 11)
+#define OMAP2430_ST_GPIO5_SHIFT				10
+#define OMAP2430_ST_GPIO5_MASK				(1 << 10)
+#define OMAP2430_ST_MCSPI3_SHIFT			9
+#define OMAP2430_ST_MCSPI3_MASK				(1 << 9)
+#define OMAP2430_ST_MMCHS2_SHIFT			8
+#define OMAP2430_ST_MMCHS2_MASK				(1 << 8)
+#define OMAP2430_ST_MMCHS1_SHIFT			7
+#define OMAP2430_ST_MMCHS1_MASK				(1 << 7)
+#define OMAP2430_ST_USBHS_SHIFT				6
+#define OMAP2430_ST_USBHS_MASK				(1 << 6)
+#define OMAP24XX_ST_UART3_SHIFT				2
+#define OMAP24XX_ST_UART3_MASK				(1 << 2)
+#define OMAP24XX_ST_USB_SHIFT				0
+#define OMAP24XX_ST_USB_MASK				(1 << 0)
+
+/* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
+#define OMAP24XX_EN_GPIOS_SHIFT				2
+#define OMAP24XX_EN_GPIOS_MASK				(1 << 2)
+#define OMAP24XX_EN_GPT1_SHIFT				0
+#define OMAP24XX_EN_GPT1_MASK				(1 << 0)
+
+/* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */
+#define OMAP24XX_ST_GPIOS_SHIFT				2
+#define OMAP24XX_ST_GPIOS_MASK				(1 << 2)
+#define OMAP24XX_ST_32KSYNC_SHIFT			1
+#define OMAP24XX_ST_32KSYNC_MASK			(1 << 1)
+#define OMAP24XX_ST_GPT1_SHIFT				0
+#define OMAP24XX_ST_GPT1_MASK				(1 << 0)
+
+/* CM_IDLEST_MDM and PM_WKST_MDM shared bits */
+#define OMAP2430_ST_MDM_SHIFT				0
+#define OMAP2430_ST_MDM_MASK				(1 << 0)
+
+
+/* 3430 register bits shared between CM & PRM registers */
+
+/* CM_REVISION, PRM_REVISION shared bits */
+#define OMAP3430_REV_SHIFT				0
+#define OMAP3430_REV_MASK				(0xff << 0)
+
+/* CM_SYSCONFIG, PRM_SYSCONFIG shared bits */
+#define OMAP3430_AUTOIDLE_MASK				(1 << 0)
+
+/* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
+#define OMAP3430_EN_MMC3_MASK				(1 << 30)
+#define OMAP3430_EN_MMC3_SHIFT				30
+#define OMAP3430_EN_MMC2_MASK				(1 << 25)
+#define OMAP3430_EN_MMC2_SHIFT				25
+#define OMAP3430_EN_MMC1_MASK				(1 << 24)
+#define OMAP3430_EN_MMC1_SHIFT				24
+#define AM35XX_EN_UART4_MASK				(1 << 23)
+#define AM35XX_EN_UART4_SHIFT				23
+#define OMAP3430_EN_MCSPI4_MASK				(1 << 21)
+#define OMAP3430_EN_MCSPI4_SHIFT			21
+#define OMAP3430_EN_MCSPI3_MASK				(1 << 20)
+#define OMAP3430_EN_MCSPI3_SHIFT			20
+#define OMAP3430_EN_MCSPI2_MASK				(1 << 19)
+#define OMAP3430_EN_MCSPI2_SHIFT			19
+#define OMAP3430_EN_MCSPI1_MASK				(1 << 18)
+#define OMAP3430_EN_MCSPI1_SHIFT			18
+#define OMAP3430_EN_I2C3_MASK				(1 << 17)
+#define OMAP3430_EN_I2C3_SHIFT				17
+#define OMAP3430_EN_I2C2_MASK				(1 << 16)
+#define OMAP3430_EN_I2C2_SHIFT				16
+#define OMAP3430_EN_I2C1_MASK				(1 << 15)
+#define OMAP3430_EN_I2C1_SHIFT				15
+#define OMAP3430_EN_UART2_MASK				(1 << 14)
+#define OMAP3430_EN_UART2_SHIFT				14
+#define OMAP3430_EN_UART1_MASK				(1 << 13)
+#define OMAP3430_EN_UART1_SHIFT				13
+#define OMAP3430_EN_GPT11_MASK				(1 << 12)
+#define OMAP3430_EN_GPT11_SHIFT				12
+#define OMAP3430_EN_GPT10_MASK				(1 << 11)
+#define OMAP3430_EN_GPT10_SHIFT				11
+#define OMAP3430_EN_MCBSP5_MASK				(1 << 10)
+#define OMAP3430_EN_MCBSP5_SHIFT			10
+#define OMAP3430_EN_MCBSP1_MASK				(1 << 9)
+#define OMAP3430_EN_MCBSP1_SHIFT			9
+#define OMAP3430_EN_FSHOSTUSB_MASK			(1 << 5)
+#define OMAP3430_EN_FSHOSTUSB_SHIFT			5
+#define OMAP3430_EN_D2D_MASK				(1 << 3)
+#define OMAP3430_EN_D2D_SHIFT				3
+
+/* CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
+#define OMAP3430_EN_HSOTGUSB_MASK			(1 << 4)
+#define OMAP3430_EN_HSOTGUSB_SHIFT			4
+
+/* PM_WKST1_CORE, CM_IDLEST1_CORE shared bits */
+#define OMAP3430_ST_MMC3_SHIFT				30
+#define OMAP3430_ST_MMC3_MASK				(1 << 30)
+#define OMAP3430_ST_MMC2_SHIFT				25
+#define OMAP3430_ST_MMC2_MASK				(1 << 25)
+#define OMAP3430_ST_MMC1_SHIFT				24
+#define OMAP3430_ST_MMC1_MASK				(1 << 24)
+#define OMAP3430_ST_MCSPI4_SHIFT			21
+#define OMAP3430_ST_MCSPI4_MASK				(1 << 21)
+#define OMAP3430_ST_MCSPI3_SHIFT			20
+#define OMAP3430_ST_MCSPI3_MASK				(1 << 20)
+#define OMAP3430_ST_MCSPI2_SHIFT			19
+#define OMAP3430_ST_MCSPI2_MASK				(1 << 19)
+#define OMAP3430_ST_MCSPI1_SHIFT			18
+#define OMAP3430_ST_MCSPI1_MASK				(1 << 18)
+#define OMAP3430_ST_I2C3_SHIFT				17
+#define OMAP3430_ST_I2C3_MASK				(1 << 17)
+#define OMAP3430_ST_I2C2_SHIFT				16
+#define OMAP3430_ST_I2C2_MASK				(1 << 16)
+#define OMAP3430_ST_I2C1_SHIFT				15
+#define OMAP3430_ST_I2C1_MASK				(1 << 15)
+#define OMAP3430_ST_UART2_SHIFT				14
+#define OMAP3430_ST_UART2_MASK				(1 << 14)
+#define OMAP3430_ST_UART1_SHIFT				13
+#define OMAP3430_ST_UART1_MASK				(1 << 13)
+#define OMAP3430_ST_GPT11_SHIFT				12
+#define OMAP3430_ST_GPT11_MASK				(1 << 12)
+#define OMAP3430_ST_GPT10_SHIFT				11
+#define OMAP3430_ST_GPT10_MASK				(1 << 11)
+#define OMAP3430_ST_MCBSP5_SHIFT			10
+#define OMAP3430_ST_MCBSP5_MASK				(1 << 10)
+#define OMAP3430_ST_MCBSP1_SHIFT			9
+#define OMAP3430_ST_MCBSP1_MASK				(1 << 9)
+#define OMAP3430ES1_ST_FSHOSTUSB_SHIFT			5
+#define OMAP3430ES1_ST_FSHOSTUSB_MASK			(1 << 5)
+#define OMAP3430ES1_ST_HSOTGUSB_SHIFT			4
+#define OMAP3430ES1_ST_HSOTGUSB_MASK			(1 << 4)
+#define OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT		5
+#define OMAP3430ES2_ST_HSOTGUSB_IDLE_MASK		(1 << 5)
+#define OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT		4
+#define OMAP3430ES2_ST_HSOTGUSB_STDBY_MASK		(1 << 4)
+#define OMAP3430_ST_D2D_SHIFT				3
+#define OMAP3430_ST_D2D_MASK				(1 << 3)
+
+/* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
+#define OMAP3430_EN_GPIO1_MASK				(1 << 3)
+#define OMAP3430_EN_GPIO1_SHIFT				3
+#define OMAP3430_EN_GPT12_MASK				(1 << 1)
+#define OMAP3430_EN_GPT12_SHIFT				1
+#define OMAP3430_EN_GPT1_MASK				(1 << 0)
+#define OMAP3430_EN_GPT1_SHIFT				0
+
+/* CM_FCLKEN_WKUP, PM_WKEN_WKUP shared bits */
+#define OMAP3430_EN_SR2_MASK				(1 << 7)
+#define OMAP3430_EN_SR2_SHIFT				7
+#define OMAP3430_EN_SR1_MASK				(1 << 6)
+#define OMAP3430_EN_SR1_SHIFT				6
+
+/* CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
+#define OMAP3430_EN_GPT12_MASK				(1 << 1)
+#define OMAP3430_EN_GPT12_SHIFT				1
+
+/* CM_IDLEST_WKUP, PM_WKST_WKUP shared bits */
+#define OMAP3430_ST_SR2_SHIFT				7
+#define OMAP3430_ST_SR2_MASK				(1 << 7)
+#define OMAP3430_ST_SR1_SHIFT				6
+#define OMAP3430_ST_SR1_MASK				(1 << 6)
+#define OMAP3430_ST_GPIO1_SHIFT				3
+#define OMAP3430_ST_GPIO1_MASK				(1 << 3)
+#define OMAP3430_ST_32KSYNC_SHIFT			2
+#define OMAP3430_ST_32KSYNC_MASK			(1 << 2)
+#define OMAP3430_ST_GPT12_SHIFT				1
+#define OMAP3430_ST_GPT12_MASK				(1 << 1)
+#define OMAP3430_ST_GPT1_SHIFT				0
+#define OMAP3430_ST_GPT1_MASK				(1 << 0)
+
+/*
+ * CM_SLEEPDEP_GFX, CM_SLEEPDEP_DSS, CM_SLEEPDEP_CAM,
+ * CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_GFX,
+ * PM_WKDEP_DSS, PM_WKDEP_CAM, PM_WKDEP_PER, PM_WKDEP_NEON shared bits
+ */
+#define OMAP3430_EN_MPU_MASK				(1 << 1)
+#define OMAP3430_EN_MPU_SHIFT				1
+
+/* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER shared bits */
+
+#define OMAP3630_EN_UART4_MASK				(1 << 18)
+#define OMAP3630_EN_UART4_SHIFT				18
+#define OMAP3430_EN_GPIO6_MASK				(1 << 17)
+#define OMAP3430_EN_GPIO6_SHIFT				17
+#define OMAP3430_EN_GPIO5_MASK				(1 << 16)
+#define OMAP3430_EN_GPIO5_SHIFT				16
+#define OMAP3430_EN_GPIO4_MASK				(1 << 15)
+#define OMAP3430_EN_GPIO4_SHIFT				15
+#define OMAP3430_EN_GPIO3_MASK				(1 << 14)
+#define OMAP3430_EN_GPIO3_SHIFT				14
+#define OMAP3430_EN_GPIO2_MASK				(1 << 13)
+#define OMAP3430_EN_GPIO2_SHIFT				13
+#define OMAP3430_EN_UART3_MASK				(1 << 11)
+#define OMAP3430_EN_UART3_SHIFT				11
+#define OMAP3430_EN_GPT9_MASK				(1 << 10)
+#define OMAP3430_EN_GPT9_SHIFT				10
+#define OMAP3430_EN_GPT8_MASK				(1 << 9)
+#define OMAP3430_EN_GPT8_SHIFT				9
+#define OMAP3430_EN_GPT7_MASK				(1 << 8)
+#define OMAP3430_EN_GPT7_SHIFT				8
+#define OMAP3430_EN_GPT6_MASK				(1 << 7)
+#define OMAP3430_EN_GPT6_SHIFT				7
+#define OMAP3430_EN_GPT5_MASK				(1 << 6)
+#define OMAP3430_EN_GPT5_SHIFT				6
+#define OMAP3430_EN_GPT4_MASK				(1 << 5)
+#define OMAP3430_EN_GPT4_SHIFT				5
+#define OMAP3430_EN_GPT3_MASK				(1 << 4)
+#define OMAP3430_EN_GPT3_SHIFT				4
+#define OMAP3430_EN_GPT2_MASK				(1 << 3)
+#define OMAP3430_EN_GPT2_SHIFT				3
+
+/* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER, PM_WKST_PER shared bits */
+/* XXX Possible TI documentation bug: should the PM_WKST_PER EN_* bits
+ * be ST_* bits instead? */
+#define OMAP3430_EN_MCBSP4_MASK				(1 << 2)
+#define OMAP3430_EN_MCBSP4_SHIFT			2
+#define OMAP3430_EN_MCBSP3_MASK				(1 << 1)
+#define OMAP3430_EN_MCBSP3_SHIFT			1
+#define OMAP3430_EN_MCBSP2_MASK				(1 << 0)
+#define OMAP3430_EN_MCBSP2_SHIFT			0
+
+/* CM_IDLEST_PER, PM_WKST_PER shared bits */
+#define OMAP3630_ST_UART4_SHIFT				18
+#define OMAP3630_ST_UART4_MASK				(1 << 18)
+#define OMAP3430_ST_GPIO6_SHIFT				17
+#define OMAP3430_ST_GPIO6_MASK				(1 << 17)
+#define OMAP3430_ST_GPIO5_SHIFT				16
+#define OMAP3430_ST_GPIO5_MASK				(1 << 16)
+#define OMAP3430_ST_GPIO4_SHIFT				15
+#define OMAP3430_ST_GPIO4_MASK				(1 << 15)
+#define OMAP3430_ST_GPIO3_SHIFT				14
+#define OMAP3430_ST_GPIO3_MASK				(1 << 14)
+#define OMAP3430_ST_GPIO2_SHIFT				13
+#define OMAP3430_ST_GPIO2_MASK				(1 << 13)
+#define OMAP3430_ST_UART3_SHIFT				11
+#define OMAP3430_ST_UART3_MASK				(1 << 11)
+#define OMAP3430_ST_GPT9_SHIFT				10
+#define OMAP3430_ST_GPT9_MASK				(1 << 10)
+#define OMAP3430_ST_GPT8_SHIFT				9
+#define OMAP3430_ST_GPT8_MASK				(1 << 9)
+#define OMAP3430_ST_GPT7_SHIFT				8
+#define OMAP3430_ST_GPT7_MASK				(1 << 8)
+#define OMAP3430_ST_GPT6_SHIFT				7
+#define OMAP3430_ST_GPT6_MASK				(1 << 7)
+#define OMAP3430_ST_GPT5_SHIFT				6
+#define OMAP3430_ST_GPT5_MASK				(1 << 6)
+#define OMAP3430_ST_GPT4_SHIFT				5
+#define OMAP3430_ST_GPT4_MASK				(1 << 5)
+#define OMAP3430_ST_GPT3_SHIFT				4
+#define OMAP3430_ST_GPT3_MASK				(1 << 4)
+#define OMAP3430_ST_GPT2_SHIFT				3
+#define OMAP3430_ST_GPT2_MASK				(1 << 3)
+
+/* CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_MPU, PM_WKDEP_PER shared bits */
+#define OMAP3430_EN_CORE_SHIFT				0
+#define OMAP3430_EN_CORE_MASK				(1 << 0)
+
+
+
+/*
+ * Maximum time(us) it takes to output the signal WUCLKOUT of the last
+ * pad of the I/O ring after asserting WUCLKIN high.  Tero measured
+ * the actual time at 7 to 8 microseconds on OMAP3 and 2 to 4
+ * microseconds on OMAP4, so this timeout may be too high.
+ */
+#define MAX_IOPAD_LATCH_TIME			100
+# ifndef __ASSEMBLER__
+
+#include <linux/delay.h>
+
+/**
+ * omap_test_timeout - busy-loop, testing a condition
+ * @cond: condition to test until it evaluates to true
+ * @timeout: maximum number of microseconds in the timeout
+ * @index: loop index (integer)
+ *
+ * Loop waiting for @cond to become true or until at least @timeout
+ * microseconds have passed.  To use, define some integer @index in the
+ * calling code.  After running, if @index == @timeout, then the loop has
+ * timed out.
+ */
+#define omap_test_timeout(cond, timeout, index)			\
+({								\
+	for (index = 0; index < timeout; index++) {		\
+		if (cond)					\
+			break;					\
+		udelay(1);					\
+	}							\
+})
+
+/**
+ * struct omap_prcm_irq - describes a PRCM interrupt bit
+ * @name: a short name describing the interrupt type, e.g. "wkup" or "io"
+ * @offset: the bit shift of the interrupt inside the IRQ{ENABLE,STATUS} regs
+ * @priority: should this interrupt be handled before @priority=false IRQs?
+ *
+ * Describes interrupt bits inside the PRM_IRQ{ENABLE,STATUS}_MPU* registers.
+ * On systems with multiple PRM MPU IRQ registers, the bitfields read from
+ * the registers are concatenated, so @offset could be > 31 on these systems -
+ * see omap_prm_irq_handler() for more details.  I/O ring interrupts should
+ * have @priority set to true.
+ */
+struct omap_prcm_irq {
+	const char *name;
+	unsigned int offset;
+	bool priority;
+};
+
+/**
+ * struct omap_prcm_irq_setup - PRCM interrupt controller details
+ * @ack: PRM register offset for the first PRM_IRQSTATUS_MPU register
+ * @mask: PRM register offset for the first PRM_IRQENABLE_MPU register
+ * @nr_regs: number of PRM_IRQ{STATUS,ENABLE}_MPU* registers
+ * @nr_irqs: number of entries in the @irqs array
+ * @irqs: ptr to an array of PRCM interrupt bits (see @nr_irqs)
+ * @irq: MPU IRQ asserted when a PRCM interrupt arrives
+ * @read_pending_irqs: fn ptr to determine if any PRCM IRQs are pending
+ * @ocp_barrier: fn ptr to force buffered PRM writes to complete
+ * @save_and_clear_irqen: fn ptr to save and clear IRQENABLE regs
+ * @restore_irqen: fn ptr to save and clear IRQENABLE regs
+ * @reconfigure_io_chain: fn ptr to reconfigure IO chain
+ * @saved_mask: IRQENABLE regs are saved here during suspend
+ * @priority_mask: 1 bit per IRQ, set to 1 if omap_prcm_irq.priority = true
+ * @base_irq: base dynamic IRQ number, returned from irq_alloc_descs() in init
+ * @suspended: set to true after Linux suspend code has called our ->prepare()
+ * @suspend_save_flag: set to true after IRQ masks have been saved and disabled
+ *
+ * @saved_mask, @priority_mask, @base_irq, @suspended, and
+ * @suspend_save_flag are populated dynamically, and are not to be
+ * specified in static initializers.
+ */
+struct omap_prcm_irq_setup {
+	u16 ack;
+	u16 mask;
+	u8 nr_regs;
+	u8 nr_irqs;
+	const struct omap_prcm_irq *irqs;
+	int irq;
+	void (*read_pending_irqs)(unsigned long *events);
+	void (*ocp_barrier)(void);
+	void (*save_and_clear_irqen)(u32 *saved_mask);
+	void (*restore_irqen)(u32 *saved_mask);
+	void (*reconfigure_io_chain)(void);
+	u32 *saved_mask;
+	u32 *priority_mask;
+	int base_irq;
+	bool suspended;
+	bool suspend_save_flag;
+};
+
+/* OMAP_PRCM_IRQ: convenience macro for creating struct omap_prcm_irq records */
+#define OMAP_PRCM_IRQ(_name, _offset, _priority) {	\
+	.name = _name,					\
+	.offset = _offset,				\
+	.priority = _priority				\
+	}
+
+struct of_device_id;
+
+extern void __iomem *clk_memmaps[];
+
+void omap_prcm_irq_cleanup(void);
+int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup);
+int omap_prcm_event_to_irq(const char *event);
+void omap_prcm_irq_prepare(void);
+void omap_prcm_irq_complete(void);
+void omap_pcs_legacy_init(int irq, void (*rearm)(void));
+int of_prcm_module_init(struct of_device_id *match_table);
+int of_cm_init(void);
+
+# endif
+
+#endif
-- 
1.7.9.5

[PATCH 48/55] ARM: OMAP2+: move prm.h header to public location

[Tero Kristo]

This file needs to be accessible from the PRCM core and mach-omap2 board
support code.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/cminst44xx.c                 |    2 +-
 arch/arm/mach-omap2/cpuidle44xx.c                |    2 +-
 arch/arm/mach-omap2/display.c                    |    2 +-
 arch/arm/mach-omap2/hdq1w.c                      |    2 +-
 arch/arm/mach-omap2/i2c.c                        |    3 +-
 arch/arm/mach-omap2/io.c                         |    2 +-
 arch/arm/mach-omap2/msdi.c                       |    2 +-
 arch/arm/mach-omap2/mux.c                        |    3 +-
 arch/arm/mach-omap2/omap_hwmod.c                 |    2 +-
 arch/arm/mach-omap2/powerdomain.c                |    2 +-
 arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c |    2 +-
 arch/arm/mach-omap2/prm-regbits-33xx.h           |    2 +-
 arch/arm/mach-omap2/prm.h                        |  164 ----------------------
 arch/arm/mach-omap2/prm2xxx.h                    |    2 +-
 arch/arm/mach-omap2/prm2xxx_3xxx_private.h       |    2 +-
 arch/arm/mach-omap2/prm33xx.c                    |    2 +-
 arch/arm/mach-omap2/prm33xx.h                    |    2 +-
 arch/arm/mach-omap2/prm3xxx.h                    |    2 +-
 arch/arm/mach-omap2/prm44xx.c                    |    2 +-
 arch/arm/mach-omap2/prm44xx.h                    |    2 +-
 arch/arm/mach-omap2/prm54xx.h                    |    2 +-
 arch/arm/mach-omap2/prm7xx.h                     |    2 +-
 arch/arm/mach-omap2/prm_common.c                 |    2 +-
 arch/arm/mach-omap2/prminst44xx.c                |    2 +-
 arch/arm/mach-omap2/wd_timer.c                   |    2 +-
 include/linux/power/omap/prm.h                   |  164 ++++++++++++++++++++++
 26 files changed, 189 insertions(+), 189 deletions(-)
 delete mode 100644 arch/arm/mach-omap2/prm.h
 create mode 100644 include/linux/power/omap/prm.h

diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c
index 5ebd8e3..0fd50d7 100644
--- a/arch/arm/mach-omap2/cminst44xx.c
+++ b/arch/arm/mach-omap2/cminst44xx.c
@@ -21,7 +21,7 @@
 #include <linux/err.h>
 #include <linux/io.h>
 
-#include "prm.h"
+#include <linux/power/omap/prm.h>
 #include "clockdomain.h"
 #include <linux/power/omap/cm.h>
 #include "cm1_44xx.h"
diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c
index 4c158c8..4324e4e 100644
--- a/arch/arm/mach-omap2/cpuidle44xx.c
+++ b/arch/arm/mach-omap2/cpuidle44xx.c
@@ -20,7 +20,7 @@
 
 #include "common.h"
 #include "pm.h"
-#include "prm.h"
+#include <linux/power/omap/prm.h>
 #include "clockdomain.h"
 
 /* Machine specific information */
diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
index 4cf1655..64a1331 100644
--- a/arch/arm/mach-omap2/display.c
+++ b/arch/arm/mach-omap2/display.c
@@ -23,6 +23,7 @@
 #include <linux/clk.h>
 #include <linux/err.h>
 #include <linux/delay.h>
+#include <linux/power/omap/prm.h>
 
 #include <video/omapdss.h>
 #include "omap_hwmod.h"
@@ -34,7 +35,6 @@
 #include "iomap.h"
 #include "control.h"
 #include "display.h"
-#include "prm.h"
 
 #define DISPC_CONTROL		0x0040
 #define DISPC_CONTROL2		0x0238
diff --git a/arch/arm/mach-omap2/hdq1w.c b/arch/arm/mach-omap2/hdq1w.c
index cbc8e3c..4bbc313 100644
--- a/arch/arm/mach-omap2/hdq1w.c
+++ b/arch/arm/mach-omap2/hdq1w.c
@@ -26,13 +26,13 @@
 #include <linux/init.h>
 #include <linux/err.h>
 #include <linux/platform_device.h>
+#include <linux/power/omap/prm.h>
 
 #include "soc.h"
 #include "omap_hwmod.h"
 #include "omap_device.h"
 #include "hdq1w.h"
 
-#include "prm.h"
 #include "common.h"
 
 /**
diff --git a/arch/arm/mach-omap2/i2c.c b/arch/arm/mach-omap2/i2c.c
index b456b44..b8f9dd5 100644
--- a/arch/arm/mach-omap2/i2c.c
+++ b/arch/arm/mach-omap2/i2c.c
@@ -19,12 +19,13 @@
  *
  */
 
+#include <linux/power/omap/prm.h>
+
 #include "soc.h"
 #include "omap_hwmod.h"
 #include "omap_device.h"
 #include "omap-pm.h"
 
-#include "prm.h"
 #include "common.h"
 #include "mux.h"
 #include "i2c.h"
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 96d498f..e9f7db9 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -45,7 +45,7 @@
 #include "sram.h"
 #include "cm2xxx.h"
 #include "cm3xxx.h"
-#include "prm.h"
+#include <linux/power/omap/prm.h>
 #include <linux/power/omap/cm.h>
 #include "prcm_mpu44xx.h"
 #include <linux/power/omap/cm44xx.h>
diff --git a/arch/arm/mach-omap2/msdi.c b/arch/arm/mach-omap2/msdi.c
index 828e0db..5abf695 100644
--- a/arch/arm/mach-omap2/msdi.c
+++ b/arch/arm/mach-omap2/msdi.c
@@ -24,8 +24,8 @@
 #include <linux/kernel.h>
 #include <linux/err.h>
 #include <linux/platform_data/gpio-omap.h>
+#include <linux/power/omap/prm.h>
 
-#include "prm.h"
 #include "common.h"
 #include "control.h"
 #include "omap_hwmod.h"
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 48094b5..8e865eb 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -34,14 +34,13 @@
 #include <linux/uaccess.h>
 #include <linux/irq.h>
 #include <linux/interrupt.h>
-
+#include <linux/power/omap/prm.h>
 
 #include "omap_hwmod.h"
 
 #include "soc.h"
 #include "control.h"
 #include "mux.h"
-#include "prm.h"
 #include "common.h"
 
 #define OMAP_MUX_BASE_OFFSET		0x30	/* Offset from CTRL_BASE */
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 096c43d..df0c2a0 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -155,7 +155,7 @@
 #include "cm3xxx.h"
 #include <linux/power/omap/cm44xx.h>
 #include "cm33xx.h"
-#include "prm.h"
+#include <linux/power/omap/prm.h>
 #include "prm3xxx.h"
 #include "prm44xx.h"
 #include "prm33xx.h"
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index a29d50c..7262b3d 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -29,7 +29,7 @@
 
 #include <asm/cpu.h>
 
-#include "prm.h"
+#include <linux/power/omap/prm.h>
 #include "powerdomain.h"
 #include "clockdomain.h"
 #include "voltage.h"
diff --git a/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c b/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c
index 57abec8..823bc4d 100644
--- a/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c
+++ b/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c
@@ -34,7 +34,7 @@
 #include "powerdomain.h"
 
 #include <linux/power/omap/prcm-common.h>
-#include "prm.h"
+#include <linux/power/omap/prm.h>
 
 /* OMAP2/3-common powerdomains */
 
diff --git a/arch/arm/mach-omap2/prm-regbits-33xx.h b/arch/arm/mach-omap2/prm-regbits-33xx.h
index 84feece..70d22b6 100644
--- a/arch/arm/mach-omap2/prm-regbits-33xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-33xx.h
@@ -16,7 +16,7 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_33XX_H
 #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_33XX_H
 
-#include "prm.h"
+#include <linux/power/omap/prm.h>
 
 #define AM33XX_GFX_MEM_ONSTATE_MASK			(0x3 << 17)
 #define AM33XX_GFX_MEM_RETSTATE_MASK			(1 << 6)
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
deleted file mode 100644
index 6a02cf3..0000000
--- a/arch/arm/mach-omap2/prm.h
+++ /dev/null
@@ -1,164 +0,0 @@
-/*
- * OMAP2/3/4 Power/Reset Management (PRM) bitfield definitions
- *
- * Copyright (C) 2007-2009, 2012 Texas Instruments, Inc.
- * Copyright (C) 2010 Nokia Corporation
- *
- * Paul Walmsley
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __ARCH_ARM_MACH_OMAP2_PRM_H
-#define __ARCH_ARM_MACH_OMAP2_PRM_H
-
-#include <linux/power/omap/prcm-common.h>
-
-# ifndef __ASSEMBLER__
-extern void __iomem *prm_base;
-extern u16 prm_dev_inst;
-extern u16 prm_features;
-extern void omap2_set_globals_prm(void __iomem *prm);
-int of_prcm_init(void);
-# endif
-
-/*
- * prm_features flag values
- *
- * PRM_HAS_IO_WAKEUP: has IO wakeup capability
- * PRM_HAS_VOLTAGE: has voltage domains
- */
-#define PRM_HAS_IO_WAKEUP	(1 << 0)
-#define PRM_HAS_VOLTAGE		(1 << 1)
-
-#ifndef __ASSEMBLER__
-enum {
-	PRM_OMAP3430 = 0,
-	PRM_OMAP3630,
-	PRM_OMAP3_OTHER,
-	PRM_OMAP4,
-	PRM_OMAP5,
-	PRM_DRA7,
-};
-#endif
-
-/*
- * MAX_MODULE_SOFTRESET_WAIT: Maximum microseconds to wait for OMAP
- * module to softreset
- */
-#define MAX_MODULE_SOFTRESET_WAIT		10000
-
-/*
- * MAX_MODULE_HARDRESET_WAIT: Maximum microseconds to wait for an OMAP
- * submodule to exit hardreset
- */
-#define MAX_MODULE_HARDRESET_WAIT		10000
-
-/*
- * Register bitfields
- */
-
-/*
- * 24XX: PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP
- *
- * 2430: PM_PWSTST_MDM
- *
- * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX,
- *	 PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU,
- *	 PM_PWSTST_NEON
- */
-#define OMAP_INTRANSITION_MASK				(1 << 20)
-
-
-/*
- * 24XX: PM_PWSTST_GFX, PM_PWSTST_DSP
- *
- * 2430: PM_PWSTST_MDM
- *
- * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX,
- *	 PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU,
- *	 PM_PWSTST_NEON
- */
-#define OMAP_POWERSTATEST_SHIFT				0
-#define OMAP_POWERSTATEST_MASK				(0x3 << 0)
-
-/*
- * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
- *       PM_PWSTCTRL_DSP, PM_PWSTST_MPU
- *
- * 2430: PM_PWSTCTRL_MDM shared bits
- *
- * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE,
- *	 PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
- *	 PM_PWSTCTRL_NEON shared bits
- */
-#define OMAP_POWERSTATE_SHIFT				0
-#define OMAP_POWERSTATE_MASK				(0x3 << 0)
-
-/*
- * Standardized OMAP reset source bits
- *
- * To the extent these happen to match the hardware register bit
- * shifts, it's purely coincidental.  Used by omap-wdt.c.
- * OMAP_UNKNOWN_RST_SRC_ID_SHIFT is a special value, used whenever
- * there are any bits remaining in the global PRM_RSTST register that
- * haven't been identified, or when the PRM code for the current SoC
- * doesn't know how to interpret the register.
- */
-#define OMAP_GLOBAL_COLD_RST_SRC_ID_SHIFT			0
-#define OMAP_GLOBAL_WARM_RST_SRC_ID_SHIFT			1
-#define OMAP_SECU_VIOL_RST_SRC_ID_SHIFT				2
-#define OMAP_MPU_WD_RST_SRC_ID_SHIFT				3
-#define OMAP_SECU_WD_RST_SRC_ID_SHIFT				4
-#define OMAP_EXTWARM_RST_SRC_ID_SHIFT				5
-#define OMAP_VDD_MPU_VM_RST_SRC_ID_SHIFT			6
-#define OMAP_VDD_IVA_VM_RST_SRC_ID_SHIFT			7
-#define OMAP_VDD_CORE_VM_RST_SRC_ID_SHIFT			8
-#define OMAP_ICEPICK_RST_SRC_ID_SHIFT				9
-#define OMAP_ICECRUSHER_RST_SRC_ID_SHIFT			10
-#define OMAP_C2C_RST_SRC_ID_SHIFT				11
-#define OMAP_UNKNOWN_RST_SRC_ID_SHIFT				12
-
-#ifndef __ASSEMBLER__
-
-/**
- * struct prm_reset_src_map - map register bitshifts to standard bitshifts
- * @reg_shift: bitshift in the PRM reset source register
- * @std_shift: bitshift equivalent in the standard reset source list
- *
- * The fields are signed because -1 is used as a terminator.
- */
-struct prm_reset_src_map {
-	s8 reg_shift;
-	s8 std_shift;
-};
-
-/**
- * struct prm_ll_data - fn ptrs to per-SoC PRM function implementations
- * @read_reset_sources: ptr to the SoC PRM-specific get_reset_source impl
- * @was_any_context_lost_old: ptr to the SoC PRM context loss test fn
- * @clear_context_loss_flags_old: ptr to the SoC PRM context loss flag clear fn
- * @late_init: ptr to the late init function
- *
- * XXX @was_any_context_lost_old and @clear_context_loss_flags_old are
- * deprecated.
- */
-struct prm_ll_data {
-	u32 (*read_reset_sources)(void);
-	bool (*was_any_context_lost_old)(u8 part, s16 inst, u16 idx);
-	void (*clear_context_loss_flags_old)(u8 part, s16 inst, u16 idx);
-	int (*late_init)(void);
-};
-
-extern int prm_register(struct prm_ll_data *pld);
-extern int prm_unregister(struct prm_ll_data *pld);
-
-extern u32 prm_read_reset_sources(void);
-extern bool prm_was_any_context_lost_old(u8 part, s16 inst, u16 idx);
-extern void prm_clear_context_loss_flags_old(u8 part, s16 inst, u16 idx);
-
-#endif
-
-
-#endif
diff --git a/arch/arm/mach-omap2/prm2xxx.h b/arch/arm/mach-omap2/prm2xxx.h
index b86486b..8f8a515 100644
--- a/arch/arm/mach-omap2/prm2xxx.h
+++ b/arch/arm/mach-omap2/prm2xxx.h
@@ -17,7 +17,7 @@
 #define __ARCH_ARM_MACH_OMAP2_PRM2XXX_H
 
 #include <linux/power/omap/prcm-common.h>
-#include "prm.h"
+#include <linux/power/omap/prm.h>
 #include <linux/power/omap/prm2xxx.h>
 #include <linux/power/omap/prm2xxx_3xxx.h>
 
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx_private.h b/arch/arm/mach-omap2/prm2xxx_3xxx_private.h
index c02a267..5d6861a 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx_private.h
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx_private.h
@@ -17,7 +17,7 @@
 #define __ARCH_ARM_MACH_OMAP2_PRM2XXX_3XXX_PRIVATE_H
 
 #include <linux/power/omap/prcm-common.h>
-#include "prm.h"
+#include <linux/power/omap/prm.h>
 #include <linux/power/omap/prm2xxx_3xxx.h>
 
 #ifndef __ASSEMBLER__
diff --git a/arch/arm/mach-omap2/prm33xx.c b/arch/arm/mach-omap2/prm33xx.c
index 436cd12..b5864c9 100644
--- a/arch/arm/mach-omap2/prm33xx.c
+++ b/arch/arm/mach-omap2/prm33xx.c
@@ -21,7 +21,7 @@
 #include <linux/power/omap/prm33xx.h>
 
 #include "powerdomain.h"
-#include "prm.h"
+#include <linux/power/omap/prm.h>
 
 #define AM33XX_LASTPOWERSTATEENTERED_SHIFT	24
 #define AM33XX_LASTPOWERSTATEENTERED_MASK	(0x3 << 24)
diff --git a/arch/arm/mach-omap2/prm33xx.h b/arch/arm/mach-omap2/prm33xx.h
index 598ba48..c27b5a0 100644
--- a/arch/arm/mach-omap2/prm33xx.h
+++ b/arch/arm/mach-omap2/prm33xx.h
@@ -17,7 +17,7 @@
 #define __ARCH_ARM_MACH_OMAP2_PRM33XX_H
 
 #include <linux/power/omap/prcm-common.h>
-#include "prm.h"
+#include <linux/power/omap/prm.h>
 #include <linux/power/omap/prm33xx.h>
 
 #define AM33XX_PRM_BASE               0x44E00000
diff --git a/arch/arm/mach-omap2/prm3xxx.h b/arch/arm/mach-omap2/prm3xxx.h
index 693b5ad..e48f7be 100644
--- a/arch/arm/mach-omap2/prm3xxx.h
+++ b/arch/arm/mach-omap2/prm3xxx.h
@@ -17,7 +17,7 @@
 #define __ARCH_ARM_MACH_OMAP2_PRM3XXX_H
 
 #include <linux/power/omap/prcm-common.h>
-#include "prm.h"
+#include <linux/power/omap/prm.h>
 #include <linux/power/omap/prm2xxx_3xxx.h>
 #include <linux/power/omap/prm3xxx.h>
 
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index 705509a..cf312a8 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -25,7 +25,7 @@
 #include "prcm44xx.h"
 #include "prminst44xx_private.h"
 #include "powerdomain.h"
-#include "prm.h"
+#include <linux/power/omap/prm.h>
 #include <linux/power/omap/prcm-common.h>
 #include <linux/power/omap/prm44xx_54xx.h>
 
diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h
index b7066fd..dc9d21c 100644
--- a/arch/arm/mach-omap2/prm44xx.h
+++ b/arch/arm/mach-omap2/prm44xx.h
@@ -27,7 +27,7 @@
 
 #include <linux/power/omap/prm44xx_54xx.h>
 #include <linux/power/omap/prcm-common.h>
-#include "prm.h"
+#include <linux/power/omap/prm.h>
 #include <linux/power/omap/prm44xx.h>
 
 #define OMAP4430_PRM_BASE		0x4a306000
diff --git a/arch/arm/mach-omap2/prm54xx.h b/arch/arm/mach-omap2/prm54xx.h
index 250c2d5..a3895f7 100644
--- a/arch/arm/mach-omap2/prm54xx.h
+++ b/arch/arm/mach-omap2/prm54xx.h
@@ -23,7 +23,7 @@
 
 #include <linux/power/omap/prm44xx_54xx.h>
 #include <linux/power/omap/prcm-common.h>
-#include "prm.h"
+#include <linux/power/omap/prm.h>
 #include <linux/power/omap/prm54xx.h>
 
 #define OMAP54XX_PRM_BASE		0x4ae06000
diff --git a/arch/arm/mach-omap2/prm7xx.h b/arch/arm/mach-omap2/prm7xx.h
index 6e84906..de2ce3d 100644
--- a/arch/arm/mach-omap2/prm7xx.h
+++ b/arch/arm/mach-omap2/prm7xx.h
@@ -24,7 +24,7 @@
 
 #include <linux/power/omap/prm44xx_54xx.h>
 #include <linux/power/omap/prcm-common.h>
-#include "prm.h"
+#include <linux/power/omap/prm.h>
 #include <linux/power/omap/prm7xx.h>
 
 #define DRA7XX_PRM_BASE		0x4ae06000
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index acdd0f1..fb377e1 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -33,7 +33,7 @@
 #include <linux/power/omap/prm3xxx.h>
 #include <linux/power/omap/prm44xx.h>
 
-#include "prm.h"
+#include <linux/power/omap/prm.h>
 #include <linux/power/omap/prcm-common.h>
 
 /*
diff --git a/arch/arm/mach-omap2/prminst44xx.c b/arch/arm/mach-omap2/prminst44xx.c
index 50c660d..30015d1 100644
--- a/arch/arm/mach-omap2/prminst44xx.c
+++ b/arch/arm/mach-omap2/prminst44xx.c
@@ -16,7 +16,7 @@
 #include <linux/err.h>
 #include <linux/io.h>
 
-#include "prm.h"
+#include <linux/power/omap/prm.h>
 #include <linux/power/omap/prcm-common.h>
 #include <linux/power/omap/prm44xx.h>
 #include <linux/power/omap/prm54xx.h>
diff --git a/arch/arm/mach-omap2/wd_timer.c b/arch/arm/mach-omap2/wd_timer.c
index d15c7bb..9d528c6 100644
--- a/arch/arm/mach-omap2/wd_timer.c
+++ b/arch/arm/mach-omap2/wd_timer.c
@@ -14,12 +14,12 @@
 #include <linux/err.h>
 
 #include <linux/platform_data/omap-wd-timer.h>
+#include <linux/power/omap/prm.h>
 
 #include "omap_hwmod.h"
 #include "omap_device.h"
 #include "wd_timer.h"
 #include "common.h"
-#include "prm.h"
 #include "soc.h"
 
 /*
diff --git a/include/linux/power/omap/prm.h b/include/linux/power/omap/prm.h
new file mode 100644
index 0000000..4bc93ca
--- /dev/null
+++ b/include/linux/power/omap/prm.h
@@ -0,0 +1,164 @@
+/*
+ * OMAP2/3/4 Power/Reset Management (PRM) bitfield definitions
+ *
+ * Copyright (C) 2007-2009, 2012 Texas Instruments, Inc.
+ * Copyright (C) 2010 Nokia Corporation
+ *
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __LINUX_POWER_OMAP_PRM_H
+#define __LINUX_POWER_OMAP_PRM_H
+
+#include <linux/power/omap/prcm-common.h>
+
+# ifndef __ASSEMBLER__
+extern void __iomem *prm_base;
+extern u16 prm_dev_inst;
+extern u16 prm_features;
+void omap2_set_globals_prm(void __iomem *prm);
+int of_prcm_init(void);
+# endif
+
+/*
+ * prm_features flag values
+ *
+ * PRM_HAS_IO_WAKEUP: has IO wakeup capability
+ * PRM_HAS_VOLTAGE: has voltage domains
+ */
+#define PRM_HAS_IO_WAKEUP	(1 << 0)
+#define PRM_HAS_VOLTAGE		(1 << 1)
+
+#ifndef __ASSEMBLER__
+enum {
+	PRM_OMAP3430 = 0,
+	PRM_OMAP3630,
+	PRM_OMAP3_OTHER,
+	PRM_OMAP4,
+	PRM_OMAP5,
+	PRM_DRA7,
+};
+#endif
+
+/*
+ * MAX_MODULE_SOFTRESET_WAIT: Maximum microseconds to wait for OMAP
+ * module to softreset
+ */
+#define MAX_MODULE_SOFTRESET_WAIT		10000
+
+/*
+ * MAX_MODULE_HARDRESET_WAIT: Maximum microseconds to wait for an OMAP
+ * submodule to exit hardreset
+ */
+#define MAX_MODULE_HARDRESET_WAIT		10000
+
+/*
+ * Register bitfields
+ */
+
+/*
+ * 24XX: PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP
+ *
+ * 2430: PM_PWSTST_MDM
+ *
+ * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX,
+ *	 PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU,
+ *	 PM_PWSTST_NEON
+ */
+#define OMAP_INTRANSITION_MASK				(1 << 20)
+
+
+/*
+ * 24XX: PM_PWSTST_GFX, PM_PWSTST_DSP
+ *
+ * 2430: PM_PWSTST_MDM
+ *
+ * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX,
+ *	 PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU,
+ *	 PM_PWSTST_NEON
+ */
+#define OMAP_POWERSTATEST_SHIFT				0
+#define OMAP_POWERSTATEST_MASK				(0x3 << 0)
+
+/*
+ * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
+ *       PM_PWSTCTRL_DSP, PM_PWSTST_MPU
+ *
+ * 2430: PM_PWSTCTRL_MDM shared bits
+ *
+ * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE,
+ *	 PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
+ *	 PM_PWSTCTRL_NEON shared bits
+ */
+#define OMAP_POWERSTATE_SHIFT				0
+#define OMAP_POWERSTATE_MASK				(0x3 << 0)
+
+/*
+ * Standardized OMAP reset source bits
+ *
+ * To the extent these happen to match the hardware register bit
+ * shifts, it's purely coincidental.  Used by omap-wdt.c.
+ * OMAP_UNKNOWN_RST_SRC_ID_SHIFT is a special value, used whenever
+ * there are any bits remaining in the global PRM_RSTST register that
+ * haven't been identified, or when the PRM code for the current SoC
+ * doesn't know how to interpret the register.
+ */
+#define OMAP_GLOBAL_COLD_RST_SRC_ID_SHIFT			0
+#define OMAP_GLOBAL_WARM_RST_SRC_ID_SHIFT			1
+#define OMAP_SECU_VIOL_RST_SRC_ID_SHIFT				2
+#define OMAP_MPU_WD_RST_SRC_ID_SHIFT				3
+#define OMAP_SECU_WD_RST_SRC_ID_SHIFT				4
+#define OMAP_EXTWARM_RST_SRC_ID_SHIFT				5
+#define OMAP_VDD_MPU_VM_RST_SRC_ID_SHIFT			6
+#define OMAP_VDD_IVA_VM_RST_SRC_ID_SHIFT			7
+#define OMAP_VDD_CORE_VM_RST_SRC_ID_SHIFT			8
+#define OMAP_ICEPICK_RST_SRC_ID_SHIFT				9
+#define OMAP_ICECRUSHER_RST_SRC_ID_SHIFT			10
+#define OMAP_C2C_RST_SRC_ID_SHIFT				11
+#define OMAP_UNKNOWN_RST_SRC_ID_SHIFT				12
+
+#ifndef __ASSEMBLER__
+
+/**
+ * struct prm_reset_src_map - map register bitshifts to standard bitshifts
+ * @reg_shift: bitshift in the PRM reset source register
+ * @std_shift: bitshift equivalent in the standard reset source list
+ *
+ * The fields are signed because -1 is used as a terminator.
+ */
+struct prm_reset_src_map {
+	s8 reg_shift;
+	s8 std_shift;
+};
+
+/**
+ * struct prm_ll_data - fn ptrs to per-SoC PRM function implementations
+ * @read_reset_sources: ptr to the SoC PRM-specific get_reset_source impl
+ * @was_any_context_lost_old: ptr to the SoC PRM context loss test fn
+ * @clear_context_loss_flags_old: ptr to the SoC PRM context loss flag clear fn
+ * @late_init: ptr to the late init function
+ *
+ * XXX @was_any_context_lost_old and @clear_context_loss_flags_old are
+ * deprecated.
+ */
+struct prm_ll_data {
+	u32 (*read_reset_sources)(void);
+	bool (*was_any_context_lost_old)(u8 part, s16 inst, u16 idx);
+	void (*clear_context_loss_flags_old)(u8 part, s16 inst, u16 idx);
+	int (*late_init)(void);
+};
+
+int prm_register(struct prm_ll_data *pld);
+int prm_unregister(struct prm_ll_data *pld);
+
+u32 prm_read_reset_sources(void);
+bool prm_was_any_context_lost_old(u8 part, s16 inst, u16 idx);
+void prm_clear_context_loss_flags_old(u8 part, s16 inst, u16 idx);
+
+#endif
+
+
+#endif
-- 
1.7.9.5

[PATCH 49/55] ARM: OMAP4: move prcm44xx.h header to public location

[Tero Kristo]

This file needs to be accessible from the PRCM core and mach-omap2 board
support code.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/clockdomains43xx_data.c   |    1 -
 arch/arm/mach-omap2/clockdomains44xx_data.c   |    2 +-
 arch/arm/mach-omap2/clockdomains54xx_data.c   |    2 +-
 arch/arm/mach-omap2/clockdomains7xx_data.c    |    2 +-
 arch/arm/mach-omap2/cminst44xx.c              |    2 +-
 arch/arm/mach-omap2/omap-mpuss-lowpower.c     |    2 +-
 arch/arm/mach-omap2/powerdomain.c             |    2 +-
 arch/arm/mach-omap2/powerdomains43xx_data.c   |    1 -
 arch/arm/mach-omap2/powerdomains44xx_data.c   |    2 +-
 arch/arm/mach-omap2/powerdomains54xx_data.c   |    2 +-
 arch/arm/mach-omap2/powerdomains7xx_data.c    |    2 +-
 arch/arm/mach-omap2/prcm44xx.h                |   53 -------------------------
 arch/arm/mach-omap2/prm44xx.c                 |    2 +-
 arch/arm/mach-omap2/prminst44xx.c             |    2 +-
 arch/arm/mach-omap2/voltage.c                 |    2 +-
 arch/arm/mach-omap2/voltagedomains44xx_data.c |    1 -
 include/linux/power/omap/prcm44xx.h           |   53 +++++++++++++++++++++++++
 17 files changed, 65 insertions(+), 68 deletions(-)
 delete mode 100644 arch/arm/mach-omap2/prcm44xx.h
 create mode 100644 include/linux/power/omap/prcm44xx.h

diff --git a/arch/arm/mach-omap2/clockdomains43xx_data.c b/arch/arm/mach-omap2/clockdomains43xx_data.c
index 6d71c60..11a319b 100644
--- a/arch/arm/mach-omap2/clockdomains43xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains43xx_data.c
@@ -12,7 +12,6 @@
 #include <linux/io.h>
 
 #include "clockdomain.h"
-#include "prcm44xx.h"
 #include "prcm43xx.h"
 
 static struct clockdomain l4_cefuse_43xx_clkdm = {
diff --git a/arch/arm/mach-omap2/clockdomains44xx_data.c b/arch/arm/mach-omap2/clockdomains44xx_data.c
index 95192a0..a335303 100644
--- a/arch/arm/mach-omap2/clockdomains44xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains44xx_data.c
@@ -28,7 +28,7 @@
 
 #include "cm-regbits-44xx.h"
 #include "prm44xx.h"
-#include "prcm44xx.h"
+#include <linux/power/omap/prcm44xx.h>
 #include "prcm_mpu44xx.h"
 
 /* Static Dependencies for OMAP4 Clock Domains */
diff --git a/arch/arm/mach-omap2/clockdomains54xx_data.c b/arch/arm/mach-omap2/clockdomains54xx_data.c
index 1a3c69d..59ea31e 100644
--- a/arch/arm/mach-omap2/clockdomains54xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains54xx_data.c
@@ -27,7 +27,7 @@
 
 #include "cm-regbits-54xx.h"
 #include "prm54xx.h"
-#include "prcm44xx.h"
+#include <linux/power/omap/prcm44xx.h>
 #include "prcm_mpu54xx.h"
 
 /* Static Dependencies for OMAP4 Clock Domains */
diff --git a/arch/arm/mach-omap2/clockdomains7xx_data.c b/arch/arm/mach-omap2/clockdomains7xx_data.c
index 57d5df0..b169667 100644
--- a/arch/arm/mach-omap2/clockdomains7xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains7xx_data.c
@@ -29,7 +29,7 @@
 
 #include "cm-regbits-7xx.h"
 #include "prm7xx.h"
-#include "prcm44xx.h"
+#include <linux/power/omap/prcm44xx.h>
 #include "prcm_mpu7xx.h"
 
 /* Static Dependencies for DRA7xx Clock Domains */
diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c
index 0fd50d7..3b95fc6 100644
--- a/arch/arm/mach-omap2/cminst44xx.c
+++ b/arch/arm/mach-omap2/cminst44xx.c
@@ -27,7 +27,7 @@
 #include "cm1_44xx.h"
 #include "cm2_44xx.h"
 #include <linux/power/omap/cm44xx.h>
-#include "prcm44xx.h"
+#include <linux/power/omap/prcm44xx.h>
 #include <linux/power/omap/prm44xx.h>
 #include "prcm_mpu44xx.h"
 #include <linux/power/omap/prcm-common.h>
diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
index 50127e1..33f5774 100644
--- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
+++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
@@ -57,7 +57,7 @@
 #include "omap4-sar-layout.h"
 #include "pm.h"
 #include "prcm_mpu44xx.h"
-#include "prcm44xx.h"
+#include <linux/power/omap/prcm44xx.h>
 #include "prm44xx.h"
 #include "prm-regbits-44xx.h"
 
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 7262b3d..86ef5f6 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -23,7 +23,7 @@
 #include <trace/events/power.h>
 
 #include <linux/power/omap/cm2xxx_3xxx.h>
-#include "prcm44xx.h"
+#include <linux/power/omap/prcm44xx.h>
 #include <linux/power/omap/prm2xxx_3xxx.h>
 #include <linux/power/omap/prm44xx.h>
 
diff --git a/arch/arm/mach-omap2/powerdomains43xx_data.c b/arch/arm/mach-omap2/powerdomains43xx_data.c
index b99eac7..91802f1 100644
--- a/arch/arm/mach-omap2/powerdomains43xx_data.c
+++ b/arch/arm/mach-omap2/powerdomains43xx_data.c
@@ -14,7 +14,6 @@
 #include "powerdomain.h"
 
 #include <linux/power/omap/prcm-common.h>
-#include "prcm44xx.h"
 #include "prcm43xx.h"
 
 static struct powerdomain gfx_43xx_pwrdm = {
diff --git a/arch/arm/mach-omap2/powerdomains44xx_data.c b/arch/arm/mach-omap2/powerdomains44xx_data.c
index ea1ffc1..793c611 100644
--- a/arch/arm/mach-omap2/powerdomains44xx_data.c
+++ b/arch/arm/mach-omap2/powerdomains44xx_data.c
@@ -25,7 +25,7 @@
 #include "powerdomain.h"
 
 #include <linux/power/omap/prcm-common.h>
-#include "prcm44xx.h"
+#include <linux/power/omap/prcm44xx.h>
 #include "prm-regbits-44xx.h"
 #include "prm44xx.h"
 #include "prcm_mpu44xx.h"
diff --git a/arch/arm/mach-omap2/powerdomains54xx_data.c b/arch/arm/mach-omap2/powerdomains54xx_data.c
index b4a815b..37017f2 100644
--- a/arch/arm/mach-omap2/powerdomains54xx_data.c
+++ b/arch/arm/mach-omap2/powerdomains54xx_data.c
@@ -24,7 +24,7 @@
 #include "powerdomain.h"
 
 #include <linux/power/omap/prcm-common.h>
-#include "prcm44xx.h"
+#include <linux/power/omap/prcm44xx.h>
 #include "prm54xx.h"
 #include "prcm_mpu54xx.h"
 
diff --git a/arch/arm/mach-omap2/powerdomains7xx_data.c b/arch/arm/mach-omap2/powerdomains7xx_data.c
index cf33ef6..cedc84b 100644
--- a/arch/arm/mach-omap2/powerdomains7xx_data.c
+++ b/arch/arm/mach-omap2/powerdomains7xx_data.c
@@ -26,7 +26,7 @@
 #include "powerdomain.h"
 
 #include <linux/power/omap/prcm-common.h>
-#include "prcm44xx.h"
+#include <linux/power/omap/prcm44xx.h>
 #include "prm7xx.h"
 #include "prcm_mpu7xx.h"
 
diff --git a/arch/arm/mach-omap2/prcm44xx.h b/arch/arm/mach-omap2/prcm44xx.h
deleted file mode 100644
index 4fea2cf..0000000
--- a/arch/arm/mach-omap2/prcm44xx.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * OMAP4 PRCM definitions
- *
- * Copyright (C) 2010 Texas Instruments, Inc.
- * Copyright (C) 2010 Nokia Corporation
- *
- * Paul Walmsley
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This file contains macros and functions that are common to all of
- * the PRM/CM/PRCM blocks on the OMAP4 devices: PRM, CM1, CM2,
- * PRCM_MPU, SCRM
- */
-
-#ifndef __ARCH_ARM_MACH_OMAP2_PRCM44XX_H
-#define __ARCH_ARM_MACH_OMAP2_PRCM44XX_H
-
-/*
- * OMAP4 PRCM partition IDs
- *
- * The numbers and order are arbitrary, but 0 is reserved for the
- * 'invalid' partition in case someone forgets to add a
- * .prcm_partition field.
- */
-#define OMAP4430_INVALID_PRCM_PARTITION		0
-#define OMAP4430_PRM_PARTITION			1
-#define OMAP4430_CM1_PARTITION			2
-#define OMAP4430_CM2_PARTITION			3
-#define OMAP4430_SCRM_PARTITION			4
-#define OMAP4430_PRCM_MPU_PARTITION		5
-
-#define OMAP54XX_PRM_PARTITION			1
-#define OMAP54XX_CM_CORE_AON_PARTITION		2
-#define OMAP54XX_CM_CORE_PARTITION		3
-#define OMAP54XX_SCRM_PARTITION			4
-#define OMAP54XX_PRCM_MPU_PARTITION		5
-
-#define DRA7XX_PRM_PARTITION                   1
-#define DRA7XX_CM_CORE_AON_PARTITION           2
-#define DRA7XX_CM_CORE_PARTITION               3
-#define DRA7XX_MPU_PRCM_PARTITION              5
-
-/*
- * OMAP4_MAX_PRCM_PARTITIONS: set to the highest value of the PRCM partition
- * IDs, plus one
- */
-#define OMAP4_MAX_PRCM_PARTITIONS		6
-
-
-#endif
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index cf312a8..69a974b 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -22,7 +22,7 @@
 #include <linux/power/omap/prm44xx.h>
 #include <linux/power/omap/prm54xx.h>
 #include <linux/power/omap/prm7xx.h>
-#include "prcm44xx.h"
+#include <linux/power/omap/prcm44xx.h>
 #include "prminst44xx_private.h"
 #include "powerdomain.h"
 #include <linux/power/omap/prm.h>
diff --git a/arch/arm/mach-omap2/prminst44xx.c b/arch/arm/mach-omap2/prminst44xx.c
index 30015d1..5b7c17e 100644
--- a/arch/arm/mach-omap2/prminst44xx.c
+++ b/arch/arm/mach-omap2/prminst44xx.c
@@ -21,7 +21,7 @@
 #include <linux/power/omap/prm44xx.h>
 #include <linux/power/omap/prm54xx.h>
 #include <linux/power/omap/prm7xx.h>
-#include "prcm44xx.h"
+#include <linux/power/omap/prcm44xx.h>
 #include "prcm_mpu44xx.h"
 
 #define OMAP4430_RST_GLOBAL_WARM_SW_MASK		(1 << 0)
diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
index 78f5a68..b707328 100644
--- a/arch/arm/mach-omap2/voltage.c
+++ b/arch/arm/mach-omap2/voltage.c
@@ -32,7 +32,7 @@
 #include "prm-regbits-34xx.h"
 #include "prm-regbits-44xx.h"
 #include "prm44xx.h"
-#include "prcm44xx.h"
+#include <linux/power/omap/prcm44xx.h>
 #include "control.h"
 
 #include "voltage.h"
diff --git a/arch/arm/mach-omap2/voltagedomains44xx_data.c b/arch/arm/mach-omap2/voltagedomains44xx_data.c
index 479b412..f452ab8 100644
--- a/arch/arm/mach-omap2/voltagedomains44xx_data.c
+++ b/arch/arm/mach-omap2/voltagedomains44xx_data.c
@@ -25,7 +25,6 @@
 #include "soc.h"
 #include "prm-regbits-44xx.h"
 #include "prm44xx.h"
-#include "prcm44xx.h"
 #include "voltage.h"
 #include "omap_opp_data.h"
 #include "vc.h"
diff --git a/include/linux/power/omap/prcm44xx.h b/include/linux/power/omap/prcm44xx.h
new file mode 100644
index 0000000..4f58ed1
--- /dev/null
+++ b/include/linux/power/omap/prcm44xx.h
@@ -0,0 +1,53 @@
+/*
+ * OMAP4 PRCM definitions
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ * Copyright (C) 2010 Nokia Corporation
+ *
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This file contains macros and functions that are common to all of
+ * the PRM/CM/PRCM blocks on the OMAP4 devices: PRM, CM1, CM2,
+ * PRCM_MPU, SCRM
+ */
+
+#ifndef __LINUX_POWER_OMAP_PRCM44XX_H
+#define __LINUX_POWER_OMAP_PRCM44XX_H
+
+/*
+ * OMAP4 PRCM partition IDs
+ *
+ * The numbers and order are arbitrary, but 0 is reserved for the
+ * 'invalid' partition in case someone forgets to add a
+ * .prcm_partition field.
+ */
+#define OMAP4430_INVALID_PRCM_PARTITION		0
+#define OMAP4430_PRM_PARTITION			1
+#define OMAP4430_CM1_PARTITION			2
+#define OMAP4430_CM2_PARTITION			3
+#define OMAP4430_SCRM_PARTITION			4
+#define OMAP4430_PRCM_MPU_PARTITION		5
+
+#define OMAP54XX_PRM_PARTITION			1
+#define OMAP54XX_CM_CORE_AON_PARTITION		2
+#define OMAP54XX_CM_CORE_PARTITION		3
+#define OMAP54XX_SCRM_PARTITION			4
+#define OMAP54XX_PRCM_MPU_PARTITION		5
+
+#define DRA7XX_PRM_PARTITION                   1
+#define DRA7XX_CM_CORE_AON_PARTITION           2
+#define DRA7XX_CM_CORE_PARTITION               3
+#define DRA7XX_MPU_PRCM_PARTITION              5
+
+/*
+ * OMAP4_MAX_PRCM_PARTITIONS: set to the highest value of the PRCM partition
+ * IDs, plus one
+ */
+#define OMAP4_MAX_PRCM_PARTITIONS		6
+
+
+#endif
-- 
1.7.9.5

[PATCH 50/55] ARM: OMAP2+: clockdomain: move clockdomain.h header to public location

[Tero Kristo]

This file needs to be accessible from the PRCM core and mach-omap2 board
support code.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/clock.c                      |    2 +-
 arch/arm/mach-omap2/clockdomain.c                |    3 +-
 arch/arm/mach-omap2/clockdomain.h                |  237 ---------------------
 arch/arm/mach-omap2/clockdomains2420_data.c      |    2 +-
 arch/arm/mach-omap2/clockdomains2430_data.c      |    2 +-
 arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c |    2 +-
 arch/arm/mach-omap2/clockdomains33xx_data.c      |    2 +-
 arch/arm/mach-omap2/clockdomains3xxx_data.c      |    2 +-
 arch/arm/mach-omap2/clockdomains43xx_data.c      |    2 +-
 arch/arm/mach-omap2/clockdomains44xx_data.c      |    2 +-
 arch/arm/mach-omap2/clockdomains54xx_data.c      |    2 +-
 arch/arm/mach-omap2/clockdomains7xx_data.c       |    2 +-
 arch/arm/mach-omap2/cm2xxx.c                     |    3 +-
 arch/arm/mach-omap2/cm33xx.c                     |    2 +-
 arch/arm/mach-omap2/cm3xxx.c                     |    3 +-
 arch/arm/mach-omap2/cminst44xx.c                 |    2 +-
 arch/arm/mach-omap2/cpuidle34xx.c                |    2 +-
 arch/arm/mach-omap2/cpuidle44xx.c                |    2 +-
 arch/arm/mach-omap2/dpll3xxx.c                   |    2 +-
 arch/arm/mach-omap2/io.c                         |    2 +-
 arch/arm/mach-omap2/omap-smp.c                   |    2 +-
 arch/arm/mach-omap2/omap_hwmod.c                 |    2 +-
 arch/arm/mach-omap2/pm-debug.c                   |    2 +-
 arch/arm/mach-omap2/pm.c                         |    2 +-
 arch/arm/mach-omap2/pm24xx.c                     |    2 +-
 arch/arm/mach-omap2/pm34xx.c                     |    2 +-
 arch/arm/mach-omap2/pm44xx.c                     |    2 +-
 arch/arm/mach-omap2/powerdomain.c                |    2 +-
 arch/arm/mach-omap2/prm2xxx.c                    |    2 +-
 arch/arm/mach-omap2/prm2xxx_3xxx.c               |    2 +-
 include/linux/power/omap/clockdomain.h           |  242 ++++++++++++++++++++++
 31 files changed, 274 insertions(+), 266 deletions(-)
 delete mode 100644 arch/arm/mach-omap2/clockdomain.h
 create mode 100644 include/linux/power/omap/clockdomain.h

diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 4276c46..035f413 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -29,7 +29,7 @@
 #include <trace/events/power.h>
 
 #include "soc.h"
-#include "clockdomain.h"
+#include <linux/power/omap/clockdomain.h>
 #include "clock.h"
 #include <linux/power/omap/cm.h>
 #include "cm2xxx.h"
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index 9a59efb..298fb05 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -29,7 +29,8 @@
 #include <linux/bitops.h>
 
 #include "soc.h"
-#include "clockdomain.h"
+#include <linux/power/omap/clockdomain.h>
+#include "powerdomain.h"
 
 /* clkdm_list contains all registered struct clockdomains */
 static LIST_HEAD(clkdm_list);
diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
deleted file mode 100644
index 4322a28..0000000
--- a/arch/arm/mach-omap2/clockdomain.h
+++ /dev/null
@@ -1,237 +0,0 @@
-/*
- * OMAP2/3 clockdomain framework functions
- *
- * Copyright (C) 2008, 2012 Texas Instruments, Inc.
- * Copyright (C) 2008-2011 Nokia Corporation
- *
- * Paul Walmsley
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ARCH_ARM_MACH_OMAP2_CLOCKDOMAIN_H
-#define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAIN_H
-
-#include <linux/init.h>
-
-#include "powerdomain.h"
-
-/*
- * Clockdomain flags
- *
- * XXX Document CLKDM_CAN_* flags
- *
- * CLKDM_NO_AUTODEPS: Prevent "autodeps" from being added/removed from this
- *     clockdomain.  (Currently, this applies to OMAP3 clockdomains only.)
- * CLKDM_ACTIVE_WITH_MPU: The PRCM guarantees that this clockdomain is
- *     active whenever the MPU is active.  True for interconnects and
- *     the WKUP clockdomains.
- * CLKDM_MISSING_IDLE_REPORTING: The idle status of the IP blocks and
- *     clocks inside this clockdomain are not taken into account by
- *     the PRCM when determining whether the clockdomain is idle.
- *     Without this flag, if the clockdomain is set to
- *     hardware-supervised idle mode, the PRCM may transition the
- *     enclosing powerdomain to a low power state, even when devices
- *     inside the clockdomain and powerdomain are in use.  (An example
- *     of such a clockdomain is the EMU clockdomain on OMAP3/4.)  If
- *     this flag is set, and the clockdomain does not support the
- *     force-sleep mode, then the HW_AUTO mode will be used to put the
- *     clockdomain to sleep.  Similarly, if the clockdomain supports
- *     the force-wakeup mode, then it will be used whenever a clock or
- *     IP block inside the clockdomain is active, rather than the
- *     HW_AUTO mode.
- */
-#define CLKDM_CAN_FORCE_SLEEP			(1 << 0)
-#define CLKDM_CAN_FORCE_WAKEUP			(1 << 1)
-#define CLKDM_CAN_ENABLE_AUTO			(1 << 2)
-#define CLKDM_CAN_DISABLE_AUTO			(1 << 3)
-#define CLKDM_NO_AUTODEPS			(1 << 4)
-#define CLKDM_ACTIVE_WITH_MPU			(1 << 5)
-#define CLKDM_MISSING_IDLE_REPORTING		(1 << 6)
-
-#define CLKDM_CAN_HWSUP		(CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_DISABLE_AUTO)
-#define CLKDM_CAN_SWSUP		(CLKDM_CAN_FORCE_SLEEP | CLKDM_CAN_FORCE_WAKEUP)
-#define CLKDM_CAN_HWSUP_SWSUP	(CLKDM_CAN_SWSUP | CLKDM_CAN_HWSUP)
-
-/**
- * struct clkdm_autodep - clkdm deps to add when entering/exiting hwsup mode
- * @clkdm: clockdomain to add wkdep+sleepdep on - set name member only
- *
- * A clockdomain that should have wkdeps and sleepdeps added when a
- * clockdomain should stay active in hwsup mode; and conversely,
- * removed when the clockdomain should be allowed to go inactive in
- * hwsup mode.
- *
- * Autodeps are deprecated and should be removed after
- * omap_hwmod-based fine-grained module idle control is added.
- */
-struct clkdm_autodep {
-	union {
-		const char *name;
-		struct clockdomain *ptr;
-	} clkdm;
-};
-
-/**
- * struct clkdm_dep - encode dependencies between clockdomains
- * @clkdm_name: clockdomain name
- * @clkdm: pointer to the struct clockdomain of @clkdm_name
- * @wkdep_usecount: Number of wakeup dependencies causing this clkdm to wake
- * @sleepdep_usecount: Number of sleep deps that could prevent clkdm from idle
- *
- * Statically defined.  @clkdm is resolved from @clkdm_name at runtime and
- * should not be pre-initialized.
- *
- * XXX Should also include hardware (fixed) dependencies.
- */
-struct clkdm_dep {
-	const char *clkdm_name;
-	struct clockdomain *clkdm;
-	s16 wkdep_usecount;
-	s16 sleepdep_usecount;
-};
-
-/* Possible flags for struct clockdomain._flags */
-#define _CLKDM_FLAG_HWSUP_ENABLED		BIT(0)
-
-struct omap_hwmod;
-struct clk;
-
-/**
- * struct clockdomain - OMAP clockdomain
- * @name: clockdomain name
- * @pwrdm: powerdomain containing this clockdomain
- * @clktrctrl_reg: CLKSTCTRL reg for the given clock domain
- * @clktrctrl_mask: CLKTRCTRL/AUTOSTATE field mask in CM_CLKSTCTRL reg
- * @flags: Clockdomain capability flags
- * @_flags: Flags for use only by internal clockdomain code
- * @dep_bit: Bit shift of this clockdomain's PM_WKDEP/CM_SLEEPDEP bit
- * @prcm_partition: (OMAP4 only) PRCM partition ID for this clkdm's registers
- * @cm_inst: (OMAP4 only) CM instance register offset
- * @clkdm_offs: (OMAP4 only) CM clockdomain register offset
- * @wkdep_srcs: Clockdomains that can be told to wake this powerdomain up
- * @sleepdep_srcs: Clockdomains that can be told to keep this clkdm from inact
- * @usecount: Usecount tracking
- * @node: list_head to link all clockdomains together
- *
- * @prcm_partition should be a macro from mach-omap2/prcm44xx.h (OMAP4 only)
- * @cm_inst should be a macro ending in _INST from the OMAP4 CM instance
- *     definitions (OMAP4 only)
- * @clkdm_offs should be a macro ending in _CDOFFS from the OMAP4 CM instance
- *     definitions (OMAP4 only)
- */
-struct clockdomain {
-	const char *name;
-	union {
-		const char *name;
-		struct powerdomain *ptr;
-	} pwrdm;
-	const u16 clktrctrl_mask;
-	const u8 flags;
-	u8 _flags;
-	const u8 dep_bit;
-	const u8 prcm_partition;
-	const u16 cm_inst;
-	const u16 clkdm_offs;
-	struct clkdm_dep *wkdep_srcs;
-	struct clkdm_dep *sleepdep_srcs;
-	int usecount;
-	struct list_head node;
-};
-
-/**
- * struct clkdm_ops - Arch specific function implementations
- * @clkdm_add_wkdep: Add a wakeup dependency between clk domains
- * @clkdm_del_wkdep: Delete a wakeup dependency between clk domains
- * @clkdm_read_wkdep: Read wakeup dependency state between clk domains
- * @clkdm_clear_all_wkdeps: Remove all wakeup dependencies from the clk domain
- * @clkdm_add_sleepdep: Add a sleep dependency between clk domains
- * @clkdm_del_sleepdep: Delete a sleep dependency between clk domains
- * @clkdm_read_sleepdep: Read sleep dependency state between clk domains
- * @clkdm_clear_all_sleepdeps: Remove all sleep dependencies from the clk domain
- * @clkdm_sleep: Force a clockdomain to sleep
- * @clkdm_wakeup: Force a clockdomain to wakeup
- * @clkdm_allow_idle: Enable hw supervised idle transitions for clock domain
- * @clkdm_deny_idle: Disable hw supervised idle transitions for clock domain
- * @clkdm_clk_enable: Put the clkdm in right state for a clock enable
- * @clkdm_clk_disable: Put the clkdm in right state for a clock disable
- */
-struct clkdm_ops {
-	int	(*clkdm_add_wkdep)(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
-	int	(*clkdm_del_wkdep)(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
-	int	(*clkdm_read_wkdep)(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
-	int	(*clkdm_clear_all_wkdeps)(struct clockdomain *clkdm);
-	int	(*clkdm_add_sleepdep)(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
-	int	(*clkdm_del_sleepdep)(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
-	int	(*clkdm_read_sleepdep)(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
-	int	(*clkdm_clear_all_sleepdeps)(struct clockdomain *clkdm);
-	int	(*clkdm_sleep)(struct clockdomain *clkdm);
-	int	(*clkdm_wakeup)(struct clockdomain *clkdm);
-	void	(*clkdm_allow_idle)(struct clockdomain *clkdm);
-	void	(*clkdm_deny_idle)(struct clockdomain *clkdm);
-	int	(*clkdm_clk_enable)(struct clockdomain *clkdm);
-	int	(*clkdm_clk_disable)(struct clockdomain *clkdm);
-};
-
-int clkdm_register_platform_funcs(struct clkdm_ops *co);
-int clkdm_register_autodeps(struct clkdm_autodep *ia);
-int clkdm_register_clkdms(struct clockdomain **c);
-int clkdm_complete_init(void);
-
-struct clockdomain *clkdm_lookup(const char *name);
-
-int clkdm_for_each(int (*fn)(struct clockdomain *clkdm, void *user),
-			void *user);
-struct powerdomain *clkdm_get_pwrdm(struct clockdomain *clkdm);
-
-int clkdm_add_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
-int clkdm_del_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
-int clkdm_read_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
-int clkdm_clear_all_wkdeps(struct clockdomain *clkdm);
-int clkdm_add_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
-int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
-int clkdm_read_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
-int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm);
-
-void clkdm_allow_idle_nolock(struct clockdomain *clkdm);
-void clkdm_allow_idle(struct clockdomain *clkdm);
-void clkdm_deny_idle_nolock(struct clockdomain *clkdm);
-void clkdm_deny_idle(struct clockdomain *clkdm);
-bool clkdm_in_hwsup(struct clockdomain *clkdm);
-bool clkdm_missing_idle_reporting(struct clockdomain *clkdm);
-
-int clkdm_wakeup_nolock(struct clockdomain *clkdm);
-int clkdm_wakeup(struct clockdomain *clkdm);
-int clkdm_sleep_nolock(struct clockdomain *clkdm);
-int clkdm_sleep(struct clockdomain *clkdm);
-
-int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk);
-int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk);
-int clkdm_hwmod_enable(struct clockdomain *clkdm, struct omap_hwmod *oh);
-int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh);
-
-extern void __init omap242x_clockdomains_init(void);
-extern void __init omap243x_clockdomains_init(void);
-extern void __init omap3xxx_clockdomains_init(void);
-extern void __init am33xx_clockdomains_init(void);
-extern void __init omap44xx_clockdomains_init(void);
-extern void __init omap54xx_clockdomains_init(void);
-extern void __init dra7xx_clockdomains_init(void);
-void am43xx_clockdomains_init(void);
-
-extern void clkdm_add_autodeps(struct clockdomain *clkdm);
-extern void clkdm_del_autodeps(struct clockdomain *clkdm);
-
-extern struct clkdm_ops omap2_clkdm_operations;
-extern struct clkdm_ops omap3_clkdm_operations;
-extern struct clkdm_ops omap4_clkdm_operations;
-extern struct clkdm_ops am33xx_clkdm_operations;
-extern struct clkdm_ops am43xx_clkdm_operations;
-
-extern struct clkdm_dep gfx_24xx_wkdeps[];
-extern struct clkdm_dep dsp_24xx_wkdeps[];
-extern struct clockdomain wkup_common_clkdm;
-
-#endif
diff --git a/arch/arm/mach-omap2/clockdomains2420_data.c b/arch/arm/mach-omap2/clockdomains2420_data.c
index 432cb14..b54a3e8 100644
--- a/arch/arm/mach-omap2/clockdomains2420_data.c
+++ b/arch/arm/mach-omap2/clockdomains2420_data.c
@@ -36,7 +36,7 @@
 #include <linux/io.h>
 
 #include "soc.h"
-#include "clockdomain.h"
+#include <linux/power/omap/clockdomain.h>
 #include <linux/power/omap/prm2xxx_3xxx.h>
 #include <linux/power/omap/cm2xxx_3xxx.h>
 #include "cm-regbits-24xx.h"
diff --git a/arch/arm/mach-omap2/clockdomains2430_data.c b/arch/arm/mach-omap2/clockdomains2430_data.c
index 48df0fb..c0030bc 100644
--- a/arch/arm/mach-omap2/clockdomains2430_data.c
+++ b/arch/arm/mach-omap2/clockdomains2430_data.c
@@ -36,7 +36,7 @@
 #include <linux/io.h>
 
 #include "soc.h"
-#include "clockdomain.h"
+#include <linux/power/omap/clockdomain.h>
 #include <linux/power/omap/prm2xxx_3xxx.h>
 #include <linux/power/omap/cm2xxx_3xxx.h>
 #include "cm-regbits-24xx.h"
diff --git a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
index 435e5c3..f8666d7 100644
--- a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
+++ b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
@@ -35,7 +35,7 @@
 #include <linux/kernel.h>
 #include <linux/io.h>
 
-#include "clockdomain.h"
+#include <linux/power/omap/clockdomain.h>
 #include <linux/power/omap/prm2xxx_3xxx.h>
 #include <linux/power/omap/cm2xxx_3xxx.h>
 #include "cm-regbits-24xx.h"
diff --git a/arch/arm/mach-omap2/clockdomains33xx_data.c b/arch/arm/mach-omap2/clockdomains33xx_data.c
index e86f84e..0a6160b 100644
--- a/arch/arm/mach-omap2/clockdomains33xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains33xx_data.c
@@ -17,7 +17,7 @@
 #include <linux/kernel.h>
 #include <linux/io.h>
 
-#include "clockdomain.h"
+#include <linux/power/omap/clockdomain.h>
 #include <linux/power/omap/cm.h>
 #include "cm33xx.h"
 #include "cm-regbits-33xx.h"
diff --git a/arch/arm/mach-omap2/clockdomains3xxx_data.c b/arch/arm/mach-omap2/clockdomains3xxx_data.c
index 9272baf..fcdee72 100644
--- a/arch/arm/mach-omap2/clockdomains3xxx_data.c
+++ b/arch/arm/mach-omap2/clockdomains3xxx_data.c
@@ -34,7 +34,7 @@
 #include <linux/io.h>
 
 #include "soc.h"
-#include "clockdomain.h"
+#include <linux/power/omap/clockdomain.h>
 #include <linux/power/omap/prm2xxx_3xxx.h>
 #include <linux/power/omap/cm2xxx_3xxx.h>
 #include "cm-regbits-34xx.h"
diff --git a/arch/arm/mach-omap2/clockdomains43xx_data.c b/arch/arm/mach-omap2/clockdomains43xx_data.c
index 11a319b..5f1ddb9 100644
--- a/arch/arm/mach-omap2/clockdomains43xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains43xx_data.c
@@ -11,7 +11,7 @@
 #include <linux/kernel.h>
 #include <linux/io.h>
 
-#include "clockdomain.h"
+#include <linux/power/omap/clockdomain.h>
 #include "prcm43xx.h"
 
 static struct clockdomain l4_cefuse_43xx_clkdm = {
diff --git a/arch/arm/mach-omap2/clockdomains44xx_data.c b/arch/arm/mach-omap2/clockdomains44xx_data.c
index a335303..965d56f 100644
--- a/arch/arm/mach-omap2/clockdomains44xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains44xx_data.c
@@ -22,7 +22,7 @@
 #include <linux/kernel.h>
 #include <linux/io.h>
 
-#include "clockdomain.h"
+#include <linux/power/omap/clockdomain.h>
 #include "cm1_44xx.h"
 #include "cm2_44xx.h"
 
diff --git a/arch/arm/mach-omap2/clockdomains54xx_data.c b/arch/arm/mach-omap2/clockdomains54xx_data.c
index 59ea31e..6699aaf6 100644
--- a/arch/arm/mach-omap2/clockdomains54xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains54xx_data.c
@@ -21,7 +21,7 @@
 #include <linux/kernel.h>
 #include <linux/io.h>
 
-#include "clockdomain.h"
+#include <linux/power/omap/clockdomain.h>
 #include "cm1_54xx.h"
 #include "cm2_54xx.h"
 
diff --git a/arch/arm/mach-omap2/clockdomains7xx_data.c b/arch/arm/mach-omap2/clockdomains7xx_data.c
index b169667..52d1226 100644
--- a/arch/arm/mach-omap2/clockdomains7xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains7xx_data.c
@@ -23,7 +23,7 @@
 #include <linux/kernel.h>
 #include <linux/io.h>
 
-#include "clockdomain.h"
+#include <linux/power/omap/clockdomain.h>
 #include "cm1_7xx.h"
 #include "cm2_7xx.h"
 
diff --git a/arch/arm/mach-omap2/cm2xxx.c b/arch/arm/mach-omap2/cm2xxx.c
index f7365c7..93efae1 100644
--- a/arch/arm/mach-omap2/cm2xxx.c
+++ b/arch/arm/mach-omap2/cm2xxx.c
@@ -22,9 +22,10 @@
 #include <linux/power/omap/cm.h>
 #include "cm2xxx_3xxx_private.h"
 #include <linux/power/omap/cm2xxx.h>
-#include "clockdomain.h"
+#include <linux/power/omap/clockdomain.h>
 #include <linux/power/omap/prcm-common.h>
 #include <linux/power/omap/prm2xxx_3xxx.h>
+#include "powerdomain.h"
 
 /* CM_AUTOIDLE_PLL.AUTO_* bit values for DPLLs */
 #define DPLL_AUTOIDLE_DISABLE				0x0
diff --git a/arch/arm/mach-omap2/cm33xx.c b/arch/arm/mach-omap2/cm33xx.c
index 1f68cde..ea9598c 100644
--- a/arch/arm/mach-omap2/cm33xx.c
+++ b/arch/arm/mach-omap2/cm33xx.c
@@ -22,7 +22,7 @@
 #include <linux/err.h>
 #include <linux/io.h>
 
-#include "clockdomain.h"
+#include <linux/power/omap/clockdomain.h>
 #include <linux/power/omap/cm.h>
 #include <linux/power/omap/cm33xx.h>
 #include <linux/power/omap/prm33xx.h>
diff --git a/arch/arm/mach-omap2/cm3xxx.c b/arch/arm/mach-omap2/cm3xxx.c
index 01c69f2..47d0e49 100644
--- a/arch/arm/mach-omap2/cm3xxx.c
+++ b/arch/arm/mach-omap2/cm3xxx.c
@@ -22,8 +22,9 @@
 #include <linux/power/omap/cm.h>
 #include "cm2xxx_3xxx_private.h"
 #include <linux/power/omap/cm3xxx.h>
-#include "clockdomain.h"
+#include <linux/power/omap/clockdomain.h>
 #include <linux/power/omap/prcm-common.h>
+#include "powerdomain.h"
 
 #define OMAP34XX_CLKSTCTRL_DISABLE_AUTO		0x0
 #define OMAP34XX_CLKSTCTRL_FORCE_SLEEP		0x1
diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c
index 3b95fc6..13c4e0b 100644
--- a/arch/arm/mach-omap2/cminst44xx.c
+++ b/arch/arm/mach-omap2/cminst44xx.c
@@ -22,7 +22,7 @@
 #include <linux/io.h>
 
 #include <linux/power/omap/prm.h>
-#include "clockdomain.h"
+#include <linux/power/omap/clockdomain.h>
 #include <linux/power/omap/cm.h>
 #include "cm1_44xx.h"
 #include "cm2_44xx.h"
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
index e18709d..858a28a 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -29,7 +29,7 @@
 #include <asm/cpuidle.h>
 
 #include "powerdomain.h"
-#include "clockdomain.h"
+#include <linux/power/omap/clockdomain.h>
 
 #include "pm.h"
 #include "control.h"
diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c
index 4324e4e..1ddc4fe 100644
--- a/arch/arm/mach-omap2/cpuidle44xx.c
+++ b/arch/arm/mach-omap2/cpuidle44xx.c
@@ -21,7 +21,7 @@
 #include "common.h"
 #include "pm.h"
 #include <linux/power/omap/prm.h>
-#include "clockdomain.h"
+#include <linux/power/omap/clockdomain.h>
 
 /* Machine specific information */
 struct idle_statedata {
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index 79ce6e8..60a58ff 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -29,7 +29,7 @@
 #include <linux/clkdev.h>
 
 #include "soc.h"
-#include "clockdomain.h"
+#include <linux/power/omap/clockdomain.h>
 #include "clock.h"
 #include <linux/power/omap/cm2xxx_3xxx.h>
 #include "cm-regbits-34xx.h"
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index e9f7db9..b12ca79 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -32,7 +32,7 @@
 #include "iomap.h"
 #include "voltage.h"
 #include "powerdomain.h"
-#include "clockdomain.h"
+#include <linux/power/omap/clockdomain.h>
 #include "common.h"
 #include "clock.h"
 #include "clock2xxx.h"
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index 17550aa..a9f4979 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -30,7 +30,7 @@
 #include "soc.h"
 #include "iomap.h"
 #include "common.h"
-#include "clockdomain.h"
+#include <linux/power/omap/clockdomain.h>
 #include "pm.h"
 
 #define CPU_MASK		0xff0ffff0
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index df0c2a0..bfd3c19 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -149,7 +149,7 @@
 
 #include "soc.h"
 #include "common.h"
-#include "clockdomain.h"
+#include <linux/power/omap/clockdomain.h>
 #include "powerdomain.h"
 #include "cm2xxx.h"
 #include "cm3xxx.h"
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index d2e4fb8..766012e 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -29,7 +29,7 @@
 
 #include "clock.h"
 #include "powerdomain.h"
-#include "clockdomain.h"
+#include <linux/power/omap/clockdomain.h>
 #include "omap-pm.h"
 
 #include "soc.h"
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index f464aed..8ee7b14 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -28,7 +28,7 @@
 #include <linux/power/omap/prcm-common.h>
 #include "voltage.h"
 #include "powerdomain.h"
-#include "clockdomain.h"
+#include <linux/power/omap/clockdomain.h>
 #include "pm.h"
 #include "twl-common.h"
 
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index 97b3831..6c1b8d6 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -52,7 +52,7 @@
 #include "pm.h"
 #include "control.h"
 #include "powerdomain.h"
-#include "clockdomain.h"
+#include <linux/power/omap/clockdomain.h>
 
 static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl,
 				  void __iomem *sdrc_power);
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 4ba0cce..119b9ff 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -37,7 +37,7 @@
 #include <asm/suspend.h>
 #include <asm/system_misc.h>
 
-#include "clockdomain.h"
+#include <linux/power/omap/clockdomain.h>
 #include "powerdomain.h"
 #include "soc.h"
 #include "common.h"
diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
index eefb30c..47f664f 100644
--- a/arch/arm/mach-omap2/pm44xx.c
+++ b/arch/arm/mach-omap2/pm44xx.c
@@ -20,7 +20,7 @@
 
 #include "soc.h"
 #include "common.h"
-#include "clockdomain.h"
+#include <linux/power/omap/clockdomain.h>
 #include "powerdomain.h"
 #include "pm.h"
 
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 86ef5f6..63fd500 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -31,7 +31,7 @@
 
 #include <linux/power/omap/prm.h>
 #include "powerdomain.h"
-#include "clockdomain.h"
+#include <linux/power/omap/clockdomain.h>
 #include "voltage.h"
 
 #include "soc.h"
diff --git a/arch/arm/mach-omap2/prm2xxx.c b/arch/arm/mach-omap2/prm2xxx.c
index 849b415..7969cb9 100644
--- a/arch/arm/mach-omap2/prm2xxx.c
+++ b/arch/arm/mach-omap2/prm2xxx.c
@@ -19,7 +19,7 @@
 #include <linux/irq.h>
 
 #include "powerdomain.h"
-#include "clockdomain.h"
+#include <linux/power/omap/clockdomain.h>
 #include <linux/power/omap/prm2xxx.h>
 #include "prm2xxx_3xxx_private.h"
 #include <linux/power/omap/cm2xxx_3xxx.h>
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c
index d8044f9..a25d1d0 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c
@@ -18,7 +18,7 @@
 
 #include "powerdomain.h"
 #include "prm2xxx_3xxx_private.h"
-#include "clockdomain.h"
+#include <linux/power/omap/clockdomain.h>
 
 /**
  * omap2_prm_is_hardreset_asserted - read the HW reset line state of
diff --git a/include/linux/power/omap/clockdomain.h b/include/linux/power/omap/clockdomain.h
new file mode 100644
index 0000000..96f1dc7
--- /dev/null
+++ b/include/linux/power/omap/clockdomain.h
@@ -0,0 +1,242 @@
+/*
+ * OMAP2/3 clockdomain framework functions
+ *
+ * Copyright (C) 2008, 2012 Texas Instruments, Inc.
+ * Copyright (C) 2008-2011 Nokia Corporation
+ *
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __LINUX_POWER_OMAP_CLOCKDOMAIN_H
+#define __LINUX_POWER_OMAP_CLOCKDOMAIN_H
+
+#include <linux/init.h>
+
+/*
+ * Clockdomain flags
+ *
+ * XXX Document CLKDM_CAN_* flags
+ *
+ * CLKDM_NO_AUTODEPS: Prevent "autodeps" from being added/removed from this
+ *     clockdomain.  (Currently, this applies to OMAP3 clockdomains only.)
+ * CLKDM_ACTIVE_WITH_MPU: The PRCM guarantees that this clockdomain is
+ *     active whenever the MPU is active.  True for interconnects and
+ *     the WKUP clockdomains.
+ * CLKDM_MISSING_IDLE_REPORTING: The idle status of the IP blocks and
+ *     clocks inside this clockdomain are not taken into account by
+ *     the PRCM when determining whether the clockdomain is idle.
+ *     Without this flag, if the clockdomain is set to
+ *     hardware-supervised idle mode, the PRCM may transition the
+ *     enclosing powerdomain to a low power state, even when devices
+ *     inside the clockdomain and powerdomain are in use.  (An example
+ *     of such a clockdomain is the EMU clockdomain on OMAP3/4.)  If
+ *     this flag is set, and the clockdomain does not support the
+ *     force-sleep mode, then the HW_AUTO mode will be used to put the
+ *     clockdomain to sleep.  Similarly, if the clockdomain supports
+ *     the force-wakeup mode, then it will be used whenever a clock or
+ *     IP block inside the clockdomain is active, rather than the
+ *     HW_AUTO mode.
+ */
+#define CLKDM_CAN_FORCE_SLEEP			(1 << 0)
+#define CLKDM_CAN_FORCE_WAKEUP			(1 << 1)
+#define CLKDM_CAN_ENABLE_AUTO			(1 << 2)
+#define CLKDM_CAN_DISABLE_AUTO			(1 << 3)
+#define CLKDM_NO_AUTODEPS			(1 << 4)
+#define CLKDM_ACTIVE_WITH_MPU			(1 << 5)
+#define CLKDM_MISSING_IDLE_REPORTING		(1 << 6)
+
+#define CLKDM_CAN_HWSUP		(CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_DISABLE_AUTO)
+#define CLKDM_CAN_SWSUP		(CLKDM_CAN_FORCE_SLEEP | CLKDM_CAN_FORCE_WAKEUP)
+#define CLKDM_CAN_HWSUP_SWSUP	(CLKDM_CAN_SWSUP | CLKDM_CAN_HWSUP)
+
+/**
+ * struct clkdm_autodep - clkdm deps to add when entering/exiting hwsup mode
+ * @clkdm: clockdomain to add wkdep+sleepdep on - set name member only
+ *
+ * A clockdomain that should have wkdeps and sleepdeps added when a
+ * clockdomain should stay active in hwsup mode; and conversely,
+ * removed when the clockdomain should be allowed to go inactive in
+ * hwsup mode.
+ *
+ * Autodeps are deprecated and should be removed after
+ * omap_hwmod-based fine-grained module idle control is added.
+ */
+struct clkdm_autodep {
+	union {
+		const char *name;
+		struct clockdomain *ptr;
+	} clkdm;
+};
+
+/**
+ * struct clkdm_dep - encode dependencies between clockdomains
+ * @clkdm_name: clockdomain name
+ * @clkdm: pointer to the struct clockdomain of @clkdm_name
+ * @wkdep_usecount: Number of wakeup dependencies causing this clkdm to wake
+ * @sleepdep_usecount: Number of sleep deps that could prevent clkdm from idle
+ *
+ * Statically defined.  @clkdm is resolved from @clkdm_name at runtime and
+ * should not be pre-initialized.
+ *
+ * XXX Should also include hardware (fixed) dependencies.
+ */
+struct clkdm_dep {
+	const char *clkdm_name;
+	struct clockdomain *clkdm;
+	s16 wkdep_usecount;
+	s16 sleepdep_usecount;
+};
+
+/* Possible flags for struct clockdomain._flags */
+#define _CLKDM_FLAG_HWSUP_ENABLED		BIT(0)
+
+struct omap_hwmod;
+struct clk;
+struct powerdomain;
+
+/**
+ * struct clockdomain - OMAP clockdomain
+ * @name: clockdomain name
+ * @pwrdm: powerdomain containing this clockdomain
+ * @clktrctrl_reg: CLKSTCTRL reg for the given clock domain
+ * @clktrctrl_mask: CLKTRCTRL/AUTOSTATE field mask in CM_CLKSTCTRL reg
+ * @flags: Clockdomain capability flags
+ * @_flags: Flags for use only by internal clockdomain code
+ * @dep_bit: Bit shift of this clockdomain's PM_WKDEP/CM_SLEEPDEP bit
+ * @prcm_partition: (OMAP4 only) PRCM partition ID for this clkdm's registers
+ * @cm_inst: (OMAP4 only) CM instance register offset
+ * @clkdm_offs: (OMAP4 only) CM clockdomain register offset
+ * @wkdep_srcs: Clockdomains that can be told to wake this powerdomain up
+ * @sleepdep_srcs: Clockdomains that can be told to keep this clkdm from inact
+ * @usecount: Usecount tracking
+ * @node: list_head to link all clockdomains together
+ *
+ * @prcm_partition should be a macro from mach-omap2/prcm44xx.h (OMAP4 only)
+ * @cm_inst should be a macro ending in _INST from the OMAP4 CM instance
+ *     definitions (OMAP4 only)
+ * @clkdm_offs should be a macro ending in _CDOFFS from the OMAP4 CM instance
+ *     definitions (OMAP4 only)
+ */
+struct clockdomain {
+	const char *name;
+	union {
+		const char *name;
+		struct powerdomain *ptr;
+	} pwrdm;
+	const u16 clktrctrl_mask;
+	const u8 flags;
+	u8 _flags;
+	const u8 dep_bit;
+	const u8 prcm_partition;
+	const u16 cm_inst;
+	const u16 clkdm_offs;
+	struct clkdm_dep *wkdep_srcs;
+	struct clkdm_dep *sleepdep_srcs;
+	int usecount;
+	struct list_head node;
+};
+
+/**
+ * struct clkdm_ops - Arch specific function implementations
+ * @clkdm_add_wkdep: Add a wakeup dependency between clk domains
+ * @clkdm_del_wkdep: Delete a wakeup dependency between clk domains
+ * @clkdm_read_wkdep: Read wakeup dependency state between clk domains
+ * @clkdm_clear_all_wkdeps: Remove all wakeup dependencies from the clk domain
+ * @clkdm_add_sleepdep: Add a sleep dependency between clk domains
+ * @clkdm_del_sleepdep: Delete a sleep dependency between clk domains
+ * @clkdm_read_sleepdep: Read sleep dependency state between clk domains
+ * @clkdm_clear_all_sleepdeps: Remove all sleep dependencies from the clk domain
+ * @clkdm_sleep: Force a clockdomain to sleep
+ * @clkdm_wakeup: Force a clockdomain to wakeup
+ * @clkdm_allow_idle: Enable hw supervised idle transitions for clock domain
+ * @clkdm_deny_idle: Disable hw supervised idle transitions for clock domain
+ * @clkdm_clk_enable: Put the clkdm in right state for a clock enable
+ * @clkdm_clk_disable: Put the clkdm in right state for a clock disable
+ */
+struct clkdm_ops {
+	int	(*clkdm_add_wkdep)(struct clockdomain *clkdm1,
+				   struct clockdomain *clkdm2);
+	int	(*clkdm_del_wkdep)(struct clockdomain *clkdm1,
+				   struct clockdomain *clkdm2);
+	int	(*clkdm_read_wkdep)(struct clockdomain *clkdm1,
+				    struct clockdomain *clkdm2);
+	int	(*clkdm_clear_all_wkdeps)(struct clockdomain *clkdm);
+	int	(*clkdm_add_sleepdep)(struct clockdomain *clkdm1,
+				      struct clockdomain *clkdm2);
+	int	(*clkdm_del_sleepdep)(struct clockdomain *clkdm1,
+				      struct clockdomain *clkdm2);
+	int	(*clkdm_read_sleepdep)(struct clockdomain *clkdm1,
+				       struct clockdomain *clkdm2);
+	int	(*clkdm_clear_all_sleepdeps)(struct clockdomain *clkdm);
+	int	(*clkdm_sleep)(struct clockdomain *clkdm);
+	int	(*clkdm_wakeup)(struct clockdomain *clkdm);
+	void	(*clkdm_allow_idle)(struct clockdomain *clkdm);
+	void	(*clkdm_deny_idle)(struct clockdomain *clkdm);
+	int	(*clkdm_clk_enable)(struct clockdomain *clkdm);
+	int	(*clkdm_clk_disable)(struct clockdomain *clkdm);
+};
+
+int clkdm_register_platform_funcs(struct clkdm_ops *co);
+int clkdm_register_autodeps(struct clkdm_autodep *ia);
+int clkdm_register_clkdms(struct clockdomain **c);
+int clkdm_complete_init(void);
+
+struct clockdomain *clkdm_lookup(const char *name);
+
+int clkdm_for_each(int (*fn)(struct clockdomain *clkdm, void *user),
+			void *user);
+struct powerdomain *clkdm_get_pwrdm(struct clockdomain *clkdm);
+
+int clkdm_add_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
+int clkdm_del_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
+int clkdm_read_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
+int clkdm_clear_all_wkdeps(struct clockdomain *clkdm);
+int clkdm_add_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
+int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
+int clkdm_read_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
+int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm);
+
+void clkdm_allow_idle_nolock(struct clockdomain *clkdm);
+void clkdm_allow_idle(struct clockdomain *clkdm);
+void clkdm_deny_idle_nolock(struct clockdomain *clkdm);
+void clkdm_deny_idle(struct clockdomain *clkdm);
+bool clkdm_in_hwsup(struct clockdomain *clkdm);
+bool clkdm_missing_idle_reporting(struct clockdomain *clkdm);
+
+int clkdm_wakeup_nolock(struct clockdomain *clkdm);
+int clkdm_wakeup(struct clockdomain *clkdm);
+int clkdm_sleep_nolock(struct clockdomain *clkdm);
+int clkdm_sleep(struct clockdomain *clkdm);
+
+int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk);
+int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk);
+int clkdm_hwmod_enable(struct clockdomain *clkdm, struct omap_hwmod *oh);
+int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh);
+
+void __init omap242x_clockdomains_init(void);
+void __init omap243x_clockdomains_init(void);
+void __init omap3xxx_clockdomains_init(void);
+void __init am33xx_clockdomains_init(void);
+void __init omap44xx_clockdomains_init(void);
+void __init omap54xx_clockdomains_init(void);
+void __init dra7xx_clockdomains_init(void);
+void am43xx_clockdomains_init(void);
+
+void clkdm_add_autodeps(struct clockdomain *clkdm);
+void clkdm_del_autodeps(struct clockdomain *clkdm);
+
+extern struct clkdm_ops omap2_clkdm_operations;
+extern struct clkdm_ops omap3_clkdm_operations;
+extern struct clkdm_ops omap4_clkdm_operations;
+extern struct clkdm_ops am33xx_clkdm_operations;
+extern struct clkdm_ops am43xx_clkdm_operations;
+
+extern struct clkdm_dep gfx_24xx_wkdeps[];
+extern struct clkdm_dep dsp_24xx_wkdeps[];
+extern struct clockdomain wkup_common_clkdm;
+
+#endif
-- 
1.7.9.5

[PATCH 51/55] ARM: OMAP2+: powerdomain: move powerdomain.h header to public location

[Tero Kristo]

This file needs to be accessible from the PRCM core and mach-omap2 board
support code.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/clockdomain.c                |    2 +-
 arch/arm/mach-omap2/cm2xxx.c                     |    2 +-
 arch/arm/mach-omap2/cm3xxx.c                     |    2 +-
 arch/arm/mach-omap2/cpuidle34xx.c                |    2 +-
 arch/arm/mach-omap2/gpio.c                       |    2 +-
 arch/arm/mach-omap2/io.c                         |    2 +-
 arch/arm/mach-omap2/omap-hotplug.c               |    2 +-
 arch/arm/mach-omap2/omap_hwmod.c                 |    2 +-
 arch/arm/mach-omap2/pm-debug.c                   |    2 +-
 arch/arm/mach-omap2/pm.c                         |    2 +-
 arch/arm/mach-omap2/pm.h                         |    2 +-
 arch/arm/mach-omap2/pm24xx.c                     |    2 +-
 arch/arm/mach-omap2/pm34xx.c                     |    2 +-
 arch/arm/mach-omap2/pm44xx.c                     |    2 +-
 arch/arm/mach-omap2/powerdomain.c                |    2 +-
 arch/arm/mach-omap2/powerdomain.h                |  277 ---------------------
 arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c |    2 +-
 arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.h |    2 +-
 arch/arm/mach-omap2/powerdomains2xxx_data.c      |    2 +-
 arch/arm/mach-omap2/powerdomains33xx_data.c      |    2 +-
 arch/arm/mach-omap2/powerdomains3xxx_data.c      |    2 +-
 arch/arm/mach-omap2/powerdomains43xx_data.c      |    2 +-
 arch/arm/mach-omap2/powerdomains44xx_data.c      |    2 +-
 arch/arm/mach-omap2/powerdomains54xx_data.c      |    2 +-
 arch/arm/mach-omap2/powerdomains7xx_data.c       |    2 +-
 arch/arm/mach-omap2/prm2xxx.c                    |    2 +-
 arch/arm/mach-omap2/prm2xxx_3xxx.c               |    2 +-
 arch/arm/mach-omap2/prm2xxx_3xxx_private.h       |    2 +-
 arch/arm/mach-omap2/prm33xx.c                    |    2 +-
 arch/arm/mach-omap2/prm3xxx.c                    |    2 +-
 arch/arm/mach-omap2/prm44xx.c                    |    2 +-
 arch/arm/mach-omap2/timer.c                      |    2 +-
 arch/arm/mach-omap2/voltage.c                    |    2 +-
 include/linux/power/omap/powerdomain.h           |  280 ++++++++++++++++++++++
 34 files changed, 312 insertions(+), 309 deletions(-)
 delete mode 100644 arch/arm/mach-omap2/powerdomain.h
 create mode 100644 include/linux/power/omap/powerdomain.h

diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index 298fb05..26d28c7 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -30,7 +30,7 @@
 
 #include "soc.h"
 #include <linux/power/omap/clockdomain.h>
-#include "powerdomain.h"
+#include <linux/power/omap/powerdomain.h>
 
 /* clkdm_list contains all registered struct clockdomains */
 static LIST_HEAD(clkdm_list);
diff --git a/arch/arm/mach-omap2/cm2xxx.c b/arch/arm/mach-omap2/cm2xxx.c
index 93efae1..c0aec2c 100644
--- a/arch/arm/mach-omap2/cm2xxx.c
+++ b/arch/arm/mach-omap2/cm2xxx.c
@@ -25,7 +25,7 @@
 #include <linux/power/omap/clockdomain.h>
 #include <linux/power/omap/prcm-common.h>
 #include <linux/power/omap/prm2xxx_3xxx.h>
-#include "powerdomain.h"
+#include <linux/power/omap/powerdomain.h>
 
 /* CM_AUTOIDLE_PLL.AUTO_* bit values for DPLLs */
 #define DPLL_AUTOIDLE_DISABLE				0x0
diff --git a/arch/arm/mach-omap2/cm3xxx.c b/arch/arm/mach-omap2/cm3xxx.c
index 47d0e49..d1b65ab 100644
--- a/arch/arm/mach-omap2/cm3xxx.c
+++ b/arch/arm/mach-omap2/cm3xxx.c
@@ -24,7 +24,7 @@
 #include <linux/power/omap/cm3xxx.h>
 #include <linux/power/omap/clockdomain.h>
 #include <linux/power/omap/prcm-common.h>
-#include "powerdomain.h"
+#include <linux/power/omap/powerdomain.h>
 
 #define OMAP34XX_CLKSTCTRL_DISABLE_AUTO		0x0
 #define OMAP34XX_CLKSTCTRL_FORCE_SLEEP		0x1
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
index 858a28a..cb4f96a 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -28,7 +28,7 @@
 #include <linux/cpu_pm.h>
 #include <asm/cpuidle.h>
 
-#include "powerdomain.h"
+#include <linux/power/omap/powerdomain.h>
 #include <linux/power/omap/clockdomain.h>
 
 #include "pm.h"
diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c
index 7a57714..7d37e50 100644
--- a/arch/arm/mach-omap2/gpio.c
+++ b/arch/arm/mach-omap2/gpio.c
@@ -28,7 +28,7 @@
 #include "omap_device.h"
 #include "omap-pm.h"
 
-#include "powerdomain.h"
+#include <linux/power/omap/powerdomain.h>
 
 static int __init omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
 {
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index b12ca79..08dd6de 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -31,7 +31,7 @@
 #include "soc.h"
 #include "iomap.h"
 #include "voltage.h"
-#include "powerdomain.h"
+#include <linux/power/omap/powerdomain.h>
 #include <linux/power/omap/clockdomain.h>
 #include "common.h"
 #include "clock.h"
diff --git a/arch/arm/mach-omap2/omap-hotplug.c b/arch/arm/mach-omap2/omap-hotplug.c
index 458f72f..5360d37 100644
--- a/arch/arm/mach-omap2/omap-hotplug.c
+++ b/arch/arm/mach-omap2/omap-hotplug.c
@@ -21,7 +21,7 @@
 
 #include "omap-wakeupgen.h"
 #include "common.h"
-#include "powerdomain.h"
+#include <linux/power/omap/powerdomain.h>
 
 /*
  * platform-specific code to shutdown a CPU
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index bfd3c19..d152ddc 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -150,7 +150,7 @@
 #include "soc.h"
 #include "common.h"
 #include <linux/power/omap/clockdomain.h>
-#include "powerdomain.h"
+#include <linux/power/omap/powerdomain.h>
 #include "cm2xxx.h"
 #include "cm3xxx.h"
 #include <linux/power/omap/cm44xx.h>
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index 766012e..5ef4c7d 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -28,7 +28,7 @@
 #include <linux/slab.h>
 
 #include "clock.h"
-#include "powerdomain.h"
+#include <linux/power/omap/powerdomain.h>
 #include <linux/power/omap/clockdomain.h>
 #include "omap-pm.h"
 
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 8ee7b14..ea6b5ad 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -27,7 +27,7 @@
 #include "soc.h"
 #include <linux/power/omap/prcm-common.h>
 #include "voltage.h"
-#include "powerdomain.h"
+#include <linux/power/omap/powerdomain.h>
 #include <linux/power/omap/clockdomain.h>
 #include "pm.h"
 #include "twl-common.h"
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 7bdd22a..b63bd1f 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -13,7 +13,7 @@
 
 #include <linux/err.h>
 
-#include "powerdomain.h"
+#include <linux/power/omap/powerdomain.h>
 
 #ifdef CONFIG_CPU_IDLE
 extern int __init omap3_idle_init(void);
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index 6c1b8d6..788ec5e 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -51,7 +51,7 @@
 #include "sram.h"
 #include "pm.h"
 #include "control.h"
-#include "powerdomain.h"
+#include <linux/power/omap/powerdomain.h>
 #include <linux/power/omap/clockdomain.h>
 
 static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl,
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 119b9ff..ca3724c 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -38,7 +38,7 @@
 #include <asm/system_misc.h>
 
 #include <linux/power/omap/clockdomain.h>
-#include "powerdomain.h"
+#include <linux/power/omap/powerdomain.h>
 #include "soc.h"
 #include "common.h"
 #include "cm3xxx.h"
diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
index 47f664f..d7b8d33 100644
--- a/arch/arm/mach-omap2/pm44xx.c
+++ b/arch/arm/mach-omap2/pm44xx.c
@@ -21,7 +21,7 @@
 #include "soc.h"
 #include "common.h"
 #include <linux/power/omap/clockdomain.h>
-#include "powerdomain.h"
+#include <linux/power/omap/powerdomain.h>
 #include "pm.h"
 
 u16 pm44xx_errata;
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 63fd500..11a5359 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -30,7 +30,7 @@
 #include <asm/cpu.h>
 
 #include <linux/power/omap/prm.h>
-#include "powerdomain.h"
+#include <linux/power/omap/powerdomain.h>
 #include <linux/power/omap/clockdomain.h>
 #include "voltage.h"
 
diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
deleted file mode 100644
index f472711..0000000
--- a/arch/arm/mach-omap2/powerdomain.h
+++ /dev/null
@@ -1,277 +0,0 @@
-/*
- * OMAP2/3/4 powerdomain control
- *
- * Copyright (C) 2007-2008, 2010 Texas Instruments, Inc.
- * Copyright (C) 2007-2011 Nokia Corporation
- *
- * Paul Walmsley
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * XXX This should be moved to the mach-omap2/ directory at the earliest
- * opportunity.
- */
-
-#ifndef __ARCH_ARM_MACH_OMAP2_POWERDOMAIN_H
-#define __ARCH_ARM_MACH_OMAP2_POWERDOMAIN_H
-
-#include <linux/types.h>
-#include <linux/list.h>
-#include <linux/spinlock.h>
-
-/* Powerdomain basic power states */
-#define PWRDM_POWER_OFF		0x0
-#define PWRDM_POWER_RET		0x1
-#define PWRDM_POWER_INACTIVE	0x2
-#define PWRDM_POWER_ON		0x3
-
-#define PWRDM_MAX_PWRSTS	4
-
-/* Powerdomain allowable state bitfields */
-#define PWRSTS_ON		(1 << PWRDM_POWER_ON)
-#define PWRSTS_INACTIVE		(1 << PWRDM_POWER_INACTIVE)
-#define PWRSTS_RET		(1 << PWRDM_POWER_RET)
-#define PWRSTS_OFF		(1 << PWRDM_POWER_OFF)
-
-#define PWRSTS_OFF_ON		(PWRSTS_OFF | PWRSTS_ON)
-#define PWRSTS_OFF_RET		(PWRSTS_OFF | PWRSTS_RET)
-#define PWRSTS_RET_ON		(PWRSTS_RET | PWRSTS_ON)
-#define PWRSTS_OFF_RET_ON	(PWRSTS_OFF_RET | PWRSTS_ON)
-
-
-/*
- * Powerdomain flags (struct powerdomain.flags)
- *
- * PWRDM_HAS_HDWR_SAR - powerdomain has hardware save-and-restore support
- *
- * PWRDM_HAS_MPU_QUIRK - MPU pwr domain has MEM bank 0 bits in MEM
- * bank 1 position. This is true for OMAP3430
- *
- * PWRDM_HAS_LOWPOWERSTATECHANGE - can transition from a sleep state
- * to a lower sleep state without waking up the powerdomain
- */
-#define PWRDM_HAS_HDWR_SAR		BIT(0)
-#define PWRDM_HAS_MPU_QUIRK		BIT(1)
-#define PWRDM_HAS_LOWPOWERSTATECHANGE	BIT(2)
-
-/*
- * Number of memory banks that are power-controllable.	On OMAP4430, the
- * maximum is 5.
- */
-#define PWRDM_MAX_MEM_BANKS	5
-
-/*
- * Maximum number of clockdomains that can be associated with a powerdomain.
- * PER powerdomain on AM33XX is the worst case
- */
-#define PWRDM_MAX_CLKDMS	11
-
-/* XXX A completely arbitrary number. What is reasonable here? */
-#define PWRDM_TRANSITION_BAILOUT 100000
-
-struct clockdomain;
-struct powerdomain;
-struct voltagedomain;
-
-/**
- * struct powerdomain - OMAP powerdomain
- * @name: Powerdomain name
- * @voltdm: voltagedomain containing this powerdomain
- * @prcm_offs: the address offset from CM_BASE/PRM_BASE
- * @prcm_partition: (OMAP4 only) the PRCM partition ID containing @prcm_offs
- * @pwrsts: Possible powerdomain power states
- * @pwrsts_logic_ret: Possible logic power states when pwrdm in RETENTION
- * @flags: Powerdomain flags
- * @banks: Number of software-controllable memory banks in this powerdomain
- * @pwrsts_mem_ret: Possible memory bank pwrstates when pwrdm in RETENTION
- * @pwrsts_mem_on: Possible memory bank pwrstates when pwrdm in ON
- * @pwrdm_clkdms: Clockdomains in this powerdomain
- * @node: list_head linking all powerdomains
- * @voltdm_node: list_head linking all powerdomains in a voltagedomain
- * @pwrstctrl_offs: (AM33XX only) XXX_PWRSTCTRL reg offset from prcm_offs
- * @pwrstst_offs: (AM33XX only) XXX_PWRSTST reg offset from prcm_offs
- * @logicretstate_mask: (AM33XX only) mask for logic retention bitfield
- *	in @pwrstctrl_offs
- * @mem_on_mask: (AM33XX only) mask for mem on bitfield in @pwrstctrl_offs
- * @mem_ret_mask: (AM33XX only) mask for mem ret bitfield in @pwrstctrl_offs
- * @mem_pwrst_mask: (AM33XX only) mask for mem state bitfield in @pwrstst_offs
- * @mem_retst_mask: (AM33XX only) mask for mem retention state bitfield
- *	in @pwrstctrl_offs
- * @state:
- * @state_counter:
- * @timer:
- * @state_timer:
- * @_lock: spinlock used to serialize powerdomain and some clockdomain ops
- * @_lock_flags: stored flags when @_lock is taken
- *
- * @prcm_partition possible values are defined in mach-omap2/prcm44xx.h.
- */
-struct powerdomain {
-	const char *name;
-	union {
-		const char *name;
-		struct voltagedomain *ptr;
-	} voltdm;
-	const s16 prcm_offs;
-	const u8 pwrsts;
-	const u8 pwrsts_logic_ret;
-	const u8 flags;
-	const u8 banks;
-	const u8 pwrsts_mem_ret[PWRDM_MAX_MEM_BANKS];
-	const u8 pwrsts_mem_on[PWRDM_MAX_MEM_BANKS];
-	const u8 prcm_partition;
-	struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS];
-	struct list_head node;
-	struct list_head voltdm_node;
-	int state;
-	unsigned state_counter[PWRDM_MAX_PWRSTS];
-	unsigned ret_logic_off_counter;
-	unsigned ret_mem_off_counter[PWRDM_MAX_MEM_BANKS];
-	spinlock_t _lock;
-	unsigned long _lock_flags;
-	const u8 pwrstctrl_offs;
-	const u8 pwrstst_offs;
-	const u32 logicretstate_mask;
-	const u32 mem_on_mask[PWRDM_MAX_MEM_BANKS];
-	const u32 mem_ret_mask[PWRDM_MAX_MEM_BANKS];
-	const u32 mem_pwrst_mask[PWRDM_MAX_MEM_BANKS];
-	const u32 mem_retst_mask[PWRDM_MAX_MEM_BANKS];
-
-#ifdef CONFIG_PM_DEBUG
-	s64 timer;
-	s64 state_timer[PWRDM_MAX_PWRSTS];
-#endif
-};
-
-/**
- * struct pwrdm_ops - Arch specific function implementations
- * @pwrdm_set_next_pwrst: Set the target power state for a pd
- * @pwrdm_read_next_pwrst: Read the target power state set for a pd
- * @pwrdm_read_pwrst: Read the current power state of a pd
- * @pwrdm_read_prev_pwrst: Read the prev power state entered by the pd
- * @pwrdm_set_logic_retst: Set the logic state in RET for a pd
- * @pwrdm_set_mem_onst: Set the Memory state in ON for a pd
- * @pwrdm_set_mem_retst: Set the Memory state in RET for a pd
- * @pwrdm_read_logic_pwrst: Read the current logic state of a pd
- * @pwrdm_read_prev_logic_pwrst: Read the previous logic state entered by a pd
- * @pwrdm_read_logic_retst: Read the logic state in RET for a pd
- * @pwrdm_read_mem_pwrst: Read the current memory state of a pd
- * @pwrdm_read_prev_mem_pwrst: Read the previous memory state entered by a pd
- * @pwrdm_read_mem_retst: Read the memory state in RET for a pd
- * @pwrdm_clear_all_prev_pwrst: Clear all previous power states logged for a pd
- * @pwrdm_enable_hdwr_sar: Enable Hardware Save-Restore feature for the pd
- * @pwrdm_disable_hdwr_sar: Disable Hardware Save-Restore feature for a pd
- * @pwrdm_set_lowpwrstchange: Enable pd transitions from a shallow to deep sleep
- * @pwrdm_wait_transition: Wait for a pd state transition to complete
- * @pwrdm_has_voltdm: Check if a voltdm association is needed
- *
- * Regarding @pwrdm_set_lowpwrstchange: On the OMAP2 and 3-family
- * chips, a powerdomain's power state is not allowed to directly
- * transition from one low-power state (e.g., CSWR) to another
- * low-power state (e.g., OFF) without first waking up the
- * powerdomain.  This wastes energy.  So OMAP4 chips support the
- * ability to transition a powerdomain power state directly from one
- * low-power state to another.  The function pointed to by
- * @pwrdm_set_lowpwrstchange is intended to configure the OMAP4
- * hardware powerdomain state machine to enable this feature.
- */
-struct pwrdm_ops {
-	int	(*pwrdm_set_next_pwrst)(struct powerdomain *pwrdm, u8 pwrst);
-	int	(*pwrdm_read_next_pwrst)(struct powerdomain *pwrdm);
-	int	(*pwrdm_read_pwrst)(struct powerdomain *pwrdm);
-	int	(*pwrdm_read_prev_pwrst)(struct powerdomain *pwrdm);
-	int	(*pwrdm_set_logic_retst)(struct powerdomain *pwrdm, u8 pwrst);
-	int	(*pwrdm_set_mem_onst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
-	int	(*pwrdm_set_mem_retst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
-	int	(*pwrdm_read_logic_pwrst)(struct powerdomain *pwrdm);
-	int	(*pwrdm_read_prev_logic_pwrst)(struct powerdomain *pwrdm);
-	int	(*pwrdm_read_logic_retst)(struct powerdomain *pwrdm);
-	int	(*pwrdm_read_mem_pwrst)(struct powerdomain *pwrdm, u8 bank);
-	int	(*pwrdm_read_prev_mem_pwrst)(struct powerdomain *pwrdm, u8 bank);
-	int	(*pwrdm_read_mem_retst)(struct powerdomain *pwrdm, u8 bank);
-	int	(*pwrdm_clear_all_prev_pwrst)(struct powerdomain *pwrdm);
-	int	(*pwrdm_enable_hdwr_sar)(struct powerdomain *pwrdm);
-	int	(*pwrdm_disable_hdwr_sar)(struct powerdomain *pwrdm);
-	int	(*pwrdm_set_lowpwrstchange)(struct powerdomain *pwrdm);
-	int	(*pwrdm_wait_transition)(struct powerdomain *pwrdm);
-	int	(*pwrdm_has_voltdm)(void);
-};
-
-int pwrdm_register_platform_funcs(struct pwrdm_ops *custom_funcs);
-int pwrdm_register_pwrdms(struct powerdomain **pwrdm_list);
-int pwrdm_complete_init(void);
-
-struct powerdomain *pwrdm_lookup(const char *name);
-
-int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user),
-			void *user);
-int pwrdm_for_each_nolock(int (*fn)(struct powerdomain *pwrdm, void *user),
-			void *user);
-
-int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
-int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
-int pwrdm_for_each_clkdm(struct powerdomain *pwrdm,
-			 int (*fn)(struct powerdomain *pwrdm,
-				   struct clockdomain *clkdm));
-struct voltagedomain *pwrdm_get_voltdm(struct powerdomain *pwrdm);
-
-int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm);
-
-int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
-int pwrdm_read_next_pwrst(struct powerdomain *pwrdm);
-int pwrdm_read_pwrst(struct powerdomain *pwrdm);
-int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm);
-int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm);
-
-int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst);
-int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
-int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
-
-int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm);
-int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm);
-int pwrdm_read_logic_retst(struct powerdomain *pwrdm);
-int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
-int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
-int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank);
-
-int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm);
-int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm);
-bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm);
-
-int pwrdm_state_switch_nolock(struct powerdomain *pwrdm);
-int pwrdm_state_switch(struct powerdomain *pwrdm);
-int pwrdm_pre_transition(struct powerdomain *pwrdm);
-int pwrdm_post_transition(struct powerdomain *pwrdm);
-int pwrdm_get_context_loss_count(struct powerdomain *pwrdm);
-bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm);
-
-extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u8 state);
-
-extern void omap242x_powerdomains_init(void);
-extern void omap243x_powerdomains_init(void);
-extern void omap3xxx_powerdomains_init(void);
-extern void am33xx_powerdomains_init(void);
-extern void omap44xx_powerdomains_init(void);
-extern void omap54xx_powerdomains_init(void);
-extern void dra7xx_powerdomains_init(void);
-void am43xx_powerdomains_init(void);
-
-extern struct pwrdm_ops omap2_pwrdm_operations;
-extern struct pwrdm_ops omap3_pwrdm_operations;
-extern struct pwrdm_ops am33xx_pwrdm_operations;
-extern struct pwrdm_ops omap4_pwrdm_operations;
-
-/* Common Internal functions used across OMAP rev's */
-extern u32 omap2_pwrdm_get_mem_bank_onstate_mask(u8 bank);
-extern u32 omap2_pwrdm_get_mem_bank_retst_mask(u8 bank);
-extern u32 omap2_pwrdm_get_mem_bank_stst_mask(u8 bank);
-
-extern struct powerdomain wkup_omap2_pwrdm;
-extern struct powerdomain gfx_omap2_pwrdm;
-
-extern void pwrdm_lock(struct powerdomain *pwrdm);
-extern void pwrdm_unlock(struct powerdomain *pwrdm);
-
-#endif
diff --git a/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c b/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c
index 823bc4d..c3d2e8a 100644
--- a/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c
+++ b/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c
@@ -31,7 +31,7 @@
  * address offset is different between the C55 and C64 DSPs.
  */
 
-#include "powerdomain.h"
+#include <linux/power/omap/powerdomain.h>
 
 #include <linux/power/omap/prcm-common.h>
 #include <linux/power/omap/prm.h>
diff --git a/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.h b/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.h
index fa31166..b22c174 100644
--- a/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.h
+++ b/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.h
@@ -14,7 +14,7 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_POWERDOMAINS2XXX_3XXX_DATA_H
 #define __ARCH_ARM_MACH_OMAP2_POWERDOMAINS2XXX_3XXX_DATA_H
 
-#include "powerdomain.h"
+#include <linux/power/omap/powerdomain.h>
 
 extern struct powerdomain gfx_omap2_pwrdm;
 extern struct powerdomain wkup_omap2_pwrdm;
diff --git a/arch/arm/mach-omap2/powerdomains2xxx_data.c b/arch/arm/mach-omap2/powerdomains2xxx_data.c
index 9506c0e..7fced02 100644
--- a/arch/arm/mach-omap2/powerdomains2xxx_data.c
+++ b/arch/arm/mach-omap2/powerdomains2xxx_data.c
@@ -15,7 +15,7 @@
 #include <linux/init.h>
 
 #include "soc.h"
-#include "powerdomain.h"
+#include <linux/power/omap/powerdomain.h>
 #include "powerdomains2xxx_3xxx_data.h"
 
 #include <linux/power/omap/prcm-common.h>
diff --git a/arch/arm/mach-omap2/powerdomains33xx_data.c b/arch/arm/mach-omap2/powerdomains33xx_data.c
index 0a7a5ca..719c541 100644
--- a/arch/arm/mach-omap2/powerdomains33xx_data.c
+++ b/arch/arm/mach-omap2/powerdomains33xx_data.c
@@ -16,7 +16,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 
-#include "powerdomain.h"
+#include <linux/power/omap/powerdomain.h>
 #include <linux/power/omap/prcm-common.h>
 #include "prm-regbits-33xx.h"
 #include "prm33xx.h"
diff --git a/arch/arm/mach-omap2/powerdomains3xxx_data.c b/arch/arm/mach-omap2/powerdomains3xxx_data.c
index be12876..01c43d4 100644
--- a/arch/arm/mach-omap2/powerdomains3xxx_data.c
+++ b/arch/arm/mach-omap2/powerdomains3xxx_data.c
@@ -16,7 +16,7 @@
 #include <linux/bug.h>
 
 #include "soc.h"
-#include "powerdomain.h"
+#include <linux/power/omap/powerdomain.h>
 #include "powerdomains2xxx_3xxx_data.h"
 #include <linux/power/omap/prcm-common.h>
 #include <linux/power/omap/prm2xxx_3xxx.h>
diff --git a/arch/arm/mach-omap2/powerdomains43xx_data.c b/arch/arm/mach-omap2/powerdomains43xx_data.c
index 91802f1..922d6ea 100644
--- a/arch/arm/mach-omap2/powerdomains43xx_data.c
+++ b/arch/arm/mach-omap2/powerdomains43xx_data.c
@@ -11,7 +11,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 
-#include "powerdomain.h"
+#include <linux/power/omap/powerdomain.h>
 
 #include <linux/power/omap/prcm-common.h>
 #include "prcm43xx.h"
diff --git a/arch/arm/mach-omap2/powerdomains44xx_data.c b/arch/arm/mach-omap2/powerdomains44xx_data.c
index 793c611..290d68d 100644
--- a/arch/arm/mach-omap2/powerdomains44xx_data.c
+++ b/arch/arm/mach-omap2/powerdomains44xx_data.c
@@ -22,7 +22,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 
-#include "powerdomain.h"
+#include <linux/power/omap/powerdomain.h>
 
 #include <linux/power/omap/prcm-common.h>
 #include <linux/power/omap/prcm44xx.h>
diff --git a/arch/arm/mach-omap2/powerdomains54xx_data.c b/arch/arm/mach-omap2/powerdomains54xx_data.c
index 37017f2..c24a991 100644
--- a/arch/arm/mach-omap2/powerdomains54xx_data.c
+++ b/arch/arm/mach-omap2/powerdomains54xx_data.c
@@ -21,7 +21,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 
-#include "powerdomain.h"
+#include <linux/power/omap/powerdomain.h>
 
 #include <linux/power/omap/prcm-common.h>
 #include <linux/power/omap/prcm44xx.h>
diff --git a/arch/arm/mach-omap2/powerdomains7xx_data.c b/arch/arm/mach-omap2/powerdomains7xx_data.c
index cedc84b..35f6ca1 100644
--- a/arch/arm/mach-omap2/powerdomains7xx_data.c
+++ b/arch/arm/mach-omap2/powerdomains7xx_data.c
@@ -23,7 +23,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 
-#include "powerdomain.h"
+#include <linux/power/omap/powerdomain.h>
 
 #include <linux/power/omap/prcm-common.h>
 #include <linux/power/omap/prcm44xx.h>
diff --git a/arch/arm/mach-omap2/prm2xxx.c b/arch/arm/mach-omap2/prm2xxx.c
index 7969cb9..735ee33 100644
--- a/arch/arm/mach-omap2/prm2xxx.c
+++ b/arch/arm/mach-omap2/prm2xxx.c
@@ -18,7 +18,7 @@
 #include <linux/io.h>
 #include <linux/irq.h>
 
-#include "powerdomain.h"
+#include <linux/power/omap/powerdomain.h>
 #include <linux/power/omap/clockdomain.h>
 #include <linux/power/omap/prm2xxx.h>
 #include "prm2xxx_3xxx_private.h"
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c
index a25d1d0..27828d0 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c
@@ -16,7 +16,7 @@
 #include <linux/err.h>
 #include <linux/io.h>
 
-#include "powerdomain.h"
+#include <linux/power/omap/powerdomain.h>
 #include "prm2xxx_3xxx_private.h"
 #include <linux/power/omap/clockdomain.h>
 
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx_private.h b/arch/arm/mach-omap2/prm2xxx_3xxx_private.h
index 5d6861a..52537fd 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx_private.h
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx_private.h
@@ -23,7 +23,7 @@
 #ifndef __ASSEMBLER__
 
 #include <linux/io.h>
-#include "powerdomain.h"
+#include <linux/power/omap/powerdomain.h>
 
 /* Power/reset management domain register get/set */
 static inline u32 omap2_prm_read_mod_reg(s16 module, u16 idx)
diff --git a/arch/arm/mach-omap2/prm33xx.c b/arch/arm/mach-omap2/prm33xx.c
index b5864c9..05356a3 100644
--- a/arch/arm/mach-omap2/prm33xx.c
+++ b/arch/arm/mach-omap2/prm33xx.c
@@ -20,7 +20,7 @@
 #include <linux/io.h>
 #include <linux/power/omap/prm33xx.h>
 
-#include "powerdomain.h"
+#include <linux/power/omap/powerdomain.h>
 #include <linux/power/omap/prm.h>
 
 #define AM33XX_LASTPOWERSTATEENTERED_SHIFT	24
diff --git a/arch/arm/mach-omap2/prm3xxx.c b/arch/arm/mach-omap2/prm3xxx.c
index e7d409c..be4c3ef 100644
--- a/arch/arm/mach-omap2/prm3xxx.c
+++ b/arch/arm/mach-omap2/prm3xxx.c
@@ -18,7 +18,7 @@
 #include <linux/io.h>
 #include <linux/irq.h>
 
-#include "powerdomain.h"
+#include <linux/power/omap/powerdomain.h>
 #include <linux/power/omap/prm3xxx.h>
 #include "prm2xxx_3xxx_private.h"
 #include "cm2xxx_3xxx_private.h"
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index 69a974b..ab04ce8 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -24,7 +24,7 @@
 #include <linux/power/omap/prm7xx.h>
 #include <linux/power/omap/prcm44xx.h>
 #include "prminst44xx_private.h"
-#include "powerdomain.h"
+#include <linux/power/omap/powerdomain.h>
 #include <linux/power/omap/prm.h>
 #include <linux/power/omap/prcm-common.h>
 #include <linux/power/omap/prm44xx_54xx.h>
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 74044aa..f10ca44 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -54,7 +54,7 @@
 
 #include "soc.h"
 #include "common.h"
-#include "powerdomain.h"
+#include <linux/power/omap/powerdomain.h>
 #include "omap-secure.h"
 
 #define REALTIME_COUNTER_BASE				0x48243200
diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
index b707328..17df5e7 100644
--- a/arch/arm/mach-omap2/voltage.c
+++ b/arch/arm/mach-omap2/voltage.c
@@ -36,7 +36,7 @@
 #include "control.h"
 
 #include "voltage.h"
-#include "powerdomain.h"
+#include <linux/power/omap/powerdomain.h>
 
 #include "vc.h"
 #include "vp.h"
diff --git a/include/linux/power/omap/powerdomain.h b/include/linux/power/omap/powerdomain.h
new file mode 100644
index 0000000..27f2750
--- /dev/null
+++ b/include/linux/power/omap/powerdomain.h
@@ -0,0 +1,280 @@
+/*
+ * OMAP2/3/4 powerdomain control
+ *
+ * Copyright (C) 2007-2008, 2010 Texas Instruments, Inc.
+ * Copyright (C) 2007-2011 Nokia Corporation
+ *
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * XXX This should be moved to the mach-omap2/ directory at the earliest
+ * opportunity.
+ */
+
+#ifndef __LINUX_POWER_OMAP_POWERDOMAIN_H
+#define __LINUX_POWER_OMAP_POWERDOMAIN_H
+
+#include <linux/types.h>
+#include <linux/list.h>
+#include <linux/spinlock.h>
+
+/* Powerdomain basic power states */
+#define PWRDM_POWER_OFF		0x0
+#define PWRDM_POWER_RET		0x1
+#define PWRDM_POWER_INACTIVE	0x2
+#define PWRDM_POWER_ON		0x3
+
+#define PWRDM_MAX_PWRSTS	4
+
+/* Powerdomain allowable state bitfields */
+#define PWRSTS_ON		(1 << PWRDM_POWER_ON)
+#define PWRSTS_INACTIVE		(1 << PWRDM_POWER_INACTIVE)
+#define PWRSTS_RET		(1 << PWRDM_POWER_RET)
+#define PWRSTS_OFF		(1 << PWRDM_POWER_OFF)
+
+#define PWRSTS_OFF_ON		(PWRSTS_OFF | PWRSTS_ON)
+#define PWRSTS_OFF_RET		(PWRSTS_OFF | PWRSTS_RET)
+#define PWRSTS_RET_ON		(PWRSTS_RET | PWRSTS_ON)
+#define PWRSTS_OFF_RET_ON	(PWRSTS_OFF_RET | PWRSTS_ON)
+
+
+/*
+ * Powerdomain flags (struct powerdomain.flags)
+ *
+ * PWRDM_HAS_HDWR_SAR - powerdomain has hardware save-and-restore support
+ *
+ * PWRDM_HAS_MPU_QUIRK - MPU pwr domain has MEM bank 0 bits in MEM
+ * bank 1 position. This is true for OMAP3430
+ *
+ * PWRDM_HAS_LOWPOWERSTATECHANGE - can transition from a sleep state
+ * to a lower sleep state without waking up the powerdomain
+ */
+#define PWRDM_HAS_HDWR_SAR		BIT(0)
+#define PWRDM_HAS_MPU_QUIRK		BIT(1)
+#define PWRDM_HAS_LOWPOWERSTATECHANGE	BIT(2)
+
+/*
+ * Number of memory banks that are power-controllable.	On OMAP4430, the
+ * maximum is 5.
+ */
+#define PWRDM_MAX_MEM_BANKS	5
+
+/*
+ * Maximum number of clockdomains that can be associated with a powerdomain.
+ * PER powerdomain on AM33XX is the worst case
+ */
+#define PWRDM_MAX_CLKDMS	11
+
+/* XXX A completely arbitrary number. What is reasonable here? */
+#define PWRDM_TRANSITION_BAILOUT 100000
+
+struct clockdomain;
+struct powerdomain;
+struct voltagedomain;
+
+/**
+ * struct powerdomain - OMAP powerdomain
+ * @name: Powerdomain name
+ * @voltdm: voltagedomain containing this powerdomain
+ * @prcm_offs: the address offset from CM_BASE/PRM_BASE
+ * @prcm_partition: (OMAP4 only) the PRCM partition ID containing @prcm_offs
+ * @pwrsts: Possible powerdomain power states
+ * @pwrsts_logic_ret: Possible logic power states when pwrdm in RETENTION
+ * @flags: Powerdomain flags
+ * @banks: Number of software-controllable memory banks in this powerdomain
+ * @pwrsts_mem_ret: Possible memory bank pwrstates when pwrdm in RETENTION
+ * @pwrsts_mem_on: Possible memory bank pwrstates when pwrdm in ON
+ * @pwrdm_clkdms: Clockdomains in this powerdomain
+ * @node: list_head linking all powerdomains
+ * @voltdm_node: list_head linking all powerdomains in a voltagedomain
+ * @pwrstctrl_offs: (AM33XX only) XXX_PWRSTCTRL reg offset from prcm_offs
+ * @pwrstst_offs: (AM33XX only) XXX_PWRSTST reg offset from prcm_offs
+ * @logicretstate_mask: (AM33XX only) mask for logic retention bitfield
+ *	in @pwrstctrl_offs
+ * @mem_on_mask: (AM33XX only) mask for mem on bitfield in @pwrstctrl_offs
+ * @mem_ret_mask: (AM33XX only) mask for mem ret bitfield in @pwrstctrl_offs
+ * @mem_pwrst_mask: (AM33XX only) mask for mem state bitfield in @pwrstst_offs
+ * @mem_retst_mask: (AM33XX only) mask for mem retention state bitfield
+ *	in @pwrstctrl_offs
+ * @state:
+ * @state_counter:
+ * @timer:
+ * @state_timer:
+ * @_lock: spinlock used to serialize powerdomain and some clockdomain ops
+ * @_lock_flags: stored flags when @_lock is taken
+ *
+ * @prcm_partition possible values are defined in mach-omap2/prcm44xx.h.
+ */
+struct powerdomain {
+	const char *name;
+	union {
+		const char *name;
+		struct voltagedomain *ptr;
+	} voltdm;
+	const s16 prcm_offs;
+	const u8 pwrsts;
+	const u8 pwrsts_logic_ret;
+	const u8 flags;
+	const u8 banks;
+	const u8 pwrsts_mem_ret[PWRDM_MAX_MEM_BANKS];
+	const u8 pwrsts_mem_on[PWRDM_MAX_MEM_BANKS];
+	const u8 prcm_partition;
+	struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS];
+	struct list_head node;
+	struct list_head voltdm_node;
+	int state;
+	unsigned state_counter[PWRDM_MAX_PWRSTS];
+	unsigned ret_logic_off_counter;
+	unsigned ret_mem_off_counter[PWRDM_MAX_MEM_BANKS];
+	spinlock_t _lock;
+	unsigned long _lock_flags;
+	const u8 pwrstctrl_offs;
+	const u8 pwrstst_offs;
+	const u32 logicretstate_mask;
+	const u32 mem_on_mask[PWRDM_MAX_MEM_BANKS];
+	const u32 mem_ret_mask[PWRDM_MAX_MEM_BANKS];
+	const u32 mem_pwrst_mask[PWRDM_MAX_MEM_BANKS];
+	const u32 mem_retst_mask[PWRDM_MAX_MEM_BANKS];
+
+#ifdef CONFIG_PM_DEBUG
+	s64 timer;
+	s64 state_timer[PWRDM_MAX_PWRSTS];
+#endif
+};
+
+/**
+ * struct pwrdm_ops - Arch specific function implementations
+ * @pwrdm_set_next_pwrst: Set the target power state for a pd
+ * @pwrdm_read_next_pwrst: Read the target power state set for a pd
+ * @pwrdm_read_pwrst: Read the current power state of a pd
+ * @pwrdm_read_prev_pwrst: Read the prev power state entered by the pd
+ * @pwrdm_set_logic_retst: Set the logic state in RET for a pd
+ * @pwrdm_set_mem_onst: Set the Memory state in ON for a pd
+ * @pwrdm_set_mem_retst: Set the Memory state in RET for a pd
+ * @pwrdm_read_logic_pwrst: Read the current logic state of a pd
+ * @pwrdm_read_prev_logic_pwrst: Read the previous logic state entered by a pd
+ * @pwrdm_read_logic_retst: Read the logic state in RET for a pd
+ * @pwrdm_read_mem_pwrst: Read the current memory state of a pd
+ * @pwrdm_read_prev_mem_pwrst: Read the previous memory state entered by a pd
+ * @pwrdm_read_mem_retst: Read the memory state in RET for a pd
+ * @pwrdm_clear_all_prev_pwrst: Clear all previous power states logged for a pd
+ * @pwrdm_enable_hdwr_sar: Enable Hardware Save-Restore feature for the pd
+ * @pwrdm_disable_hdwr_sar: Disable Hardware Save-Restore feature for a pd
+ * @pwrdm_set_lowpwrstchange: Enable pd transitions from a shallow to deep sleep
+ * @pwrdm_wait_transition: Wait for a pd state transition to complete
+ * @pwrdm_has_voltdm: Check if a voltdm association is needed
+ *
+ * Regarding @pwrdm_set_lowpwrstchange: On the OMAP2 and 3-family
+ * chips, a powerdomain's power state is not allowed to directly
+ * transition from one low-power state (e.g., CSWR) to another
+ * low-power state (e.g., OFF) without first waking up the
+ * powerdomain.  This wastes energy.  So OMAP4 chips support the
+ * ability to transition a powerdomain power state directly from one
+ * low-power state to another.  The function pointed to by
+ * @pwrdm_set_lowpwrstchange is intended to configure the OMAP4
+ * hardware powerdomain state machine to enable this feature.
+ */
+struct pwrdm_ops {
+	int	(*pwrdm_set_next_pwrst)(struct powerdomain *pwrdm, u8 pwrst);
+	int	(*pwrdm_read_next_pwrst)(struct powerdomain *pwrdm);
+	int	(*pwrdm_read_pwrst)(struct powerdomain *pwrdm);
+	int	(*pwrdm_read_prev_pwrst)(struct powerdomain *pwrdm);
+	int	(*pwrdm_set_logic_retst)(struct powerdomain *pwrdm, u8 pwrst);
+	int	(*pwrdm_set_mem_onst)(struct powerdomain *pwrdm, u8 bank,
+				      u8 pwrst);
+	int	(*pwrdm_set_mem_retst)(struct powerdomain *pwrdm, u8 bank,
+				       u8 pwrst);
+	int	(*pwrdm_read_logic_pwrst)(struct powerdomain *pwrdm);
+	int	(*pwrdm_read_prev_logic_pwrst)(struct powerdomain *pwrdm);
+	int	(*pwrdm_read_logic_retst)(struct powerdomain *pwrdm);
+	int	(*pwrdm_read_mem_pwrst)(struct powerdomain *pwrdm, u8 bank);
+	int	(*pwrdm_read_prev_mem_pwrst)(struct powerdomain *pwrdm,
+					     u8 bank);
+	int	(*pwrdm_read_mem_retst)(struct powerdomain *pwrdm, u8 bank);
+	int	(*pwrdm_clear_all_prev_pwrst)(struct powerdomain *pwrdm);
+	int	(*pwrdm_enable_hdwr_sar)(struct powerdomain *pwrdm);
+	int	(*pwrdm_disable_hdwr_sar)(struct powerdomain *pwrdm);
+	int	(*pwrdm_set_lowpwrstchange)(struct powerdomain *pwrdm);
+	int	(*pwrdm_wait_transition)(struct powerdomain *pwrdm);
+	int	(*pwrdm_has_voltdm)(void);
+};
+
+int pwrdm_register_platform_funcs(struct pwrdm_ops *custom_funcs);
+int pwrdm_register_pwrdms(struct powerdomain **pwrdm_list);
+int pwrdm_complete_init(void);
+
+struct powerdomain *pwrdm_lookup(const char *name);
+
+int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user),
+			void *user);
+int pwrdm_for_each_nolock(int (*fn)(struct powerdomain *pwrdm, void *user),
+			void *user);
+
+int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
+int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
+int pwrdm_for_each_clkdm(struct powerdomain *pwrdm,
+			 int (*fn)(struct powerdomain *pwrdm,
+				   struct clockdomain *clkdm));
+struct voltagedomain *pwrdm_get_voltdm(struct powerdomain *pwrdm);
+
+int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm);
+
+int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
+int pwrdm_read_next_pwrst(struct powerdomain *pwrdm);
+int pwrdm_read_pwrst(struct powerdomain *pwrdm);
+int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm);
+int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm);
+
+int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst);
+int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
+int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
+
+int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm);
+int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm);
+int pwrdm_read_logic_retst(struct powerdomain *pwrdm);
+int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
+int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
+int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank);
+
+int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm);
+int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm);
+bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm);
+
+int pwrdm_state_switch_nolock(struct powerdomain *pwrdm);
+int pwrdm_state_switch(struct powerdomain *pwrdm);
+int pwrdm_pre_transition(struct powerdomain *pwrdm);
+int pwrdm_post_transition(struct powerdomain *pwrdm);
+int pwrdm_get_context_loss_count(struct powerdomain *pwrdm);
+bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm);
+
+int omap_set_pwrdm_state(struct powerdomain *pwrdm, u8 state);
+
+void omap242x_powerdomains_init(void);
+void omap243x_powerdomains_init(void);
+void omap3xxx_powerdomains_init(void);
+void am33xx_powerdomains_init(void);
+void omap44xx_powerdomains_init(void);
+void omap54xx_powerdomains_init(void);
+void dra7xx_powerdomains_init(void);
+void am43xx_powerdomains_init(void);
+
+extern struct pwrdm_ops omap2_pwrdm_operations;
+extern struct pwrdm_ops omap3_pwrdm_operations;
+extern struct pwrdm_ops am33xx_pwrdm_operations;
+extern struct pwrdm_ops omap4_pwrdm_operations;
+
+/* Common Internal functions used across OMAP rev's */
+u32 omap2_pwrdm_get_mem_bank_onstate_mask(u8 bank);
+u32 omap2_pwrdm_get_mem_bank_retst_mask(u8 bank);
+u32 omap2_pwrdm_get_mem_bank_stst_mask(u8 bank);
+
+extern struct powerdomain wkup_omap2_pwrdm;
+extern struct powerdomain gfx_omap2_pwrdm;
+
+void pwrdm_lock(struct powerdomain *pwrdm);
+void pwrdm_unlock(struct powerdomain *pwrdm);
+
+#endif
-- 
1.7.9.5

[PATCH 52/55] ARM: OMAP2+: PRCM: add prcm_base init call for DT boot

[Tero Kristo]

This parses the prm, cm and scrm base addresses from DT if available,
avoiding the need for various omap2_set_globals_* calls.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/cm_common.c        |   57 ++++++++++++++++---
 arch/arm/mach-omap2/control.c          |   36 ++++++++++--
 arch/arm/mach-omap2/io.c               |   50 ++++++++--------
 arch/arm/mach-omap2/prm_common.c       |   97 ++++++++++++++++++++++++--------
 include/linux/power/omap/prcm-common.h |   18 ++++++
 5 files changed, 196 insertions(+), 62 deletions(-)

diff --git a/arch/arm/mach-omap2/cm_common.c b/arch/arm/mach-omap2/cm_common.c
index 0a21fa9..67d4888 100644
--- a/arch/arm/mach-omap2/cm_common.c
+++ b/arch/arm/mach-omap2/cm_common.c
@@ -15,6 +15,7 @@
 #include <linux/init.h>
 #include <linux/errno.h>
 #include <linux/of.h>
+#include <linux/of_address.h>
 
 #include <linux/power/omap/cm2xxx.h>
 #include <linux/power/omap/cm3xxx.h>
@@ -140,14 +141,32 @@ int cm_unregister(struct cm_ll_data *cld)
 	return 0;
 }
 
+static const struct prcm_match_data cm_base_data = {
+	.flags = PRCM_REGISTER_CLOCKS,
+	.index = PRCM_CLK_MEMMAP_INDEX_CM1,
+};
+
+static const struct prcm_match_data cm2_base_data = {
+	.flags = PRCM_REGISTER_CLOCKS,
+	.index = PRCM_CLK_MEMMAP_INDEX_CM2,
+};
+
+static const struct prcm_match_data omap3_cm_data = {
+	.flags = PRCM_REGISTER_CLOCKS,
+	.index = PRCM_CLK_MEMMAP_INDEX_CM1,
+	.offset = 0x800,
+};
+
 static struct of_device_id omap_cm_dt_match_table[] = {
-	{ .compatible = "ti,omap3-cm" },
-	{ .compatible = "ti,omap4-cm1" },
-	{ .compatible = "ti,omap4-cm2" },
-	{ .compatible = "ti,omap5-cm-core-aon" },
-	{ .compatible = "ti,omap5-cm-core" },
-	{ .compatible = "ti,dra7-cm-core-aon" },
-	{ .compatible = "ti,dra7-cm-core" },
+	{ .compatible = "ti,omap3-cm", .data = &omap3_cm_data },
+	{ .compatible = "ti,omap4-cm1", .data = &cm_base_data },
+	{ .compatible = "ti,omap4-cm2", .data = &cm2_base_data },
+	{ .compatible = "ti,omap5-cm-core-aon", .data = &cm_base_data },
+	{ .compatible = "ti,omap5-cm-core", .data = &cm2_base_data },
+	{ .compatible = "ti,dra7-cm-core-aon", .data = &cm_base_data },
+	{ .compatible = "ti,dra7-cm-core", .data = &cm2_base_data },
+	{ .compatible = "ti,am3-prcm", .data = &cm_base_data },
+	{ .compatible = "ti,am4-prcm", .data = &cm_base_data },
 	{ }
 };
 
@@ -156,3 +175,27 @@ int __init of_cm_init(void)
 {
 	return of_prcm_module_init(omap_cm_dt_match_table);
 }
+
+int __init of_cm_base_init(void)
+{
+	struct device_node *np;
+	const struct of_device_id *match;
+	const struct prcm_match_data *data;
+
+	for_each_matching_node_and_match(np, omap_cm_dt_match_table, &match) {
+		data = match->data;
+		if (clk_memmaps[data->index])
+			pr_warn("WARNING: multiple cm compatible mods %d\n",
+				data->index);
+
+		clk_memmaps[data->index] = of_iomap(np, 0);
+
+		if (data->index == PRCM_CLK_MEMMAP_INDEX_CM1)
+			cm_base = clk_memmaps[data->index] + data->offset;
+
+		if (data->index == PRCM_CLK_MEMMAP_INDEX_CM2)
+			cm2_base = clk_memmaps[data->index] + data->offset;
+	}
+
+	return 0;
+}
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index 90a7add..c404987 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -14,6 +14,8 @@
 
 #include <linux/kernel.h>
 #include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
 
 #include "soc.h"
 #include "iomap.h"
@@ -612,13 +614,16 @@ void __init omap3_ctrl_init(void)
 }
 #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
 
+static const struct prcm_match_data scrm_base_data = {
+	.flags = PRCM_REGISTER_CLOCKS,
+	.index = PRCM_CLK_MEMMAP_INDEX_SCRM,
+};
+
 static struct of_device_id omap_scrm_dt_match_table[] = {
-	{ .compatible = "ti,am3-scrm" },
-	{ .compatible = "ti,am4-scrm" },
-	{ .compatible = "ti,omap2-scrm" },
-	{ .compatible = "ti,omap3-scrm" },
-	{ .compatible = "ti,omap4-scrm" },
-	{ .compatible = "ti,omap5-scrm" },
+	{ .compatible = "ti,am3-scrm", .data = &scrm_base_data },
+	{ .compatible = "ti,am4-scrm", .data = &scrm_base_data },
+	{ .compatible = "ti,omap2-scrm", .data = &scrm_base_data },
+	{ .compatible = "ti,omap3-scrm", .data = &scrm_base_data },
 	{ }
 };
 
@@ -626,3 +631,22 @@ int __init of_scrm_init(void)
 {
 	return of_prcm_module_init(omap_scrm_dt_match_table);
 }
+
+int __init of_scrm_base_init(void)
+{
+	struct device_node *np;
+	const struct of_device_id *match;
+	const struct prcm_match_data *data;
+
+	for_each_matching_node_and_match(np, omap_scrm_dt_match_table, &match) {
+		data = match->data;
+
+		if (clk_memmaps[data->index])
+			pr_warn("WARN: multiple scrm compatible mods\n");
+
+		clk_memmaps[data->index] = of_iomap(np, 0);
+		omap2_ctrl_base = clk_memmaps[data->index];
+	}
+
+	return 0;
+}
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 08dd6de..6072f4a 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -398,10 +398,15 @@ void __init omap2420_init_early(void)
 	omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000));
 	omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
 			       OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE));
+	/*
+	 * XXX: following three set_globals_* calls can be removed
+	 * once omap2 is DT only boot
+	 */
 	omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE),
 				  NULL);
 	omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE));
 	omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE), NULL);
+	of_prcm_base_init();
 	omap2xxx_check_revision();
 	omap2xxx_prm_init();
 	omap2xxx_cm_init();
@@ -428,10 +433,15 @@ void __init omap2430_init_early(void)
 	omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000));
 	omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
 			       OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE));
+	/*
+	 * XXX: following three set_globals_* calls can be removed
+	 * once omap2 is DT only boot
+	 */
 	omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE),
 				  NULL);
 	omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE));
 	omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE), NULL);
+	of_prcm_base_init();
 	omap2xxx_check_revision();
 	omap2xxx_prm_init();
 	omap2xxx_cm_init();
@@ -471,10 +481,15 @@ void __init omap3_init_early(void)
 	omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000));
 	omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
 			       OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE));
+	/*
+	 * XXX: following three set_globals_* calls can be removed
+	 * once omap3 is DT only boot
+	 */
 	omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE),
 				  NULL);
 	omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE));
 	omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE), NULL);
+	of_prcm_base_init();
 	omap3xxx_check_revision();
 	omap3xxx_check_features();
 	omap3xxx_prm_init(omap3_prm_type());
@@ -519,10 +534,15 @@ void __init ti81xx_init_early(void)
 {
 	omap2_set_globals_tap(OMAP343X_CLASS,
 			      OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
+	/*
+	 * XXX: following three set_globals_control calls can be removed
+	 * once ti81xx is DT only boot
+	 */
 	omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE),
 				  NULL);
 	omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE));
 	omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), NULL);
+	of_prcm_base_init();
 	omap3xxx_check_revision();
 	ti81xx_check_features();
 	omap3xxx_voltagedomains_init();
@@ -584,10 +604,7 @@ void __init am33xx_init_early(void)
 {
 	omap2_set_globals_tap(AM335X_CLASS,
 			      AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
-	omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE),
-				  NULL);
-	omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE));
-	omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE), NULL);
+	of_prcm_base_init();
 	omap3xxx_check_revision();
 	am33xx_check_features();
 	am33xx_powerdomains_init();
@@ -608,12 +625,7 @@ void __init am43xx_init_early(void)
 {
 	omap2_set_globals_tap(AM335X_CLASS,
 			      AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
-	omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE),
-				  NULL);
-	omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE));
-	omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE), NULL);
-	omap_prm_base_init();
-	omap_cm_base_init();
+	of_prcm_base_init();
 	omap3xxx_check_revision();
 	am43xx_powerdomains_init();
 	am43xx_clockdomains_init();
@@ -635,12 +647,8 @@ void __init omap4430_init_early(void)
 			      OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE));
 	omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE),
 				  OMAP2_L4_IO_ADDRESS(OMAP443X_CTRL_BASE));
-	omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE));
-	omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE),
-			     OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE));
 	omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE));
-	omap_prm_base_init();
-	omap_cm_base_init();
+	of_prcm_base_init();
 	omap4xxx_check_revision();
 	omap4xxx_check_features();
 	omap4_pm_init_early();
@@ -668,12 +676,8 @@ void __init omap5_init_early(void)
 			      OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
 	omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
 				  OMAP2_L4_IO_ADDRESS(OMAP54XX_CTRL_BASE));
-	omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE));
-	omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE),
-			     OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE));
 	omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
-	omap_prm_base_init();
-	omap_cm_base_init();
+	of_prcm_base_init();
 	omap44xx_prm_init(PRM_OMAP5);
 	omap5xxx_check_revision();
 	omap54xx_voltagedomains_init();
@@ -696,12 +700,8 @@ void __init dra7xx_init_early(void)
 	omap2_set_globals_tap(-1, OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE));
 	omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
 				  OMAP2_L4_IO_ADDRESS(DRA7XX_CTRL_BASE));
-	omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE));
-	omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_AON_BASE),
-			     OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE));
 	omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
-	omap_prm_base_init();
-	omap_cm_base_init();
+	of_prcm_base_init();
 	omap44xx_prm_init(PRM_DRA7);
 	dra7xx_powerdomains_init();
 	dra7xx_clockdomains_init();
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index fb377e1..cc1e0d2 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -32,6 +32,7 @@
 #include <linux/power/omap/prm2xxx.h>
 #include <linux/power/omap/prm3xxx.h>
 #include <linux/power/omap/prm44xx.h>
+#include <linux/power/omap/cm44xx.h>
 
 #include <linux/power/omap/prm.h>
 #include <linux/power/omap/prcm-common.h>
@@ -468,18 +469,38 @@ int prm_unregister(struct prm_ll_data *pld)
 	return 0;
 }
 
-static struct of_device_id omap_prm_dt_match_table[] = {
-	{ .compatible = "ti,omap3-prm" },
-	{ .compatible = "ti,omap4-prm" },
-	{ .compatible = "ti,omap5-prm" },
-	{ .compatible = "ti,dra7-prm" },
-	{ }
+static const struct prcm_match_data prm_base_data = {
+	.flags = PRCM_REGISTER_CLOCKS,
+	.index = PRCM_CLK_MEMMAP_INDEX_PRM,
+};
+
+static const struct prcm_match_data prcm_base_data = {
+	.flags = 0,
+	.index = PRCM_CLK_MEMMAP_INDEX_PRM,
+};
+
+static const struct prcm_match_data scrm_base_data = {
+	.flags = PRCM_REGISTER_CLOCKS,
+	.index = PRCM_CLK_MEMMAP_INDEX_SCRM,
+};
+
+static const struct prcm_match_data omap3_prm_data = {
+	.flags = PRCM_REGISTER_CLOCKS,
+	.index = PRCM_CLK_MEMMAP_INDEX_PRM,
+	.offset = 0x800,
 };
 
-static struct of_device_id omap_prcm_dt_match_table[] = {
-	{ .compatible = "ti,am3-prcm" },
-	{ .compatible = "ti,am4-prcm" },
-	{ .compatible = "ti,omap2-prcm" },
+
+static struct of_device_id omap_prm_dt_match_table[] = {
+	{ .compatible = "ti,omap3-prm", .data = &omap3_prm_data },
+	{ .compatible = "ti,omap4-prm", .data = &prm_base_data },
+	{ .compatible = "ti,omap5-prm", .data = &prm_base_data },
+	{ .compatible = "ti,dra7-prm", .data = &prm_base_data },
+	{ .compatible = "ti,am3-prcm", .data = &prcm_base_data },
+	{ .compatible = "ti,am4-prcm", .data = &prcm_base_data },
+	{ .compatible = "ti,omap2-prcm", .data = &prcm_base_data },
+	{ .compatible = "ti,omap4-scrm", .data = &scrm_base_data },
+	{ .compatible = "ti,omap5-scrm", .data = &scrm_base_data },
 	{ }
 };
 
@@ -500,38 +521,66 @@ static struct ti_clk_ll_ops omap_clk_ll_ops = {
 	.clk_writel = prm_clk_writel,
 };
 
-static int prcm_memmap_index;
-
 int __init of_prcm_module_init(struct of_device_id *match_table)
 {
 	struct device_node *np;
-	void __iomem *mem;
+	const struct of_device_id *match;
+	const struct prcm_match_data *data;
 
 	ti_clk_ll_ops = &omap_clk_ll_ops;
 
-	for_each_matching_node(np, match_table) {
-		mem = of_iomap(np, 0);
-		clk_memmaps[prcm_memmap_index] = mem;
-		ti_dt_clk_init_provider(np, prcm_memmap_index);
+	for_each_matching_node_and_match(np, match_table, &match) {
+		data = match->data;
+		if (!(data->flags & PRCM_REGISTER_CLOCKS))
+			continue;
+		ti_dt_clk_init_provider(np, data->index);
 		ti_dt_clockdomains_setup(np);
-		prcm_memmap_index++;
 	}
 
 	return 0;
 }
 
-int __init of_prm_init(void)
+int __init of_prcm_init(void)
+{
+	int ret;
+
+	ret = of_prcm_module_init(omap_prm_dt_match_table);
+	ret |= of_cm_init();
+	return ret;
+}
+
+static int of_prm_base_init(void)
 {
-	return of_prcm_module_init(omap_prm_dt_match_table);
+	struct device_node *np;
+	const struct of_device_id *match;
+	const struct prcm_match_data *data;
+
+	for_each_matching_node_and_match(np, omap_prm_dt_match_table, &match) {
+		data = match->data;
+		if (clk_memmaps[data->index])
+			pr_warn("WARNING: multiple prcm compatible mods, %d\n",
+				data->index);
+
+		clk_memmaps[data->index] = of_iomap(np, 0);
+
+		if (data->index == PRCM_CLK_MEMMAP_INDEX_PRM)
+			prm_base = clk_memmaps[data->index] + data->offset;
+	}
+
+	return 0;
 }
 
-int __init of_prcm_init(void)
+
+int __init of_prcm_base_init(void)
 {
 	int ret;
 
-	ret = of_prm_init();
-	ret |= of_cm_init();
-	ret |= of_prcm_module_init(omap_prcm_dt_match_table);
+	ret = of_prm_base_init();
+	ret |= of_cm_base_init();
+	ret |= of_scrm_base_init();
+
+	omap_prm_base_init();
+	omap_cm_base_init();
 
 	return ret;
 }
diff --git a/include/linux/power/omap/prcm-common.h b/include/linux/power/omap/prcm-common.h
index 67143a2..b9cce23 100644
--- a/include/linux/power/omap/prcm-common.h
+++ b/include/linux/power/omap/prcm-common.h
@@ -519,6 +519,21 @@ struct omap_prcm_irq_setup {
 
 struct of_device_id;
 
+#define PRCM_REGISTER_CLOCKS			0x1
+
+struct prcm_match_data {
+	u32 flags;
+	u16 index;
+	u16 offset;
+};
+
+enum {
+	PRCM_CLK_MEMMAP_INDEX_PRM = 0,
+	PRCM_CLK_MEMMAP_INDEX_CM1,
+	PRCM_CLK_MEMMAP_INDEX_CM2,
+	PRCM_CLK_MEMMAP_INDEX_SCRM,
+};
+
 extern void __iomem *clk_memmaps[];
 
 void omap_prcm_irq_cleanup(void);
@@ -529,6 +544,9 @@ void omap_prcm_irq_complete(void);
 void omap_pcs_legacy_init(int irq, void (*rearm)(void));
 int of_prcm_module_init(struct of_device_id *match_table);
 int of_cm_init(void);
+int of_cm_base_init(void);
+int of_prcm_base_init(void);
+int of_scrm_base_init(void);
 
 # endif
 
-- 
1.7.9.5

[PATCH 53/55] ARM: OMAP4: CM: remove unnecessary cm*_44xx.h header files from core code

[Tero Kristo]

These are not needed for anything.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/cm44xx.c     |    2 --
 arch/arm/mach-omap2/cminst44xx.c |    2 --
 2 files changed, 4 deletions(-)

diff --git a/arch/arm/mach-omap2/cm44xx.c b/arch/arm/mach-omap2/cm44xx.c
index 506974b..14d8256 100644
--- a/arch/arm/mach-omap2/cm44xx.c
+++ b/arch/arm/mach-omap2/cm44xx.c
@@ -19,8 +19,6 @@
 #include <linux/io.h>
 
 #include <linux/power/omap/cm.h>
-#include "cm1_44xx.h"
-#include "cm2_44xx.h"
 
 /* CM1 hardware module low-level functions */
 
diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c
index 13c4e0b..3d0b8ae 100644
--- a/arch/arm/mach-omap2/cminst44xx.c
+++ b/arch/arm/mach-omap2/cminst44xx.c
@@ -24,8 +24,6 @@
 #include <linux/power/omap/prm.h>
 #include <linux/power/omap/clockdomain.h>
 #include <linux/power/omap/cm.h>
-#include "cm1_44xx.h"
-#include "cm2_44xx.h"
 #include <linux/power/omap/cm44xx.h>
 #include <linux/power/omap/prcm44xx.h>
 #include <linux/power/omap/prm44xx.h>
-- 
1.7.9.5

[PATCH 54/55] ARM: OMAP4: PRCM: move prcm_mpu_base definition to a public header

[Tero Kristo]

Needed from both PRCM core code and mach-omap2 board code. This gets
rid of need to include the prcm_mpu_44xx_54xx.h header to the PRCM
core code.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/cminst44xx.c         |    1 -
 arch/arm/mach-omap2/prcm_mpu_44xx_54xx.h |    2 --
 arch/arm/mach-omap2/prminst44xx.c        |    1 -
 include/linux/power/omap/prcm-common.h   |    1 +
 4 files changed, 1 insertion(+), 4 deletions(-)

diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c
index 3d0b8ae..875634b 100644
--- a/arch/arm/mach-omap2/cminst44xx.c
+++ b/arch/arm/mach-omap2/cminst44xx.c
@@ -27,7 +27,6 @@
 #include <linux/power/omap/cm44xx.h>
 #include <linux/power/omap/prcm44xx.h>
 #include <linux/power/omap/prm44xx.h>
-#include "prcm_mpu44xx.h"
 #include <linux/power/omap/prcm-common.h>
 
 #define OMAP4430_IDLEST_SHIFT		16
diff --git a/arch/arm/mach-omap2/prcm_mpu_44xx_54xx.h b/arch/arm/mach-omap2/prcm_mpu_44xx_54xx.h
index ca149e7..2b1c995 100644
--- a/arch/arm/mach-omap2/prcm_mpu_44xx_54xx.h
+++ b/arch/arm/mach-omap2/prcm_mpu_44xx_54xx.h
@@ -24,8 +24,6 @@
 #define __ARCH_ARM_MACH_OMAP2_PRCM_MPU_44XX_54XX_H
 
 #ifndef __ASSEMBLER__
-extern void __iomem *prcm_mpu_base;
-
 extern u32 omap4_prcm_mpu_read_inst_reg(s16 inst, u16 idx);
 extern void omap4_prcm_mpu_write_inst_reg(u32 val, s16 inst, u16 idx);
 extern u32 omap4_prcm_mpu_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst,
diff --git a/arch/arm/mach-omap2/prminst44xx.c b/arch/arm/mach-omap2/prminst44xx.c
index 5b7c17e..e97d877 100644
--- a/arch/arm/mach-omap2/prminst44xx.c
+++ b/arch/arm/mach-omap2/prminst44xx.c
@@ -22,7 +22,6 @@
 #include <linux/power/omap/prm54xx.h>
 #include <linux/power/omap/prm7xx.h>
 #include <linux/power/omap/prcm44xx.h>
-#include "prcm_mpu44xx.h"
 
 #define OMAP4430_RST_GLOBAL_WARM_SW_MASK		(1 << 0)
 
diff --git a/include/linux/power/omap/prcm-common.h b/include/linux/power/omap/prcm-common.h
index b9cce23..a881607 100644
--- a/include/linux/power/omap/prcm-common.h
+++ b/include/linux/power/omap/prcm-common.h
@@ -535,6 +535,7 @@ enum {
 };
 
 extern void __iomem *clk_memmaps[];
+extern void __iomem *prcm_mpu_base;
 
 void omap_prcm_irq_cleanup(void);
 int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup);
-- 
1.7.9.5

Re: [PATCH 00/55]: ARM: OMAP2+: PRCM move to drivers

[Nishanth Menon]

On 03/31/2014 10:15 AM, Tero Kristo wrote:
> Hi,
> 
> This set is continuation for the work started earlier to cleanup the CM/PRM
> and attempt to make it a separate driver. This set depends on these
> two sets:
> 
> CM/PRM cleanup set:
> http://marc.info/?l=linux-omap&m=139395000918201&w=2
> 
> OMAP2 clock DT set:
> http://comments.gmane.org/gmane.linux.ports.arm.omap/111257
> 
> This set is pretty huge but the patches can be applied in stages if need be.
> Anyway, it would be good to get some feedback whether the driver folder
> locations etc. are good, and whether the effort taken here will be enough
> to actually move the driver. Clockdomain / powerdomain code can also be
> moved easily under the drivers/power/omap folder (or someplace else if
> requested) once this set is in. Also, clockdomain / powerdomain data
> should be possible to convert to DT format or some sort of firmware
> blob once this is done.
> 
> Patch #55 in this set is pretty massive as it moves all the C files at
> the same time, this should probably be split up as multiple patches.
> 
> Testing branch pushed here (contains also the CM/PRM cleanup set and OMAP2
> clock DT conversion):
> 
> tree: https://github.com/t-kristo/linux-pm.git
> branch: 3.14-rc4-cm-prm-driver-v1
> 

Tested this branch after rebase to v3.14 final (needed a few manual
rebase fixes.. trivial ones)

major fail is around sdp2430 which fails to boot ->
with DEBUG_LL sdp2430 : http://slexy.org/raw/s2MRoxsaJH


kristo-3.14-cm-prm-driver-v1-omap2plus_defconfig
 1: am335x-evm:  Boot PASS: http://slexy.org/raw/s2YLPt80Ui
 2:  am335x-sk:  Boot PASS: http://slexy.org/raw/s21fyrFaCx
 3: am3517-evm:  Boot PASS: http://slexy.org/raw/s21lquhrjO
 4:  am37x-evm:  Boot PASS: http://slexy.org/raw/s2VAGZMV5L
 5: am43xx-epos:  Boot PASS: http://slexy.org/raw/s21vX0JPy6
 6: BeagleBoard-XM:  Boot PASS: http://slexy.org/raw/s2tfyxYceR
 7: beaglebone-black:  Boot PASS: http://slexy.org/raw/s2zQOfp9JM
 8: beaglebone:  Boot PASS: http://slexy.org/raw/s2K848ipJj
 9: DRA7xx-EVM:  Boot PASS: http://slexy.org/raw/s20OteG4I3
10: OMAP3430-Labrador(LDP):  Boot FAIL: http://slexy.org/raw/s21DupyTRc
^^ legacy behavior
11: pandaboard-es:  Boot PASS: http://slexy.org/raw/s21HMWU7XE
12:    sdp2430:  Boot FAIL: http://slexy.org/raw/s2ex7L8gYg
^^ regression
13:    sdp3430:  Boot PASS: http://slexy.org/raw/s21Xl1pQGp
14:    sdp4430:  Boot PASS: http://slexy.org/raw/s2oYwjOXu5
15: OMAP5432uEVM:  Boot PASS: http://slexy.org/raw/s20havbuwY
TOTAL = 15 boards, Booted Boards = 13, No Boot boards = 2

v3.14-omap2plus_defconfig
 1: am335x-evm:  Boot PASS: http://slexy.org/raw/s2fsTX7RLo
 2:  am335x-sk:  Boot PASS: http://slexy.org/raw/s204it5W7s
 3: am3517-evm:  Boot PASS: http://slexy.org/raw/s20RHMAlQk
 4:  am37x-evm:  Boot PASS: http://slexy.org/raw/s2y0jKiClC
 5: am43xx-epos:  Boot PASS: http://slexy.org/raw/s2094U1Iwa
 6: BeagleBoard-XM:  Boot PASS: http://slexy.org/raw/s2jfuRAl9n
 7: beaglebone-black:  Boot PASS: http://slexy.org/raw/s28LGuHny3
 8: beaglebone:  Boot PASS: http://slexy.org/raw/s2zSlZ6hbK
 9: DRA7xx-EVM:  Boot PASS: http://slexy.org/raw/s21IA9TS0U
10: OMAP3430-Labrador(LDP):  Boot FAIL: http://slexy.org/raw/s2ZKEdCt2g
^^ legacy behavior
11: pandaboard-es:  Boot PASS: http://slexy.org/raw/s2IJBjcuU1
12:    sdp2430:  Boot PASS: http://slexy.org/raw/s2YjBF8dq8
13:    sdp3430:  Boot PASS: http://slexy.org/raw/s22vE9i5W5
14:    sdp4430:  Boot PASS: http://slexy.org/raw/s2EIb4li37
15: OMAP5432uEVM:  Boot PASS: http://slexy.org/raw/s2hBJQyZ4M
TOTAL = 15 boards, Booted Boards = 14, No Boot boards = 1


-- 
Regards,
Nishanth Menon

Re: [PATCH 00/55]: ARM: OMAP2+: PRCM move to drivers

[Nishanth Menon]

On 03/31/2014 11:47 AM, Nishanth Menon wrote:
> On 03/31/2014 10:15 AM, Tero Kristo wrote:
>> Hi,
>>
>> This set is continuation for the work started earlier to cleanup the CM/PRM
>> and attempt to make it a separate driver. This set depends on these
>> two sets:
>>
>> CM/PRM cleanup set:
>> http://marc.info/?l=linux-omap&m=139395000918201&w=2
>>
>> OMAP2 clock DT set:
>> http://comments.gmane.org/gmane.linux.ports.arm.omap/111257
>>
>> This set is pretty huge but the patches can be applied in stages if need be.
>> Anyway, it would be good to get some feedback whether the driver folder
>> locations etc. are good, and whether the effort taken here will be enough
>> to actually move the driver. Clockdomain / powerdomain code can also be
>> moved easily under the drivers/power/omap folder (or someplace else if
>> requested) once this set is in. Also, clockdomain / powerdomain data
>> should be possible to convert to DT format or some sort of firmware
>> blob once this is done.
>>
>> Patch #55 in this set is pretty massive as it moves all the C files at
>> the same time, this should probably be split up as multiple patches.
>>
>> Testing branch pushed here (contains also the CM/PRM cleanup set and OMAP2
>> clock DT conversion):
>>
>> tree: https://github.com/t-kristo/linux-pm.git
>> branch: 3.14-rc4-cm-prm-driver-v1
>>
> 
> Tested this branch after rebase to v3.14 final (needed a few manual
> rebase fixes.. trivial ones)
> 
> major fail is around sdp2430 which fails to boot ->
> with DEBUG_LL sdp2430 : http://slexy.org/raw/s2MRoxsaJH
> 
> 
> kristo-3.14-cm-prm-driver-v1-omap2plus_defconfig
>  1: am335x-evm:  Boot PASS: http://slexy.org/raw/s2YLPt80Ui
>  2:  am335x-sk:  Boot PASS: http://slexy.org/raw/s21fyrFaCx
>  3: am3517-evm:  Boot PASS: http://slexy.org/raw/s21lquhrjO
>  4:  am37x-evm:  Boot PASS: http://slexy.org/raw/s2VAGZMV5L
>  5: am43xx-epos:  Boot PASS: http://slexy.org/raw/s21vX0JPy6
>  6: BeagleBoard-XM:  Boot PASS: http://slexy.org/raw/s2tfyxYceR
>  7: beaglebone-black:  Boot PASS: http://slexy.org/raw/s2zQOfp9JM
>  8: beaglebone:  Boot PASS: http://slexy.org/raw/s2K848ipJj
>  9: DRA7xx-EVM:  Boot PASS: http://slexy.org/raw/s20OteG4I3
> 10: OMAP3430-Labrador(LDP):  Boot FAIL: http://slexy.org/raw/s21DupyTRc
> ^^ legacy behavior
> 11: pandaboard-es:  Boot PASS: http://slexy.org/raw/s21HMWU7XE
> 12:    sdp2430:  Boot FAIL: http://slexy.org/raw/s2ex7L8gYg
> ^^ regression
> 13:    sdp3430:  Boot PASS: http://slexy.org/raw/s21Xl1pQGp
> 14:    sdp4430:  Boot PASS: http://slexy.org/raw/s2oYwjOXu5
> 15: OMAP5432uEVM:  Boot PASS: http://slexy.org/raw/s20havbuwY
> TOTAL = 15 boards, Booted Boards = 13, No Boot boards = 2
> 
> v3.14-omap2plus_defconfig
>  1: am335x-evm:  Boot PASS: http://slexy.org/raw/s2fsTX7RLo
>  2:  am335x-sk:  Boot PASS: http://slexy.org/raw/s204it5W7s
>  3: am3517-evm:  Boot PASS: http://slexy.org/raw/s20RHMAlQk
>  4:  am37x-evm:  Boot PASS: http://slexy.org/raw/s2y0jKiClC
>  5: am43xx-epos:  Boot PASS: http://slexy.org/raw/s2094U1Iwa
>  6: BeagleBoard-XM:  Boot PASS: http://slexy.org/raw/s2jfuRAl9n
>  7: beaglebone-black:  Boot PASS: http://slexy.org/raw/s28LGuHny3
>  8: beaglebone:  Boot PASS: http://slexy.org/raw/s2zSlZ6hbK
>  9: DRA7xx-EVM:  Boot PASS: http://slexy.org/raw/s21IA9TS0U
> 10: OMAP3430-Labrador(LDP):  Boot FAIL: http://slexy.org/raw/s2ZKEdCt2g
> ^^ legacy behavior
> 11: pandaboard-es:  Boot PASS: http://slexy.org/raw/s2IJBjcuU1
> 12:    sdp2430:  Boot PASS: http://slexy.org/raw/s2YjBF8dq8
> 13:    sdp3430:  Boot PASS: http://slexy.org/raw/s22vE9i5W5
> 14:    sdp4430:  Boot PASS: http://slexy.org/raw/s2EIb4li37
> 15: OMAP5432uEVM:  Boot PASS: http://slexy.org/raw/s2hBJQyZ4M
> TOTAL = 15 boards, Booted Boards = 14, No Boot boards = 1
> 
> 

and a kernel_patch_verify static check report:
http://slexy.org/view/s20MhigkXd

I think many of these could be squelched as well.

-- 
Regards,
Nishanth Menon

Re: [PATCH 00/55]: ARM: OMAP2+: PRCM move to drivers

[Felipe Balbi]

[-- Attachment #1: Type: text/plain, Size: 13208 bytes --]

Hi,

On Mon, Mar 31, 2014 at 06:15:39PM +0300, Tero Kristo wrote:
> This set is continuation for the work started earlier to cleanup the CM/PRM
> and attempt to make it a separate driver. This set depends on these
> two sets:
> 
> CM/PRM cleanup set:
> http://marc.info/?l=linux-omap&m=139395000918201&w=2
> 
> OMAP2 clock DT set:
> http://comments.gmane.org/gmane.linux.ports.arm.omap/111257
> 
> This set is pretty huge but the patches can be applied in stages if need be.
> Anyway, it would be good to get some feedback whether the driver folder
> locations etc. are good, and whether the effort taken here will be enough
> to actually move the driver. Clockdomain / powerdomain code can also be
> moved easily under the drivers/power/omap folder (or someplace else if
> requested) once this set is in. Also, clockdomain / powerdomain data
> should be possible to convert to DT format or some sort of firmware
> blob once this is done.
> 
> Patch #55 in this set is pretty massive as it moves all the C files at
> the same time, this should probably be split up as multiple patches.
> 
> Testing branch pushed here (contains also the CM/PRM cleanup set and OMAP2
> clock DT conversion):
> 
> tree: https://github.com/t-kristo/linux-pm.git
> branch: 3.14-rc4-cm-prm-driver-v1
> 
> Testing done:
> - am335x-bone: boot
> - omap3-beagle: boot, suspend-resume (ret/off)
> - omap4-panda-es: boot, suspend-resume (ret)
> - omap5-uevm: boot

150 randconfigs later, I finally have logs and here are all defconfigs
and stderr outputs of the failures only:

=== am33xx-multiplatform.config ===
randconfig0:
	defconfig: http://slexy.org/view/s2zdy5LV9u
	stderr: http://slexy.org/view/s2MDiGoSrx

randconfig1:
	defconfig: http://slexy.org/view/s2IxFfsaxf
	stderr: http://slexy.org/view/s20MnJB0bl

randconfig2:
	defconfig: http://slexy.org/view/s2BzbaASOq
	stderr: http://slexy.org/view/s20S65Pnj4

randconfig3:
	defconfig: http://slexy.org/view/s2Xd8cSZOH
	stderr: http://slexy.org/view/s20mf75wr0

randconfig5:
	defconfig: http://slexy.org/view/s21dZjiy5Z
	stderr: http://slexy.org/view/s2SAabweiD

randconfig6:
	defconfig: http://slexy.org/view/s20f02s9yf
	stderr: http://slexy.org/view/s2AMLLBc2c

randconfig7:
	defconfig: http://slexy.org/view/s21YMC7Fb1
	stderr: http://slexy.org/view/s21VmmcHu8

randconfig8:
	defconfig: http://slexy.org/view/s21NM3It3Z
	stderr: http://slexy.org/view/s2cg5YDZsA

randconfig9:
	defconfig: http://slexy.org/view/s2CqErrueL
	stderr: http://slexy.org/view/s21DCegKXO

=== am33xx-only.config ===
randconfig2:
	defconfig: http://slexy.org/view/s26Kuo34pl
	stderr: http://slexy.org/view/s20nQdrBf3

randconfig5:
	defconfig: http://slexy.org/view/s21kLO4EbJ
	stderr: http://slexy.org/view/s2MbA4q1PH

randconfig8:
	defconfig: http://slexy.org/view/s21xUPWCgh
	stderr: http://slexy.org/view/s2Mz889r6V

=== am43xx-multiplatform.config ===
randconfig0:
	defconfig: http://slexy.org/view/s20nOHwtyj
	stderr: http://slexy.org/view/s2PgUQG73h

randconfig1:
	defconfig: http://slexy.org/view/s2wBCQM0Wv
	stderr: http://slexy.org/view/s2sXSaLzRf

randconfig2:
	defconfig: http://slexy.org/view/s20JF7tNEv
	stderr: http://slexy.org/view/s2IFi7RDzV

randconfig4:
	defconfig: http://slexy.org/view/s21J5c88u0
	stderr: http://slexy.org/view/s2GuhgkwuI

randconfig5:
	defconfig: http://slexy.org/view/s20vRmugso
	stderr: http://slexy.org/view/s20AfVQszg

randconfig6:
	defconfig: http://slexy.org/view/s2nO7OZd9r
	stderr: http://slexy.org/view/s204vfoBIB

randconfig7:
	defconfig: http://slexy.org/view/s2k8I2YVI1
	stderr: http://slexy.org/view/s2wsGB0ubx

randconfig9:
	defconfig: http://slexy.org/view/s2u5ig7saX
	stderr: http://slexy.org/view/s28rVgHJFo

=== am43xx-only.config ===
randconfig0:
	defconfig: http://slexy.org/view/s2OVt1yfgy
	stderr: http://slexy.org/view/s22AU3Ex2p

randconfig1:
	defconfig: http://slexy.org/view/s25Gpu3Kr9
	stderr: http://slexy.org/view/s2uO3TnMDs

randconfig3:
	defconfig: http://slexy.org/view/s2Lf9Q5h9Q
	stderr: http://slexy.org/view/s2CRZMJAR9

randconfig6:
	defconfig: http://slexy.org/view/s21ncdem0O
	stderr: http://slexy.org/view/s20gzGaJcK

randconfig9:
	defconfig: http://slexy.org/view/s2UWL1gFqN
	stderr: http://slexy.org/view/s21S7zXfwh

=== dra7xx-multiplatform.config ===
randconfig0:
	defconfig: http://slexy.org/view/s20HNnv3Gf
	stderr: http://slexy.org/view/s21VztibKv

randconfig1:
	defconfig: http://slexy.org/view/s218qJ9E4x
	stderr: http://slexy.org/view/s2V28GPksP

randconfig2:
	defconfig: http://slexy.org/view/s2YcaCyUKS
	stderr: http://slexy.org/view/s20Mgzt8pa

randconfig3:
	defconfig: http://slexy.org/view/s20zE9a4dW
	stderr: http://slexy.org/view/s20Xy7r17N

randconfig4:
	defconfig: http://slexy.org/view/s21CUAW6Yz
	stderr: http://slexy.org/view/s20k6n5Gx8

randconfig5:
	defconfig: http://slexy.org/view/s21cLkzCHp
	stderr: http://slexy.org/view/s21JQfioUs

randconfig6:
	defconfig: http://slexy.org/view/s2EMvORY8U
	stderr: http://slexy.org/view/s20CetADJx

randconfig7:
	defconfig: http://slexy.org/view/s2JO5xHGgM
	stderr: http://slexy.org/view/s21sujleRC

randconfig9:
	defconfig: http://slexy.org/view/s2dz7jgBR4
	stderr: http://slexy.org/view/s20hqcdATY

=== dra7xx-only.config ===
randconfig3:
	defconfig: http://slexy.org/view/s20zRk0AZN
	stderr: http://slexy.org/view/s21G5p7LUQ

randconfig7:
	defconfig: http://slexy.org/view/s21FCqxaXM
	stderr: http://slexy.org/view/s278Tbgp9S

randconfig9:
	defconfig: http://slexy.org/view/s20Gfmk6lJ
	stderr: http://slexy.org/view/s20ehb1qwZ

=== omap1-only.config ===
randconfig0:
	defconfig: http://slexy.org/view/s2MUvMwOLs
	stderr: http://slexy.org/view/s2qZs1vTxV

randconfig1:
	defconfig: http://slexy.org/view/s27WloNxZM
	stderr: http://slexy.org/view/s2JWSJfmEd

randconfig2:
	defconfig: http://slexy.org/view/s21eKcaLyv
	stderr: http://slexy.org/view/s23rdJn5Z6

randconfig4:
	defconfig: http://slexy.org/view/s2jCoCS6bR
	stderr: http://slexy.org/view/s2BFCNCzGE

randconfig5:
	defconfig: http://slexy.org/view/s26ZOMTjY2
	stderr: http://slexy.org/view/s2tS8X3izE

randconfig7:
	defconfig: http://slexy.org/view/s20mS2BhrM
	stderr: http://slexy.org/view/s21ZhQjmyZ

=== omap2-multiplatform.config ===
randconfig0:
	defconfig: http://slexy.org/view/s206lY3Iu9
	stderr: http://slexy.org/view/s2VFufPUrS

randconfig1:
	defconfig: http://slexy.org/view/s2BmE32F7s
	stderr: http://slexy.org/view/s28siuKJgl

randconfig2:
	defconfig: http://slexy.org/view/s21wyH6vtV
	stderr: http://slexy.org/view/s2i5hb6R1s

randconfig3:
	defconfig: http://slexy.org/view/s211ydZ9zL
	stderr: http://slexy.org/view/s2TnjPod0j

randconfig4:
	defconfig: http://slexy.org/view/s2BKoNv98b
	stderr: http://slexy.org/view/s2VLHLTBcK

randconfig5:
	defconfig: http://slexy.org/view/s20TmPmPdE
	stderr: http://slexy.org/view/s2TNOe2h4l

randconfig6:
	defconfig: http://slexy.org/view/s2FFn9nUuj
	stderr: http://slexy.org/view/s2Ox6D9fnC

randconfig7:
	defconfig: http://slexy.org/view/s2CnsemL7b
	stderr: http://slexy.org/view/s206FpFZpJ

randconfig8:
	defconfig: http://slexy.org/view/s24W1I71zh
	stderr: http://slexy.org/view/s20TQftJBb

randconfig9:
	defconfig: http://slexy.org/view/s2I1F7c6TU
	stderr: http://slexy.org/view/s2mKIia8Sv

=== omap2-only.config ===
randconfig0:
	defconfig: http://slexy.org/view/s2dotWO9Ql
	stderr: http://slexy.org/view/s20hxmA4vX

randconfig1:
	defconfig: http://slexy.org/view/s2iRumb8dH
	stderr: http://slexy.org/view/s21Fw0XxqU

randconfig3:
	defconfig: http://slexy.org/view/s20QWVWG5i
	stderr: http://slexy.org/view/s21vyg1zop

randconfig4:
	defconfig: http://slexy.org/view/s21mGDCq51
	stderr: http://slexy.org/view/s20TIuj4IX

randconfig6:
	defconfig: http://slexy.org/view/s20sYfiX3d
	stderr: http://slexy.org/view/s20rPoepm3

randconfig7:
	defconfig: http://slexy.org/view/s2nvBuOuxW
	stderr: http://slexy.org/view/s20E0IdY6F

randconfig8:
	defconfig: http://slexy.org/view/s2N76xJ3X9
	stderr: http://slexy.org/view/s21VfZJhHV

randconfig9:
	defconfig: http://slexy.org/view/s2RV36kehk
	stderr: http://slexy.org/view/s2CTWr5Vpb

=== omap3-multiplatform.config ===
randconfig0:
	defconfig: http://slexy.org/view/s20VtHyvBH
	stderr: http://slexy.org/view/s2kBg5HvhD

randconfig1:
	defconfig: http://slexy.org/view/s20ypZW2Ko
	stderr: http://slexy.org/view/s21OUz1Xzn

randconfig2:
	defconfig: http://slexy.org/view/s21GjiKHkk
	stderr: http://slexy.org/view/s20asYuGKI

randconfig3:
	defconfig: http://slexy.org/view/s21O5wypd0
	stderr: http://slexy.org/view/s2IkuBLuZP

randconfig4:
	defconfig: http://slexy.org/view/s2ENuvZIYn
	stderr: http://slexy.org/view/s2S9qPIR0A

randconfig5:
	defconfig: http://slexy.org/view/s20nPLMlgQ
	stderr: http://slexy.org/view/s2m4JwHSM8

randconfig6:
	defconfig: http://slexy.org/view/s2DGcTkHkC
	stderr: http://slexy.org/view/s20AspBOww

randconfig7:
	defconfig: http://slexy.org/view/s20kCMwUU7
	stderr: http://slexy.org/view/s2z6D9QvQJ

randconfig8:
	defconfig: http://slexy.org/view/s20I1AOSQk
	stderr: http://slexy.org/view/s2q01zO9Iy

randconfig9:
	defconfig: http://slexy.org/view/s204fkNHxb
	stderr: http://slexy.org/view/s21qriyPF3

=== omap3-only.config ===
randconfig0:
	defconfig: http://slexy.org/view/s2abbP39Uk
	stderr: http://slexy.org/view/s29usoI8Nl

randconfig1:
	defconfig: http://slexy.org/view/s204hCXm6K
	stderr: http://slexy.org/view/s2kNZV9uAp

randconfig3:
	defconfig: http://slexy.org/view/s20vqEhTiO
	stderr: http://slexy.org/view/s205S2pZNA

randconfig6:
	defconfig: http://slexy.org/view/s20TycQLjY
	stderr: http://slexy.org/view/s20HC7hhns

randconfig7:
	defconfig: http://slexy.org/view/s2aw70jjPn
	stderr: http://slexy.org/view/s20isfqiL2

randconfig9:
	defconfig: http://slexy.org/view/s2MZFMURBn
	stderr: http://slexy.org/view/s2XoYqLhu9

=== omap4-multiplatform.config ===
randconfig0:
	defconfig: http://slexy.org/view/s2vidWfwTH
	stderr: http://slexy.org/view/s2HTOgfMmF

randconfig1:
	defconfig: http://slexy.org/view/s2Dt05nhkT
	stderr: http://slexy.org/view/s2Gj8YvAVs

randconfig2:
	defconfig: http://slexy.org/view/s25AhJw365
	stderr: http://slexy.org/view/s20beEPCwC

randconfig3:
	defconfig: http://slexy.org/view/s2dewbdjz7
	stderr: http://slexy.org/view/s20HGxzWpE

randconfig4:
	defconfig: http://slexy.org/view/s21WJUmCW0
	stderr: http://slexy.org/view/s2LRgFFbGA

randconfig5:
	defconfig: http://slexy.org/view/s2xGTl58jP
	stderr: http://slexy.org/view/s21aJCo6xK

randconfig6:
	defconfig: http://slexy.org/view/s20lpLX6Lu
	stderr: http://slexy.org/view/s21a4HxCyS

randconfig7:
	defconfig: http://slexy.org/view/s21AT1lTJf
	stderr: http://slexy.org/view/s21FaPb3xR

randconfig8:
	defconfig: http://slexy.org/view/s2CgY5DQQG
	stderr: http://slexy.org/view/s25VUF6wMD

randconfig9:
	defconfig: http://slexy.org/view/s2QiYHO40h
	stderr: http://slexy.org/view/s2t2wYKX0q

=== omap4-only.config ===
randconfig1:
	defconfig: http://slexy.org/view/s21qSK8EGJ
	stderr: http://slexy.org/view/s21srzKlAT

randconfig3:
	defconfig: http://slexy.org/view/s20QbcE067
	stderr: http://slexy.org/view/s27LksMVGl

randconfig5:
	defconfig: http://slexy.org/view/s21S8MLzbl
	stderr: http://slexy.org/view/s26IKp0DOJ

randconfig7:
	defconfig: http://slexy.org/view/s28VWw4Oh2
	stderr: http://slexy.org/view/s20RGLZjqY

randconfig8:
	defconfig: http://slexy.org/view/s2vwTsPqZa
	stderr: http://slexy.org/view/s21G96fSWU

=== omap5-multiplatform.config ===
randconfig0:
	defconfig: http://slexy.org/view/s20Bamou4U
	stderr: http://slexy.org/view/s208AsoX7s

randconfig1:
	defconfig: http://slexy.org/view/s21XKs3Q5G
	stderr: http://slexy.org/view/s21gtUSLml

randconfig2:
	defconfig: http://slexy.org/view/s2wvw3iOkG
	stderr: http://slexy.org/view/s208uF3SGG

randconfig3:
	defconfig: http://slexy.org/view/s2fagfl6tb
	stderr: http://slexy.org/view/s21YdRf46l

randconfig4:
	defconfig: http://slexy.org/view/s20eitFSpQ
	stderr: http://slexy.org/view/s21NNgKKun

randconfig5:
	defconfig: http://slexy.org/view/s2vmxZxslV
	stderr: http://slexy.org/view/s20u5IlZIL

randconfig6:
	defconfig: http://slexy.org/view/s23ba5vjtP
	stderr: http://slexy.org/view/s20KHhbgjO

randconfig7:
	defconfig: http://slexy.org/view/s2AiHp902I
	stderr: http://slexy.org/view/s2d2LK0QDi

randconfig8:
	defconfig: http://slexy.org/view/s2U1JNwOcK
	stderr: http://slexy.org/view/s2ftX1ECVO

randconfig9:
	defconfig: http://slexy.org/view/s2fqXgF0tG
	stderr: http://slexy.org/view/s21HrxjCq1

=== omap5-only.config ===
randconfig0:
	defconfig: http://slexy.org/view/s2hS1gplYB
	stderr: http://slexy.org/view/s20Zjhtbyz

randconfig2:
	defconfig: http://slexy.org/view/s2XMMPIHmK
	stderr: http://slexy.org/view/s22fG8VCFk

randconfig3:
	defconfig: http://slexy.org/view/s2LSrPTIho
	stderr: http://slexy.org/view/s20Zzv2Jb5

randconfig8:
	defconfig: http://slexy.org/view/s20ftaOa2H
	stderr: http://slexy.org/view/s21JmD1FZ3


-- 
balbi

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Re: [PATCH 00/55]: ARM: OMAP2+: PRCM move to drivers

[Tony Lindgren]

* Tero Kristo <t-kristo@ti.com> [140331 08:20]:
> Hi,
> 
> This set is continuation for the work started earlier to cleanup the CM/PRM
> and attempt to make it a separate driver. This set depends on these
> two sets:
> 
> CM/PRM cleanup set:
> http://marc.info/?l=linux-omap&m=139395000918201&w=2
> 
> OMAP2 clock DT set:
> http://comments.gmane.org/gmane.linux.ports.arm.omap/111257
> 
> This set is pretty huge but the patches can be applied in stages if need be.
> Anyway, it would be good to get some feedback whether the driver folder
> locations etc. are good, and whether the effort taken here will be enough
> to actually move the driver. Clockdomain / powerdomain code can also be
> moved easily under the drivers/power/omap folder (or someplace else if
> requested) once this set is in. Also, clockdomain / powerdomain data
> should be possible to convert to DT format or some sort of firmware
> blob once this is done.

Good to see this happening :)
 
> Patch #55 in this set is pretty massive as it moves all the C files at
> the same time, this should probably be split up as multiple patches.

Maybe try to break this series into few smaller sets of patches?

Then a diffstat with these kind of large patch sets would be nice
in the cover letter to get some kind of idea what's going on :)

Browsing through the set it seems that all the patches in this
series moving register defines "to a public location" are bad news.

We don't want to make access to these registers available without
proper frameworks as that will lead into misuse by various drivers.
And cleaning up that mess later in is a huge pain.

To avoid that, you can probably do something like this:

1. Set up the PRCM registers as multiple regmap areas

See for example these commits in linux next how one of the SCM misc
register areas is now available for drivers as tisyscon defined
in the .dts files:

11469e0bb1c5 regulator: add pbias regulator support
cd042fe5c1f6 ARM: dts: add pbias dt node

So basically we now have drivers/regulators/pbias-regulator.c
that claims some of the tisyscon registers and implements a
regulator. Then the MMC driver can just use the standard regulator
related functions.

It seems that you can set up multiple PRCM register ranges in a
similar way as regmap ranges and that way partition the PRCM
register areas to something that's private to individual drivers.

2. Have the core PRCM driver(s) claim some of the regmap ranges

Some PRCM features can potentially be implemented using existing
Linux generic frameworks where possible for clocks, regulators, reset
drivers etc. That way you can keep the register defines for these
ranges private to the core PRCM driver(s). Ideally with no need
to add _any_ custom exported functions here.

3. Have the other drivers claim some regmap ranges

The register ranges that are clearly owned by some driver should
be claimed by those drivers. Then the defines for those registers
can stay private to that driver. Some drivers that can probably
own some PRCM ranges are clock drivers and voltage related drivers.

Regards,

Tony

Re: [PATCH 00/55]: ARM: OMAP2+: PRCM move to drivers

[Tero Kristo]

On 04/01/2014 01:09 AM, Tony Lindgren wrote:
> * Tero Kristo <t-kristo@ti.com> [140331 08:20]:
>> Hi,
>>
>> This set is continuation for the work started earlier to cleanup the CM/PRM
>> and attempt to make it a separate driver. This set depends on these
>> two sets:
>>
>> CM/PRM cleanup set:
>> http://marc.info/?l=linux-omap&m=139395000918201&w=2
>>
>> OMAP2 clock DT set:
>> http://comments.gmane.org/gmane.linux.ports.arm.omap/111257
>>
>> This set is pretty huge but the patches can be applied in stages if need be.
>> Anyway, it would be good to get some feedback whether the driver folder
>> locations etc. are good, and whether the effort taken here will be enough
>> to actually move the driver. Clockdomain / powerdomain code can also be
>> moved easily under the drivers/power/omap folder (or someplace else if
>> requested) once this set is in. Also, clockdomain / powerdomain data
>> should be possible to convert to DT format or some sort of firmware
>> blob once this is done.
>
> Good to see this happening :)
>
>> Patch #55 in this set is pretty massive as it moves all the C files at
>> the same time, this should probably be split up as multiple patches.
>
> Maybe try to break this series into few smaller sets of patches?

Yes, this was the idea once getting the initial feedback for the 
approach itself. I will post smaller sets (split from this one) once the 
CM/PRM cleanup set referenced above gets in.

>
> Then a diffstat with these kind of large patch sets would be nice
> in the cover letter to get some kind of idea what's going on :)
>
> Browsing through the set it seems that all the patches in this
> series moving register defines "to a public location" are bad news.
>
> We don't want to make access to these registers available without
> proper frameworks as that will lead into misuse by various drivers.
> And cleaning up that mess later in is a huge pain.

Currently, only thing that requires access to the register offsets is 
basically all the legacy clock data still in the kernel (when can we get 
rid of this, I have posted patches for it already?) and also the 
clockdomain / powerdomain data. I can work on getting clockdomain + 
powerdomain data to DT format if this would be preferred, then we can 
remove these data files also. Alternatively I can just move all these 
defines to the C files which actually use them.

>
> To avoid that, you can probably do something like this:
>
> 1. Set up the PRCM registers as multiple regmap areas
>
> See for example these commits in linux next how one of the SCM misc
> register areas is now available for drivers as tisyscon defined
> in the .dts files:
>
> 11469e0bb1c5 regulator: add pbias regulator support
> cd042fe5c1f6 ARM: dts: add pbias dt node
>
> So basically we now have drivers/regulators/pbias-regulator.c
> that claims some of the tisyscon registers and implements a
> regulator. Then the MMC driver can just use the standard regulator
> related functions.
>
> It seems that you can set up multiple PRCM register ranges in a
> similar way as regmap ranges and that way partition the PRCM
> register areas to something that's private to individual drivers.

So, basically you are proposing to add a regmap or regmap like API for 
the PRCM, which would provide access to a subset of registers only 
outside the PRCM driver? Some functions provided by PRCM spawn to 
multiple registers (like clocks), and the ranges have holes, and would 
require finetuning a register / bit level access map (some registers may 
contain functions for several drivers.)

> 2. Have the core PRCM driver(s) claim some of the regmap ranges
>
> Some PRCM features can potentially be implemented using existing
> Linux generic frameworks where possible for clocks, regulators, reset
> drivers etc. That way you can keep the register defines for these
> ranges private to the core PRCM driver(s). Ideally with no need
> to add _any_ custom exported functions here.

There is separate work ongoing for reset driver, and for VC/VP, there 
has been some regulator related work. But yes, mostly this approach 
should be fine.

> 3. Have the other drivers claim some regmap ranges
>
> The register ranges that are clearly owned by some driver should
> be claimed by those drivers. Then the defines for those registers
> can stay private to that driver. Some drivers that can probably
> own some PRCM ranges are clock drivers and voltage related drivers.

Yeah, this sounds reasonable.

-Tero

Re: [PATCH 00/55]: ARM: OMAP2+: PRCM move to drivers

[Tony Lindgren]

* Tero Kristo <t-kristo@ti.com> [140401 01:38]:
> On 04/01/2014 01:09 AM, Tony Lindgren wrote:
> >
> >We don't want to make access to these registers available without
> >proper frameworks as that will lead into misuse by various drivers.
> >And cleaning up that mess later in is a huge pain.
> 
> Currently, only thing that requires access to the register offsets
> is basically all the legacy clock data still in the kernel (when can
> we get rid of this, I have posted patches for it already?) and also
> the clockdomain / powerdomain data. I can work on getting
> clockdomain + powerdomain data to DT format if this would be
> preferred, then we can remove these data files also. Alternatively I
> can just move all these defines to the C files which actually use
> them.

With display support getting merged hopefully we can retry
dropping omap3 legacy booting as long as we get the missing
boards working.

I don't know how urgent of an issue the clock and power domains
are for the data compared to clocks and muxes. But if it allows us
to easily add support for new SoC variants, then yes it makes sense.

But in any case the defines should be private to the code claiming
the PRCM register area.

> So, basically you are proposing to add a regmap or regmap like API
> for the PRCM, which would provide access to a subset of registers
> only outside the PRCM driver? Some functions provided by PRCM spawn
> to multiple registers (like clocks), and the ranges have holes, and
> would require finetuning a register / bit level access map (some
> registers may contain functions for several drivers.)

Yeah something like that as that allows implementing the Linux
generic frameworks where the code really should be. And does not
require exporting tons of custom functions.
 
> >2. Have the core PRCM driver(s) claim some of the regmap ranges
> >
> >Some PRCM features can potentially be implemented using existing
> >Linux generic frameworks where possible for clocks, regulators, reset
> >drivers etc. That way you can keep the register defines for these
> >ranges private to the core PRCM driver(s). Ideally with no need
> >to add _any_ custom exported functions here.
> 
> There is separate work ongoing for reset driver, and for VC/VP,
> there has been some regulator related work. But yes, mostly this
> approach should be fine.

OK cool.
 
> >3. Have the other drivers claim some regmap ranges
> >
> >The register ranges that are clearly owned by some driver should
> >be claimed by those drivers. Then the defines for those registers
> >can stay private to that driver. Some drivers that can probably
> >own some PRCM ranges are clock drivers and voltage related drivers.
> 
> Yeah, this sounds reasonable.

OK

Tony

Re: [PATCH 00/55]: ARM: OMAP2+: PRCM move to drivers

[Tero Kristo]

On 04/01/2014 08:13 PM, Tony Lindgren wrote:
> * Tero Kristo <t-kristo@ti.com> [140401 01:38]:
>> On 04/01/2014 01:09 AM, Tony Lindgren wrote:
>>>
>>> We don't want to make access to these registers available without
>>> proper frameworks as that will lead into misuse by various drivers.
>>> And cleaning up that mess later in is a huge pain.
>>
>> Currently, only thing that requires access to the register offsets
>> is basically all the legacy clock data still in the kernel (when can
>> we get rid of this, I have posted patches for it already?) and also
>> the clockdomain / powerdomain data. I can work on getting
>> clockdomain + powerdomain data to DT format if this would be
>> preferred, then we can remove these data files also. Alternatively I
>> can just move all these defines to the C files which actually use
>> them.
>
> With display support getting merged hopefully we can retry
> dropping omap3 legacy booting as long as we get the missing
> boards working.
>
> I don't know how urgent of an issue the clock and power domains
> are for the data compared to clocks and muxes. But if it allows us
> to easily add support for new SoC variants, then yes it makes sense.
>
> But in any case the defines should be private to the code claiming
> the PRCM register area.
>
>> So, basically you are proposing to add a regmap or regmap like API
>> for the PRCM, which would provide access to a subset of registers
>> only outside the PRCM driver? Some functions provided by PRCM spawn
>> to multiple registers (like clocks), and the ranges have holes, and
>> would require finetuning a register / bit level access map (some
>> registers may contain functions for several drivers.)
>
> Yeah something like that as that allows implementing the Linux
> generic frameworks where the code really should be. And does not
> require exporting tons of custom functions.
>
>>> 2. Have the core PRCM driver(s) claim some of the regmap ranges
>>>
>>> Some PRCM features can potentially be implemented using existing
>>> Linux generic frameworks where possible for clocks, regulators, reset
>>> drivers etc. That way you can keep the register defines for these
>>> ranges private to the core PRCM driver(s). Ideally with no need
>>> to add _any_ custom exported functions here.
>>
>> There is separate work ongoing for reset driver, and for VC/VP,
>> there has been some regulator related work. But yes, mostly this
>> approach should be fine.
>
> OK cool.
>
>>> 3. Have the other drivers claim some regmap ranges
>>>
>>> The register ranges that are clearly owned by some driver should
>>> be claimed by those drivers. Then the defines for those registers
>>> can stay private to that driver. Some drivers that can probably
>>> own some PRCM ranges are clock drivers and voltage related drivers.
>>
>> Yeah, this sounds reasonable.

Hi all,

Just letting you know, that I created a kind of v2 for this set, however 
I am not going to post it publicly before the pre-reqs for this set are 
covered, basically the OMAP2 clock DT set. CM/PRM cleanup set is 
outdated with this series though (I'll post a note on it separately) and 
its contents are merged to this latest re-work.

The latest wip branch is available publicly if someone is interested:

https://github.com/t-kristo/linux-pm/tree/3.14-rc4-cm-prm-driver-wip

I also added Tony's vc fixes set to this branch and removed the direct 
prm register accesses added there.

-Tero

Re: [PATCH 00/55]: ARM: OMAP2+: PRCM move to drivers

[Tony Lindgren]

* Tero Kristo <t-kristo@ti.com> [140412 03:25]:
> 
> Just letting you know, that I created a kind of v2 for this set,
> however I am not going to post it publicly before the pre-reqs for
> this set are covered, basically the OMAP2 clock DT set. CM/PRM
> cleanup set is outdated with this series though (I'll post a note on
> it separately) and its contents are merged to this latest re-work.
> 
> The latest wip branch is available publicly if someone is interested:
> 
> https://github.com/t-kristo/linux-pm/tree/3.14-rc4-cm-prm-driver-wip
> 
> I also added Tony's vc fixes set to this branch and removed the
> direct prm register accesses added there.

Well let's merge the fixes first. Sounds like the prm register access
changes for the vc can be merged already so care to post those
changes against v3.14 or v3.15-rc1 separately?

Regards,

Tony