* [PATCH] arm: dts: am43x-clock: add tbclk data for ehrpwm.
@ 2014-04-22 10:25 Sourav Poddar
2014-04-22 12:41 ` Tero Kristo
0 siblings, 1 reply; 7+ messages in thread
From: Sourav Poddar @ 2014-04-22 10:25 UTC (permalink / raw)
To: t-kristo, mturquette, tony, devicetree, linux-arm-kernel,
linux-omap, balbi
Cc: Sourav Poddar
We need "tblclk" clock data for the functioning of ehrpwm
module. Hence, populating the required clock information
in clock dts file.
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
---
arch/arm/boot/dts/am43xx-clocks.dtsi | 84 ++++++++++++++++++++++++++++++++++
drivers/clk/ti/clk-43xx.c | 6 +++
2 files changed, 90 insertions(+)
diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi
index 142009c..869f9a5 100644
--- a/arch/arm/boot/dts/am43xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am43xx-clocks.dtsi
@@ -87,6 +87,90 @@
clock-mult = <1>;
clock-div = <1>;
};
+
+ ehrpwm0_gate_tbclk: ehrpwm0_gate_tbclk {
+ #clock-cells = <0>;
+ compatible = "ti,composite-no-wait-gate-clock";
+ clocks = <&dpll_per_m2_ck>;
+ ti,bit-shift = <0>;
+ reg = <0x0664>;
+ };
+
+ ehrpwm0_tbclk: ehrpwm0_tbclk {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&ehrpwm0_gate_tbclk>;
+ };
+
+ ehrpwm1_gate_tbclk: ehrpwm1_gate_tbclk {
+ #clock-cells = <0>;
+ compatible = "ti,composite-no-wait-gate-clock";
+ clocks = <&dpll_per_m2_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x0664>;
+ };
+
+ ehrpwm1_tbclk: ehrpwm1_tbclk {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&ehrpwm1_gate_tbclk>;
+ };
+
+ ehrpwm2_gate_tbclk: ehrpwm2_gate_tbclk {
+ #clock-cells = <0>;
+ compatible = "ti,composite-no-wait-gate-clock";
+ clocks = <&dpll_per_m2_ck>;
+ ti,bit-shift = <2>;
+ reg = <0x0664>;
+ };
+
+ ehrpwm2_tbclk: ehrpwm2_tbclk {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&ehrpwm2_gate_tbclk>;
+ };
+
+ ehrpwm3_gate_tbclk: ehrpwm3_gate_tbclk {
+ #clock-cells = <0>;
+ compatible = "ti,composite-no-wait-gate-clock";
+ clocks = <&dpll_per_m2_ck>;
+ ti,bit-shift = <2>;
+ reg = <0x0664>;
+ };
+
+ ehrpwm3_tbclk: ehrpwm3_tbclk {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&ehrpwm3_gate_tbclk>;
+ };
+
+ ehrpwm4_gate_tbclk: ehrpwm4_gate_tbclk {
+ #clock-cells = <0>;
+ compatible = "ti,composite-no-wait-gate-clock";
+ clocks = <&dpll_per_m2_ck>;
+ ti,bit-shift = <2>;
+ reg = <0x0664>;
+ };
+
+ ehrpwm4_tbclk: ehrpwm4_tbclk {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&ehrpwm4_gate_tbclk>;
+ };
+
+ ehrpwm5_gate_tbclk: ehrpwm5_gate_tbclk {
+ #clock-cells = <0>;
+ compatible = "ti,composite-no-wait-gate-clock";
+ clocks = <&dpll_per_m2_ck>;
+ ti,bit-shift = <2>;
+ reg = <0x0664>;
+ };
+
+ ehrpwm5_tbclk: ehrpwm5_tbclk {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&ehrpwm5_gate_tbclk>;
+ };
};
&prcm_clocks {
clk_32768_ck: clk_32768_ck {
diff --git a/drivers/clk/ti/clk-43xx.c b/drivers/clk/ti/clk-43xx.c
index 67c8de5..5413a6a 100644
--- a/drivers/clk/ti/clk-43xx.c
+++ b/drivers/clk/ti/clk-43xx.c
@@ -105,6 +105,12 @@ static struct ti_dt_clk am43xx_clks[] = {
DT_CLK(NULL, "func_12m_clk", "func_12m_clk"),
DT_CLK(NULL, "vtp_clk_div", "vtp_clk_div"),
DT_CLK(NULL, "usbphy_32khz_clkmux", "usbphy_32khz_clkmux"),
+ DT_CLK("48300200.ehrpwm", "tbclk", "ehrpwm0_tbclk"),
+ DT_CLK("48302200.ehrpwm", "tbclk", "ehrpwm1_tbclk"),
+ DT_CLK("48304200.ehrpwm", "tbclk", "ehrpwm2_tbclk"),
+ DT_CLK("48306200.ehrpwm", "tbclk", "ehrpwm0_tbclk"),
+ DT_CLK("48308200.ehrpwm", "tbclk", "ehrpwm1_tbclk"),
+ DT_CLK("4830a200.ehrpwm", "tbclk", "ehrpwm2_tbclk"),
{ .node_name = NULL },
};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH] arm: dts: am43x-clock: add tbclk data for ehrpwm.
2014-04-22 10:25 [PATCH] arm: dts: am43x-clock: add tbclk data for ehrpwm Sourav Poddar
@ 2014-04-22 12:41 ` Tero Kristo
2014-04-25 5:42 ` sourav
0 siblings, 1 reply; 7+ messages in thread
From: Tero Kristo @ 2014-04-22 12:41 UTC (permalink / raw)
To: Sourav Poddar, mturquette, tony, devicetree, linux-arm-kernel,
linux-omap, balbi
On 04/22/2014 01:25 PM, Sourav Poddar wrote:
> We need "tblclk" clock data for the functioning of ehrpwm
> module. Hence, populating the required clock information
> in clock dts file.
>
> Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
> ---
> arch/arm/boot/dts/am43xx-clocks.dtsi | 84 ++++++++++++++++++++++++++++++++++
> drivers/clk/ti/clk-43xx.c | 6 +++
> 2 files changed, 90 insertions(+)
>
> diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi
> index 142009c..869f9a5 100644
> --- a/arch/arm/boot/dts/am43xx-clocks.dtsi
> +++ b/arch/arm/boot/dts/am43xx-clocks.dtsi
> @@ -87,6 +87,90 @@
> clock-mult = <1>;
> clock-div = <1>;
> };
> +
> + ehrpwm0_gate_tbclk: ehrpwm0_gate_tbclk {
> + #clock-cells = <0>;
> + compatible = "ti,composite-no-wait-gate-clock";
> + clocks = <&dpll_per_m2_ck>;
> + ti,bit-shift = <0>;
> + reg = <0x0664>;
> + };
> +
> + ehrpwm0_tbclk: ehrpwm0_tbclk {
> + #clock-cells = <0>;
> + compatible = "ti,composite-clock";
> + clocks = <&ehrpwm0_gate_tbclk>;
> + };
Why do you use composite-clock type here? I see only add one sub-clock
to the composite, thus the composite part is unused. How about using a
gate-clock type only? Same question applies for the rest of the patch also.
-Tero
> +
> + ehrpwm1_gate_tbclk: ehrpwm1_gate_tbclk {
> + #clock-cells = <0>;
> + compatible = "ti,composite-no-wait-gate-clock";
> + clocks = <&dpll_per_m2_ck>;
> + ti,bit-shift = <1>;
> + reg = <0x0664>;
> + };
> +
> + ehrpwm1_tbclk: ehrpwm1_tbclk {
> + #clock-cells = <0>;
> + compatible = "ti,composite-clock";
> + clocks = <&ehrpwm1_gate_tbclk>;
> + };
> +
> + ehrpwm2_gate_tbclk: ehrpwm2_gate_tbclk {
> + #clock-cells = <0>;
> + compatible = "ti,composite-no-wait-gate-clock";
> + clocks = <&dpll_per_m2_ck>;
> + ti,bit-shift = <2>;
> + reg = <0x0664>;
> + };
> +
> + ehrpwm2_tbclk: ehrpwm2_tbclk {
> + #clock-cells = <0>;
> + compatible = "ti,composite-clock";
> + clocks = <&ehrpwm2_gate_tbclk>;
> + };
> +
> + ehrpwm3_gate_tbclk: ehrpwm3_gate_tbclk {
> + #clock-cells = <0>;
> + compatible = "ti,composite-no-wait-gate-clock";
> + clocks = <&dpll_per_m2_ck>;
> + ti,bit-shift = <2>;
> + reg = <0x0664>;
> + };
> +
> + ehrpwm3_tbclk: ehrpwm3_tbclk {
> + #clock-cells = <0>;
> + compatible = "ti,composite-clock";
> + clocks = <&ehrpwm3_gate_tbclk>;
> + };
> +
> + ehrpwm4_gate_tbclk: ehrpwm4_gate_tbclk {
> + #clock-cells = <0>;
> + compatible = "ti,composite-no-wait-gate-clock";
> + clocks = <&dpll_per_m2_ck>;
> + ti,bit-shift = <2>;
> + reg = <0x0664>;
> + };
> +
> + ehrpwm4_tbclk: ehrpwm4_tbclk {
> + #clock-cells = <0>;
> + compatible = "ti,composite-clock";
> + clocks = <&ehrpwm4_gate_tbclk>;
> + };
> +
> + ehrpwm5_gate_tbclk: ehrpwm5_gate_tbclk {
> + #clock-cells = <0>;
> + compatible = "ti,composite-no-wait-gate-clock";
> + clocks = <&dpll_per_m2_ck>;
> + ti,bit-shift = <2>;
> + reg = <0x0664>;
> + };
> +
> + ehrpwm5_tbclk: ehrpwm5_tbclk {
> + #clock-cells = <0>;
> + compatible = "ti,composite-clock";
> + clocks = <&ehrpwm5_gate_tbclk>;
> + };
> };
> &prcm_clocks {
> clk_32768_ck: clk_32768_ck {
> diff --git a/drivers/clk/ti/clk-43xx.c b/drivers/clk/ti/clk-43xx.c
> index 67c8de5..5413a6a 100644
> --- a/drivers/clk/ti/clk-43xx.c
> +++ b/drivers/clk/ti/clk-43xx.c
> @@ -105,6 +105,12 @@ static struct ti_dt_clk am43xx_clks[] = {
> DT_CLK(NULL, "func_12m_clk", "func_12m_clk"),
> DT_CLK(NULL, "vtp_clk_div", "vtp_clk_div"),
> DT_CLK(NULL, "usbphy_32khz_clkmux", "usbphy_32khz_clkmux"),
> + DT_CLK("48300200.ehrpwm", "tbclk", "ehrpwm0_tbclk"),
> + DT_CLK("48302200.ehrpwm", "tbclk", "ehrpwm1_tbclk"),
> + DT_CLK("48304200.ehrpwm", "tbclk", "ehrpwm2_tbclk"),
> + DT_CLK("48306200.ehrpwm", "tbclk", "ehrpwm0_tbclk"),
> + DT_CLK("48308200.ehrpwm", "tbclk", "ehrpwm1_tbclk"),
> + DT_CLK("4830a200.ehrpwm", "tbclk", "ehrpwm2_tbclk"),
> { .node_name = NULL },
> };
>
>
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH] arm: dts: am43x-clock: add tbclk data for ehrpwm.
2014-04-22 12:41 ` Tero Kristo
@ 2014-04-25 5:42 ` sourav
2014-04-25 6:49 ` Tero Kristo
0 siblings, 1 reply; 7+ messages in thread
From: sourav @ 2014-04-25 5:42 UTC (permalink / raw)
To: Tero Kristo
Cc: mturquette, tony, devicetree, linux-arm-kernel, linux-omap, balbi
Hi Tero,
On Tuesday 22 April 2014 06:11 PM, Tero Kristo wrote:
> On 04/22/2014 01:25 PM, Sourav Poddar wrote:
>> We need "tblclk" clock data for the functioning of ehrpwm
>> module. Hence, populating the required clock information
>> in clock dts file.
>>
>> Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
>> ---
>> arch/arm/boot/dts/am43xx-clocks.dtsi | 84
>> ++++++++++++++++++++++++++++++++++
>> drivers/clk/ti/clk-43xx.c | 6 +++
>> 2 files changed, 90 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi
>> b/arch/arm/boot/dts/am43xx-clocks.dtsi
>> index 142009c..869f9a5 100644
>> --- a/arch/arm/boot/dts/am43xx-clocks.dtsi
>> +++ b/arch/arm/boot/dts/am43xx-clocks.dtsi
>> @@ -87,6 +87,90 @@
>> clock-mult = <1>;
>> clock-div = <1>;
>> };
>> +
>> + ehrpwm0_gate_tbclk: ehrpwm0_gate_tbclk {
>> + #clock-cells = <0>;
>> + compatible = "ti,composite-no-wait-gate-clock";
>> + clocks = <&dpll_per_m2_ck>;
>> + ti,bit-shift = <0>;
>> + reg = <0x0664>;
>> + };
>> +
>> + ehrpwm0_tbclk: ehrpwm0_tbclk {
>> + #clock-cells = <0>;
>> + compatible = "ti,composite-clock";
>> + clocks = <&ehrpwm0_gate_tbclk>;
>> + };
>
> Why do you use composite-clock type here? I see only add one sub-clock
> to the composite, thus the composite part is unused. How about using a
> gate-clock type only? Same question applies for the rest of the patch
> also.
>
Yes, I though of doing so and I think it should be fine to use
gate-clock only. I did this following the ehrpwm clock data in
"am33xx-clock.dtsi" file, where we use composite clock for ehrpwm. I
think it needs to be changed there also.?
-Sourav
> -Tero
>
>> +
>> + ehrpwm1_gate_tbclk: ehrpwm1_gate_tbclk {
>> + #clock-cells = <0>;
>> + compatible = "ti,composite-no-wait-gate-clock";
>> + clocks = <&dpll_per_m2_ck>;
>> + ti,bit-shift = <1>;
>> + reg = <0x0664>;
>> + };
>> +
>> + ehrpwm1_tbclk: ehrpwm1_tbclk {
>> + #clock-cells = <0>;
>> + compatible = "ti,composite-clock";
>> + clocks = <&ehrpwm1_gate_tbclk>;
>> + };
>> +
>> + ehrpwm2_gate_tbclk: ehrpwm2_gate_tbclk {
>> + #clock-cells = <0>;
>> + compatible = "ti,composite-no-wait-gate-clock";
>> + clocks = <&dpll_per_m2_ck>;
>> + ti,bit-shift = <2>;
>> + reg = <0x0664>;
>> + };
>> +
>> + ehrpwm2_tbclk: ehrpwm2_tbclk {
>> + #clock-cells = <0>;
>> + compatible = "ti,composite-clock";
>> + clocks = <&ehrpwm2_gate_tbclk>;
>> + };
>> +
>> + ehrpwm3_gate_tbclk: ehrpwm3_gate_tbclk {
>> + #clock-cells = <0>;
>> + compatible = "ti,composite-no-wait-gate-clock";
>> + clocks = <&dpll_per_m2_ck>;
>> + ti,bit-shift = <2>;
>> + reg = <0x0664>;
>> + };
>> +
>> + ehrpwm3_tbclk: ehrpwm3_tbclk {
>> + #clock-cells = <0>;
>> + compatible = "ti,composite-clock";
>> + clocks = <&ehrpwm3_gate_tbclk>;
>> + };
>> +
>> + ehrpwm4_gate_tbclk: ehrpwm4_gate_tbclk {
>> + #clock-cells = <0>;
>> + compatible = "ti,composite-no-wait-gate-clock";
>> + clocks = <&dpll_per_m2_ck>;
>> + ti,bit-shift = <2>;
>> + reg = <0x0664>;
>> + };
>> +
>> + ehrpwm4_tbclk: ehrpwm4_tbclk {
>> + #clock-cells = <0>;
>> + compatible = "ti,composite-clock";
>> + clocks = <&ehrpwm4_gate_tbclk>;
>> + };
>> +
>> + ehrpwm5_gate_tbclk: ehrpwm5_gate_tbclk {
>> + #clock-cells = <0>;
>> + compatible = "ti,composite-no-wait-gate-clock";
>> + clocks = <&dpll_per_m2_ck>;
>> + ti,bit-shift = <2>;
>> + reg = <0x0664>;
>> + };
>> +
>> + ehrpwm5_tbclk: ehrpwm5_tbclk {
>> + #clock-cells = <0>;
>> + compatible = "ti,composite-clock";
>> + clocks = <&ehrpwm5_gate_tbclk>;
>> + };
>> };
>> &prcm_clocks {
>> clk_32768_ck: clk_32768_ck {
>> diff --git a/drivers/clk/ti/clk-43xx.c b/drivers/clk/ti/clk-43xx.c
>> index 67c8de5..5413a6a 100644
>> --- a/drivers/clk/ti/clk-43xx.c
>> +++ b/drivers/clk/ti/clk-43xx.c
>> @@ -105,6 +105,12 @@ static struct ti_dt_clk am43xx_clks[] = {
>> DT_CLK(NULL, "func_12m_clk", "func_12m_clk"),
>> DT_CLK(NULL, "vtp_clk_div", "vtp_clk_div"),
>> DT_CLK(NULL, "usbphy_32khz_clkmux", "usbphy_32khz_clkmux"),
>> + DT_CLK("48300200.ehrpwm", "tbclk", "ehrpwm0_tbclk"),
>> + DT_CLK("48302200.ehrpwm", "tbclk", "ehrpwm1_tbclk"),
>> + DT_CLK("48304200.ehrpwm", "tbclk", "ehrpwm2_tbclk"),
>> + DT_CLK("48306200.ehrpwm", "tbclk", "ehrpwm0_tbclk"),
>> + DT_CLK("48308200.ehrpwm", "tbclk", "ehrpwm1_tbclk"),
>> + DT_CLK("4830a200.ehrpwm", "tbclk", "ehrpwm2_tbclk"),
>> { .node_name = NULL },
>> };
>>
>>
>
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH] arm: dts: am43x-clock: add tbclk data for ehrpwm.
2014-04-25 5:42 ` sourav
@ 2014-04-25 6:49 ` Tero Kristo
2014-04-25 6:51 ` sourav
0 siblings, 1 reply; 7+ messages in thread
From: Tero Kristo @ 2014-04-25 6:49 UTC (permalink / raw)
To: sourav; +Cc: mturquette, tony, devicetree, linux-arm-kernel, linux-omap, balbi
On 04/25/2014 08:42 AM, sourav wrote:
> Hi Tero,
>
> On Tuesday 22 April 2014 06:11 PM, Tero Kristo wrote:
>> On 04/22/2014 01:25 PM, Sourav Poddar wrote:
>>> We need "tblclk" clock data for the functioning of ehrpwm
>>> module. Hence, populating the required clock information
>>> in clock dts file.
>>>
>>> Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
>>> ---
>>> arch/arm/boot/dts/am43xx-clocks.dtsi | 84
>>> ++++++++++++++++++++++++++++++++++
>>> drivers/clk/ti/clk-43xx.c | 6 +++
>>> 2 files changed, 90 insertions(+)
>>>
>>> diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi
>>> b/arch/arm/boot/dts/am43xx-clocks.dtsi
>>> index 142009c..869f9a5 100644
>>> --- a/arch/arm/boot/dts/am43xx-clocks.dtsi
>>> +++ b/arch/arm/boot/dts/am43xx-clocks.dtsi
>>> @@ -87,6 +87,90 @@
>>> clock-mult = <1>;
>>> clock-div = <1>;
>>> };
>>> +
>>> + ehrpwm0_gate_tbclk: ehrpwm0_gate_tbclk {
>>> + #clock-cells = <0>;
>>> + compatible = "ti,composite-no-wait-gate-clock";
>>> + clocks = <&dpll_per_m2_ck>;
>>> + ti,bit-shift = <0>;
>>> + reg = <0x0664>;
>>> + };
>>> +
>>> + ehrpwm0_tbclk: ehrpwm0_tbclk {
>>> + #clock-cells = <0>;
>>> + compatible = "ti,composite-clock";
>>> + clocks = <&ehrpwm0_gate_tbclk>;
>>> + };
>>
>> Why do you use composite-clock type here? I see only add one sub-clock
>> to the composite, thus the composite part is unused. How about using a
>> gate-clock type only? Same question applies for the rest of the patch
>> also.
>>
>
> Yes, I though of doing so and I think it should be fine to use
> gate-clock only. I did this following the ehrpwm clock data in
> "am33xx-clock.dtsi" file, where we use composite clock for ehrpwm. I
> think it needs to be changed there also.?
Yeah, that seems to be a quirk that was generated by the automatic
conversion script, there is no reason for these being composite clocks
either.
-Tero
>
> -Sourav
>> -Tero
>>
>>> +
>>> + ehrpwm1_gate_tbclk: ehrpwm1_gate_tbclk {
>>> + #clock-cells = <0>;
>>> + compatible = "ti,composite-no-wait-gate-clock";
>>> + clocks = <&dpll_per_m2_ck>;
>>> + ti,bit-shift = <1>;
>>> + reg = <0x0664>;
>>> + };
>>> +
>>> + ehrpwm1_tbclk: ehrpwm1_tbclk {
>>> + #clock-cells = <0>;
>>> + compatible = "ti,composite-clock";
>>> + clocks = <&ehrpwm1_gate_tbclk>;
>>> + };
>>> +
>>> + ehrpwm2_gate_tbclk: ehrpwm2_gate_tbclk {
>>> + #clock-cells = <0>;
>>> + compatible = "ti,composite-no-wait-gate-clock";
>>> + clocks = <&dpll_per_m2_ck>;
>>> + ti,bit-shift = <2>;
>>> + reg = <0x0664>;
>>> + };
>>> +
>>> + ehrpwm2_tbclk: ehrpwm2_tbclk {
>>> + #clock-cells = <0>;
>>> + compatible = "ti,composite-clock";
>>> + clocks = <&ehrpwm2_gate_tbclk>;
>>> + };
>>> +
>>> + ehrpwm3_gate_tbclk: ehrpwm3_gate_tbclk {
>>> + #clock-cells = <0>;
>>> + compatible = "ti,composite-no-wait-gate-clock";
>>> + clocks = <&dpll_per_m2_ck>;
>>> + ti,bit-shift = <2>;
>>> + reg = <0x0664>;
>>> + };
>>> +
>>> + ehrpwm3_tbclk: ehrpwm3_tbclk {
>>> + #clock-cells = <0>;
>>> + compatible = "ti,composite-clock";
>>> + clocks = <&ehrpwm3_gate_tbclk>;
>>> + };
>>> +
>>> + ehrpwm4_gate_tbclk: ehrpwm4_gate_tbclk {
>>> + #clock-cells = <0>;
>>> + compatible = "ti,composite-no-wait-gate-clock";
>>> + clocks = <&dpll_per_m2_ck>;
>>> + ti,bit-shift = <2>;
>>> + reg = <0x0664>;
>>> + };
>>> +
>>> + ehrpwm4_tbclk: ehrpwm4_tbclk {
>>> + #clock-cells = <0>;
>>> + compatible = "ti,composite-clock";
>>> + clocks = <&ehrpwm4_gate_tbclk>;
>>> + };
>>> +
>>> + ehrpwm5_gate_tbclk: ehrpwm5_gate_tbclk {
>>> + #clock-cells = <0>;
>>> + compatible = "ti,composite-no-wait-gate-clock";
>>> + clocks = <&dpll_per_m2_ck>;
>>> + ti,bit-shift = <2>;
>>> + reg = <0x0664>;
>>> + };
>>> +
>>> + ehrpwm5_tbclk: ehrpwm5_tbclk {
>>> + #clock-cells = <0>;
>>> + compatible = "ti,composite-clock";
>>> + clocks = <&ehrpwm5_gate_tbclk>;
>>> + };
>>> };
>>> &prcm_clocks {
>>> clk_32768_ck: clk_32768_ck {
>>> diff --git a/drivers/clk/ti/clk-43xx.c b/drivers/clk/ti/clk-43xx.c
>>> index 67c8de5..5413a6a 100644
>>> --- a/drivers/clk/ti/clk-43xx.c
>>> +++ b/drivers/clk/ti/clk-43xx.c
>>> @@ -105,6 +105,12 @@ static struct ti_dt_clk am43xx_clks[] = {
>>> DT_CLK(NULL, "func_12m_clk", "func_12m_clk"),
>>> DT_CLK(NULL, "vtp_clk_div", "vtp_clk_div"),
>>> DT_CLK(NULL, "usbphy_32khz_clkmux", "usbphy_32khz_clkmux"),
>>> + DT_CLK("48300200.ehrpwm", "tbclk", "ehrpwm0_tbclk"),
>>> + DT_CLK("48302200.ehrpwm", "tbclk", "ehrpwm1_tbclk"),
>>> + DT_CLK("48304200.ehrpwm", "tbclk", "ehrpwm2_tbclk"),
>>> + DT_CLK("48306200.ehrpwm", "tbclk", "ehrpwm0_tbclk"),
>>> + DT_CLK("48308200.ehrpwm", "tbclk", "ehrpwm1_tbclk"),
>>> + DT_CLK("4830a200.ehrpwm", "tbclk", "ehrpwm2_tbclk"),
>>> { .node_name = NULL },
>>> };
>>>
>>>
>>
>
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH] arm: dts: am43x-clock: add tbclk data for ehrpwm.
2014-04-25 6:49 ` Tero Kristo
@ 2014-04-25 6:51 ` sourav
0 siblings, 0 replies; 7+ messages in thread
From: sourav @ 2014-04-25 6:51 UTC (permalink / raw)
To: Tero Kristo
Cc: mturquette, tony, devicetree, linux-arm-kernel, linux-omap, balbi
On Friday 25 April 2014 12:19 PM, Tero Kristo wrote:
> On 04/25/2014 08:42 AM, sourav wrote:
>> Hi Tero,
>>
>> On Tuesday 22 April 2014 06:11 PM, Tero Kristo wrote:
>>> On 04/22/2014 01:25 PM, Sourav Poddar wrote:
>>>> We need "tblclk" clock data for the functioning of ehrpwm
>>>> module. Hence, populating the required clock information
>>>> in clock dts file.
>>>>
>>>> Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
>>>> ---
>>>> arch/arm/boot/dts/am43xx-clocks.dtsi | 84
>>>> ++++++++++++++++++++++++++++++++++
>>>> drivers/clk/ti/clk-43xx.c | 6 +++
>>>> 2 files changed, 90 insertions(+)
>>>>
>>>> diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi
>>>> b/arch/arm/boot/dts/am43xx-clocks.dtsi
>>>> index 142009c..869f9a5 100644
>>>> --- a/arch/arm/boot/dts/am43xx-clocks.dtsi
>>>> +++ b/arch/arm/boot/dts/am43xx-clocks.dtsi
>>>> @@ -87,6 +87,90 @@
>>>> clock-mult = <1>;
>>>> clock-div = <1>;
>>>> };
>>>> +
>>>> + ehrpwm0_gate_tbclk: ehrpwm0_gate_tbclk {
>>>> + #clock-cells = <0>;
>>>> + compatible = "ti,composite-no-wait-gate-clock";
>>>> + clocks = <&dpll_per_m2_ck>;
>>>> + ti,bit-shift = <0>;
>>>> + reg = <0x0664>;
>>>> + };
>>>> +
>>>> + ehrpwm0_tbclk: ehrpwm0_tbclk {
>>>> + #clock-cells = <0>;
>>>> + compatible = "ti,composite-clock";
>>>> + clocks = <&ehrpwm0_gate_tbclk>;
>>>> + };
>>>
>>> Why do you use composite-clock type here? I see only add one sub-clock
>>> to the composite, thus the composite part is unused. How about using a
>>> gate-clock type only? Same question applies for the rest of the patch
>>> also.
>>>
>>
>> Yes, I though of doing so and I think it should be fine to use
>> gate-clock only. I did this following the ehrpwm clock data in
>> "am33xx-clock.dtsi" file, where we use composite clock for ehrpwm. I
>> think it needs to be changed there also.?
>
> Yeah, that seems to be a quirk that was generated by the automatic
> conversion script, there is no reason for these being composite clocks
> either.
OK, I will send the updated patch for both am33xx and am43xx devices.
Thanks,
Sourav
>
> -Tero
>
>>
>> -Sourav
>>> -Tero
>>>
>>>> +
>>>> + ehrpwm1_gate_tbclk: ehrpwm1_gate_tbclk {
>>>> + #clock-cells = <0>;
>>>> + compatible = "ti,composite-no-wait-gate-clock";
>>>> + clocks = <&dpll_per_m2_ck>;
>>>> + ti,bit-shift = <1>;
>>>> + reg = <0x0664>;
>>>> + };
>>>> +
>>>> + ehrpwm1_tbclk: ehrpwm1_tbclk {
>>>> + #clock-cells = <0>;
>>>> + compatible = "ti,composite-clock";
>>>> + clocks = <&ehrpwm1_gate_tbclk>;
>>>> + };
>>>> +
>>>> + ehrpwm2_gate_tbclk: ehrpwm2_gate_tbclk {
>>>> + #clock-cells = <0>;
>>>> + compatible = "ti,composite-no-wait-gate-clock";
>>>> + clocks = <&dpll_per_m2_ck>;
>>>> + ti,bit-shift = <2>;
>>>> + reg = <0x0664>;
>>>> + };
>>>> +
>>>> + ehrpwm2_tbclk: ehrpwm2_tbclk {
>>>> + #clock-cells = <0>;
>>>> + compatible = "ti,composite-clock";
>>>> + clocks = <&ehrpwm2_gate_tbclk>;
>>>> + };
>>>> +
>>>> + ehrpwm3_gate_tbclk: ehrpwm3_gate_tbclk {
>>>> + #clock-cells = <0>;
>>>> + compatible = "ti,composite-no-wait-gate-clock";
>>>> + clocks = <&dpll_per_m2_ck>;
>>>> + ti,bit-shift = <2>;
>>>> + reg = <0x0664>;
>>>> + };
>>>> +
>>>> + ehrpwm3_tbclk: ehrpwm3_tbclk {
>>>> + #clock-cells = <0>;
>>>> + compatible = "ti,composite-clock";
>>>> + clocks = <&ehrpwm3_gate_tbclk>;
>>>> + };
>>>> +
>>>> + ehrpwm4_gate_tbclk: ehrpwm4_gate_tbclk {
>>>> + #clock-cells = <0>;
>>>> + compatible = "ti,composite-no-wait-gate-clock";
>>>> + clocks = <&dpll_per_m2_ck>;
>>>> + ti,bit-shift = <2>;
>>>> + reg = <0x0664>;
>>>> + };
>>>> +
>>>> + ehrpwm4_tbclk: ehrpwm4_tbclk {
>>>> + #clock-cells = <0>;
>>>> + compatible = "ti,composite-clock";
>>>> + clocks = <&ehrpwm4_gate_tbclk>;
>>>> + };
>>>> +
>>>> + ehrpwm5_gate_tbclk: ehrpwm5_gate_tbclk {
>>>> + #clock-cells = <0>;
>>>> + compatible = "ti,composite-no-wait-gate-clock";
>>>> + clocks = <&dpll_per_m2_ck>;
>>>> + ti,bit-shift = <2>;
>>>> + reg = <0x0664>;
>>>> + };
>>>> +
>>>> + ehrpwm5_tbclk: ehrpwm5_tbclk {
>>>> + #clock-cells = <0>;
>>>> + compatible = "ti,composite-clock";
>>>> + clocks = <&ehrpwm5_gate_tbclk>;
>>>> + };
>>>> };
>>>> &prcm_clocks {
>>>> clk_32768_ck: clk_32768_ck {
>>>> diff --git a/drivers/clk/ti/clk-43xx.c b/drivers/clk/ti/clk-43xx.c
>>>> index 67c8de5..5413a6a 100644
>>>> --- a/drivers/clk/ti/clk-43xx.c
>>>> +++ b/drivers/clk/ti/clk-43xx.c
>>>> @@ -105,6 +105,12 @@ static struct ti_dt_clk am43xx_clks[] = {
>>>> DT_CLK(NULL, "func_12m_clk", "func_12m_clk"),
>>>> DT_CLK(NULL, "vtp_clk_div", "vtp_clk_div"),
>>>> DT_CLK(NULL, "usbphy_32khz_clkmux", "usbphy_32khz_clkmux"),
>>>> + DT_CLK("48300200.ehrpwm", "tbclk", "ehrpwm0_tbclk"),
>>>> + DT_CLK("48302200.ehrpwm", "tbclk", "ehrpwm1_tbclk"),
>>>> + DT_CLK("48304200.ehrpwm", "tbclk", "ehrpwm2_tbclk"),
>>>> + DT_CLK("48306200.ehrpwm", "tbclk", "ehrpwm0_tbclk"),
>>>> + DT_CLK("48308200.ehrpwm", "tbclk", "ehrpwm1_tbclk"),
>>>> + DT_CLK("4830a200.ehrpwm", "tbclk", "ehrpwm2_tbclk"),
>>>> { .node_name = NULL },
>>>> };
>>>>
>>>>
>>>
>>
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH] arm: dts: am43x-clock: add tbclk data for ehrpwm.
@ 2014-04-25 8:55 Sourav Poddar
2014-04-25 12:10 ` Tero Kristo
0 siblings, 1 reply; 7+ messages in thread
From: Sourav Poddar @ 2014-04-25 8:55 UTC (permalink / raw)
To: t-kristo, mturquette, tony, devicetree, linux-arm-kernel,
linux-omap, balbi
Cc: Sourav Poddar
We need "tbclk" clock data for the functioning of ehrpwm
module. Hence, populating the required clock information
in clock dts file.
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
---
arch/arm/boot/dts/am43xx-clocks.dtsi | 48 ++++++++++++++++++++++++++++++++++
drivers/clk/ti/clk-43xx.c | 6 +++++
2 files changed, 54 insertions(+)
diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi
index 142009c..54f68e8 100644
--- a/arch/arm/boot/dts/am43xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am43xx-clocks.dtsi
@@ -87,6 +87,54 @@
clock-mult = <1>;
clock-div = <1>;
};
+
+ ehrpwm0_tbclk: ehrpwm0_tbclk@44e10664 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&dpll_per_m2_ck>;
+ bit-shift = <0>;
+ reg = <0x44e10664 0x4>;
+ };
+
+ ehrpwm1_tbclk: ehrpwm1_tbclk@44e10664 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&dpll_per_m2_ck>;
+ bit-shift = <1>;
+ reg = <0x44e10664 0x4>;
+ };
+
+ ehrpwm2_tbclk: ehrpwm2_tbclk@44e10664 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&dpll_per_m2_ck>;
+ bit-shift = <2>;
+ reg = <0x44e10664 0x4>;
+ };
+
+ ehrpwm3_tbclk: ehrpwm3_tbclk@44e10664 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&dpll_per_m2_ck>;
+ bit-shift = <3>;
+ reg = <0x44e10664 0x4>;
+ };
+
+ ehrpwm4_tbclk: ehrpwm4_tbclk@44e10664 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&dpll_per_m2_ck>;
+ bit-shift = <4>;
+ reg = <0x44e10664 0x4>;
+ };
+
+ ehrpwm5_tbclk: ehrpwm5_tbclk@44e10664 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&dpll_per_m2_ck>;
+ bit-shift = <5>;
+ reg = <0x44e10664 0x4>;
+ };
};
&prcm_clocks {
clk_32768_ck: clk_32768_ck {
diff --git a/drivers/clk/ti/clk-43xx.c b/drivers/clk/ti/clk-43xx.c
index 67c8de5..527a43d 100644
--- a/drivers/clk/ti/clk-43xx.c
+++ b/drivers/clk/ti/clk-43xx.c
@@ -105,6 +105,12 @@ static struct ti_dt_clk am43xx_clks[] = {
DT_CLK(NULL, "func_12m_clk", "func_12m_clk"),
DT_CLK(NULL, "vtp_clk_div", "vtp_clk_div"),
DT_CLK(NULL, "usbphy_32khz_clkmux", "usbphy_32khz_clkmux"),
+ DT_CLK("48300200.ehrpwm", "tbclk", "ehrpwm0_tbclk"),
+ DT_CLK("48302200.ehrpwm", "tbclk", "ehrpwm1_tbclk"),
+ DT_CLK("48304200.ehrpwm", "tbclk", "ehrpwm2_tbclk"),
+ DT_CLK("48306200.ehrpwm", "tbclk", "ehrpwm3_tbclk"),
+ DT_CLK("48308200.ehrpwm", "tbclk", "ehrpwm4_tbclk"),
+ DT_CLK("4830a200.ehrpwm", "tbclk", "ehrpwm5_tbclk"),
{ .node_name = NULL },
};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH] arm: dts: am43x-clock: add tbclk data for ehrpwm.
2014-04-25 8:55 Sourav Poddar
@ 2014-04-25 12:10 ` Tero Kristo
0 siblings, 0 replies; 7+ messages in thread
From: Tero Kristo @ 2014-04-25 12:10 UTC (permalink / raw)
To: Sourav Poddar, mturquette, tony, devicetree, linux-arm-kernel,
linux-omap, balbi
On 04/25/2014 11:55 AM, Sourav Poddar wrote:
> We need "tbclk" clock data for the functioning of ehrpwm
> module. Hence, populating the required clock information
> in clock dts file.
>
> Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
> ---
> arch/arm/boot/dts/am43xx-clocks.dtsi | 48 ++++++++++++++++++++++++++++++++++
> drivers/clk/ti/clk-43xx.c | 6 +++++
> 2 files changed, 54 insertions(+)
>
> diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi
> index 142009c..54f68e8 100644
> --- a/arch/arm/boot/dts/am43xx-clocks.dtsi
> +++ b/arch/arm/boot/dts/am43xx-clocks.dtsi
> @@ -87,6 +87,54 @@
> clock-mult = <1>;
> clock-div = <1>;
> };
> +
> + ehrpwm0_tbclk: ehrpwm0_tbclk@44e10664 {
> + #clock-cells = <0>;
> + compatible = "gate-clock";
Should be ti,gate-clock.
> + clocks = <&dpll_per_m2_ck>;
> + bit-shift = <0>;
Should be ti,bit-shift.
> + reg = <0x44e10664 0x4>;
Should be reg = <0x664>. Mainline kernel uses offsets for clock data,
not absolute register addresses.
Similar comments for the rest of the patch.
-Tero
> + };
> +
> + ehrpwm1_tbclk: ehrpwm1_tbclk@44e10664 {
> + #clock-cells = <0>;
> + compatible = "gate-clock";
> + clocks = <&dpll_per_m2_ck>;
> + bit-shift = <1>;
> + reg = <0x44e10664 0x4>;
> + };
> +
> + ehrpwm2_tbclk: ehrpwm2_tbclk@44e10664 {
> + #clock-cells = <0>;
> + compatible = "gate-clock";
> + clocks = <&dpll_per_m2_ck>;
> + bit-shift = <2>;
> + reg = <0x44e10664 0x4>;
> + };
> +
> + ehrpwm3_tbclk: ehrpwm3_tbclk@44e10664 {
> + #clock-cells = <0>;
> + compatible = "gate-clock";
> + clocks = <&dpll_per_m2_ck>;
> + bit-shift = <3>;
> + reg = <0x44e10664 0x4>;
> + };
> +
> + ehrpwm4_tbclk: ehrpwm4_tbclk@44e10664 {
> + #clock-cells = <0>;
> + compatible = "gate-clock";
> + clocks = <&dpll_per_m2_ck>;
> + bit-shift = <4>;
> + reg = <0x44e10664 0x4>;
> + };
> +
> + ehrpwm5_tbclk: ehrpwm5_tbclk@44e10664 {
> + #clock-cells = <0>;
> + compatible = "gate-clock";
> + clocks = <&dpll_per_m2_ck>;
> + bit-shift = <5>;
> + reg = <0x44e10664 0x4>;
> + };
> };
> &prcm_clocks {
> clk_32768_ck: clk_32768_ck {
> diff --git a/drivers/clk/ti/clk-43xx.c b/drivers/clk/ti/clk-43xx.c
> index 67c8de5..527a43d 100644
> --- a/drivers/clk/ti/clk-43xx.c
> +++ b/drivers/clk/ti/clk-43xx.c
> @@ -105,6 +105,12 @@ static struct ti_dt_clk am43xx_clks[] = {
> DT_CLK(NULL, "func_12m_clk", "func_12m_clk"),
> DT_CLK(NULL, "vtp_clk_div", "vtp_clk_div"),
> DT_CLK(NULL, "usbphy_32khz_clkmux", "usbphy_32khz_clkmux"),
> + DT_CLK("48300200.ehrpwm", "tbclk", "ehrpwm0_tbclk"),
> + DT_CLK("48302200.ehrpwm", "tbclk", "ehrpwm1_tbclk"),
> + DT_CLK("48304200.ehrpwm", "tbclk", "ehrpwm2_tbclk"),
> + DT_CLK("48306200.ehrpwm", "tbclk", "ehrpwm3_tbclk"),
> + DT_CLK("48308200.ehrpwm", "tbclk", "ehrpwm4_tbclk"),
> + DT_CLK("4830a200.ehrpwm", "tbclk", "ehrpwm5_tbclk"),
> { .node_name = NULL },
> };
>
>
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2014-04-25 12:10 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
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2014-04-22 10:25 [PATCH] arm: dts: am43x-clock: add tbclk data for ehrpwm Sourav Poddar
2014-04-22 12:41 ` Tero Kristo
2014-04-25 5:42 ` sourav
2014-04-25 6:49 ` Tero Kristo
2014-04-25 6:51 ` sourav
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2014-04-25 8:55 Sourav Poddar
2014-04-25 12:10 ` Tero Kristo
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