From: Roger Quadros <rogerq@ti.com>
To: "Gupta, Pekon" <pekon@ti.com>,
Javier Martinez Canillas <javier@dowhile0.org>
Cc: Tony Lindgren <tony@atomide.com>,
Benoit Cousson <bcousson@baylibre.com>,
linux-omap <linux-omap@vger.kernel.org>,
Minal Shah <minalkshah@gmail.com>
Subject: Re: [PATCH v4 3/6] ARM: dts: dra7: add support for parallel NAND flash
Date: Wed, 14 May 2014 12:00:03 +0300 [thread overview]
Message-ID: <53733093.6000904@ti.com> (raw)
In-Reply-To: <53732896.6060109@ti.com>
On 05/14/2014 11:25 AM, Roger Quadros wrote:
> Hi Pekon,
>
> On 05/12/2014 12:05 PM, Gupta, Pekon wrote:
>>> From: Javier Martinez Canillas [mailto:javier@dowhile0.org]
>> [...]
>>
>>>> Newer platforms have upgraded version of GPMC engine which supports
>>>> BCH16 ECC scheme in hardware. Thus the GPMC address space was
>>>> expanded to include some extra registers required for BCH16 ECC [2].
>>>>
>>>>
>>>
>>> I see and did the GPMC register space became that big to need to map 8KB?
>>>
>>> Although the smallest unit for ioremap is PAGE_SIZE and using any of
>>> these reg sizes:
>>>
>>> reg = <0x6e000000 0x02d0>;
>>> reg = <0x6e000000 0x0400>;
>>> reg = <0x6e000000 0x1000>;
>>>
>>> in practice have the same effect, DTS should describe the hardware and
>>> not an implementation detail so I think that we should use only the
>>> register size that is defined in the TRM.
>>>
>> Yes, I agree with you.
>> I have fixed this in newer version of the patch and will be sending it soon.
>> But this series will only contain updates for new platforms with addition
>> of NAND node in DTS, so that this series is not stalled for any reason.
>> For fixing existing platform/boards DTS I'll send another series soon.
>>
>> For now, I'll use GPMC address-space size = 0x380 as it matches with
>> actual hardware and is working.
>
> How did you get 0x380?
>
> From DRA7 TRM, GPMC address range is 0x5000 0000 : 0x5000 02D0
> So the address-space size should be 0x2D4 (as last register@2D0 is 32-bits wide)
Sorry for the noise.
Just figured out that the register space is not numerically arranged in the TRM.
The last register is P GPMC_BCH_RESULT6_i
0x5000 0308 + (0x0000 0010 * i)
i = 0 to 7
So size should be 0x37C.
cheers,
-roger
>
> For the ELM module it should be 4KB i.e. 0x1000
>
> cheers,
> -roger
>
>>>>
>>>> [1] http://www.ti.com/lit/gpn/am3359 (Section 7.4 to 7.4.5)
>>>>
>>>> [2] http://www.ti.com/lit/gpn/am3359 (Section 7.1 to 7.1.5)
>>>> (Though the AM335x address space mentions 0x368 as last address,
>>>> it should be 0x378. I have raised documentation bug for it).
>>>>
>>>>
>>>> with regards, pekon
>>>
>>> Best regards,
>>> Javier
>>>
>>> [0]: http://lxr.free-electrons.com/source/arch/arm/mm/ioremap.c#L334
>> \x04�{.n�+�������+%��lzwm��b�맲��r��zX��\x1a&j���\x17��ܨ}���Ơz�&j:+v���\a����zZ+��+zf���h���~����i���z�\x1e�w���?����&�)ߢ^[f
>>
>
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next prev parent reply other threads:[~2014-05-14 9:00 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-05-09 20:46 [PATCH v4 3/6] ARM: dts: dra7: add support for parallel NAND flash Pekon Gupta
2014-05-09 20:46 ` [PATCH v4 4/6] ARM: dts: am43xx: fix starting offset of NAND.filesystem MTD partition Pekon Gupta
2014-05-10 17:02 ` Javier Martinez Canillas
2014-05-09 20:46 ` [PATCH v4 5/6] ARM: dts: am43x-epos-evm: fix reg and range property of GPMC NAND node Pekon Gupta
2014-05-13 17:32 ` Tony Lindgren
2014-05-09 20:46 ` [PATCH v4 6/6] ARM: dts: am335x-evm: " Pekon Gupta
2014-05-10 17:11 ` Javier Martinez Canillas
2014-05-12 19:44 ` Tony Lindgren
2014-05-10 17:57 ` [PATCH v4 3/6] ARM: dts: dra7: add support for parallel NAND flash Javier Martinez Canillas
2014-05-12 7:03 ` Gupta, Pekon
2014-05-12 8:49 ` Javier Martinez Canillas
2014-05-12 9:05 ` Gupta, Pekon
2014-05-12 9:08 ` Javier Martinez Canillas
2014-05-14 8:25 ` Roger Quadros
2014-05-14 8:47 ` Gupta, Pekon
2014-05-14 9:00 ` Roger Quadros [this message]
2014-05-14 9:09 ` Gupta, Pekon
2014-05-14 9:17 ` Roger Quadros
2014-05-14 9:23 ` Javier Martinez Canillas
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