* [PATCH 0/5] tps65917: Add support for for TPS65917 PMIC
@ 2014-05-26 9:56 Keerthy
2014-05-26 9:56 ` [PATCH 1/5] mfd: Add DT bindings for tps65917 PMIC Keerthy
` (4 more replies)
0 siblings, 5 replies; 13+ messages in thread
From: Keerthy @ 2014-05-26 9:56 UTC (permalink / raw)
To: linux-omap; +Cc: lgirdwood, broonie, linux-kernel, sameo, lee.jones, Keerthy
The TPS65917 chip is a power management IC for Portable Navigation Systems
and Tablet Computing devices. It contains the following components:
- Regulators.
- GPADC.
- Over Temperature warning and Shut down.
This patch series adds support for TPS65917 mfd device. At this time only
the regulator functionality is made available.
The closest drivers are PALMAS series drivers. Hence adapted palmas mfd
driver to support the tps65917 PMIC.
The register set for SMPSs and LDOs are changed and the ramp delay support
is also changed. Bit-field defenitions are changed.
Hence based on the PALMAS drivers and created a new driver
for regulator with code changes as required.
The patches are boot tested on DRA72-EVM.
Keerthy (5):
mfd: Add DT bindings for tps65917 PMIC
Regulators: Add TPS65917 Bindings
mfd: palmas: Add tps65917 specific definitions and enums
mfd: palmas: Add tps65917 support
regulator: tps65917: Add Regulator driver for tps65917 PMIC
Documentation/devicetree/bindings/mfd/palmas.txt | 2 +
.../bindings/regulator/tps65917-pmic.txt | 67 ++
drivers/mfd/palmas.c | 177 ++++-
drivers/regulator/Kconfig | 12 +
drivers/regulator/Makefile | 1 +
drivers/regulator/tps65917-regulator.c | 825 ++++++++++++++++++++
include/linux/mfd/palmas.h | 793 +++++++++++++++++++
7 files changed, 1872 insertions(+), 5 deletions(-)
create mode 100644 Documentation/devicetree/bindings/regulator/tps65917-pmic.txt
create mode 100644 drivers/regulator/tps65917-regulator.c
--
1.7.9.5
^ permalink raw reply [flat|nested] 13+ messages in thread* [PATCH 1/5] mfd: Add DT bindings for tps65917 PMIC 2014-05-26 9:56 [PATCH 0/5] tps65917: Add support for for TPS65917 PMIC Keerthy @ 2014-05-26 9:56 ` Keerthy 2014-05-26 9:56 ` [PATCH 2/5] Regulators: Add TPS65917 Bindings Keerthy ` (3 subsequent siblings) 4 siblings, 0 replies; 13+ messages in thread From: Keerthy @ 2014-05-26 9:56 UTC (permalink / raw) To: linux-omap; +Cc: lgirdwood, broonie, linux-kernel, sameo, lee.jones, Keerthy Add DT bindings for tps65917 PMIC. Signed-off-by: Keerthy <j-keerthy@ti.com> --- Documentation/devicetree/bindings/mfd/palmas.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/palmas.txt b/Documentation/devicetree/bindings/mfd/palmas.txt index e5f0f83..eda8989 100644 --- a/Documentation/devicetree/bindings/mfd/palmas.txt +++ b/Documentation/devicetree/bindings/mfd/palmas.txt @@ -6,6 +6,7 @@ twl6037 (palmas) tps65913 (palmas) tps65914 (palmas) tps659038 +tps65917 Required properties: - compatible : Should be from the list @@ -16,6 +17,7 @@ Required properties: ti,tps65914 ti,tps80036 ti,tps659038 + ti,tps65917 and also the generic series names ti,palmas - interrupt-controller : palmas has its own internal IRQs -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 2/5] Regulators: Add TPS65917 Bindings 2014-05-26 9:56 [PATCH 0/5] tps65917: Add support for for TPS65917 PMIC Keerthy 2014-05-26 9:56 ` [PATCH 1/5] mfd: Add DT bindings for tps65917 PMIC Keerthy @ 2014-05-26 9:56 ` Keerthy 2014-05-26 9:56 ` [PATCH 3/5] mfd: palmas: Add tps65917 specific definitions and enums Keerthy ` (2 subsequent siblings) 4 siblings, 0 replies; 13+ messages in thread From: Keerthy @ 2014-05-26 9:56 UTC (permalink / raw) To: linux-omap; +Cc: lgirdwood, broonie, linux-kernel, sameo, lee.jones, Keerthy Add TPS65917 Bindings. Signed-off-by: Keerthy <j-keerthy@ti.com> --- .../bindings/regulator/tps65917-pmic.txt | 67 ++++++++++++++++++++ 1 file changed, 67 insertions(+) create mode 100644 Documentation/devicetree/bindings/regulator/tps65917-pmic.txt diff --git a/Documentation/devicetree/bindings/regulator/tps65917-pmic.txt b/Documentation/devicetree/bindings/regulator/tps65917-pmic.txt new file mode 100644 index 0000000..96d1fb7 --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/tps65917-pmic.txt @@ -0,0 +1,67 @@ +* tps65917 regulator IP block devicetree bindings + +Required properties: +- compatible : Should be + ti,tps65917-pmic + +- interrupt-parent : The parent interrupt controller which is tps65917. +- interrupts : The interrupt number and the type which can be looked up here: + arch/arm/boot/dts/include/dt-bindings/interrupt-controller/irq.h +- interrupts-name: The names of the individual interrupts. + +Optional nodes: +- regulators : Must contain a sub-node per regulator from the list below. + Each sub-node should contain the constraints and initialization + information for that regulator. See regulator.txt for a + description of standard properties for these sub-nodes. + Additional custom properties are listed below. + + Optional sub-node properties: + ti,warm-reset - maintain voltage during warm reset(boolean) + ti,roof-floor - This takes as optional argument on platform supporting + the rail from desired external control. If there is no argument then + it will be assume that it is controlled by NSLEEP pin. + The valid value for external pins are: + ENABLE1 then 1, + ENABLE2 then 2 or + NSLEEP then 3. + ti,mode-sleep - mode to adopt in pmic sleep 0 - off, 1 - auto, + 2 - eco, 3 - forced pwm + ti,smps-range - OTP has the wrong range set for the hardware so override + 0 - low range, 1 - high range. + +- ti,system-power-controller: Telling whether or not this pmic is controlling + the system power. + +Example: + +#include <dt-bindings/interrupt-controller/irq.h> + +pmic { + compatible = "ti,tps65917-pmic"; + interrupt-parent = <&tps65917>; + interrupts = <14 IRQ_TYPE_NONE>; + interrupts-name = "short-irq"; + + ti,system-power-controller; + + regulators { + smps1_reg : smps1 { + regulator-name = "smps1"; + regulator-min-microvolt = < 600000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + ti,warm-reset; + ti,roof-floor = <1>; /* ENABLE1 control */ + ti,mode-sleep = <0>; + ti,smps-range = <1>; + }; + + ldo1_reg: ldo1 { + regulator-name = "ldo1"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + }; +}; -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 3/5] mfd: palmas: Add tps65917 specific definitions and enums 2014-05-26 9:56 [PATCH 0/5] tps65917: Add support for for TPS65917 PMIC Keerthy 2014-05-26 9:56 ` [PATCH 1/5] mfd: Add DT bindings for tps65917 PMIC Keerthy 2014-05-26 9:56 ` [PATCH 2/5] Regulators: Add TPS65917 Bindings Keerthy @ 2014-05-26 9:56 ` Keerthy 2014-05-27 8:41 ` Lee Jones 2014-05-26 9:56 ` [PATCH 4/5] mfd: palmas: Add tps65917 support Keerthy 2014-05-26 9:56 ` [PATCH 5/5] regulator: tps65917: Add Regulator driver for tps65917 PMIC Keerthy 4 siblings, 1 reply; 13+ messages in thread From: Keerthy @ 2014-05-26 9:56 UTC (permalink / raw) To: linux-omap; +Cc: lgirdwood, broonie, linux-kernel, sameo, lee.jones, Keerthy Add tps65917 specific definitions and enums. Signed-off-by: Keerthy <j-keerthy@ti.com> --- include/linux/mfd/palmas.h | 793 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 793 insertions(+) diff --git a/include/linux/mfd/palmas.h b/include/linux/mfd/palmas.h index ccbb21f..52a24a9 100644 --- a/include/linux/mfd/palmas.h +++ b/include/linux/mfd/palmas.h @@ -30,6 +30,8 @@ #define PALMAS_CHIP_ID 0xC035 #define PALMAS_CHIP_CHARGER_ID 0xC036 +#define TPS65917_RESERVED -1 + #define is_palmas(a) (((a) == PALMAS_CHIP_OLD_ID) || \ ((a) == PALMAS_CHIP_ID)) #define is_palmas_charger(a) ((a) == PALMAS_CHIP_CHARGER_ID) @@ -184,6 +186,27 @@ enum palmas_regulators { PALMAS_NUM_REGS, }; +enum tps65917_regulators { + /* SMPS regulators */ + TPS65917_REG_SMPS1, + TPS65917_REG_SMPS2, + TPS65917_REG_SMPS3, + TPS65917_REG_SMPS4, + TPS65917_REG_SMPS5, + /* LDO regulators */ + TPS65917_REG_LDO1, + TPS65917_REG_LDO2, + TPS65917_REG_LDO3, + TPS65917_REG_LDO4, + TPS65917_REG_LDO5, + TPS65917_REG_REGEN1, + TPS65917_REG_REGEN2, + TPS65917_REG_REGEN3, + + /* Total number of regulators */ + TPS65917_NUM_REGS, +}; + /* External controll signal name */ enum { PALMAS_EXT_CONTROL_ENABLE1 = 0x1, @@ -228,6 +251,24 @@ enum palmas_external_requestor_id { PALMAS_EXTERNAL_REQSTR_ID_MAX, }; +enum tps65917_external_requestor_id { + TPS65917_EXTERNAL_REQSTR_ID_REGEN1, + TPS65917_EXTERNAL_REQSTR_ID_REGEN2, + TPS65917_EXTERNAL_REQSTR_ID_REGEN3, + TPS65917_EXTERNAL_REQSTR_ID_SMPS1, + TPS65917_EXTERNAL_REQSTR_ID_SMPS2, + TPS65917_EXTERNAL_REQSTR_ID_SMPS3, + TPS65917_EXTERNAL_REQSTR_ID_SMPS4, + TPS65917_EXTERNAL_REQSTR_ID_SMPS5, + TPS65917_EXTERNAL_REQSTR_ID_LDO1, + TPS65917_EXTERNAL_REQSTR_ID_LDO2, + TPS65917_EXTERNAL_REQSTR_ID_LDO3, + TPS65917_EXTERNAL_REQSTR_ID_LDO4, + TPS65917_EXTERNAL_REQSTR_ID_LDO5, + /* Last entry */ + TPS65917_EXTERNAL_REQSTR_ID_MAX, +}; + struct palmas_pmic_platform_data { /* An array of pointers to regulator init data indexed by regulator * ID @@ -349,6 +390,48 @@ struct palmas_gpadc_result { #define PALMAS_MAX_CHANNELS 16 +/* Define the tps65917 IRQ numbers */ +enum tps65917_irqs { + /* INT1 registers */ + TPS65917_RESERVED1, + TPS65917_PWRON_IRQ, + TPS65917_LONG_PRESS_KEY_IRQ, + TPS65917_RESERVED2, + TPS65917_PWRDOWN_IRQ, + TPS65917_HOTDIE_IRQ, + TPS65917_VSYS_MON_IRQ, + TPS65917_RESERVED3, + /* INT2 registers */ + TPS65917_RESERVED4, + TPS65917_OTP_ERROR_IRQ, + TPS65917_WDT_IRQ, + TPS65917_RESERVED5, + TPS65917_RESET_IN_IRQ, + TPS65917_FSD_IRQ, + TPS65917_SHORT_IRQ, + TPS65917_RESERVED6, + /* INT3 registers */ + TPS65917_GPADC_AUTO_0_IRQ, + TPS65917_GPADC_AUTO_1_IRQ, + TPS65917_GPADC_EOC_SW_IRQ, + TPS65917_RESREVED6, + TPS65917_RESERVED7, + TPS65917_RESERVED8, + TPS65917_RESERVED9, + TPS65917_VBUS_IRQ, + /* INT4 registers */ + TPS65917_GPIO_0_IRQ, + TPS65917_GPIO_1_IRQ, + TPS65917_GPIO_2_IRQ, + TPS65917_GPIO_3_IRQ, + TPS65917_GPIO_4_IRQ, + TPS65917_GPIO_5_IRQ, + TPS65917_GPIO_6_IRQ, + TPS65917_RESERVED10, + /* Total Number IRQs */ + TPS65917_NUM_IRQ, +}; + /* Define the palmas IRQ numbers */ enum palmas_irqs { /* INT1 registers */ @@ -400,6 +483,7 @@ struct palmas_pmic { int smps123; int smps457; + int smps12; int range[PALMAS_REG_SMPS10_OUT1]; unsigned int ramp_delay[PALMAS_REG_SMPS10_OUT1]; @@ -2871,6 +2955,715 @@ enum usb_irq_events { #define PALMAS_GPADC_TRIM15 0x0E #define PALMAS_GPADC_TRIM16 0x0F +/* TPS65917 Interrupt registers */ + +/* Registers for function INTERRUPT */ +#define TPS65917_INT1_STATUS 0x00 +#define TPS65917_INT1_MASK 0x01 +#define TPS65917_INT1_LINE_STATE 0x02 +#define TPS65917_INT2_STATUS 0x05 +#define TPS65917_INT2_MASK 0x06 +#define TPS65917_INT2_LINE_STATE 0x07 +#define TPS65917_INT3_STATUS 0x0A +#define TPS65917_INT3_MASK 0x0B +#define TPS65917_INT3_LINE_STATE 0x0C +#define TPS65917_INT4_STATUS 0x0F +#define TPS65917_INT4_MASK 0x10 +#define TPS65917_INT4_LINE_STATE 0x11 +#define TPS65917_INT4_EDGE_DETECT1 0x12 +#define TPS65917_INT4_EDGE_DETECT2 0x13 +#define TPS65917_INT_CTRL 0x14 + +/* Bit definitions for INT1_STATUS */ +#define TPS65917_INT1_STATUS_VSYS_MON 0x40 +#define TPS65917_INT1_STATUS_VSYS_MON_SHIFT 0x06 +#define TPS65917_INT1_STATUS_HOTDIE 0x20 +#define TPS65917_INT1_STATUS_HOTDIE_SHIFT 0x05 +#define TPS65917_INT1_STATUS_PWRDOWN 0x10 +#define TPS65917_INT1_STATUS_PWRDOWN_SHIFT 0x04 +#define TPS65917_INT1_STATUS_LONG_PRESS_KEY 0x04 +#define TPS65917_INT1_STATUS_LONG_PRESS_KEY_SHIFT 0x02 +#define TPS65917_INT1_STATUS_PWRON 0x02 +#define TPS65917_INT1_STATUS_PWRON_SHIFT 0x01 + +/* Bit definitions for INT1_MASK */ +#define TPS65917_INT1_MASK_VSYS_MON 0x40 +#define TPS65917_INT1_MASK_VSYS_MON_SHIFT 0x06 +#define TPS65917_INT1_MASK_HOTDIE 0x20 +#define TPS65917_INT1_MASK_HOTDIE_SHIFT 0x05 +#define TPS65917_INT1_MASK_PWRDOWN 0x10 +#define TPS65917_INT1_MASK_PWRDOWN_SHIFT 0x04 +#define TPS65917_INT1_MASK_LONG_PRESS_KEY 0x04 +#define TPS65917_INT1_MASK_LONG_PRESS_KEY_SHIFT 0x02 +#define TPS65917_INT1_MASK_PWRON 0x02 +#define TPS65917_INT1_MASK_PWRON_SHIFT 0x01 + +/* Bit definitions for INT1_LINE_STATE */ +#define TPS65917_INT1_LINE_STATE_VSYS_MON 0x40 +#define TPS65917_INT1_LINE_STATE_VSYS_MON_SHIFT 0x06 +#define TPS65917_INT1_LINE_STATE_HOTDIE 0x20 +#define TPS65917_INT1_LINE_STATE_HOTDIE_SHIFT 0x05 +#define TPS65917_INT1_LINE_STATE_PWRDOWN 0x10 +#define TPS65917_INT1_LINE_STATE_PWRDOWN_SHIFT 0x04 +#define TPS65917_INT1_LINE_STATE_LONG_PRESS_KEY 0x04 +#define TPS65917_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT 0x02 +#define TPS65917_INT1_LINE_STATE_PWRON 0x02 +#define TPS65917_INT1_LINE_STATE_PWRON_SHIFT 0x01 + +/* Bit definitions for INT2_STATUS */ +#define TPS65917_INT2_STATUS_SHORT 0x40 +#define TPS65917_INT2_STATUS_SHORT_SHIFT 0x06 +#define TPS65917_INT2_STATUS_FSD 0x20 +#define TPS65917_INT2_STATUS_FSD_SHIFT 0x05 +#define TPS65917_INT2_STATUS_RESET_IN 0x10 +#define TPS65917_INT2_STATUS_RESET_IN_SHIFT 0x04 +#define TPS65917_INT2_STATUS_WDT 0x04 +#define TPS65917_INT2_STATUS_WDT_SHIFT 0x02 +#define TPS65917_INT2_STATUS_OTP_ERROR 0x02 +#define TPS65917_INT2_STATUS_OTP_ERROR_SHIFT 0x01 + +/* Bit definitions for INT2_MASK */ +#define TPS65917_INT2_MASK_SHORT 0x40 +#define TPS65917_INT2_MASK_SHORT_SHIFT 0x06 +#define TPS65917_INT2_MASK_FSD 0x20 +#define TPS65917_INT2_MASK_FSD_SHIFT 0x05 +#define TPS65917_INT2_MASK_RESET_IN 0x10 +#define TPS65917_INT2_MASK_RESET_IN_SHIFT 0x04 +#define TPS65917_INT2_MASK_WDT 0x04 +#define TPS65917_INT2_MASK_WDT_SHIFT 0x02 +#define TPS65917_INT2_MASK_OTP_ERROR_TIMER 0x02 +#define TPS65917_INT2_MASK_OTP_ERROR_SHIFT 0x01 + +/* Bit definitions for INT2_LINE_STATE */ +#define TPS65917_INT2_LINE_STATE_SHORT 0x40 +#define TPS65917_INT2_LINE_STATE_SHORT_SHIFT 0x06 +#define TPS65917_INT2_LINE_STATE_FSD 0x20 +#define TPS65917_INT2_LINE_STATE_FSD_SHIFT 0x05 +#define TPS65917_INT2_LINE_STATE_RESET_IN 0x10 +#define TPS65917_INT2_LINE_STATE_RESET_IN_SHIFT 0x04 +#define TPS65917_INT2_LINE_STATE_WDT 0x04 +#define TPS65917_INT2_LINE_STATE_WDT_SHIFT 0x02 +#define TPS65917_INT2_LINE_STATE_OTP_ERROR 0x02 +#define TPS65917_INT2_LINE_STATE_OTP_ERROR_SHIFT 0x01 + +/* Bit definitions for INT3_STATUS */ +#define TPS65917_INT3_STATUS_VBUS 0x80 +#define TPS65917_INT3_STATUS_VBUS_SHIFT 0x07 +#define TPS65917_INT3_STATUS_GPADC_EOC_SW 0x04 +#define TPS65917_INT3_STATUS_GPADC_EOC_SW_SHIFT 0x02 +#define TPS65917_INT3_STATUS_GPADC_AUTO_1 0x02 +#define TPS65917_INT3_STATUS_GPADC_AUTO_1_SHIFT 0x01 +#define TPS65917_INT3_STATUS_GPADC_AUTO_0 0x01 +#define TPS65917_INT3_STATUS_GPADC_AUTO_0_SHIFT 0x00 + +/* Bit definitions for INT3_MASK */ +#define TPS65917_INT3_MASK_VBUS 0x80 +#define TPS65917_INT3_MASK_VBUS_SHIFT 0x07 +#define TPS65917_INT3_MASK_GPADC_EOC_SW 0x04 +#define TPS65917_INT3_MASK_GPADC_EOC_SW_SHIFT 0x02 +#define TPS65917_INT3_MASK_GPADC_AUTO_1 0x02 +#define TPS65917_INT3_MASK_GPADC_AUTO_1_SHIFT 0x01 +#define TPS65917_INT3_MASK_GPADC_AUTO_0 0x01 +#define TPS65917_INT3_MASK_GPADC_AUTO_0_SHIFT 0x00 + +/* Bit definitions for INT3_LINE_STATE */ +#define TPS65917_INT3_LINE_STATE_VBUS 0x80 +#define TPS65917_INT3_LINE_STATE_VBUS_SHIFT 0x07 +#define TPS65917_INT3_LINE_STATE_GPADC_EOC_SW 0x04 +#define TPS65917_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT 0x02 +#define TPS65917_INT3_LINE_STATE_GPADC_AUTO_1 0x02 +#define TPS65917_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT 0x01 +#define TPS65917_INT3_LINE_STATE_GPADC_AUTO_0 0x01 +#define TPS65917_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT 0x00 + +/* Bit definitions for INT4_STATUS */ +#define TPS65917_INT4_STATUS_GPIO_6 0x40 +#define TPS65917_INT4_STATUS_GPIO_6_SHIFT 0x06 +#define TPS65917_INT4_STATUS_GPIO_5 0x20 +#define TPS65917_INT4_STATUS_GPIO_5_SHIFT 0x05 +#define TPS65917_INT4_STATUS_GPIO_4 0x10 +#define TPS65917_INT4_STATUS_GPIO_4_SHIFT 0x04 +#define TPS65917_INT4_STATUS_GPIO_3 0x08 +#define TPS65917_INT4_STATUS_GPIO_3_SHIFT 0x03 +#define TPS65917_INT4_STATUS_GPIO_2 0x04 +#define TPS65917_INT4_STATUS_GPIO_2_SHIFT 0x02 +#define TPS65917_INT4_STATUS_GPIO_1 0x02 +#define TPS65917_INT4_STATUS_GPIO_1_SHIFT 0x01 +#define TPS65917_INT4_STATUS_GPIO_0 0x01 +#define TPS65917_INT4_STATUS_GPIO_0_SHIFT 0x00 + +/* Bit definitions for INT4_MASK */ +#define TPS65917_INT4_MASK_GPIO_6 0x40 +#define TPS65917_INT4_MASK_GPIO_6_SHIFT 0x06 +#define TPS65917_INT4_MASK_GPIO_5 0x20 +#define TPS65917_INT4_MASK_GPIO_5_SHIFT 0x05 +#define TPS65917_INT4_MASK_GPIO_4 0x10 +#define TPS65917_INT4_MASK_GPIO_4_SHIFT 0x04 +#define TPS65917_INT4_MASK_GPIO_3 0x08 +#define TPS65917_INT4_MASK_GPIO_3_SHIFT 0x03 +#define TPS65917_INT4_MASK_GPIO_2 0x04 +#define TPS65917_INT4_MASK_GPIO_2_SHIFT 0x02 +#define TPS65917_INT4_MASK_GPIO_1 0x02 +#define TPS65917_INT4_MASK_GPIO_1_SHIFT 0x01 +#define TPS65917_INT4_MASK_GPIO_0 0x01 +#define TPS65917_INT4_MASK_GPIO_0_SHIFT 0x00 + +/* Bit definitions for INT4_LINE_STATE */ +#define TPS65917_INT4_LINE_STATE_GPIO_6 0x40 +#define TPS65917_INT4_LINE_STATE_GPIO_6_SHIFT 0x06 +#define TPS65917_INT4_LINE_STATE_GPIO_5 0x20 +#define TPS65917_INT4_LINE_STATE_GPIO_5_SHIFT 0x05 +#define TPS65917_INT4_LINE_STATE_GPIO_4 0x10 +#define TPS65917_INT4_LINE_STATE_GPIO_4_SHIFT 0x04 +#define TPS65917_INT4_LINE_STATE_GPIO_3 0x08 +#define TPS65917_INT4_LINE_STATE_GPIO_3_SHIFT 0x03 +#define TPS65917_INT4_LINE_STATE_GPIO_2 0x04 +#define TPS65917_INT4_LINE_STATE_GPIO_2_SHIFT 0x02 +#define TPS65917_INT4_LINE_STATE_GPIO_1 0x02 +#define TPS65917_INT4_LINE_STATE_GPIO_1_SHIFT 0x01 +#define TPS65917_INT4_LINE_STATE_GPIO_0 0x01 +#define TPS65917_INT4_LINE_STATE_GPIO_0_SHIFT 0x00 + +/* Bit definitions for INT4_EDGE_DETECT1 */ +#define TPS65917_INT4_EDGE_DETECT1_GPIO_3_RISING 0x80 +#define TPS65917_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT 0x07 +#define TPS65917_INT4_EDGE_DETECT1_GPIO_3_FALLING 0x40 +#define TPS65917_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT 0x06 +#define TPS65917_INT4_EDGE_DETECT1_GPIO_2_RISING 0x20 +#define TPS65917_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT 0x05 +#define TPS65917_INT4_EDGE_DETECT1_GPIO_2_FALLING 0x10 +#define TPS65917_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT 0x04 +#define TPS65917_INT4_EDGE_DETECT1_GPIO_1_RISING 0x08 +#define TPS65917_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT 0x03 +#define TPS65917_INT4_EDGE_DETECT1_GPIO_1_FALLING 0x04 +#define TPS65917_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT 0x02 +#define TPS65917_INT4_EDGE_DETECT1_GPIO_0_RISING 0x02 +#define TPS65917_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT 0x01 +#define TPS65917_INT4_EDGE_DETECT1_GPIO_0_FALLING 0x01 +#define TPS65917_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT 0x00 + +/* Bit definitions for INT4_EDGE_DETECT2 */ +#define TPS65917_INT4_EDGE_DETECT2_GPIO_6_RISING 0x20 +#define TPS65917_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT 0x05 +#define TPS65917_INT4_EDGE_DETECT2_GPIO_6_FALLING 0x10 +#define TPS65917_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT 0x04 +#define TPS65917_INT4_EDGE_DETECT2_GPIO_5_RISING 0x08 +#define TPS65917_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT 0x03 +#define TPS65917_INT4_EDGE_DETECT2_GPIO_5_FALLING 0x04 +#define TPS65917_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT 0x02 +#define TPS65917_INT4_EDGE_DETECT2_GPIO_4_RISING 0x02 +#define TPS65917_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT 0x01 +#define TPS65917_INT4_EDGE_DETECT2_GPIO_4_FALLING 0x01 +#define TPS65917_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT 0x00 + +/* Bit definitions for INT_CTRL */ +#define TPS65917_INT_CTRL_INT_PENDING 0x04 +#define TPS65917_INT_CTRL_INT_PENDING_SHIFT 0x02 +#define TPS65917_INT_CTRL_INT_CLEAR 0x01 +#define TPS65917_INT_CTRL_INT_CLEAR_SHIFT 0x00 + +/* TPS65917 SMPS Registers */ + +/* Registers for function SMPS */ +#define TPS65917_SMPS1_CTRL 0x00 +#define TPS65917_SMPS1_FORCE 0x02 +#define TPS65917_SMPS1_VOLTAGE 0x03 +#define TPS65917_SMPS2_CTRL 0x04 +#define TPS65917_SMPS2_FORCE 0x06 +#define TPS65917_SMPS2_VOLTAGE 0x07 +#define TPS65917_SMPS3_CTRL 0x0C +#define TPS65917_SMPS3_FORCE 0x0E +#define TPS65917_SMPS3_VOLTAGE 0x0F +#define TPS65917_SMPS4_CTRL 0x10 +#define TPS65917_SMPS4_VOLTAGE 0x13 +#define TPS65917_SMPS5_CTRL 0x18 +#define TPS65917_SMPS5_VOLTAGE 0x1B +#define TPS65917_SMPS_CTRL 0x24 +#define TPS65917_SMPS_PD_CTRL 0x25 +#define TPS65917_SMPS_THERMAL_EN 0x27 +#define TPS65917_SMPS_THERMAL_STATUS 0x28 +#define TPS65917_SMPS_SHORT_STATUS 0x29 +#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN 0x2A +#define TPS65917_SMPS_POWERGOOD_MASK1 0x2B +#define TPS65917_SMPS_POWERGOOD_MASK2 0x2C + +/* Bit definitions for SMPS1_CTRL */ +#define TPS65917_SMPS1_CTRL_WR_S 0x80 +#define TPS65917_SMPS1_CTRL_WR_S_SHIFT 0x07 +#define TPS65917_SMPS1_CTRL_ROOF_FLOOR_EN 0x40 +#define TPS65917_SMPS1_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 +#define TPS65917_SMPS1_CTRL_STATUS_MASK 0x30 +#define TPS65917_SMPS1_CTRL_STATUS_SHIFT 0x04 +#define TPS65917_SMPS1_CTRL_MODE_SLEEP_MASK 0x0C +#define TPS65917_SMPS1_CTRL_MODE_SLEEP_SHIFT 0x02 +#define TPS65917_SMPS1_CTRL_MODE_ACTIVE_MASK 0x03 +#define TPS65917_SMPS1_CTRL_MODE_ACTIVE_SHIFT 0x00 + +/* Bit definitions for SMPS1_FORCE */ +#define TPS65917_SMPS1_FORCE_CMD 0x80 +#define TPS65917_SMPS1_FORCE_CMD_SHIFT 0x07 +#define TPS65917_SMPS1_FORCE_VSEL_MASK 0x7F +#define TPS65917_SMPS1_FORCE_VSEL_SHIFT 0x00 + +/* Bit definitions for SMPS1_VOLTAGE */ +#define TPS65917_SMPS1_VOLTAGE_RANGE 0x80 +#define TPS65917_SMPS1_VOLTAGE_RANGE_SHIFT 0x07 +#define TPS65917_SMPS1_VOLTAGE_VSEL_MASK 0x7F +#define TPS65917_SMPS1_VOLTAGE_VSEL_SHIFT 0x00 + +/* Bit definitions for SMPS2_CTRL */ +#define TPS65917_SMPS2_CTRL_WR_S 0x80 +#define TPS65917_SMPS2_CTRL_WR_S_SHIFT 0x07 +#define TPS65917_SMPS2_CTRL_ROOF_FLOOR_EN 0x40 +#define TPS65917_SMPS2_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 +#define TPS65917_SMPS2_CTRL_STATUS_MASK 0x30 +#define TPS65917_SMPS2_CTRL_STATUS_SHIFT 0x04 +#define TPS65917_SMPS2_CTRL_MODE_SLEEP_MASK 0x0C +#define TPS65917_SMPS2_CTRL_MODE_SLEEP_SHIFT 0x02 +#define TPS65917_SMPS2_CTRL_MODE_ACTIVE_MASK 0x03 +#define TPS65917_SMPS2_CTRL_MODE_ACTIVE_SHIFT 0x00 + +/* Bit definitions for SMPS2_FORCE */ +#define TPS65917_SMPS2_FORCE_CMD 0x80 +#define TPS65917_SMPS2_FORCE_CMD_SHIFT 0x07 +#define TPS65917_SMPS2_FORCE_VSEL_MASK 0x7F +#define TPS65917_SMPS2_FORCE_VSEL_SHIFT 0x00 + +/* Bit definitions for SMPS2_VOLTAGE */ +#define TPS65917_SMPS2_VOLTAGE_RANGE 0x80 +#define TPS65917_SMPS2_VOLTAGE_RANGE_SHIFT 0x07 +#define TPS65917_SMPS2_VOLTAGE_VSEL_MASK 0x7F +#define TPS65917_SMPS2_VOLTAGE_VSEL_SHIFT 0x00 + +/* Bit definitions for SMPS3_CTRL */ +#define TPS65917_SMPS3_CTRL_WR_S 0x80 +#define TPS65917_SMPS3_CTRL_WR_S_SHIFT 0x07 +#define TPS65917_SMPS3_CTRL_ROOF_FLOOR_EN 0x40 +#define TPS65917_SMPS3_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 +#define TPS65917_SMPS3_CTRL_STATUS_MASK 0x30 +#define TPS65917_SMPS3_CTRL_STATUS_SHIFT 0x04 +#define TPS65917_SMPS3_CTRL_MODE_SLEEP_MASK 0x0C +#define TPS65917_SMPS3_CTRL_MODE_SLEEP_SHIFT 0x02 +#define TPS65917_SMPS3_CTRL_MODE_ACTIVE_MASK 0x03 +#define TPS65917_SMPS3_CTRL_MODE_ACTIVE_SHIFT 0x00 + +/* Bit definitions for SMPS3_FORCE */ +#define TPS65917_SMPS3_FORCE_CMD 0x80 +#define TPS65917_SMPS3_FORCE_CMD_SHIFT 0x07 +#define TPS65917_SMPS3_FORCE_VSEL_MASK 0x7F +#define TPS65917_SMPS3_FORCE_VSEL_SHIFT 0x00 + +/* Bit definitions for SMPS3_VOLTAGE */ +#define TPS65917_SMPS3_VOLTAGE_RANGE 0x80 +#define TPS65917_SMPS3_VOLTAGE_RANGE_SHIFT 0x07 +#define TPS65917_SMPS3_VOLTAGE_VSEL_MASK 0x7F +#define TPS65917_SMPS3_VOLTAGE_VSEL_SHIFT 0x00 + +/* Bit definitions for SMPS4_CTRL */ +#define TPS65917_SMPS4_CTRL_WR_S 0x80 +#define TPS65917_SMPS4_CTRL_WR_S_SHIFT 0x07 +#define TPS65917_SMPS4_CTRL_ROOF_FLOOR_EN 0x40 +#define TPS65917_SMPS4_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 +#define TPS65917_SMPS4_CTRL_STATUS_MASK 0x30 +#define TPS65917_SMPS4_CTRL_STATUS_SHIFT 0x04 +#define TPS65917_SMPS4_CTRL_MODE_SLEEP_MASK 0x0C +#define TPS65917_SMPS4_CTRL_MODE_SLEEP_SHIFT 0x02 +#define TPS65917_SMPS4_CTRL_MODE_ACTIVE_MASK 0x03 +#define TPS65917_SMPS4_CTRL_MODE_ACTIVE_SHIFT 0x00 + +/* Bit definitions for SMPS4_VOLTAGE */ +#define TPS65917_SMPS4_VOLTAGE_RANGE 0x80 +#define TPS65917_SMPS4_VOLTAGE_RANGE_SHIFT 0x07 +#define TPS65917_SMPS4_VOLTAGE_VSEL_MASK 0x7F +#define TPS65917_SMPS4_VOLTAGE_VSEL_SHIFT 0x00 + +/* Bit definitions for SMPS5_CTRL */ +#define TPS65917_SMPS5_CTRL_WR_S 0x80 +#define TPS65917_SMPS5_CTRL_WR_S_SHIFT 0x07 +#define TPS65917_SMPS5_CTRL_ROOF_FLOOR_EN 0x40 +#define TPS65917_SMPS5_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 +#define TPS65917_SMPS5_CTRL_STATUS_MASK 0x30 +#define TPS65917_SMPS5_CTRL_STATUS_SHIFT 0x04 +#define TPS65917_SMPS5_CTRL_MODE_SLEEP_MASK 0x0C +#define TPS65917_SMPS5_CTRL_MODE_SLEEP_SHIFT 0x02 +#define TPS65917_SMPS5_CTRL_MODE_ACTIVE_MASK 0x03 +#define TPS65917_SMPS5_CTRL_MODE_ACTIVE_SHIFT 0x00 + +/* Bit definitions for SMPS5_VOLTAGE */ +#define TPS65917_SMPS5_VOLTAGE_RANGE 0x80 +#define TPS65917_SMPS5_VOLTAGE_RANGE_SHIFT 0x07 +#define TPS65917_SMPS5_VOLTAGE_VSEL_MASK 0x7F +#define TPS65917_SMPS5_VOLTAGE_VSEL_SHIFT 0x00 + +/* Bit definitions for SMPS_CTRL */ +#define TPS65917_SMPS_CTRL_SMPS1_SMPS12_EN 0x10 +#define TPS65917_SMPS_CTRL_SMPS1_SMPS12_EN_SHIFT 0x04 +#define TPS65917_SMPS_CTRL_SMPS12_PHASE_CTRL 0x03 +#define TPS65917_SMPS_CTRL_SMPS12_PHASE_CTRL_SHIFT 0x00 + +/* Bit definitions for SMPS_PD_CTRL */ +#define TPS65917_SMPS_PD_CTRL_SMPS5 0x40 +#define TPS65917_SMPS_PD_CTRL_SMPS5_SHIFT 0x06 +#define TPS65917_SMPS_PD_CTRL_SMPS4 0x10 +#define TPS65917_SMPS_PD_CTRL_SMPS4_SHIFT 0x04 +#define TPS65917_SMPS_PD_CTRL_SMPS3 0x08 +#define TPS65917_SMPS_PD_CTRL_SMPS3_SHIFT 0x03 +#define TPS65917_SMPS_PD_CTRL_SMPS2 0x02 +#define TPS65917_SMPS_PD_CTRL_SMPS2_SHIFT 0x01 +#define TPS65917_SMPS_PD_CTRL_SMPS1 0x01 +#define TPS65917_SMPS_PD_CTRL_SMPS1_SHIFT 0x00 + +/* Bit definitions for SMPS_THERMAL_EN */ +#define TPS65917_SMPS_THERMAL_EN_SMPS5 0x40 +#define TPS65917_SMPS_THERMAL_EN_SMPS5_SHIFT 0x06 +#define TPS65917_SMPS_THERMAL_EN_SMPS3 0x08 +#define TPS65917_SMPS_THERMAL_EN_SMPS3_SHIFT 0x03 +#define TPS65917_SMPS_THERMAL_EN_SMPS12 0x01 +#define TPS65917_SMPS_THERMAL_EN_SMPS12_SHIFT 0x00 + +/* Bit definitions for SMPS_THERMAL_STATUS */ +#define TPS65917_SMPS_THERMAL_STATUS_SMPS5 0x40 +#define TPS65917_SMPS_THERMAL_STATUS_SMPS5_SHIFT 0x06 +#define TPS65917_SMPS_THERMAL_STATUS_SMPS3 0x08 +#define TPS65917_SMPS_THERMAL_STATUS_SMPS3_SHIFT 0x03 +#define TPS65917_SMPS_THERMAL_STATUS_SMPS12 0x01 +#define TPS65917_SMPS_THERMAL_STATUS_SMPS12_SHIFT 0x00 + +/* Bit definitions for SMPS_SHORT_STATUS */ +#define TPS65917_SMPS_SHORT_STATUS_SMPS5 0x40 +#define TPS65917_SMPS_SHORT_STATUS_SMPS5_SHIFT 0x06 +#define TPS65917_SMPS_SHORT_STATUS_SMPS4 0x10 +#define TPS65917_SMPS_SHORT_STATUS_SMPS4_SHIFT 0x04 +#define TPS65917_SMPS_SHORT_STATUS_SMPS3 0x08 +#define TPS65917_SMPS_SHORT_STATUS_SMPS3_SHIFT 0x03 +#define TPS65917_SMPS_SHORT_STATUS_SMPS2 0x02 +#define TPS65917_SMPS_SHORT_STATUS_SMPS2_SHIFT 0x01 +#define TPS65917_SMPS_SHORT_STATUS_SMPS1 0x01 +#define TPS65917_SMPS_SHORT_STATUS_SMPS1_SHIFT 0x00 + +/* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */ +#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS5 0x40 +#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS5_SHIFT 0x06 +#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS4 0x10 +#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS4_SHIFT 0x04 +#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3 0x08 +#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT 0x03 +#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS2 0x02 +#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS2_SHIFT 0x01 +#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS1 0x01 +#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS1_SHIFT 0x00 + +/* Bit definitions for SMPS_POWERGOOD_MASK1 */ +#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS5 0x40 +#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS5_SHIFT 0x06 +#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS4 0x10 +#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS4_SHIFT 0x04 +#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS3 0x08 +#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT 0x03 +#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS2 0x02 +#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS2_SHIFT 0x01 +#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS1 0x01 +#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS1_SHIFT 0x00 + +/* Bit definitions for SMPS_POWERGOOD_MASK2 */ +#define TPS65917_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT 0x80 +#define TPS65917_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT 0x07 +#define TPS65917_SMPS_POWERGOOD_MASK2_OVC_ALARM_SHIFT 0x10 +#define TPS65917_SMPS_POWERGOOD_MASK2_OVC_ALARM 0x04 + +/* Bit definitions for SMPS_PLL_CTRL */ + +#define TPS65917_SMPS_PLL_CTRL_PLL_EN_PLL_BYPASS_SHIFT 0x08 +#define TPS65917_SMPS_PLL_CTRL_PLL_PLL_EN_BYPASS 0x03 +#define TPS65917_SMPS_PLL_CTRL_PLL_PLL_BYPASS_CLK_SHIFT 0x04 +#define TPS65917_SMPS_PLL_CTRL_PLL_PLL_BYPASS_CLK 0x02 + +/* Registers for function LDO */ +#define TPS65917_LDO1_CTRL 0x00 +#define TPS65917_LDO1_VOLTAGE 0x01 +#define TPS65917_LDO2_CTRL 0x02 +#define TPS65917_LDO2_VOLTAGE 0x03 +#define TPS65917_LDO3_CTRL 0x04 +#define TPS65917_LDO3_VOLTAGE 0x05 +#define TPS65917_LDO4_CTRL 0x0E +#define TPS65917_LDO4_VOLTAGE 0x0F +#define TPS65917_LDO5_CTRL 0x12 +#define TPS65917_LDO5_VOLTAGE 0x13 +#define TPS65917_LDO_PD_CTRL1 0x1B +#define TPS65917_LDO_PD_CTRL2 0x1C +#define TPS65917_LDO_SHORT_STATUS1 0x1D +#define TPS65917_LDO_SHORT_STATUS2 0x1E +#define TPS65917_LDO_PD_CTRL3 0x2D +#define TPS65917_LDO_SHORT_STATUS3 0x2E + +/* Bit definitions for LDO1_CTRL */ +#define TPS65917_LDO1_CTRL_WR_S 0x80 +#define TPS65917_LDO1_CTRL_WR_S_SHIFT 0x07 +#define TPS65917_LDO1_CTRL_BYPASS_EN 0x40 +#define TPS65917_LDO1_CTRL_BYPASS_EN_SHIFT 0x06 +#define TPS65917_LDO1_CTRL_STATUS 0x10 +#define TPS65917_LDO1_CTRL_STATUS_SHIFT 0x04 +#define TPS65917_LDO1_CTRL_MODE_SLEEP 0x04 +#define TPS65917_LDO1_CTRL_MODE_SLEEP_SHIFT 0x02 +#define TPS65917_LDO1_CTRL_MODE_ACTIVE 0x01 +#define TPS65917_LDO1_CTRL_MODE_ACTIVE_SHIFT 0x00 + +/* Bit definitions for LDO1_VOLTAGE */ +#define TPS65917_LDO1_VOLTAGE_VSEL_MASK 0x2F +#define TPS65917_LDO1_VOLTAGE_VSEL_SHIFT 0x00 + +/* Bit definitions for LDO2_CTRL */ +#define TPS65917_LDO2_CTRL_WR_S 0x80 +#define TPS65917_LDO2_CTRL_WR_S_SHIFT 0x07 +#define TPS65917_LDO2_CTRL_BYPASS_EN 0x40 +#define TPS65917_LDO2_CTRL_BYPASS_EN_SHIFT 0x06 +#define TPS65917_LDO2_CTRL_STATUS 0x10 +#define TPS65917_LDO2_CTRL_STATUS_SHIFT 0x04 +#define TPS65917_LDO2_CTRL_MODE_SLEEP 0x04 +#define TPS65917_LDO2_CTRL_MODE_SLEEP_SHIFT 0x02 +#define TPS65917_LDO2_CTRL_MODE_ACTIVE 0x01 +#define TPS65917_LDO2_CTRL_MODE_ACTIVE_SHIFT 0x00 + +/* Bit definitions for LDO2_VOLTAGE */ +#define TPS65917_LDO2_VOLTAGE_VSEL_MASK 0x2F +#define TPS65917_LDO2_VOLTAGE_VSEL_SHIFT 0x00 + +/* Bit definitions for LDO3_CTRL */ +#define TPS65917_LDO3_CTRL_WR_S 0x80 +#define TPS65917_LDO3_CTRL_WR_S_SHIFT 0x07 +#define TPS65917_LDO3_CTRL_STATUS 0x10 +#define TPS65917_LDO3_CTRL_STATUS_SHIFT 0x04 +#define TPS65917_LDO3_CTRL_MODE_SLEEP 0x04 +#define TPS65917_LDO3_CTRL_MODE_SLEEP_SHIFT 0x02 +#define TPS65917_LDO3_CTRL_MODE_ACTIVE 0x01 +#define TPS65917_LDO3_CTRL_MODE_ACTIVE_SHIFT 0x00 + +/* Bit definitions for LDO3_VOLTAGE */ +#define TPS65917_LDO3_VOLTAGE_VSEL_MASK 0x2F +#define TPS65917_LDO3_VOLTAGE_VSEL_SHIFT 0x00 + +/* Bit definitions for LDO4_CTRL */ +#define TPS65917_LDO4_CTRL_WR_S 0x80 +#define TPS65917_LDO4_CTRL_WR_S_SHIFT 0x07 +#define TPS65917_LDO4_CTRL_STATUS 0x10 +#define TPS65917_LDO4_CTRL_STATUS_SHIFT 0x04 +#define TPS65917_LDO4_CTRL_MODE_SLEEP 0x04 +#define TPS65917_LDO4_CTRL_MODE_SLEEP_SHIFT 0x02 +#define TPS65917_LDO4_CTRL_MODE_ACTIVE 0x01 +#define TPS65917_LDO4_CTRL_MODE_ACTIVE_SHIFT 0x00 + +/* Bit definitions for LDO4_VOLTAGE */ +#define TPS65917_LDO4_VOLTAGE_VSEL_MASK 0x2F +#define TPS65917_LDO4_VOLTAGE_VSEL_SHIFT 0x00 + +/* Bit definitions for LDO5_CTRL */ +#define TPS65917_LDO5_CTRL_WR_S 0x80 +#define TPS65917_LDO5_CTRL_WR_S_SHIFT 0x07 +#define TPS65917_LDO5_CTRL_STATUS 0x10 +#define TPS65917_LDO5_CTRL_STATUS_SHIFT 0x04 +#define TPS65917_LDO5_CTRL_MODE_SLEEP 0x04 +#define TPS65917_LDO5_CTRL_MODE_SLEEP_SHIFT 0x02 +#define TPS65917_LDO5_CTRL_MODE_ACTIVE 0x01 +#define TPS65917_LDO5_CTRL_MODE_ACTIVE_SHIFT 0x00 + +/* Bit definitions for LDO5_VOLTAGE */ +#define TPS65917_LDO5_VOLTAGE_VSEL_MASK 0x2F +#define TPS65917_LDO5_VOLTAGE_VSEL_SHIFT 0x00 + +/* Bit definitions for LDO_PD_CTRL1 */ +#define TPS65917_LDO_PD_CTRL1_LDO4 0x80 +#define TPS65917_LDO_PD_CTRL1_LDO4_SHIFT 0x07 +#define TPS65917_LDO_PD_CTRL1_LDO2 0x02 +#define TPS65917_LDO_PD_CTRL1_LDO2_SHIFT 0x01 +#define TPS65917_LDO_PD_CTRL1_LDO1 0x01 +#define TPS65917_LDO_PD_CTRL1_LDO1_SHIFT 0x00 + +/* Bit definitions for LDO_PD_CTRL2 */ +#define TPS65917_LDO_PD_CTRL2_LDO3 0x04 +#define TPS65917_LDO_PD_CTRL2_LDO3_SHIFT 0x02 +#define TPS65917_LDO_PD_CTRL2_LDO5 0x02 +#define TPS65917_LDO_PD_CTRL2_LDO5_SHIFT 0x01 + +/* Bit definitions for LDO_PD_CTRL3 */ +#define TPS65917_LDO_PD_CTRL2_LDOVANA 0x80 +#define TPS65917_LDO_PD_CTRL2_LDOVANA_SHIFT 0x07 + +/* Bit definitions for LDO_SHORT_STATUS1 */ +#define TPS65917_LDO_SHORT_STATUS1_LDO4 0x80 +#define TPS65917_LDO_SHORT_STATUS1_LDO4_SHIFT 0x07 +#define TPS65917_LDO_SHORT_STATUS1_LDO2 0x02 +#define TPS65917_LDO_SHORT_STATUS1_LDO2_SHIFT 0x01 +#define TPS65917_LDO_SHORT_STATUS1_LDO1 0x01 +#define TPS65917_LDO_SHORT_STATUS1_LDO1_SHIFT 0x00 + +/* Bit definitions for LDO_SHORT_STATUS2 */ +#define TPS65917_LDO_SHORT_STATUS2_LDO3 0x04 +#define TPS65917_LDO_SHORT_STATUS2_LDO3_SHIFT 0x02 +#define TPS65917_LDO_SHORT_STATUS2_LDO5 0x02 +#define TPS65917_LDO_SHORT_STATUS2_LDO5_SHIFT 0x01 + +/* Bit definitions for LDO_SHORT_STATUS2 */ +#define TPS65917_LDO_SHORT_STATUS2_LDOVANA 0x80 +#define TPS65917_LDO_SHORT_STATUS2_LDOVANA_SHIFT 0x07 + +/* Bit definitions for REGEN1_CTRL */ +#define TPS65917_REGEN1_CTRL_STATUS 0x10 +#define TPS65917_REGEN1_CTRL_STATUS_SHIFT 0x04 +#define TPS65917_REGEN1_CTRL_MODE_SLEEP 0x04 +#define TPS65917_REGEN1_CTRL_MODE_SLEEP_SHIFT 0x02 +#define TPS65917_REGEN1_CTRL_MODE_ACTIVE 0x01 +#define TPS65917_REGEN1_CTRL_MODE_ACTIVE_SHIFT 0x00 + +/* Bit definitions for PLLEN_CTRL */ +#define TPS65917_PLLEN_CTRL_STATUS 0x10 +#define TPS65917_PLLEN_CTRL_STATUS_SHIFT 0x04 +#define TPS65917_PLLEN_CTRL_MODE_SLEEP 0x04 +#define TPS65917_PLLEN_CTRL_MODE_SLEEP_SHIFT 0x02 +#define TPS65917_PLLEN_CTRL_MODE_ACTIVE 0x01 +#define TPS65917_PLLEN_CTRL_MODE_ACTIVE_SHIFT 0x00 + +/* Bit definitions for REGEN2_CTRL */ +#define TPS65917_REGEN2_CTRL_STATUS 0x10 +#define TPS65917_REGEN2_CTRL_STATUS_SHIFT 0x04 +#define TPS65917_REGEN2_CTRL_MODE_SLEEP 0x04 +#define TPS65917_REGEN2_CTRL_MODE_SLEEP_SHIFT 0x02 +#define TPS65917_REGEN2_CTRL_MODE_ACTIVE 0x01 +#define TPS65917_REGEN2_CTRL_MODE_ACTIVE_SHIFT 0x00 + +/* Bit definitions for NSLEEP_RES_ASSIGN */ +#define TPS65917_NSLEEP_RES_ASSIGN_PLL_EN 0x08 +#define TPS65917_NSLEEP_RES_ASSIGN_PLL_EN_SHIFT 0x03 +#define TPS65917_NSLEEP_RES_ASSIGN_REGEN3 0x04 +#define TPS65917_NSLEEP_RES_ASSIGN_REGEN3_SHIFT 0x02 +#define TPS65917_NSLEEP_RES_ASSIGN_REGEN2 0x02 +#define TPS65917_NSLEEP_RES_ASSIGN_REGEN2_SHIFT 0x01 +#define TPS65917_NSLEEP_RES_ASSIGN_REGEN1 0x01 +#define TPS65917_NSLEEP_RES_ASSIGN_REGEN1_SHIFT 0x00 + +/* Bit definitions for NSLEEP_SMPS_ASSIGN */ +#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS5 0x40 +#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS5_SHIFT 0x06 +#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS4 0x10 +#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS4_SHIFT 0x04 +#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS3 0x08 +#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT 0x03 +#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS2 0x02 +#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS2_SHIFT 0x01 +#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS1 0x01 +#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS1_SHIFT 0x00 + +/* Bit definitions for NSLEEP_LDO_ASSIGN1 */ +#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO4 0x80 +#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT 0x07 +#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO2 0x02 +#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT 0x01 +#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO1 0x01 +#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT 0x00 + +/* Bit definitions for NSLEEP_LDO_ASSIGN2 */ +#define TPS65917_NSLEEP_LDO_ASSIGN2_LDO3 0x04 +#define TPS65917_NSLEEP_LDO_ASSIGN2_LDO3_SHIFT 0x02 +#define TPS65917_NSLEEP_LDO_ASSIGN2_LDO5 0x02 +#define TPS65917_NSLEEP_LDO_ASSIGN2_LDO5_SHIFT 0x01 + +/* Bit definitions for ENABLE1_RES_ASSIGN */ +#define TPS65917_ENABLE1_RES_ASSIGN_PLLEN 0x08 +#define TPS65917_ENABLE1_RES_ASSIGN_PLLEN_SHIFT 0x03 +#define TPS65917_ENABLE1_RES_ASSIGN_REGEN3 0x04 +#define TPS65917_ENABLE1_RES_ASSIGN_REGEN3_SHIFT 0x02 +#define TPS65917_ENABLE1_RES_ASSIGN_REGEN2 0x02 +#define TPS65917_ENABLE1_RES_ASSIGN_REGEN2_SHIFT 0x01 +#define TPS65917_ENABLE1_RES_ASSIGN_REGEN1 0x01 +#define TPS65917_ENABLE1_RES_ASSIGN_REGEN1_SHIFT 0x00 + +/* Bit definitions for ENABLE1_SMPS_ASSIGN */ +#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS5 0x40 +#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS5_SHIFT 0x06 +#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS4 0x10 +#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS4_SHIFT 0x04 +#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS3 0x08 +#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT 0x03 +#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS2 0x02 +#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS2_SHIFT 0x01 +#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS1 0x01 +#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS1_SHIFT 0x00 + +/* Bit definitions for ENABLE1_LDO_ASSIGN1 */ +#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO4 0x80 +#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT 0x07 +#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO2 0x02 +#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT 0x01 +#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO1 0x01 +#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT 0x00 + +/* Bit definitions for ENABLE1_LDO_ASSIGN2 */ +#define TPS65917_ENABLE1_LDO_ASSIGN2_LDO3 0x04 +#define TPS65917_ENABLE1_LDO_ASSIGN2_LDO3_SHIFT 0x02 +#define TPS65917_ENABLE1_LDO_ASSIGN2_LDO5 0x02 +#define TPS65917_ENABLE1_LDO_ASSIGN2_LDO5_SHIFT 0x01 + +/* Bit definitions for ENABLE2_RES_ASSIGN */ +#define TPS65917_ENABLE2_RES_ASSIGN_PLLEN 0x08 +#define TPS65917_ENABLE2_RES_ASSIGN_PLLEN_SHIFT 0x03 +#define TPS65917_ENABLE2_RES_ASSIGN_REGEN3 0x04 +#define TPS65917_ENABLE2_RES_ASSIGN_REGEN3_SHIFT 0x02 +#define TPS65917_ENABLE2_RES_ASSIGN_REGEN2 0x02 +#define TPS65917_ENABLE2_RES_ASSIGN_REGEN2_SHIFT 0x01 +#define TPS65917_ENABLE2_RES_ASSIGN_REGEN1 0x01 +#define TPS65917_ENABLE2_RES_ASSIGN_REGEN1_SHIFT 0x00 + +/* Bit definitions for ENABLE2_SMPS_ASSIGN */ +#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS5 0x40 +#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS5_SHIFT 0x06 +#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS4 0x10 +#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS4_SHIFT 0x04 +#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS3 0x08 +#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT 0x03 +#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS2 0x02 +#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS2_SHIFT 0x01 +#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS1 0x01 +#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS1_SHIFT 0x00 + +/* Bit definitions for ENABLE2_LDO_ASSIGN1 */ +#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO4 0x80 +#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT 0x07 +#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO2 0x02 +#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT 0x01 +#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO1 0x01 +#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT 0x00 + +/* Bit definitions for ENABLE2_LDO_ASSIGN2 */ +#define TPS65917_ENABLE2_LDO_ASSIGN2_LDO3 0x04 +#define TPS65917_ENABLE2_LDO_ASSIGN2_LDO3_SHIFT 0x02 +#define TPS65917_ENABLE2_LDO_ASSIGN2_LDO5 0x02 +#define TPS65917_ENABLE2_LDO_ASSIGN2_LDO5_SHIFT 0x01 + +/* Bit definitions for REGEN3_CTRL */ +#define TPS65917_REGEN3_CTRL_STATUS 0x10 +#define TPS65917_REGEN3_CTRL_STATUS_SHIFT 0x04 +#define TPS65917_REGEN3_CTRL_MODE_SLEEP 0x04 +#define TPS65917_REGEN3_CTRL_MODE_SLEEP_SHIFT 0x02 +#define TPS65917_REGEN3_CTRL_MODE_ACTIVE 0x01 +#define TPS65917_REGEN3_CTRL_MODE_ACTIVE_SHIFT 0x00 + +/* Registers for function RESOURCE */ +#define TPS65917_REGEN1_CTRL 0x2 +#define TPS65917_PLLEN_CTRL 0x3 +#define TPS65917_NSLEEP_RES_ASSIGN 0x6 +#define TPS65917_NSLEEP_SMPS_ASSIGN 0x7 +#define TPS65917_NSLEEP_LDO_ASSIGN1 0x8 +#define TPS65917_NSLEEP_LDO_ASSIGN2 0x9 +#define TPS65917_ENABLE1_RES_ASSIGN 0xA +#define TPS65917_ENABLE1_SMPS_ASSIGN 0xB +#define TPS65917_ENABLE1_LDO_ASSIGN1 0xC +#define TPS65917_ENABLE1_LDO_ASSIGN2 0xD +#define TPS65917_ENABLE2_RES_ASSIGN 0xE +#define TPS65917_ENABLE2_SMPS_ASSIGN 0xF +#define TPS65917_ENABLE2_LDO_ASSIGN1 0x10 +#define TPS65917_ENABLE2_LDO_ASSIGN2 0x11 +#define TPS65917_REGEN2_CTRL 0x12 +#define TPS65917_REGEN3_CTRL 0x13 + static inline int palmas_read(struct palmas *palmas, unsigned int base, unsigned int reg, unsigned int *val) { -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH 3/5] mfd: palmas: Add tps65917 specific definitions and enums 2014-05-26 9:56 ` [PATCH 3/5] mfd: palmas: Add tps65917 specific definitions and enums Keerthy @ 2014-05-27 8:41 ` Lee Jones 2014-05-27 8:43 ` Keerthy 0 siblings, 1 reply; 13+ messages in thread From: Lee Jones @ 2014-05-27 8:41 UTC (permalink / raw) To: Keerthy; +Cc: linux-omap, lgirdwood, broonie, linux-kernel, sameo > Add tps65917 specific definitions and enums. > > Signed-off-by: Keerthy <j-keerthy@ti.com> > --- > include/linux/mfd/palmas.h | 793 ++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 793 insertions(+) Looks okay to me: Acked-by: Lee Jones <lee.jones@linaro.org> Do the MFD patches have dependencies or are they depended on by the others in the set? > diff --git a/include/linux/mfd/palmas.h b/include/linux/mfd/palmas.h > index ccbb21f..52a24a9 100644 > --- a/include/linux/mfd/palmas.h > +++ b/include/linux/mfd/palmas.h > @@ -30,6 +30,8 @@ > #define PALMAS_CHIP_ID 0xC035 > #define PALMAS_CHIP_CHARGER_ID 0xC036 > > +#define TPS65917_RESERVED -1 > + > #define is_palmas(a) (((a) == PALMAS_CHIP_OLD_ID) || \ > ((a) == PALMAS_CHIP_ID)) > #define is_palmas_charger(a) ((a) == PALMAS_CHIP_CHARGER_ID) > @@ -184,6 +186,27 @@ enum palmas_regulators { > PALMAS_NUM_REGS, > }; > > +enum tps65917_regulators { > + /* SMPS regulators */ > + TPS65917_REG_SMPS1, > + TPS65917_REG_SMPS2, > + TPS65917_REG_SMPS3, > + TPS65917_REG_SMPS4, > + TPS65917_REG_SMPS5, > + /* LDO regulators */ > + TPS65917_REG_LDO1, > + TPS65917_REG_LDO2, > + TPS65917_REG_LDO3, > + TPS65917_REG_LDO4, > + TPS65917_REG_LDO5, > + TPS65917_REG_REGEN1, > + TPS65917_REG_REGEN2, > + TPS65917_REG_REGEN3, > + > + /* Total number of regulators */ > + TPS65917_NUM_REGS, > +}; > + > /* External controll signal name */ > enum { > PALMAS_EXT_CONTROL_ENABLE1 = 0x1, > @@ -228,6 +251,24 @@ enum palmas_external_requestor_id { > PALMAS_EXTERNAL_REQSTR_ID_MAX, > }; > > +enum tps65917_external_requestor_id { > + TPS65917_EXTERNAL_REQSTR_ID_REGEN1, > + TPS65917_EXTERNAL_REQSTR_ID_REGEN2, > + TPS65917_EXTERNAL_REQSTR_ID_REGEN3, > + TPS65917_EXTERNAL_REQSTR_ID_SMPS1, > + TPS65917_EXTERNAL_REQSTR_ID_SMPS2, > + TPS65917_EXTERNAL_REQSTR_ID_SMPS3, > + TPS65917_EXTERNAL_REQSTR_ID_SMPS4, > + TPS65917_EXTERNAL_REQSTR_ID_SMPS5, > + TPS65917_EXTERNAL_REQSTR_ID_LDO1, > + TPS65917_EXTERNAL_REQSTR_ID_LDO2, > + TPS65917_EXTERNAL_REQSTR_ID_LDO3, > + TPS65917_EXTERNAL_REQSTR_ID_LDO4, > + TPS65917_EXTERNAL_REQSTR_ID_LDO5, > + /* Last entry */ > + TPS65917_EXTERNAL_REQSTR_ID_MAX, > +}; > + > struct palmas_pmic_platform_data { > /* An array of pointers to regulator init data indexed by regulator > * ID > @@ -349,6 +390,48 @@ struct palmas_gpadc_result { > > #define PALMAS_MAX_CHANNELS 16 > > +/* Define the tps65917 IRQ numbers */ > +enum tps65917_irqs { > + /* INT1 registers */ > + TPS65917_RESERVED1, > + TPS65917_PWRON_IRQ, > + TPS65917_LONG_PRESS_KEY_IRQ, > + TPS65917_RESERVED2, > + TPS65917_PWRDOWN_IRQ, > + TPS65917_HOTDIE_IRQ, > + TPS65917_VSYS_MON_IRQ, > + TPS65917_RESERVED3, > + /* INT2 registers */ > + TPS65917_RESERVED4, > + TPS65917_OTP_ERROR_IRQ, > + TPS65917_WDT_IRQ, > + TPS65917_RESERVED5, > + TPS65917_RESET_IN_IRQ, > + TPS65917_FSD_IRQ, > + TPS65917_SHORT_IRQ, > + TPS65917_RESERVED6, > + /* INT3 registers */ > + TPS65917_GPADC_AUTO_0_IRQ, > + TPS65917_GPADC_AUTO_1_IRQ, > + TPS65917_GPADC_EOC_SW_IRQ, > + TPS65917_RESREVED6, > + TPS65917_RESERVED7, > + TPS65917_RESERVED8, > + TPS65917_RESERVED9, > + TPS65917_VBUS_IRQ, > + /* INT4 registers */ > + TPS65917_GPIO_0_IRQ, > + TPS65917_GPIO_1_IRQ, > + TPS65917_GPIO_2_IRQ, > + TPS65917_GPIO_3_IRQ, > + TPS65917_GPIO_4_IRQ, > + TPS65917_GPIO_5_IRQ, > + TPS65917_GPIO_6_IRQ, > + TPS65917_RESERVED10, > + /* Total Number IRQs */ > + TPS65917_NUM_IRQ, > +}; > + > /* Define the palmas IRQ numbers */ > enum palmas_irqs { > /* INT1 registers */ > @@ -400,6 +483,7 @@ struct palmas_pmic { > > int smps123; > int smps457; > + int smps12; > > int range[PALMAS_REG_SMPS10_OUT1]; > unsigned int ramp_delay[PALMAS_REG_SMPS10_OUT1]; > @@ -2871,6 +2955,715 @@ enum usb_irq_events { > #define PALMAS_GPADC_TRIM15 0x0E > #define PALMAS_GPADC_TRIM16 0x0F > > +/* TPS65917 Interrupt registers */ > + > +/* Registers for function INTERRUPT */ > +#define TPS65917_INT1_STATUS 0x00 > +#define TPS65917_INT1_MASK 0x01 > +#define TPS65917_INT1_LINE_STATE 0x02 > +#define TPS65917_INT2_STATUS 0x05 > +#define TPS65917_INT2_MASK 0x06 > +#define TPS65917_INT2_LINE_STATE 0x07 > +#define TPS65917_INT3_STATUS 0x0A > +#define TPS65917_INT3_MASK 0x0B > +#define TPS65917_INT3_LINE_STATE 0x0C > +#define TPS65917_INT4_STATUS 0x0F > +#define TPS65917_INT4_MASK 0x10 > +#define TPS65917_INT4_LINE_STATE 0x11 > +#define TPS65917_INT4_EDGE_DETECT1 0x12 > +#define TPS65917_INT4_EDGE_DETECT2 0x13 > +#define TPS65917_INT_CTRL 0x14 > + > +/* Bit definitions for INT1_STATUS */ > +#define TPS65917_INT1_STATUS_VSYS_MON 0x40 > +#define TPS65917_INT1_STATUS_VSYS_MON_SHIFT 0x06 > +#define TPS65917_INT1_STATUS_HOTDIE 0x20 > +#define TPS65917_INT1_STATUS_HOTDIE_SHIFT 0x05 > +#define TPS65917_INT1_STATUS_PWRDOWN 0x10 > +#define TPS65917_INT1_STATUS_PWRDOWN_SHIFT 0x04 > +#define TPS65917_INT1_STATUS_LONG_PRESS_KEY 0x04 > +#define TPS65917_INT1_STATUS_LONG_PRESS_KEY_SHIFT 0x02 > +#define TPS65917_INT1_STATUS_PWRON 0x02 > +#define TPS65917_INT1_STATUS_PWRON_SHIFT 0x01 > + > +/* Bit definitions for INT1_MASK */ > +#define TPS65917_INT1_MASK_VSYS_MON 0x40 > +#define TPS65917_INT1_MASK_VSYS_MON_SHIFT 0x06 > +#define TPS65917_INT1_MASK_HOTDIE 0x20 > +#define TPS65917_INT1_MASK_HOTDIE_SHIFT 0x05 > +#define TPS65917_INT1_MASK_PWRDOWN 0x10 > +#define TPS65917_INT1_MASK_PWRDOWN_SHIFT 0x04 > +#define TPS65917_INT1_MASK_LONG_PRESS_KEY 0x04 > +#define TPS65917_INT1_MASK_LONG_PRESS_KEY_SHIFT 0x02 > +#define TPS65917_INT1_MASK_PWRON 0x02 > +#define TPS65917_INT1_MASK_PWRON_SHIFT 0x01 > + > +/* Bit definitions for INT1_LINE_STATE */ > +#define TPS65917_INT1_LINE_STATE_VSYS_MON 0x40 > +#define TPS65917_INT1_LINE_STATE_VSYS_MON_SHIFT 0x06 > +#define TPS65917_INT1_LINE_STATE_HOTDIE 0x20 > +#define TPS65917_INT1_LINE_STATE_HOTDIE_SHIFT 0x05 > +#define TPS65917_INT1_LINE_STATE_PWRDOWN 0x10 > +#define TPS65917_INT1_LINE_STATE_PWRDOWN_SHIFT 0x04 > +#define TPS65917_INT1_LINE_STATE_LONG_PRESS_KEY 0x04 > +#define TPS65917_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT 0x02 > +#define TPS65917_INT1_LINE_STATE_PWRON 0x02 > +#define TPS65917_INT1_LINE_STATE_PWRON_SHIFT 0x01 > + > +/* Bit definitions for INT2_STATUS */ > +#define TPS65917_INT2_STATUS_SHORT 0x40 > +#define TPS65917_INT2_STATUS_SHORT_SHIFT 0x06 > +#define TPS65917_INT2_STATUS_FSD 0x20 > +#define TPS65917_INT2_STATUS_FSD_SHIFT 0x05 > +#define TPS65917_INT2_STATUS_RESET_IN 0x10 > +#define TPS65917_INT2_STATUS_RESET_IN_SHIFT 0x04 > +#define TPS65917_INT2_STATUS_WDT 0x04 > +#define TPS65917_INT2_STATUS_WDT_SHIFT 0x02 > +#define TPS65917_INT2_STATUS_OTP_ERROR 0x02 > +#define TPS65917_INT2_STATUS_OTP_ERROR_SHIFT 0x01 > + > +/* Bit definitions for INT2_MASK */ > +#define TPS65917_INT2_MASK_SHORT 0x40 > +#define TPS65917_INT2_MASK_SHORT_SHIFT 0x06 > +#define TPS65917_INT2_MASK_FSD 0x20 > +#define TPS65917_INT2_MASK_FSD_SHIFT 0x05 > +#define TPS65917_INT2_MASK_RESET_IN 0x10 > +#define TPS65917_INT2_MASK_RESET_IN_SHIFT 0x04 > +#define TPS65917_INT2_MASK_WDT 0x04 > +#define TPS65917_INT2_MASK_WDT_SHIFT 0x02 > +#define TPS65917_INT2_MASK_OTP_ERROR_TIMER 0x02 > +#define TPS65917_INT2_MASK_OTP_ERROR_SHIFT 0x01 > + > +/* Bit definitions for INT2_LINE_STATE */ > +#define TPS65917_INT2_LINE_STATE_SHORT 0x40 > +#define TPS65917_INT2_LINE_STATE_SHORT_SHIFT 0x06 > +#define TPS65917_INT2_LINE_STATE_FSD 0x20 > +#define TPS65917_INT2_LINE_STATE_FSD_SHIFT 0x05 > +#define TPS65917_INT2_LINE_STATE_RESET_IN 0x10 > +#define TPS65917_INT2_LINE_STATE_RESET_IN_SHIFT 0x04 > +#define TPS65917_INT2_LINE_STATE_WDT 0x04 > +#define TPS65917_INT2_LINE_STATE_WDT_SHIFT 0x02 > +#define TPS65917_INT2_LINE_STATE_OTP_ERROR 0x02 > +#define TPS65917_INT2_LINE_STATE_OTP_ERROR_SHIFT 0x01 > + > +/* Bit definitions for INT3_STATUS */ > +#define TPS65917_INT3_STATUS_VBUS 0x80 > +#define TPS65917_INT3_STATUS_VBUS_SHIFT 0x07 > +#define TPS65917_INT3_STATUS_GPADC_EOC_SW 0x04 > +#define TPS65917_INT3_STATUS_GPADC_EOC_SW_SHIFT 0x02 > +#define TPS65917_INT3_STATUS_GPADC_AUTO_1 0x02 > +#define TPS65917_INT3_STATUS_GPADC_AUTO_1_SHIFT 0x01 > +#define TPS65917_INT3_STATUS_GPADC_AUTO_0 0x01 > +#define TPS65917_INT3_STATUS_GPADC_AUTO_0_SHIFT 0x00 > + > +/* Bit definitions for INT3_MASK */ > +#define TPS65917_INT3_MASK_VBUS 0x80 > +#define TPS65917_INT3_MASK_VBUS_SHIFT 0x07 > +#define TPS65917_INT3_MASK_GPADC_EOC_SW 0x04 > +#define TPS65917_INT3_MASK_GPADC_EOC_SW_SHIFT 0x02 > +#define TPS65917_INT3_MASK_GPADC_AUTO_1 0x02 > +#define TPS65917_INT3_MASK_GPADC_AUTO_1_SHIFT 0x01 > +#define TPS65917_INT3_MASK_GPADC_AUTO_0 0x01 > +#define TPS65917_INT3_MASK_GPADC_AUTO_0_SHIFT 0x00 > + > +/* Bit definitions for INT3_LINE_STATE */ > +#define TPS65917_INT3_LINE_STATE_VBUS 0x80 > +#define TPS65917_INT3_LINE_STATE_VBUS_SHIFT 0x07 > +#define TPS65917_INT3_LINE_STATE_GPADC_EOC_SW 0x04 > +#define TPS65917_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT 0x02 > +#define TPS65917_INT3_LINE_STATE_GPADC_AUTO_1 0x02 > +#define TPS65917_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT 0x01 > +#define TPS65917_INT3_LINE_STATE_GPADC_AUTO_0 0x01 > +#define TPS65917_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT 0x00 > + > +/* Bit definitions for INT4_STATUS */ > +#define TPS65917_INT4_STATUS_GPIO_6 0x40 > +#define TPS65917_INT4_STATUS_GPIO_6_SHIFT 0x06 > +#define TPS65917_INT4_STATUS_GPIO_5 0x20 > +#define TPS65917_INT4_STATUS_GPIO_5_SHIFT 0x05 > +#define TPS65917_INT4_STATUS_GPIO_4 0x10 > +#define TPS65917_INT4_STATUS_GPIO_4_SHIFT 0x04 > +#define TPS65917_INT4_STATUS_GPIO_3 0x08 > +#define TPS65917_INT4_STATUS_GPIO_3_SHIFT 0x03 > +#define TPS65917_INT4_STATUS_GPIO_2 0x04 > +#define TPS65917_INT4_STATUS_GPIO_2_SHIFT 0x02 > +#define TPS65917_INT4_STATUS_GPIO_1 0x02 > +#define TPS65917_INT4_STATUS_GPIO_1_SHIFT 0x01 > +#define TPS65917_INT4_STATUS_GPIO_0 0x01 > +#define TPS65917_INT4_STATUS_GPIO_0_SHIFT 0x00 > + > +/* Bit definitions for INT4_MASK */ > +#define TPS65917_INT4_MASK_GPIO_6 0x40 > +#define TPS65917_INT4_MASK_GPIO_6_SHIFT 0x06 > +#define TPS65917_INT4_MASK_GPIO_5 0x20 > +#define TPS65917_INT4_MASK_GPIO_5_SHIFT 0x05 > +#define TPS65917_INT4_MASK_GPIO_4 0x10 > +#define TPS65917_INT4_MASK_GPIO_4_SHIFT 0x04 > +#define TPS65917_INT4_MASK_GPIO_3 0x08 > +#define TPS65917_INT4_MASK_GPIO_3_SHIFT 0x03 > +#define TPS65917_INT4_MASK_GPIO_2 0x04 > +#define TPS65917_INT4_MASK_GPIO_2_SHIFT 0x02 > +#define TPS65917_INT4_MASK_GPIO_1 0x02 > +#define TPS65917_INT4_MASK_GPIO_1_SHIFT 0x01 > +#define TPS65917_INT4_MASK_GPIO_0 0x01 > +#define TPS65917_INT4_MASK_GPIO_0_SHIFT 0x00 > + > +/* Bit definitions for INT4_LINE_STATE */ > +#define TPS65917_INT4_LINE_STATE_GPIO_6 0x40 > +#define TPS65917_INT4_LINE_STATE_GPIO_6_SHIFT 0x06 > +#define TPS65917_INT4_LINE_STATE_GPIO_5 0x20 > +#define TPS65917_INT4_LINE_STATE_GPIO_5_SHIFT 0x05 > +#define TPS65917_INT4_LINE_STATE_GPIO_4 0x10 > +#define TPS65917_INT4_LINE_STATE_GPIO_4_SHIFT 0x04 > +#define TPS65917_INT4_LINE_STATE_GPIO_3 0x08 > +#define TPS65917_INT4_LINE_STATE_GPIO_3_SHIFT 0x03 > +#define TPS65917_INT4_LINE_STATE_GPIO_2 0x04 > +#define TPS65917_INT4_LINE_STATE_GPIO_2_SHIFT 0x02 > +#define TPS65917_INT4_LINE_STATE_GPIO_1 0x02 > +#define TPS65917_INT4_LINE_STATE_GPIO_1_SHIFT 0x01 > +#define TPS65917_INT4_LINE_STATE_GPIO_0 0x01 > +#define TPS65917_INT4_LINE_STATE_GPIO_0_SHIFT 0x00 > + > +/* Bit definitions for INT4_EDGE_DETECT1 */ > +#define TPS65917_INT4_EDGE_DETECT1_GPIO_3_RISING 0x80 > +#define TPS65917_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT 0x07 > +#define TPS65917_INT4_EDGE_DETECT1_GPIO_3_FALLING 0x40 > +#define TPS65917_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT 0x06 > +#define TPS65917_INT4_EDGE_DETECT1_GPIO_2_RISING 0x20 > +#define TPS65917_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT 0x05 > +#define TPS65917_INT4_EDGE_DETECT1_GPIO_2_FALLING 0x10 > +#define TPS65917_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT 0x04 > +#define TPS65917_INT4_EDGE_DETECT1_GPIO_1_RISING 0x08 > +#define TPS65917_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT 0x03 > +#define TPS65917_INT4_EDGE_DETECT1_GPIO_1_FALLING 0x04 > +#define TPS65917_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT 0x02 > +#define TPS65917_INT4_EDGE_DETECT1_GPIO_0_RISING 0x02 > +#define TPS65917_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT 0x01 > +#define TPS65917_INT4_EDGE_DETECT1_GPIO_0_FALLING 0x01 > +#define TPS65917_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT 0x00 > + > +/* Bit definitions for INT4_EDGE_DETECT2 */ > +#define TPS65917_INT4_EDGE_DETECT2_GPIO_6_RISING 0x20 > +#define TPS65917_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT 0x05 > +#define TPS65917_INT4_EDGE_DETECT2_GPIO_6_FALLING 0x10 > +#define TPS65917_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT 0x04 > +#define TPS65917_INT4_EDGE_DETECT2_GPIO_5_RISING 0x08 > +#define TPS65917_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT 0x03 > +#define TPS65917_INT4_EDGE_DETECT2_GPIO_5_FALLING 0x04 > +#define TPS65917_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT 0x02 > +#define TPS65917_INT4_EDGE_DETECT2_GPIO_4_RISING 0x02 > +#define TPS65917_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT 0x01 > +#define TPS65917_INT4_EDGE_DETECT2_GPIO_4_FALLING 0x01 > +#define TPS65917_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT 0x00 > + > +/* Bit definitions for INT_CTRL */ > +#define TPS65917_INT_CTRL_INT_PENDING 0x04 > +#define TPS65917_INT_CTRL_INT_PENDING_SHIFT 0x02 > +#define TPS65917_INT_CTRL_INT_CLEAR 0x01 > +#define TPS65917_INT_CTRL_INT_CLEAR_SHIFT 0x00 > + > +/* TPS65917 SMPS Registers */ > + > +/* Registers for function SMPS */ > +#define TPS65917_SMPS1_CTRL 0x00 > +#define TPS65917_SMPS1_FORCE 0x02 > +#define TPS65917_SMPS1_VOLTAGE 0x03 > +#define TPS65917_SMPS2_CTRL 0x04 > +#define TPS65917_SMPS2_FORCE 0x06 > +#define TPS65917_SMPS2_VOLTAGE 0x07 > +#define TPS65917_SMPS3_CTRL 0x0C > +#define TPS65917_SMPS3_FORCE 0x0E > +#define TPS65917_SMPS3_VOLTAGE 0x0F > +#define TPS65917_SMPS4_CTRL 0x10 > +#define TPS65917_SMPS4_VOLTAGE 0x13 > +#define TPS65917_SMPS5_CTRL 0x18 > +#define TPS65917_SMPS5_VOLTAGE 0x1B > +#define TPS65917_SMPS_CTRL 0x24 > +#define TPS65917_SMPS_PD_CTRL 0x25 > +#define TPS65917_SMPS_THERMAL_EN 0x27 > +#define TPS65917_SMPS_THERMAL_STATUS 0x28 > +#define TPS65917_SMPS_SHORT_STATUS 0x29 > +#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN 0x2A > +#define TPS65917_SMPS_POWERGOOD_MASK1 0x2B > +#define TPS65917_SMPS_POWERGOOD_MASK2 0x2C > + > +/* Bit definitions for SMPS1_CTRL */ > +#define TPS65917_SMPS1_CTRL_WR_S 0x80 > +#define TPS65917_SMPS1_CTRL_WR_S_SHIFT 0x07 > +#define TPS65917_SMPS1_CTRL_ROOF_FLOOR_EN 0x40 > +#define TPS65917_SMPS1_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 > +#define TPS65917_SMPS1_CTRL_STATUS_MASK 0x30 > +#define TPS65917_SMPS1_CTRL_STATUS_SHIFT 0x04 > +#define TPS65917_SMPS1_CTRL_MODE_SLEEP_MASK 0x0C > +#define TPS65917_SMPS1_CTRL_MODE_SLEEP_SHIFT 0x02 > +#define TPS65917_SMPS1_CTRL_MODE_ACTIVE_MASK 0x03 > +#define TPS65917_SMPS1_CTRL_MODE_ACTIVE_SHIFT 0x00 > + > +/* Bit definitions for SMPS1_FORCE */ > +#define TPS65917_SMPS1_FORCE_CMD 0x80 > +#define TPS65917_SMPS1_FORCE_CMD_SHIFT 0x07 > +#define TPS65917_SMPS1_FORCE_VSEL_MASK 0x7F > +#define TPS65917_SMPS1_FORCE_VSEL_SHIFT 0x00 > + > +/* Bit definitions for SMPS1_VOLTAGE */ > +#define TPS65917_SMPS1_VOLTAGE_RANGE 0x80 > +#define TPS65917_SMPS1_VOLTAGE_RANGE_SHIFT 0x07 > +#define TPS65917_SMPS1_VOLTAGE_VSEL_MASK 0x7F > +#define TPS65917_SMPS1_VOLTAGE_VSEL_SHIFT 0x00 > + > +/* Bit definitions for SMPS2_CTRL */ > +#define TPS65917_SMPS2_CTRL_WR_S 0x80 > +#define TPS65917_SMPS2_CTRL_WR_S_SHIFT 0x07 > +#define TPS65917_SMPS2_CTRL_ROOF_FLOOR_EN 0x40 > +#define TPS65917_SMPS2_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 > +#define TPS65917_SMPS2_CTRL_STATUS_MASK 0x30 > +#define TPS65917_SMPS2_CTRL_STATUS_SHIFT 0x04 > +#define TPS65917_SMPS2_CTRL_MODE_SLEEP_MASK 0x0C > +#define TPS65917_SMPS2_CTRL_MODE_SLEEP_SHIFT 0x02 > +#define TPS65917_SMPS2_CTRL_MODE_ACTIVE_MASK 0x03 > +#define TPS65917_SMPS2_CTRL_MODE_ACTIVE_SHIFT 0x00 > + > +/* Bit definitions for SMPS2_FORCE */ > +#define TPS65917_SMPS2_FORCE_CMD 0x80 > +#define TPS65917_SMPS2_FORCE_CMD_SHIFT 0x07 > +#define TPS65917_SMPS2_FORCE_VSEL_MASK 0x7F > +#define TPS65917_SMPS2_FORCE_VSEL_SHIFT 0x00 > + > +/* Bit definitions for SMPS2_VOLTAGE */ > +#define TPS65917_SMPS2_VOLTAGE_RANGE 0x80 > +#define TPS65917_SMPS2_VOLTAGE_RANGE_SHIFT 0x07 > +#define TPS65917_SMPS2_VOLTAGE_VSEL_MASK 0x7F > +#define TPS65917_SMPS2_VOLTAGE_VSEL_SHIFT 0x00 > + > +/* Bit definitions for SMPS3_CTRL */ > +#define TPS65917_SMPS3_CTRL_WR_S 0x80 > +#define TPS65917_SMPS3_CTRL_WR_S_SHIFT 0x07 > +#define TPS65917_SMPS3_CTRL_ROOF_FLOOR_EN 0x40 > +#define TPS65917_SMPS3_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 > +#define TPS65917_SMPS3_CTRL_STATUS_MASK 0x30 > +#define TPS65917_SMPS3_CTRL_STATUS_SHIFT 0x04 > +#define TPS65917_SMPS3_CTRL_MODE_SLEEP_MASK 0x0C > +#define TPS65917_SMPS3_CTRL_MODE_SLEEP_SHIFT 0x02 > +#define TPS65917_SMPS3_CTRL_MODE_ACTIVE_MASK 0x03 > +#define TPS65917_SMPS3_CTRL_MODE_ACTIVE_SHIFT 0x00 > + > +/* Bit definitions for SMPS3_FORCE */ > +#define TPS65917_SMPS3_FORCE_CMD 0x80 > +#define TPS65917_SMPS3_FORCE_CMD_SHIFT 0x07 > +#define TPS65917_SMPS3_FORCE_VSEL_MASK 0x7F > +#define TPS65917_SMPS3_FORCE_VSEL_SHIFT 0x00 > + > +/* Bit definitions for SMPS3_VOLTAGE */ > +#define TPS65917_SMPS3_VOLTAGE_RANGE 0x80 > +#define TPS65917_SMPS3_VOLTAGE_RANGE_SHIFT 0x07 > +#define TPS65917_SMPS3_VOLTAGE_VSEL_MASK 0x7F > +#define TPS65917_SMPS3_VOLTAGE_VSEL_SHIFT 0x00 > + > +/* Bit definitions for SMPS4_CTRL */ > +#define TPS65917_SMPS4_CTRL_WR_S 0x80 > +#define TPS65917_SMPS4_CTRL_WR_S_SHIFT 0x07 > +#define TPS65917_SMPS4_CTRL_ROOF_FLOOR_EN 0x40 > +#define TPS65917_SMPS4_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 > +#define TPS65917_SMPS4_CTRL_STATUS_MASK 0x30 > +#define TPS65917_SMPS4_CTRL_STATUS_SHIFT 0x04 > +#define TPS65917_SMPS4_CTRL_MODE_SLEEP_MASK 0x0C > +#define TPS65917_SMPS4_CTRL_MODE_SLEEP_SHIFT 0x02 > +#define TPS65917_SMPS4_CTRL_MODE_ACTIVE_MASK 0x03 > +#define TPS65917_SMPS4_CTRL_MODE_ACTIVE_SHIFT 0x00 > + > +/* Bit definitions for SMPS4_VOLTAGE */ > +#define TPS65917_SMPS4_VOLTAGE_RANGE 0x80 > +#define TPS65917_SMPS4_VOLTAGE_RANGE_SHIFT 0x07 > +#define TPS65917_SMPS4_VOLTAGE_VSEL_MASK 0x7F > +#define TPS65917_SMPS4_VOLTAGE_VSEL_SHIFT 0x00 > + > +/* Bit definitions for SMPS5_CTRL */ > +#define TPS65917_SMPS5_CTRL_WR_S 0x80 > +#define TPS65917_SMPS5_CTRL_WR_S_SHIFT 0x07 > +#define TPS65917_SMPS5_CTRL_ROOF_FLOOR_EN 0x40 > +#define TPS65917_SMPS5_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 > +#define TPS65917_SMPS5_CTRL_STATUS_MASK 0x30 > +#define TPS65917_SMPS5_CTRL_STATUS_SHIFT 0x04 > +#define TPS65917_SMPS5_CTRL_MODE_SLEEP_MASK 0x0C > +#define TPS65917_SMPS5_CTRL_MODE_SLEEP_SHIFT 0x02 > +#define TPS65917_SMPS5_CTRL_MODE_ACTIVE_MASK 0x03 > +#define TPS65917_SMPS5_CTRL_MODE_ACTIVE_SHIFT 0x00 > + > +/* Bit definitions for SMPS5_VOLTAGE */ > +#define TPS65917_SMPS5_VOLTAGE_RANGE 0x80 > +#define TPS65917_SMPS5_VOLTAGE_RANGE_SHIFT 0x07 > +#define TPS65917_SMPS5_VOLTAGE_VSEL_MASK 0x7F > +#define TPS65917_SMPS5_VOLTAGE_VSEL_SHIFT 0x00 > + > +/* Bit definitions for SMPS_CTRL */ > +#define TPS65917_SMPS_CTRL_SMPS1_SMPS12_EN 0x10 > +#define TPS65917_SMPS_CTRL_SMPS1_SMPS12_EN_SHIFT 0x04 > +#define TPS65917_SMPS_CTRL_SMPS12_PHASE_CTRL 0x03 > +#define TPS65917_SMPS_CTRL_SMPS12_PHASE_CTRL_SHIFT 0x00 > + > +/* Bit definitions for SMPS_PD_CTRL */ > +#define TPS65917_SMPS_PD_CTRL_SMPS5 0x40 > +#define TPS65917_SMPS_PD_CTRL_SMPS5_SHIFT 0x06 > +#define TPS65917_SMPS_PD_CTRL_SMPS4 0x10 > +#define TPS65917_SMPS_PD_CTRL_SMPS4_SHIFT 0x04 > +#define TPS65917_SMPS_PD_CTRL_SMPS3 0x08 > +#define TPS65917_SMPS_PD_CTRL_SMPS3_SHIFT 0x03 > +#define TPS65917_SMPS_PD_CTRL_SMPS2 0x02 > +#define TPS65917_SMPS_PD_CTRL_SMPS2_SHIFT 0x01 > +#define TPS65917_SMPS_PD_CTRL_SMPS1 0x01 > +#define TPS65917_SMPS_PD_CTRL_SMPS1_SHIFT 0x00 > + > +/* Bit definitions for SMPS_THERMAL_EN */ > +#define TPS65917_SMPS_THERMAL_EN_SMPS5 0x40 > +#define TPS65917_SMPS_THERMAL_EN_SMPS5_SHIFT 0x06 > +#define TPS65917_SMPS_THERMAL_EN_SMPS3 0x08 > +#define TPS65917_SMPS_THERMAL_EN_SMPS3_SHIFT 0x03 > +#define TPS65917_SMPS_THERMAL_EN_SMPS12 0x01 > +#define TPS65917_SMPS_THERMAL_EN_SMPS12_SHIFT 0x00 > + > +/* Bit definitions for SMPS_THERMAL_STATUS */ > +#define TPS65917_SMPS_THERMAL_STATUS_SMPS5 0x40 > +#define TPS65917_SMPS_THERMAL_STATUS_SMPS5_SHIFT 0x06 > +#define TPS65917_SMPS_THERMAL_STATUS_SMPS3 0x08 > +#define TPS65917_SMPS_THERMAL_STATUS_SMPS3_SHIFT 0x03 > +#define TPS65917_SMPS_THERMAL_STATUS_SMPS12 0x01 > +#define TPS65917_SMPS_THERMAL_STATUS_SMPS12_SHIFT 0x00 > + > +/* Bit definitions for SMPS_SHORT_STATUS */ > +#define TPS65917_SMPS_SHORT_STATUS_SMPS5 0x40 > +#define TPS65917_SMPS_SHORT_STATUS_SMPS5_SHIFT 0x06 > +#define TPS65917_SMPS_SHORT_STATUS_SMPS4 0x10 > +#define TPS65917_SMPS_SHORT_STATUS_SMPS4_SHIFT 0x04 > +#define TPS65917_SMPS_SHORT_STATUS_SMPS3 0x08 > +#define TPS65917_SMPS_SHORT_STATUS_SMPS3_SHIFT 0x03 > +#define TPS65917_SMPS_SHORT_STATUS_SMPS2 0x02 > +#define TPS65917_SMPS_SHORT_STATUS_SMPS2_SHIFT 0x01 > +#define TPS65917_SMPS_SHORT_STATUS_SMPS1 0x01 > +#define TPS65917_SMPS_SHORT_STATUS_SMPS1_SHIFT 0x00 > + > +/* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */ > +#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS5 0x40 > +#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS5_SHIFT 0x06 > +#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS4 0x10 > +#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS4_SHIFT 0x04 > +#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3 0x08 > +#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT 0x03 > +#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS2 0x02 > +#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS2_SHIFT 0x01 > +#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS1 0x01 > +#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS1_SHIFT 0x00 > + > +/* Bit definitions for SMPS_POWERGOOD_MASK1 */ > +#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS5 0x40 > +#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS5_SHIFT 0x06 > +#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS4 0x10 > +#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS4_SHIFT 0x04 > +#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS3 0x08 > +#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT 0x03 > +#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS2 0x02 > +#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS2_SHIFT 0x01 > +#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS1 0x01 > +#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS1_SHIFT 0x00 > + > +/* Bit definitions for SMPS_POWERGOOD_MASK2 */ > +#define TPS65917_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT 0x80 > +#define TPS65917_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT 0x07 > +#define TPS65917_SMPS_POWERGOOD_MASK2_OVC_ALARM_SHIFT 0x10 > +#define TPS65917_SMPS_POWERGOOD_MASK2_OVC_ALARM 0x04 > + > +/* Bit definitions for SMPS_PLL_CTRL */ > + > +#define TPS65917_SMPS_PLL_CTRL_PLL_EN_PLL_BYPASS_SHIFT 0x08 > +#define TPS65917_SMPS_PLL_CTRL_PLL_PLL_EN_BYPASS 0x03 > +#define TPS65917_SMPS_PLL_CTRL_PLL_PLL_BYPASS_CLK_SHIFT 0x04 > +#define TPS65917_SMPS_PLL_CTRL_PLL_PLL_BYPASS_CLK 0x02 > + > +/* Registers for function LDO */ > +#define TPS65917_LDO1_CTRL 0x00 > +#define TPS65917_LDO1_VOLTAGE 0x01 > +#define TPS65917_LDO2_CTRL 0x02 > +#define TPS65917_LDO2_VOLTAGE 0x03 > +#define TPS65917_LDO3_CTRL 0x04 > +#define TPS65917_LDO3_VOLTAGE 0x05 > +#define TPS65917_LDO4_CTRL 0x0E > +#define TPS65917_LDO4_VOLTAGE 0x0F > +#define TPS65917_LDO5_CTRL 0x12 > +#define TPS65917_LDO5_VOLTAGE 0x13 > +#define TPS65917_LDO_PD_CTRL1 0x1B > +#define TPS65917_LDO_PD_CTRL2 0x1C > +#define TPS65917_LDO_SHORT_STATUS1 0x1D > +#define TPS65917_LDO_SHORT_STATUS2 0x1E > +#define TPS65917_LDO_PD_CTRL3 0x2D > +#define TPS65917_LDO_SHORT_STATUS3 0x2E > + > +/* Bit definitions for LDO1_CTRL */ > +#define TPS65917_LDO1_CTRL_WR_S 0x80 > +#define TPS65917_LDO1_CTRL_WR_S_SHIFT 0x07 > +#define TPS65917_LDO1_CTRL_BYPASS_EN 0x40 > +#define TPS65917_LDO1_CTRL_BYPASS_EN_SHIFT 0x06 > +#define TPS65917_LDO1_CTRL_STATUS 0x10 > +#define TPS65917_LDO1_CTRL_STATUS_SHIFT 0x04 > +#define TPS65917_LDO1_CTRL_MODE_SLEEP 0x04 > +#define TPS65917_LDO1_CTRL_MODE_SLEEP_SHIFT 0x02 > +#define TPS65917_LDO1_CTRL_MODE_ACTIVE 0x01 > +#define TPS65917_LDO1_CTRL_MODE_ACTIVE_SHIFT 0x00 > + > +/* Bit definitions for LDO1_VOLTAGE */ > +#define TPS65917_LDO1_VOLTAGE_VSEL_MASK 0x2F > +#define TPS65917_LDO1_VOLTAGE_VSEL_SHIFT 0x00 > + > +/* Bit definitions for LDO2_CTRL */ > +#define TPS65917_LDO2_CTRL_WR_S 0x80 > +#define TPS65917_LDO2_CTRL_WR_S_SHIFT 0x07 > +#define TPS65917_LDO2_CTRL_BYPASS_EN 0x40 > +#define TPS65917_LDO2_CTRL_BYPASS_EN_SHIFT 0x06 > +#define TPS65917_LDO2_CTRL_STATUS 0x10 > +#define TPS65917_LDO2_CTRL_STATUS_SHIFT 0x04 > +#define TPS65917_LDO2_CTRL_MODE_SLEEP 0x04 > +#define TPS65917_LDO2_CTRL_MODE_SLEEP_SHIFT 0x02 > +#define TPS65917_LDO2_CTRL_MODE_ACTIVE 0x01 > +#define TPS65917_LDO2_CTRL_MODE_ACTIVE_SHIFT 0x00 > + > +/* Bit definitions for LDO2_VOLTAGE */ > +#define TPS65917_LDO2_VOLTAGE_VSEL_MASK 0x2F > +#define TPS65917_LDO2_VOLTAGE_VSEL_SHIFT 0x00 > + > +/* Bit definitions for LDO3_CTRL */ > +#define TPS65917_LDO3_CTRL_WR_S 0x80 > +#define TPS65917_LDO3_CTRL_WR_S_SHIFT 0x07 > +#define TPS65917_LDO3_CTRL_STATUS 0x10 > +#define TPS65917_LDO3_CTRL_STATUS_SHIFT 0x04 > +#define TPS65917_LDO3_CTRL_MODE_SLEEP 0x04 > +#define TPS65917_LDO3_CTRL_MODE_SLEEP_SHIFT 0x02 > +#define TPS65917_LDO3_CTRL_MODE_ACTIVE 0x01 > +#define TPS65917_LDO3_CTRL_MODE_ACTIVE_SHIFT 0x00 > + > +/* Bit definitions for LDO3_VOLTAGE */ > +#define TPS65917_LDO3_VOLTAGE_VSEL_MASK 0x2F > +#define TPS65917_LDO3_VOLTAGE_VSEL_SHIFT 0x00 > + > +/* Bit definitions for LDO4_CTRL */ > +#define TPS65917_LDO4_CTRL_WR_S 0x80 > +#define TPS65917_LDO4_CTRL_WR_S_SHIFT 0x07 > +#define TPS65917_LDO4_CTRL_STATUS 0x10 > +#define TPS65917_LDO4_CTRL_STATUS_SHIFT 0x04 > +#define TPS65917_LDO4_CTRL_MODE_SLEEP 0x04 > +#define TPS65917_LDO4_CTRL_MODE_SLEEP_SHIFT 0x02 > +#define TPS65917_LDO4_CTRL_MODE_ACTIVE 0x01 > +#define TPS65917_LDO4_CTRL_MODE_ACTIVE_SHIFT 0x00 > + > +/* Bit definitions for LDO4_VOLTAGE */ > +#define TPS65917_LDO4_VOLTAGE_VSEL_MASK 0x2F > +#define TPS65917_LDO4_VOLTAGE_VSEL_SHIFT 0x00 > + > +/* Bit definitions for LDO5_CTRL */ > +#define TPS65917_LDO5_CTRL_WR_S 0x80 > +#define TPS65917_LDO5_CTRL_WR_S_SHIFT 0x07 > +#define TPS65917_LDO5_CTRL_STATUS 0x10 > +#define TPS65917_LDO5_CTRL_STATUS_SHIFT 0x04 > +#define TPS65917_LDO5_CTRL_MODE_SLEEP 0x04 > +#define TPS65917_LDO5_CTRL_MODE_SLEEP_SHIFT 0x02 > +#define TPS65917_LDO5_CTRL_MODE_ACTIVE 0x01 > +#define TPS65917_LDO5_CTRL_MODE_ACTIVE_SHIFT 0x00 > + > +/* Bit definitions for LDO5_VOLTAGE */ > +#define TPS65917_LDO5_VOLTAGE_VSEL_MASK 0x2F > +#define TPS65917_LDO5_VOLTAGE_VSEL_SHIFT 0x00 > + > +/* Bit definitions for LDO_PD_CTRL1 */ > +#define TPS65917_LDO_PD_CTRL1_LDO4 0x80 > +#define TPS65917_LDO_PD_CTRL1_LDO4_SHIFT 0x07 > +#define TPS65917_LDO_PD_CTRL1_LDO2 0x02 > +#define TPS65917_LDO_PD_CTRL1_LDO2_SHIFT 0x01 > +#define TPS65917_LDO_PD_CTRL1_LDO1 0x01 > +#define TPS65917_LDO_PD_CTRL1_LDO1_SHIFT 0x00 > + > +/* Bit definitions for LDO_PD_CTRL2 */ > +#define TPS65917_LDO_PD_CTRL2_LDO3 0x04 > +#define TPS65917_LDO_PD_CTRL2_LDO3_SHIFT 0x02 > +#define TPS65917_LDO_PD_CTRL2_LDO5 0x02 > +#define TPS65917_LDO_PD_CTRL2_LDO5_SHIFT 0x01 > + > +/* Bit definitions for LDO_PD_CTRL3 */ > +#define TPS65917_LDO_PD_CTRL2_LDOVANA 0x80 > +#define TPS65917_LDO_PD_CTRL2_LDOVANA_SHIFT 0x07 > + > +/* Bit definitions for LDO_SHORT_STATUS1 */ > +#define TPS65917_LDO_SHORT_STATUS1_LDO4 0x80 > +#define TPS65917_LDO_SHORT_STATUS1_LDO4_SHIFT 0x07 > +#define TPS65917_LDO_SHORT_STATUS1_LDO2 0x02 > +#define TPS65917_LDO_SHORT_STATUS1_LDO2_SHIFT 0x01 > +#define TPS65917_LDO_SHORT_STATUS1_LDO1 0x01 > +#define TPS65917_LDO_SHORT_STATUS1_LDO1_SHIFT 0x00 > + > +/* Bit definitions for LDO_SHORT_STATUS2 */ > +#define TPS65917_LDO_SHORT_STATUS2_LDO3 0x04 > +#define TPS65917_LDO_SHORT_STATUS2_LDO3_SHIFT 0x02 > +#define TPS65917_LDO_SHORT_STATUS2_LDO5 0x02 > +#define TPS65917_LDO_SHORT_STATUS2_LDO5_SHIFT 0x01 > + > +/* Bit definitions for LDO_SHORT_STATUS2 */ > +#define TPS65917_LDO_SHORT_STATUS2_LDOVANA 0x80 > +#define TPS65917_LDO_SHORT_STATUS2_LDOVANA_SHIFT 0x07 > + > +/* Bit definitions for REGEN1_CTRL */ > +#define TPS65917_REGEN1_CTRL_STATUS 0x10 > +#define TPS65917_REGEN1_CTRL_STATUS_SHIFT 0x04 > +#define TPS65917_REGEN1_CTRL_MODE_SLEEP 0x04 > +#define TPS65917_REGEN1_CTRL_MODE_SLEEP_SHIFT 0x02 > +#define TPS65917_REGEN1_CTRL_MODE_ACTIVE 0x01 > +#define TPS65917_REGEN1_CTRL_MODE_ACTIVE_SHIFT 0x00 > + > +/* Bit definitions for PLLEN_CTRL */ > +#define TPS65917_PLLEN_CTRL_STATUS 0x10 > +#define TPS65917_PLLEN_CTRL_STATUS_SHIFT 0x04 > +#define TPS65917_PLLEN_CTRL_MODE_SLEEP 0x04 > +#define TPS65917_PLLEN_CTRL_MODE_SLEEP_SHIFT 0x02 > +#define TPS65917_PLLEN_CTRL_MODE_ACTIVE 0x01 > +#define TPS65917_PLLEN_CTRL_MODE_ACTIVE_SHIFT 0x00 > + > +/* Bit definitions for REGEN2_CTRL */ > +#define TPS65917_REGEN2_CTRL_STATUS 0x10 > +#define TPS65917_REGEN2_CTRL_STATUS_SHIFT 0x04 > +#define TPS65917_REGEN2_CTRL_MODE_SLEEP 0x04 > +#define TPS65917_REGEN2_CTRL_MODE_SLEEP_SHIFT 0x02 > +#define TPS65917_REGEN2_CTRL_MODE_ACTIVE 0x01 > +#define TPS65917_REGEN2_CTRL_MODE_ACTIVE_SHIFT 0x00 > + > +/* Bit definitions for NSLEEP_RES_ASSIGN */ > +#define TPS65917_NSLEEP_RES_ASSIGN_PLL_EN 0x08 > +#define TPS65917_NSLEEP_RES_ASSIGN_PLL_EN_SHIFT 0x03 > +#define TPS65917_NSLEEP_RES_ASSIGN_REGEN3 0x04 > +#define TPS65917_NSLEEP_RES_ASSIGN_REGEN3_SHIFT 0x02 > +#define TPS65917_NSLEEP_RES_ASSIGN_REGEN2 0x02 > +#define TPS65917_NSLEEP_RES_ASSIGN_REGEN2_SHIFT 0x01 > +#define TPS65917_NSLEEP_RES_ASSIGN_REGEN1 0x01 > +#define TPS65917_NSLEEP_RES_ASSIGN_REGEN1_SHIFT 0x00 > + > +/* Bit definitions for NSLEEP_SMPS_ASSIGN */ > +#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS5 0x40 > +#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS5_SHIFT 0x06 > +#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS4 0x10 > +#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS4_SHIFT 0x04 > +#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS3 0x08 > +#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT 0x03 > +#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS2 0x02 > +#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS2_SHIFT 0x01 > +#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS1 0x01 > +#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS1_SHIFT 0x00 > + > +/* Bit definitions for NSLEEP_LDO_ASSIGN1 */ > +#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO4 0x80 > +#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT 0x07 > +#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO2 0x02 > +#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT 0x01 > +#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO1 0x01 > +#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT 0x00 > + > +/* Bit definitions for NSLEEP_LDO_ASSIGN2 */ > +#define TPS65917_NSLEEP_LDO_ASSIGN2_LDO3 0x04 > +#define TPS65917_NSLEEP_LDO_ASSIGN2_LDO3_SHIFT 0x02 > +#define TPS65917_NSLEEP_LDO_ASSIGN2_LDO5 0x02 > +#define TPS65917_NSLEEP_LDO_ASSIGN2_LDO5_SHIFT 0x01 > + > +/* Bit definitions for ENABLE1_RES_ASSIGN */ > +#define TPS65917_ENABLE1_RES_ASSIGN_PLLEN 0x08 > +#define TPS65917_ENABLE1_RES_ASSIGN_PLLEN_SHIFT 0x03 > +#define TPS65917_ENABLE1_RES_ASSIGN_REGEN3 0x04 > +#define TPS65917_ENABLE1_RES_ASSIGN_REGEN3_SHIFT 0x02 > +#define TPS65917_ENABLE1_RES_ASSIGN_REGEN2 0x02 > +#define TPS65917_ENABLE1_RES_ASSIGN_REGEN2_SHIFT 0x01 > +#define TPS65917_ENABLE1_RES_ASSIGN_REGEN1 0x01 > +#define TPS65917_ENABLE1_RES_ASSIGN_REGEN1_SHIFT 0x00 > + > +/* Bit definitions for ENABLE1_SMPS_ASSIGN */ > +#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS5 0x40 > +#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS5_SHIFT 0x06 > +#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS4 0x10 > +#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS4_SHIFT 0x04 > +#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS3 0x08 > +#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT 0x03 > +#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS2 0x02 > +#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS2_SHIFT 0x01 > +#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS1 0x01 > +#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS1_SHIFT 0x00 > + > +/* Bit definitions for ENABLE1_LDO_ASSIGN1 */ > +#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO4 0x80 > +#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT 0x07 > +#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO2 0x02 > +#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT 0x01 > +#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO1 0x01 > +#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT 0x00 > + > +/* Bit definitions for ENABLE1_LDO_ASSIGN2 */ > +#define TPS65917_ENABLE1_LDO_ASSIGN2_LDO3 0x04 > +#define TPS65917_ENABLE1_LDO_ASSIGN2_LDO3_SHIFT 0x02 > +#define TPS65917_ENABLE1_LDO_ASSIGN2_LDO5 0x02 > +#define TPS65917_ENABLE1_LDO_ASSIGN2_LDO5_SHIFT 0x01 > + > +/* Bit definitions for ENABLE2_RES_ASSIGN */ > +#define TPS65917_ENABLE2_RES_ASSIGN_PLLEN 0x08 > +#define TPS65917_ENABLE2_RES_ASSIGN_PLLEN_SHIFT 0x03 > +#define TPS65917_ENABLE2_RES_ASSIGN_REGEN3 0x04 > +#define TPS65917_ENABLE2_RES_ASSIGN_REGEN3_SHIFT 0x02 > +#define TPS65917_ENABLE2_RES_ASSIGN_REGEN2 0x02 > +#define TPS65917_ENABLE2_RES_ASSIGN_REGEN2_SHIFT 0x01 > +#define TPS65917_ENABLE2_RES_ASSIGN_REGEN1 0x01 > +#define TPS65917_ENABLE2_RES_ASSIGN_REGEN1_SHIFT 0x00 > + > +/* Bit definitions for ENABLE2_SMPS_ASSIGN */ > +#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS5 0x40 > +#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS5_SHIFT 0x06 > +#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS4 0x10 > +#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS4_SHIFT 0x04 > +#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS3 0x08 > +#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT 0x03 > +#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS2 0x02 > +#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS2_SHIFT 0x01 > +#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS1 0x01 > +#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS1_SHIFT 0x00 > + > +/* Bit definitions for ENABLE2_LDO_ASSIGN1 */ > +#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO4 0x80 > +#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT 0x07 > +#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO2 0x02 > +#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT 0x01 > +#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO1 0x01 > +#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT 0x00 > + > +/* Bit definitions for ENABLE2_LDO_ASSIGN2 */ > +#define TPS65917_ENABLE2_LDO_ASSIGN2_LDO3 0x04 > +#define TPS65917_ENABLE2_LDO_ASSIGN2_LDO3_SHIFT 0x02 > +#define TPS65917_ENABLE2_LDO_ASSIGN2_LDO5 0x02 > +#define TPS65917_ENABLE2_LDO_ASSIGN2_LDO5_SHIFT 0x01 > + > +/* Bit definitions for REGEN3_CTRL */ > +#define TPS65917_REGEN3_CTRL_STATUS 0x10 > +#define TPS65917_REGEN3_CTRL_STATUS_SHIFT 0x04 > +#define TPS65917_REGEN3_CTRL_MODE_SLEEP 0x04 > +#define TPS65917_REGEN3_CTRL_MODE_SLEEP_SHIFT 0x02 > +#define TPS65917_REGEN3_CTRL_MODE_ACTIVE 0x01 > +#define TPS65917_REGEN3_CTRL_MODE_ACTIVE_SHIFT 0x00 > + > +/* Registers for function RESOURCE */ > +#define TPS65917_REGEN1_CTRL 0x2 > +#define TPS65917_PLLEN_CTRL 0x3 > +#define TPS65917_NSLEEP_RES_ASSIGN 0x6 > +#define TPS65917_NSLEEP_SMPS_ASSIGN 0x7 > +#define TPS65917_NSLEEP_LDO_ASSIGN1 0x8 > +#define TPS65917_NSLEEP_LDO_ASSIGN2 0x9 > +#define TPS65917_ENABLE1_RES_ASSIGN 0xA > +#define TPS65917_ENABLE1_SMPS_ASSIGN 0xB > +#define TPS65917_ENABLE1_LDO_ASSIGN1 0xC > +#define TPS65917_ENABLE1_LDO_ASSIGN2 0xD > +#define TPS65917_ENABLE2_RES_ASSIGN 0xE > +#define TPS65917_ENABLE2_SMPS_ASSIGN 0xF > +#define TPS65917_ENABLE2_LDO_ASSIGN1 0x10 > +#define TPS65917_ENABLE2_LDO_ASSIGN2 0x11 > +#define TPS65917_REGEN2_CTRL 0x12 > +#define TPS65917_REGEN3_CTRL 0x13 > + > static inline int palmas_read(struct palmas *palmas, unsigned int base, > unsigned int reg, unsigned int *val) > { -- Lee Jones Linaro STMicroelectronics Landing Team Lead Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 3/5] mfd: palmas: Add tps65917 specific definitions and enums 2014-05-27 8:41 ` Lee Jones @ 2014-05-27 8:43 ` Keerthy 0 siblings, 0 replies; 13+ messages in thread From: Keerthy @ 2014-05-27 8:43 UTC (permalink / raw) To: Lee Jones; +Cc: Keerthy, linux-omap, lgirdwood, broonie, linux-kernel, sameo On Tuesday 27 May 2014 02:11 PM, Lee Jones wrote: >> Add tps65917 specific definitions and enums. >> >> Signed-off-by: Keerthy <j-keerthy@ti.com> >> --- >> include/linux/mfd/palmas.h | 793 ++++++++++++++++++++++++++++++++++++++++++++ >> 1 file changed, 793 insertions(+) > Looks okay to me: > > Acked-by: Lee Jones <lee.jones@linaro.org> > > Do the MFD patches have dependencies or are they depended on by the > others in the set? No Dependency as such. These can be applied independently. I will work on unifying the regulator driver for palmas and tps65917. > >> diff --git a/include/linux/mfd/palmas.h b/include/linux/mfd/palmas.h >> index ccbb21f..52a24a9 100644 >> --- a/include/linux/mfd/palmas.h >> +++ b/include/linux/mfd/palmas.h >> @@ -30,6 +30,8 @@ >> #define PALMAS_CHIP_ID 0xC035 >> #define PALMAS_CHIP_CHARGER_ID 0xC036 >> >> +#define TPS65917_RESERVED -1 >> + >> #define is_palmas(a) (((a) == PALMAS_CHIP_OLD_ID) || \ >> ((a) == PALMAS_CHIP_ID)) >> #define is_palmas_charger(a) ((a) == PALMAS_CHIP_CHARGER_ID) >> @@ -184,6 +186,27 @@ enum palmas_regulators { >> PALMAS_NUM_REGS, >> }; >> >> +enum tps65917_regulators { >> + /* SMPS regulators */ >> + TPS65917_REG_SMPS1, >> + TPS65917_REG_SMPS2, >> + TPS65917_REG_SMPS3, >> + TPS65917_REG_SMPS4, >> + TPS65917_REG_SMPS5, >> + /* LDO regulators */ >> + TPS65917_REG_LDO1, >> + TPS65917_REG_LDO2, >> + TPS65917_REG_LDO3, >> + TPS65917_REG_LDO4, >> + TPS65917_REG_LDO5, >> + TPS65917_REG_REGEN1, >> + TPS65917_REG_REGEN2, >> + TPS65917_REG_REGEN3, >> + >> + /* Total number of regulators */ >> + TPS65917_NUM_REGS, >> +}; >> + >> /* External controll signal name */ >> enum { >> PALMAS_EXT_CONTROL_ENABLE1 = 0x1, >> @@ -228,6 +251,24 @@ enum palmas_external_requestor_id { >> PALMAS_EXTERNAL_REQSTR_ID_MAX, >> }; >> >> +enum tps65917_external_requestor_id { >> + TPS65917_EXTERNAL_REQSTR_ID_REGEN1, >> + TPS65917_EXTERNAL_REQSTR_ID_REGEN2, >> + TPS65917_EXTERNAL_REQSTR_ID_REGEN3, >> + TPS65917_EXTERNAL_REQSTR_ID_SMPS1, >> + TPS65917_EXTERNAL_REQSTR_ID_SMPS2, >> + TPS65917_EXTERNAL_REQSTR_ID_SMPS3, >> + TPS65917_EXTERNAL_REQSTR_ID_SMPS4, >> + TPS65917_EXTERNAL_REQSTR_ID_SMPS5, >> + TPS65917_EXTERNAL_REQSTR_ID_LDO1, >> + TPS65917_EXTERNAL_REQSTR_ID_LDO2, >> + TPS65917_EXTERNAL_REQSTR_ID_LDO3, >> + TPS65917_EXTERNAL_REQSTR_ID_LDO4, >> + TPS65917_EXTERNAL_REQSTR_ID_LDO5, >> + /* Last entry */ >> + TPS65917_EXTERNAL_REQSTR_ID_MAX, >> +}; >> + >> struct palmas_pmic_platform_data { >> /* An array of pointers to regulator init data indexed by regulator >> * ID >> @@ -349,6 +390,48 @@ struct palmas_gpadc_result { >> >> #define PALMAS_MAX_CHANNELS 16 >> >> +/* Define the tps65917 IRQ numbers */ >> +enum tps65917_irqs { >> + /* INT1 registers */ >> + TPS65917_RESERVED1, >> + TPS65917_PWRON_IRQ, >> + TPS65917_LONG_PRESS_KEY_IRQ, >> + TPS65917_RESERVED2, >> + TPS65917_PWRDOWN_IRQ, >> + TPS65917_HOTDIE_IRQ, >> + TPS65917_VSYS_MON_IRQ, >> + TPS65917_RESERVED3, >> + /* INT2 registers */ >> + TPS65917_RESERVED4, >> + TPS65917_OTP_ERROR_IRQ, >> + TPS65917_WDT_IRQ, >> + TPS65917_RESERVED5, >> + TPS65917_RESET_IN_IRQ, >> + TPS65917_FSD_IRQ, >> + TPS65917_SHORT_IRQ, >> + TPS65917_RESERVED6, >> + /* INT3 registers */ >> + TPS65917_GPADC_AUTO_0_IRQ, >> + TPS65917_GPADC_AUTO_1_IRQ, >> + TPS65917_GPADC_EOC_SW_IRQ, >> + TPS65917_RESREVED6, >> + TPS65917_RESERVED7, >> + TPS65917_RESERVED8, >> + TPS65917_RESERVED9, >> + TPS65917_VBUS_IRQ, >> + /* INT4 registers */ >> + TPS65917_GPIO_0_IRQ, >> + TPS65917_GPIO_1_IRQ, >> + TPS65917_GPIO_2_IRQ, >> + TPS65917_GPIO_3_IRQ, >> + TPS65917_GPIO_4_IRQ, >> + TPS65917_GPIO_5_IRQ, >> + TPS65917_GPIO_6_IRQ, >> + TPS65917_RESERVED10, >> + /* Total Number IRQs */ >> + TPS65917_NUM_IRQ, >> +}; >> + >> /* Define the palmas IRQ numbers */ >> enum palmas_irqs { >> /* INT1 registers */ >> @@ -400,6 +483,7 @@ struct palmas_pmic { >> >> int smps123; >> int smps457; >> + int smps12; >> >> int range[PALMAS_REG_SMPS10_OUT1]; >> unsigned int ramp_delay[PALMAS_REG_SMPS10_OUT1]; >> @@ -2871,6 +2955,715 @@ enum usb_irq_events { >> #define PALMAS_GPADC_TRIM15 0x0E >> #define PALMAS_GPADC_TRIM16 0x0F >> >> +/* TPS65917 Interrupt registers */ >> + >> +/* Registers for function INTERRUPT */ >> +#define TPS65917_INT1_STATUS 0x00 >> +#define TPS65917_INT1_MASK 0x01 >> +#define TPS65917_INT1_LINE_STATE 0x02 >> +#define TPS65917_INT2_STATUS 0x05 >> +#define TPS65917_INT2_MASK 0x06 >> +#define TPS65917_INT2_LINE_STATE 0x07 >> +#define TPS65917_INT3_STATUS 0x0A >> +#define TPS65917_INT3_MASK 0x0B >> +#define TPS65917_INT3_LINE_STATE 0x0C >> +#define TPS65917_INT4_STATUS 0x0F >> +#define TPS65917_INT4_MASK 0x10 >> +#define TPS65917_INT4_LINE_STATE 0x11 >> +#define TPS65917_INT4_EDGE_DETECT1 0x12 >> +#define TPS65917_INT4_EDGE_DETECT2 0x13 >> +#define TPS65917_INT_CTRL 0x14 >> + >> +/* Bit definitions for INT1_STATUS */ >> +#define TPS65917_INT1_STATUS_VSYS_MON 0x40 >> +#define TPS65917_INT1_STATUS_VSYS_MON_SHIFT 0x06 >> +#define TPS65917_INT1_STATUS_HOTDIE 0x20 >> +#define TPS65917_INT1_STATUS_HOTDIE_SHIFT 0x05 >> +#define TPS65917_INT1_STATUS_PWRDOWN 0x10 >> +#define TPS65917_INT1_STATUS_PWRDOWN_SHIFT 0x04 >> +#define TPS65917_INT1_STATUS_LONG_PRESS_KEY 0x04 >> +#define TPS65917_INT1_STATUS_LONG_PRESS_KEY_SHIFT 0x02 >> +#define TPS65917_INT1_STATUS_PWRON 0x02 >> +#define TPS65917_INT1_STATUS_PWRON_SHIFT 0x01 >> + >> +/* Bit definitions for INT1_MASK */ >> +#define TPS65917_INT1_MASK_VSYS_MON 0x40 >> +#define TPS65917_INT1_MASK_VSYS_MON_SHIFT 0x06 >> +#define TPS65917_INT1_MASK_HOTDIE 0x20 >> +#define TPS65917_INT1_MASK_HOTDIE_SHIFT 0x05 >> +#define TPS65917_INT1_MASK_PWRDOWN 0x10 >> +#define TPS65917_INT1_MASK_PWRDOWN_SHIFT 0x04 >> +#define TPS65917_INT1_MASK_LONG_PRESS_KEY 0x04 >> +#define TPS65917_INT1_MASK_LONG_PRESS_KEY_SHIFT 0x02 >> +#define TPS65917_INT1_MASK_PWRON 0x02 >> +#define TPS65917_INT1_MASK_PWRON_SHIFT 0x01 >> + >> +/* Bit definitions for INT1_LINE_STATE */ >> +#define TPS65917_INT1_LINE_STATE_VSYS_MON 0x40 >> +#define TPS65917_INT1_LINE_STATE_VSYS_MON_SHIFT 0x06 >> +#define TPS65917_INT1_LINE_STATE_HOTDIE 0x20 >> +#define TPS65917_INT1_LINE_STATE_HOTDIE_SHIFT 0x05 >> +#define TPS65917_INT1_LINE_STATE_PWRDOWN 0x10 >> +#define TPS65917_INT1_LINE_STATE_PWRDOWN_SHIFT 0x04 >> +#define TPS65917_INT1_LINE_STATE_LONG_PRESS_KEY 0x04 >> +#define TPS65917_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT 0x02 >> +#define TPS65917_INT1_LINE_STATE_PWRON 0x02 >> +#define TPS65917_INT1_LINE_STATE_PWRON_SHIFT 0x01 >> + >> +/* Bit definitions for INT2_STATUS */ >> +#define TPS65917_INT2_STATUS_SHORT 0x40 >> +#define TPS65917_INT2_STATUS_SHORT_SHIFT 0x06 >> +#define TPS65917_INT2_STATUS_FSD 0x20 >> +#define TPS65917_INT2_STATUS_FSD_SHIFT 0x05 >> +#define TPS65917_INT2_STATUS_RESET_IN 0x10 >> +#define TPS65917_INT2_STATUS_RESET_IN_SHIFT 0x04 >> +#define TPS65917_INT2_STATUS_WDT 0x04 >> +#define TPS65917_INT2_STATUS_WDT_SHIFT 0x02 >> +#define TPS65917_INT2_STATUS_OTP_ERROR 0x02 >> +#define TPS65917_INT2_STATUS_OTP_ERROR_SHIFT 0x01 >> + >> +/* Bit definitions for INT2_MASK */ >> +#define TPS65917_INT2_MASK_SHORT 0x40 >> +#define TPS65917_INT2_MASK_SHORT_SHIFT 0x06 >> +#define TPS65917_INT2_MASK_FSD 0x20 >> +#define TPS65917_INT2_MASK_FSD_SHIFT 0x05 >> +#define TPS65917_INT2_MASK_RESET_IN 0x10 >> +#define TPS65917_INT2_MASK_RESET_IN_SHIFT 0x04 >> +#define TPS65917_INT2_MASK_WDT 0x04 >> +#define TPS65917_INT2_MASK_WDT_SHIFT 0x02 >> +#define TPS65917_INT2_MASK_OTP_ERROR_TIMER 0x02 >> +#define TPS65917_INT2_MASK_OTP_ERROR_SHIFT 0x01 >> + >> +/* Bit definitions for INT2_LINE_STATE */ >> +#define TPS65917_INT2_LINE_STATE_SHORT 0x40 >> +#define TPS65917_INT2_LINE_STATE_SHORT_SHIFT 0x06 >> +#define TPS65917_INT2_LINE_STATE_FSD 0x20 >> +#define TPS65917_INT2_LINE_STATE_FSD_SHIFT 0x05 >> +#define TPS65917_INT2_LINE_STATE_RESET_IN 0x10 >> +#define TPS65917_INT2_LINE_STATE_RESET_IN_SHIFT 0x04 >> +#define TPS65917_INT2_LINE_STATE_WDT 0x04 >> +#define TPS65917_INT2_LINE_STATE_WDT_SHIFT 0x02 >> +#define TPS65917_INT2_LINE_STATE_OTP_ERROR 0x02 >> +#define TPS65917_INT2_LINE_STATE_OTP_ERROR_SHIFT 0x01 >> + >> +/* Bit definitions for INT3_STATUS */ >> +#define TPS65917_INT3_STATUS_VBUS 0x80 >> +#define TPS65917_INT3_STATUS_VBUS_SHIFT 0x07 >> +#define TPS65917_INT3_STATUS_GPADC_EOC_SW 0x04 >> +#define TPS65917_INT3_STATUS_GPADC_EOC_SW_SHIFT 0x02 >> +#define TPS65917_INT3_STATUS_GPADC_AUTO_1 0x02 >> +#define TPS65917_INT3_STATUS_GPADC_AUTO_1_SHIFT 0x01 >> +#define TPS65917_INT3_STATUS_GPADC_AUTO_0 0x01 >> +#define TPS65917_INT3_STATUS_GPADC_AUTO_0_SHIFT 0x00 >> + >> +/* Bit definitions for INT3_MASK */ >> +#define TPS65917_INT3_MASK_VBUS 0x80 >> +#define TPS65917_INT3_MASK_VBUS_SHIFT 0x07 >> +#define TPS65917_INT3_MASK_GPADC_EOC_SW 0x04 >> +#define TPS65917_INT3_MASK_GPADC_EOC_SW_SHIFT 0x02 >> +#define TPS65917_INT3_MASK_GPADC_AUTO_1 0x02 >> +#define TPS65917_INT3_MASK_GPADC_AUTO_1_SHIFT 0x01 >> +#define TPS65917_INT3_MASK_GPADC_AUTO_0 0x01 >> +#define TPS65917_INT3_MASK_GPADC_AUTO_0_SHIFT 0x00 >> + >> +/* Bit definitions for INT3_LINE_STATE */ >> +#define TPS65917_INT3_LINE_STATE_VBUS 0x80 >> +#define TPS65917_INT3_LINE_STATE_VBUS_SHIFT 0x07 >> +#define TPS65917_INT3_LINE_STATE_GPADC_EOC_SW 0x04 >> +#define TPS65917_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT 0x02 >> +#define TPS65917_INT3_LINE_STATE_GPADC_AUTO_1 0x02 >> +#define TPS65917_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT 0x01 >> +#define TPS65917_INT3_LINE_STATE_GPADC_AUTO_0 0x01 >> +#define TPS65917_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT 0x00 >> + >> +/* Bit definitions for INT4_STATUS */ >> +#define TPS65917_INT4_STATUS_GPIO_6 0x40 >> +#define TPS65917_INT4_STATUS_GPIO_6_SHIFT 0x06 >> +#define TPS65917_INT4_STATUS_GPIO_5 0x20 >> +#define TPS65917_INT4_STATUS_GPIO_5_SHIFT 0x05 >> +#define TPS65917_INT4_STATUS_GPIO_4 0x10 >> +#define TPS65917_INT4_STATUS_GPIO_4_SHIFT 0x04 >> +#define TPS65917_INT4_STATUS_GPIO_3 0x08 >> +#define TPS65917_INT4_STATUS_GPIO_3_SHIFT 0x03 >> +#define TPS65917_INT4_STATUS_GPIO_2 0x04 >> +#define TPS65917_INT4_STATUS_GPIO_2_SHIFT 0x02 >> +#define TPS65917_INT4_STATUS_GPIO_1 0x02 >> +#define TPS65917_INT4_STATUS_GPIO_1_SHIFT 0x01 >> +#define TPS65917_INT4_STATUS_GPIO_0 0x01 >> +#define TPS65917_INT4_STATUS_GPIO_0_SHIFT 0x00 >> + >> +/* Bit definitions for INT4_MASK */ >> +#define TPS65917_INT4_MASK_GPIO_6 0x40 >> +#define TPS65917_INT4_MASK_GPIO_6_SHIFT 0x06 >> +#define TPS65917_INT4_MASK_GPIO_5 0x20 >> +#define TPS65917_INT4_MASK_GPIO_5_SHIFT 0x05 >> +#define TPS65917_INT4_MASK_GPIO_4 0x10 >> +#define TPS65917_INT4_MASK_GPIO_4_SHIFT 0x04 >> +#define TPS65917_INT4_MASK_GPIO_3 0x08 >> +#define TPS65917_INT4_MASK_GPIO_3_SHIFT 0x03 >> +#define TPS65917_INT4_MASK_GPIO_2 0x04 >> +#define TPS65917_INT4_MASK_GPIO_2_SHIFT 0x02 >> +#define TPS65917_INT4_MASK_GPIO_1 0x02 >> +#define TPS65917_INT4_MASK_GPIO_1_SHIFT 0x01 >> +#define TPS65917_INT4_MASK_GPIO_0 0x01 >> +#define TPS65917_INT4_MASK_GPIO_0_SHIFT 0x00 >> + >> +/* Bit definitions for INT4_LINE_STATE */ >> +#define TPS65917_INT4_LINE_STATE_GPIO_6 0x40 >> +#define TPS65917_INT4_LINE_STATE_GPIO_6_SHIFT 0x06 >> +#define TPS65917_INT4_LINE_STATE_GPIO_5 0x20 >> +#define TPS65917_INT4_LINE_STATE_GPIO_5_SHIFT 0x05 >> +#define TPS65917_INT4_LINE_STATE_GPIO_4 0x10 >> +#define TPS65917_INT4_LINE_STATE_GPIO_4_SHIFT 0x04 >> +#define TPS65917_INT4_LINE_STATE_GPIO_3 0x08 >> +#define TPS65917_INT4_LINE_STATE_GPIO_3_SHIFT 0x03 >> +#define TPS65917_INT4_LINE_STATE_GPIO_2 0x04 >> +#define TPS65917_INT4_LINE_STATE_GPIO_2_SHIFT 0x02 >> +#define TPS65917_INT4_LINE_STATE_GPIO_1 0x02 >> +#define TPS65917_INT4_LINE_STATE_GPIO_1_SHIFT 0x01 >> +#define TPS65917_INT4_LINE_STATE_GPIO_0 0x01 >> +#define TPS65917_INT4_LINE_STATE_GPIO_0_SHIFT 0x00 >> + >> +/* Bit definitions for INT4_EDGE_DETECT1 */ >> +#define TPS65917_INT4_EDGE_DETECT1_GPIO_3_RISING 0x80 >> +#define TPS65917_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT 0x07 >> +#define TPS65917_INT4_EDGE_DETECT1_GPIO_3_FALLING 0x40 >> +#define TPS65917_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT 0x06 >> +#define TPS65917_INT4_EDGE_DETECT1_GPIO_2_RISING 0x20 >> +#define TPS65917_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT 0x05 >> +#define TPS65917_INT4_EDGE_DETECT1_GPIO_2_FALLING 0x10 >> +#define TPS65917_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT 0x04 >> +#define TPS65917_INT4_EDGE_DETECT1_GPIO_1_RISING 0x08 >> +#define TPS65917_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT 0x03 >> +#define TPS65917_INT4_EDGE_DETECT1_GPIO_1_FALLING 0x04 >> +#define TPS65917_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT 0x02 >> +#define TPS65917_INT4_EDGE_DETECT1_GPIO_0_RISING 0x02 >> +#define TPS65917_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT 0x01 >> +#define TPS65917_INT4_EDGE_DETECT1_GPIO_0_FALLING 0x01 >> +#define TPS65917_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT 0x00 >> + >> +/* Bit definitions for INT4_EDGE_DETECT2 */ >> +#define TPS65917_INT4_EDGE_DETECT2_GPIO_6_RISING 0x20 >> +#define TPS65917_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT 0x05 >> +#define TPS65917_INT4_EDGE_DETECT2_GPIO_6_FALLING 0x10 >> +#define TPS65917_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT 0x04 >> +#define TPS65917_INT4_EDGE_DETECT2_GPIO_5_RISING 0x08 >> +#define TPS65917_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT 0x03 >> +#define TPS65917_INT4_EDGE_DETECT2_GPIO_5_FALLING 0x04 >> +#define TPS65917_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT 0x02 >> +#define TPS65917_INT4_EDGE_DETECT2_GPIO_4_RISING 0x02 >> +#define TPS65917_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT 0x01 >> +#define TPS65917_INT4_EDGE_DETECT2_GPIO_4_FALLING 0x01 >> +#define TPS65917_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT 0x00 >> + >> +/* Bit definitions for INT_CTRL */ >> +#define TPS65917_INT_CTRL_INT_PENDING 0x04 >> +#define TPS65917_INT_CTRL_INT_PENDING_SHIFT 0x02 >> +#define TPS65917_INT_CTRL_INT_CLEAR 0x01 >> +#define TPS65917_INT_CTRL_INT_CLEAR_SHIFT 0x00 >> + >> +/* TPS65917 SMPS Registers */ >> + >> +/* Registers for function SMPS */ >> +#define TPS65917_SMPS1_CTRL 0x00 >> +#define TPS65917_SMPS1_FORCE 0x02 >> +#define TPS65917_SMPS1_VOLTAGE 0x03 >> +#define TPS65917_SMPS2_CTRL 0x04 >> +#define TPS65917_SMPS2_FORCE 0x06 >> +#define TPS65917_SMPS2_VOLTAGE 0x07 >> +#define TPS65917_SMPS3_CTRL 0x0C >> +#define TPS65917_SMPS3_FORCE 0x0E >> +#define TPS65917_SMPS3_VOLTAGE 0x0F >> +#define TPS65917_SMPS4_CTRL 0x10 >> +#define TPS65917_SMPS4_VOLTAGE 0x13 >> +#define TPS65917_SMPS5_CTRL 0x18 >> +#define TPS65917_SMPS5_VOLTAGE 0x1B >> +#define TPS65917_SMPS_CTRL 0x24 >> +#define TPS65917_SMPS_PD_CTRL 0x25 >> +#define TPS65917_SMPS_THERMAL_EN 0x27 >> +#define TPS65917_SMPS_THERMAL_STATUS 0x28 >> +#define TPS65917_SMPS_SHORT_STATUS 0x29 >> +#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN 0x2A >> +#define TPS65917_SMPS_POWERGOOD_MASK1 0x2B >> +#define TPS65917_SMPS_POWERGOOD_MASK2 0x2C >> + >> +/* Bit definitions for SMPS1_CTRL */ >> +#define TPS65917_SMPS1_CTRL_WR_S 0x80 >> +#define TPS65917_SMPS1_CTRL_WR_S_SHIFT 0x07 >> +#define TPS65917_SMPS1_CTRL_ROOF_FLOOR_EN 0x40 >> +#define TPS65917_SMPS1_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 >> +#define TPS65917_SMPS1_CTRL_STATUS_MASK 0x30 >> +#define TPS65917_SMPS1_CTRL_STATUS_SHIFT 0x04 >> +#define TPS65917_SMPS1_CTRL_MODE_SLEEP_MASK 0x0C >> +#define TPS65917_SMPS1_CTRL_MODE_SLEEP_SHIFT 0x02 >> +#define TPS65917_SMPS1_CTRL_MODE_ACTIVE_MASK 0x03 >> +#define TPS65917_SMPS1_CTRL_MODE_ACTIVE_SHIFT 0x00 >> + >> +/* Bit definitions for SMPS1_FORCE */ >> +#define TPS65917_SMPS1_FORCE_CMD 0x80 >> +#define TPS65917_SMPS1_FORCE_CMD_SHIFT 0x07 >> +#define TPS65917_SMPS1_FORCE_VSEL_MASK 0x7F >> +#define TPS65917_SMPS1_FORCE_VSEL_SHIFT 0x00 >> + >> +/* Bit definitions for SMPS1_VOLTAGE */ >> +#define TPS65917_SMPS1_VOLTAGE_RANGE 0x80 >> +#define TPS65917_SMPS1_VOLTAGE_RANGE_SHIFT 0x07 >> +#define TPS65917_SMPS1_VOLTAGE_VSEL_MASK 0x7F >> +#define TPS65917_SMPS1_VOLTAGE_VSEL_SHIFT 0x00 >> + >> +/* Bit definitions for SMPS2_CTRL */ >> +#define TPS65917_SMPS2_CTRL_WR_S 0x80 >> +#define TPS65917_SMPS2_CTRL_WR_S_SHIFT 0x07 >> +#define TPS65917_SMPS2_CTRL_ROOF_FLOOR_EN 0x40 >> +#define TPS65917_SMPS2_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 >> +#define TPS65917_SMPS2_CTRL_STATUS_MASK 0x30 >> +#define TPS65917_SMPS2_CTRL_STATUS_SHIFT 0x04 >> +#define TPS65917_SMPS2_CTRL_MODE_SLEEP_MASK 0x0C >> +#define TPS65917_SMPS2_CTRL_MODE_SLEEP_SHIFT 0x02 >> +#define TPS65917_SMPS2_CTRL_MODE_ACTIVE_MASK 0x03 >> +#define TPS65917_SMPS2_CTRL_MODE_ACTIVE_SHIFT 0x00 >> + >> +/* Bit definitions for SMPS2_FORCE */ >> +#define TPS65917_SMPS2_FORCE_CMD 0x80 >> +#define TPS65917_SMPS2_FORCE_CMD_SHIFT 0x07 >> +#define TPS65917_SMPS2_FORCE_VSEL_MASK 0x7F >> +#define TPS65917_SMPS2_FORCE_VSEL_SHIFT 0x00 >> + >> +/* Bit definitions for SMPS2_VOLTAGE */ >> +#define TPS65917_SMPS2_VOLTAGE_RANGE 0x80 >> +#define TPS65917_SMPS2_VOLTAGE_RANGE_SHIFT 0x07 >> +#define TPS65917_SMPS2_VOLTAGE_VSEL_MASK 0x7F >> +#define TPS65917_SMPS2_VOLTAGE_VSEL_SHIFT 0x00 >> + >> +/* Bit definitions for SMPS3_CTRL */ >> +#define TPS65917_SMPS3_CTRL_WR_S 0x80 >> +#define TPS65917_SMPS3_CTRL_WR_S_SHIFT 0x07 >> +#define TPS65917_SMPS3_CTRL_ROOF_FLOOR_EN 0x40 >> +#define TPS65917_SMPS3_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 >> +#define TPS65917_SMPS3_CTRL_STATUS_MASK 0x30 >> +#define TPS65917_SMPS3_CTRL_STATUS_SHIFT 0x04 >> +#define TPS65917_SMPS3_CTRL_MODE_SLEEP_MASK 0x0C >> +#define TPS65917_SMPS3_CTRL_MODE_SLEEP_SHIFT 0x02 >> +#define TPS65917_SMPS3_CTRL_MODE_ACTIVE_MASK 0x03 >> +#define TPS65917_SMPS3_CTRL_MODE_ACTIVE_SHIFT 0x00 >> + >> +/* Bit definitions for SMPS3_FORCE */ >> +#define TPS65917_SMPS3_FORCE_CMD 0x80 >> +#define TPS65917_SMPS3_FORCE_CMD_SHIFT 0x07 >> +#define TPS65917_SMPS3_FORCE_VSEL_MASK 0x7F >> +#define TPS65917_SMPS3_FORCE_VSEL_SHIFT 0x00 >> + >> +/* Bit definitions for SMPS3_VOLTAGE */ >> +#define TPS65917_SMPS3_VOLTAGE_RANGE 0x80 >> +#define TPS65917_SMPS3_VOLTAGE_RANGE_SHIFT 0x07 >> +#define TPS65917_SMPS3_VOLTAGE_VSEL_MASK 0x7F >> +#define TPS65917_SMPS3_VOLTAGE_VSEL_SHIFT 0x00 >> + >> +/* Bit definitions for SMPS4_CTRL */ >> +#define TPS65917_SMPS4_CTRL_WR_S 0x80 >> +#define TPS65917_SMPS4_CTRL_WR_S_SHIFT 0x07 >> +#define TPS65917_SMPS4_CTRL_ROOF_FLOOR_EN 0x40 >> +#define TPS65917_SMPS4_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 >> +#define TPS65917_SMPS4_CTRL_STATUS_MASK 0x30 >> +#define TPS65917_SMPS4_CTRL_STATUS_SHIFT 0x04 >> +#define TPS65917_SMPS4_CTRL_MODE_SLEEP_MASK 0x0C >> +#define TPS65917_SMPS4_CTRL_MODE_SLEEP_SHIFT 0x02 >> +#define TPS65917_SMPS4_CTRL_MODE_ACTIVE_MASK 0x03 >> +#define TPS65917_SMPS4_CTRL_MODE_ACTIVE_SHIFT 0x00 >> + >> +/* Bit definitions for SMPS4_VOLTAGE */ >> +#define TPS65917_SMPS4_VOLTAGE_RANGE 0x80 >> +#define TPS65917_SMPS4_VOLTAGE_RANGE_SHIFT 0x07 >> +#define TPS65917_SMPS4_VOLTAGE_VSEL_MASK 0x7F >> +#define TPS65917_SMPS4_VOLTAGE_VSEL_SHIFT 0x00 >> + >> +/* Bit definitions for SMPS5_CTRL */ >> +#define TPS65917_SMPS5_CTRL_WR_S 0x80 >> +#define TPS65917_SMPS5_CTRL_WR_S_SHIFT 0x07 >> +#define TPS65917_SMPS5_CTRL_ROOF_FLOOR_EN 0x40 >> +#define TPS65917_SMPS5_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 >> +#define TPS65917_SMPS5_CTRL_STATUS_MASK 0x30 >> +#define TPS65917_SMPS5_CTRL_STATUS_SHIFT 0x04 >> +#define TPS65917_SMPS5_CTRL_MODE_SLEEP_MASK 0x0C >> +#define TPS65917_SMPS5_CTRL_MODE_SLEEP_SHIFT 0x02 >> +#define TPS65917_SMPS5_CTRL_MODE_ACTIVE_MASK 0x03 >> +#define TPS65917_SMPS5_CTRL_MODE_ACTIVE_SHIFT 0x00 >> + >> +/* Bit definitions for SMPS5_VOLTAGE */ >> +#define TPS65917_SMPS5_VOLTAGE_RANGE 0x80 >> +#define TPS65917_SMPS5_VOLTAGE_RANGE_SHIFT 0x07 >> +#define TPS65917_SMPS5_VOLTAGE_VSEL_MASK 0x7F >> +#define TPS65917_SMPS5_VOLTAGE_VSEL_SHIFT 0x00 >> + >> +/* Bit definitions for SMPS_CTRL */ >> +#define TPS65917_SMPS_CTRL_SMPS1_SMPS12_EN 0x10 >> +#define TPS65917_SMPS_CTRL_SMPS1_SMPS12_EN_SHIFT 0x04 >> +#define TPS65917_SMPS_CTRL_SMPS12_PHASE_CTRL 0x03 >> +#define TPS65917_SMPS_CTRL_SMPS12_PHASE_CTRL_SHIFT 0x00 >> + >> +/* Bit definitions for SMPS_PD_CTRL */ >> +#define TPS65917_SMPS_PD_CTRL_SMPS5 0x40 >> +#define TPS65917_SMPS_PD_CTRL_SMPS5_SHIFT 0x06 >> +#define TPS65917_SMPS_PD_CTRL_SMPS4 0x10 >> +#define TPS65917_SMPS_PD_CTRL_SMPS4_SHIFT 0x04 >> +#define TPS65917_SMPS_PD_CTRL_SMPS3 0x08 >> +#define TPS65917_SMPS_PD_CTRL_SMPS3_SHIFT 0x03 >> +#define TPS65917_SMPS_PD_CTRL_SMPS2 0x02 >> +#define TPS65917_SMPS_PD_CTRL_SMPS2_SHIFT 0x01 >> +#define TPS65917_SMPS_PD_CTRL_SMPS1 0x01 >> +#define TPS65917_SMPS_PD_CTRL_SMPS1_SHIFT 0x00 >> + >> +/* Bit definitions for SMPS_THERMAL_EN */ >> +#define TPS65917_SMPS_THERMAL_EN_SMPS5 0x40 >> +#define TPS65917_SMPS_THERMAL_EN_SMPS5_SHIFT 0x06 >> +#define TPS65917_SMPS_THERMAL_EN_SMPS3 0x08 >> +#define TPS65917_SMPS_THERMAL_EN_SMPS3_SHIFT 0x03 >> +#define TPS65917_SMPS_THERMAL_EN_SMPS12 0x01 >> +#define TPS65917_SMPS_THERMAL_EN_SMPS12_SHIFT 0x00 >> + >> +/* Bit definitions for SMPS_THERMAL_STATUS */ >> +#define TPS65917_SMPS_THERMAL_STATUS_SMPS5 0x40 >> +#define TPS65917_SMPS_THERMAL_STATUS_SMPS5_SHIFT 0x06 >> +#define TPS65917_SMPS_THERMAL_STATUS_SMPS3 0x08 >> +#define TPS65917_SMPS_THERMAL_STATUS_SMPS3_SHIFT 0x03 >> +#define TPS65917_SMPS_THERMAL_STATUS_SMPS12 0x01 >> +#define TPS65917_SMPS_THERMAL_STATUS_SMPS12_SHIFT 0x00 >> + >> +/* Bit definitions for SMPS_SHORT_STATUS */ >> +#define TPS65917_SMPS_SHORT_STATUS_SMPS5 0x40 >> +#define TPS65917_SMPS_SHORT_STATUS_SMPS5_SHIFT 0x06 >> +#define TPS65917_SMPS_SHORT_STATUS_SMPS4 0x10 >> +#define TPS65917_SMPS_SHORT_STATUS_SMPS4_SHIFT 0x04 >> +#define TPS65917_SMPS_SHORT_STATUS_SMPS3 0x08 >> +#define TPS65917_SMPS_SHORT_STATUS_SMPS3_SHIFT 0x03 >> +#define TPS65917_SMPS_SHORT_STATUS_SMPS2 0x02 >> +#define TPS65917_SMPS_SHORT_STATUS_SMPS2_SHIFT 0x01 >> +#define TPS65917_SMPS_SHORT_STATUS_SMPS1 0x01 >> +#define TPS65917_SMPS_SHORT_STATUS_SMPS1_SHIFT 0x00 >> + >> +/* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */ >> +#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS5 0x40 >> +#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS5_SHIFT 0x06 >> +#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS4 0x10 >> +#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS4_SHIFT 0x04 >> +#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3 0x08 >> +#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT 0x03 >> +#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS2 0x02 >> +#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS2_SHIFT 0x01 >> +#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS1 0x01 >> +#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS1_SHIFT 0x00 >> + >> +/* Bit definitions for SMPS_POWERGOOD_MASK1 */ >> +#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS5 0x40 >> +#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS5_SHIFT 0x06 >> +#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS4 0x10 >> +#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS4_SHIFT 0x04 >> +#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS3 0x08 >> +#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT 0x03 >> +#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS2 0x02 >> +#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS2_SHIFT 0x01 >> +#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS1 0x01 >> +#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS1_SHIFT 0x00 >> + >> +/* Bit definitions for SMPS_POWERGOOD_MASK2 */ >> +#define TPS65917_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT 0x80 >> +#define TPS65917_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT 0x07 >> +#define TPS65917_SMPS_POWERGOOD_MASK2_OVC_ALARM_SHIFT 0x10 >> +#define TPS65917_SMPS_POWERGOOD_MASK2_OVC_ALARM 0x04 >> + >> +/* Bit definitions for SMPS_PLL_CTRL */ >> + >> +#define TPS65917_SMPS_PLL_CTRL_PLL_EN_PLL_BYPASS_SHIFT 0x08 >> +#define TPS65917_SMPS_PLL_CTRL_PLL_PLL_EN_BYPASS 0x03 >> +#define TPS65917_SMPS_PLL_CTRL_PLL_PLL_BYPASS_CLK_SHIFT 0x04 >> +#define TPS65917_SMPS_PLL_CTRL_PLL_PLL_BYPASS_CLK 0x02 >> + >> +/* Registers for function LDO */ >> +#define TPS65917_LDO1_CTRL 0x00 >> +#define TPS65917_LDO1_VOLTAGE 0x01 >> +#define TPS65917_LDO2_CTRL 0x02 >> +#define TPS65917_LDO2_VOLTAGE 0x03 >> +#define TPS65917_LDO3_CTRL 0x04 >> +#define TPS65917_LDO3_VOLTAGE 0x05 >> +#define TPS65917_LDO4_CTRL 0x0E >> +#define TPS65917_LDO4_VOLTAGE 0x0F >> +#define TPS65917_LDO5_CTRL 0x12 >> +#define TPS65917_LDO5_VOLTAGE 0x13 >> +#define TPS65917_LDO_PD_CTRL1 0x1B >> +#define TPS65917_LDO_PD_CTRL2 0x1C >> +#define TPS65917_LDO_SHORT_STATUS1 0x1D >> +#define TPS65917_LDO_SHORT_STATUS2 0x1E >> +#define TPS65917_LDO_PD_CTRL3 0x2D >> +#define TPS65917_LDO_SHORT_STATUS3 0x2E >> + >> +/* Bit definitions for LDO1_CTRL */ >> +#define TPS65917_LDO1_CTRL_WR_S 0x80 >> +#define TPS65917_LDO1_CTRL_WR_S_SHIFT 0x07 >> +#define TPS65917_LDO1_CTRL_BYPASS_EN 0x40 >> +#define TPS65917_LDO1_CTRL_BYPASS_EN_SHIFT 0x06 >> +#define TPS65917_LDO1_CTRL_STATUS 0x10 >> +#define TPS65917_LDO1_CTRL_STATUS_SHIFT 0x04 >> +#define TPS65917_LDO1_CTRL_MODE_SLEEP 0x04 >> +#define TPS65917_LDO1_CTRL_MODE_SLEEP_SHIFT 0x02 >> +#define TPS65917_LDO1_CTRL_MODE_ACTIVE 0x01 >> +#define TPS65917_LDO1_CTRL_MODE_ACTIVE_SHIFT 0x00 >> + >> +/* Bit definitions for LDO1_VOLTAGE */ >> +#define TPS65917_LDO1_VOLTAGE_VSEL_MASK 0x2F >> +#define TPS65917_LDO1_VOLTAGE_VSEL_SHIFT 0x00 >> + >> +/* Bit definitions for LDO2_CTRL */ >> +#define TPS65917_LDO2_CTRL_WR_S 0x80 >> +#define TPS65917_LDO2_CTRL_WR_S_SHIFT 0x07 >> +#define TPS65917_LDO2_CTRL_BYPASS_EN 0x40 >> +#define TPS65917_LDO2_CTRL_BYPASS_EN_SHIFT 0x06 >> +#define TPS65917_LDO2_CTRL_STATUS 0x10 >> +#define TPS65917_LDO2_CTRL_STATUS_SHIFT 0x04 >> +#define TPS65917_LDO2_CTRL_MODE_SLEEP 0x04 >> +#define TPS65917_LDO2_CTRL_MODE_SLEEP_SHIFT 0x02 >> +#define TPS65917_LDO2_CTRL_MODE_ACTIVE 0x01 >> +#define TPS65917_LDO2_CTRL_MODE_ACTIVE_SHIFT 0x00 >> + >> +/* Bit definitions for LDO2_VOLTAGE */ >> +#define TPS65917_LDO2_VOLTAGE_VSEL_MASK 0x2F >> +#define TPS65917_LDO2_VOLTAGE_VSEL_SHIFT 0x00 >> + >> +/* Bit definitions for LDO3_CTRL */ >> +#define TPS65917_LDO3_CTRL_WR_S 0x80 >> +#define TPS65917_LDO3_CTRL_WR_S_SHIFT 0x07 >> +#define TPS65917_LDO3_CTRL_STATUS 0x10 >> +#define TPS65917_LDO3_CTRL_STATUS_SHIFT 0x04 >> +#define TPS65917_LDO3_CTRL_MODE_SLEEP 0x04 >> +#define TPS65917_LDO3_CTRL_MODE_SLEEP_SHIFT 0x02 >> +#define TPS65917_LDO3_CTRL_MODE_ACTIVE 0x01 >> +#define TPS65917_LDO3_CTRL_MODE_ACTIVE_SHIFT 0x00 >> + >> +/* Bit definitions for LDO3_VOLTAGE */ >> +#define TPS65917_LDO3_VOLTAGE_VSEL_MASK 0x2F >> +#define TPS65917_LDO3_VOLTAGE_VSEL_SHIFT 0x00 >> + >> +/* Bit definitions for LDO4_CTRL */ >> +#define TPS65917_LDO4_CTRL_WR_S 0x80 >> +#define TPS65917_LDO4_CTRL_WR_S_SHIFT 0x07 >> +#define TPS65917_LDO4_CTRL_STATUS 0x10 >> +#define TPS65917_LDO4_CTRL_STATUS_SHIFT 0x04 >> +#define TPS65917_LDO4_CTRL_MODE_SLEEP 0x04 >> +#define TPS65917_LDO4_CTRL_MODE_SLEEP_SHIFT 0x02 >> +#define TPS65917_LDO4_CTRL_MODE_ACTIVE 0x01 >> +#define TPS65917_LDO4_CTRL_MODE_ACTIVE_SHIFT 0x00 >> + >> +/* Bit definitions for LDO4_VOLTAGE */ >> +#define TPS65917_LDO4_VOLTAGE_VSEL_MASK 0x2F >> +#define TPS65917_LDO4_VOLTAGE_VSEL_SHIFT 0x00 >> + >> +/* Bit definitions for LDO5_CTRL */ >> +#define TPS65917_LDO5_CTRL_WR_S 0x80 >> +#define TPS65917_LDO5_CTRL_WR_S_SHIFT 0x07 >> +#define TPS65917_LDO5_CTRL_STATUS 0x10 >> +#define TPS65917_LDO5_CTRL_STATUS_SHIFT 0x04 >> +#define TPS65917_LDO5_CTRL_MODE_SLEEP 0x04 >> +#define TPS65917_LDO5_CTRL_MODE_SLEEP_SHIFT 0x02 >> +#define TPS65917_LDO5_CTRL_MODE_ACTIVE 0x01 >> +#define TPS65917_LDO5_CTRL_MODE_ACTIVE_SHIFT 0x00 >> + >> +/* Bit definitions for LDO5_VOLTAGE */ >> +#define TPS65917_LDO5_VOLTAGE_VSEL_MASK 0x2F >> +#define TPS65917_LDO5_VOLTAGE_VSEL_SHIFT 0x00 >> + >> +/* Bit definitions for LDO_PD_CTRL1 */ >> +#define TPS65917_LDO_PD_CTRL1_LDO4 0x80 >> +#define TPS65917_LDO_PD_CTRL1_LDO4_SHIFT 0x07 >> +#define TPS65917_LDO_PD_CTRL1_LDO2 0x02 >> +#define TPS65917_LDO_PD_CTRL1_LDO2_SHIFT 0x01 >> +#define TPS65917_LDO_PD_CTRL1_LDO1 0x01 >> +#define TPS65917_LDO_PD_CTRL1_LDO1_SHIFT 0x00 >> + >> +/* Bit definitions for LDO_PD_CTRL2 */ >> +#define TPS65917_LDO_PD_CTRL2_LDO3 0x04 >> +#define TPS65917_LDO_PD_CTRL2_LDO3_SHIFT 0x02 >> +#define TPS65917_LDO_PD_CTRL2_LDO5 0x02 >> +#define TPS65917_LDO_PD_CTRL2_LDO5_SHIFT 0x01 >> + >> +/* Bit definitions for LDO_PD_CTRL3 */ >> +#define TPS65917_LDO_PD_CTRL2_LDOVANA 0x80 >> +#define TPS65917_LDO_PD_CTRL2_LDOVANA_SHIFT 0x07 >> + >> +/* Bit definitions for LDO_SHORT_STATUS1 */ >> +#define TPS65917_LDO_SHORT_STATUS1_LDO4 0x80 >> +#define TPS65917_LDO_SHORT_STATUS1_LDO4_SHIFT 0x07 >> +#define TPS65917_LDO_SHORT_STATUS1_LDO2 0x02 >> +#define TPS65917_LDO_SHORT_STATUS1_LDO2_SHIFT 0x01 >> +#define TPS65917_LDO_SHORT_STATUS1_LDO1 0x01 >> +#define TPS65917_LDO_SHORT_STATUS1_LDO1_SHIFT 0x00 >> + >> +/* Bit definitions for LDO_SHORT_STATUS2 */ >> +#define TPS65917_LDO_SHORT_STATUS2_LDO3 0x04 >> +#define TPS65917_LDO_SHORT_STATUS2_LDO3_SHIFT 0x02 >> +#define TPS65917_LDO_SHORT_STATUS2_LDO5 0x02 >> +#define TPS65917_LDO_SHORT_STATUS2_LDO5_SHIFT 0x01 >> + >> +/* Bit definitions for LDO_SHORT_STATUS2 */ >> +#define TPS65917_LDO_SHORT_STATUS2_LDOVANA 0x80 >> +#define TPS65917_LDO_SHORT_STATUS2_LDOVANA_SHIFT 0x07 >> + >> +/* Bit definitions for REGEN1_CTRL */ >> +#define TPS65917_REGEN1_CTRL_STATUS 0x10 >> +#define TPS65917_REGEN1_CTRL_STATUS_SHIFT 0x04 >> +#define TPS65917_REGEN1_CTRL_MODE_SLEEP 0x04 >> +#define TPS65917_REGEN1_CTRL_MODE_SLEEP_SHIFT 0x02 >> +#define TPS65917_REGEN1_CTRL_MODE_ACTIVE 0x01 >> +#define TPS65917_REGEN1_CTRL_MODE_ACTIVE_SHIFT 0x00 >> + >> +/* Bit definitions for PLLEN_CTRL */ >> +#define TPS65917_PLLEN_CTRL_STATUS 0x10 >> +#define TPS65917_PLLEN_CTRL_STATUS_SHIFT 0x04 >> +#define TPS65917_PLLEN_CTRL_MODE_SLEEP 0x04 >> +#define TPS65917_PLLEN_CTRL_MODE_SLEEP_SHIFT 0x02 >> +#define TPS65917_PLLEN_CTRL_MODE_ACTIVE 0x01 >> +#define TPS65917_PLLEN_CTRL_MODE_ACTIVE_SHIFT 0x00 >> + >> +/* Bit definitions for REGEN2_CTRL */ >> +#define TPS65917_REGEN2_CTRL_STATUS 0x10 >> +#define TPS65917_REGEN2_CTRL_STATUS_SHIFT 0x04 >> +#define TPS65917_REGEN2_CTRL_MODE_SLEEP 0x04 >> +#define TPS65917_REGEN2_CTRL_MODE_SLEEP_SHIFT 0x02 >> +#define TPS65917_REGEN2_CTRL_MODE_ACTIVE 0x01 >> +#define TPS65917_REGEN2_CTRL_MODE_ACTIVE_SHIFT 0x00 >> + >> +/* Bit definitions for NSLEEP_RES_ASSIGN */ >> +#define TPS65917_NSLEEP_RES_ASSIGN_PLL_EN 0x08 >> +#define TPS65917_NSLEEP_RES_ASSIGN_PLL_EN_SHIFT 0x03 >> +#define TPS65917_NSLEEP_RES_ASSIGN_REGEN3 0x04 >> +#define TPS65917_NSLEEP_RES_ASSIGN_REGEN3_SHIFT 0x02 >> +#define TPS65917_NSLEEP_RES_ASSIGN_REGEN2 0x02 >> +#define TPS65917_NSLEEP_RES_ASSIGN_REGEN2_SHIFT 0x01 >> +#define TPS65917_NSLEEP_RES_ASSIGN_REGEN1 0x01 >> +#define TPS65917_NSLEEP_RES_ASSIGN_REGEN1_SHIFT 0x00 >> + >> +/* Bit definitions for NSLEEP_SMPS_ASSIGN */ >> +#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS5 0x40 >> +#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS5_SHIFT 0x06 >> +#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS4 0x10 >> +#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS4_SHIFT 0x04 >> +#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS3 0x08 >> +#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT 0x03 >> +#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS2 0x02 >> +#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS2_SHIFT 0x01 >> +#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS1 0x01 >> +#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS1_SHIFT 0x00 >> + >> +/* Bit definitions for NSLEEP_LDO_ASSIGN1 */ >> +#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO4 0x80 >> +#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT 0x07 >> +#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO2 0x02 >> +#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT 0x01 >> +#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO1 0x01 >> +#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT 0x00 >> + >> +/* Bit definitions for NSLEEP_LDO_ASSIGN2 */ >> +#define TPS65917_NSLEEP_LDO_ASSIGN2_LDO3 0x04 >> +#define TPS65917_NSLEEP_LDO_ASSIGN2_LDO3_SHIFT 0x02 >> +#define TPS65917_NSLEEP_LDO_ASSIGN2_LDO5 0x02 >> +#define TPS65917_NSLEEP_LDO_ASSIGN2_LDO5_SHIFT 0x01 >> + >> +/* Bit definitions for ENABLE1_RES_ASSIGN */ >> +#define TPS65917_ENABLE1_RES_ASSIGN_PLLEN 0x08 >> +#define TPS65917_ENABLE1_RES_ASSIGN_PLLEN_SHIFT 0x03 >> +#define TPS65917_ENABLE1_RES_ASSIGN_REGEN3 0x04 >> +#define TPS65917_ENABLE1_RES_ASSIGN_REGEN3_SHIFT 0x02 >> +#define TPS65917_ENABLE1_RES_ASSIGN_REGEN2 0x02 >> +#define TPS65917_ENABLE1_RES_ASSIGN_REGEN2_SHIFT 0x01 >> +#define TPS65917_ENABLE1_RES_ASSIGN_REGEN1 0x01 >> +#define TPS65917_ENABLE1_RES_ASSIGN_REGEN1_SHIFT 0x00 >> + >> +/* Bit definitions for ENABLE1_SMPS_ASSIGN */ >> +#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS5 0x40 >> +#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS5_SHIFT 0x06 >> +#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS4 0x10 >> +#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS4_SHIFT 0x04 >> +#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS3 0x08 >> +#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT 0x03 >> +#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS2 0x02 >> +#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS2_SHIFT 0x01 >> +#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS1 0x01 >> +#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS1_SHIFT 0x00 >> + >> +/* Bit definitions for ENABLE1_LDO_ASSIGN1 */ >> +#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO4 0x80 >> +#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT 0x07 >> +#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO2 0x02 >> +#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT 0x01 >> +#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO1 0x01 >> +#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT 0x00 >> + >> +/* Bit definitions for ENABLE1_LDO_ASSIGN2 */ >> +#define TPS65917_ENABLE1_LDO_ASSIGN2_LDO3 0x04 >> +#define TPS65917_ENABLE1_LDO_ASSIGN2_LDO3_SHIFT 0x02 >> +#define TPS65917_ENABLE1_LDO_ASSIGN2_LDO5 0x02 >> +#define TPS65917_ENABLE1_LDO_ASSIGN2_LDO5_SHIFT 0x01 >> + >> +/* Bit definitions for ENABLE2_RES_ASSIGN */ >> +#define TPS65917_ENABLE2_RES_ASSIGN_PLLEN 0x08 >> +#define TPS65917_ENABLE2_RES_ASSIGN_PLLEN_SHIFT 0x03 >> +#define TPS65917_ENABLE2_RES_ASSIGN_REGEN3 0x04 >> +#define TPS65917_ENABLE2_RES_ASSIGN_REGEN3_SHIFT 0x02 >> +#define TPS65917_ENABLE2_RES_ASSIGN_REGEN2 0x02 >> +#define TPS65917_ENABLE2_RES_ASSIGN_REGEN2_SHIFT 0x01 >> +#define TPS65917_ENABLE2_RES_ASSIGN_REGEN1 0x01 >> +#define TPS65917_ENABLE2_RES_ASSIGN_REGEN1_SHIFT 0x00 >> + >> +/* Bit definitions for ENABLE2_SMPS_ASSIGN */ >> +#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS5 0x40 >> +#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS5_SHIFT 0x06 >> +#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS4 0x10 >> +#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS4_SHIFT 0x04 >> +#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS3 0x08 >> +#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT 0x03 >> +#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS2 0x02 >> +#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS2_SHIFT 0x01 >> +#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS1 0x01 >> +#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS1_SHIFT 0x00 >> + >> +/* Bit definitions for ENABLE2_LDO_ASSIGN1 */ >> +#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO4 0x80 >> +#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT 0x07 >> +#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO2 0x02 >> +#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT 0x01 >> +#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO1 0x01 >> +#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT 0x00 >> + >> +/* Bit definitions for ENABLE2_LDO_ASSIGN2 */ >> +#define TPS65917_ENABLE2_LDO_ASSIGN2_LDO3 0x04 >> +#define TPS65917_ENABLE2_LDO_ASSIGN2_LDO3_SHIFT 0x02 >> +#define TPS65917_ENABLE2_LDO_ASSIGN2_LDO5 0x02 >> +#define TPS65917_ENABLE2_LDO_ASSIGN2_LDO5_SHIFT 0x01 >> + >> +/* Bit definitions for REGEN3_CTRL */ >> +#define TPS65917_REGEN3_CTRL_STATUS 0x10 >> +#define TPS65917_REGEN3_CTRL_STATUS_SHIFT 0x04 >> +#define TPS65917_REGEN3_CTRL_MODE_SLEEP 0x04 >> +#define TPS65917_REGEN3_CTRL_MODE_SLEEP_SHIFT 0x02 >> +#define TPS65917_REGEN3_CTRL_MODE_ACTIVE 0x01 >> +#define TPS65917_REGEN3_CTRL_MODE_ACTIVE_SHIFT 0x00 >> + >> +/* Registers for function RESOURCE */ >> +#define TPS65917_REGEN1_CTRL 0x2 >> +#define TPS65917_PLLEN_CTRL 0x3 >> +#define TPS65917_NSLEEP_RES_ASSIGN 0x6 >> +#define TPS65917_NSLEEP_SMPS_ASSIGN 0x7 >> +#define TPS65917_NSLEEP_LDO_ASSIGN1 0x8 >> +#define TPS65917_NSLEEP_LDO_ASSIGN2 0x9 >> +#define TPS65917_ENABLE1_RES_ASSIGN 0xA >> +#define TPS65917_ENABLE1_SMPS_ASSIGN 0xB >> +#define TPS65917_ENABLE1_LDO_ASSIGN1 0xC >> +#define TPS65917_ENABLE1_LDO_ASSIGN2 0xD >> +#define TPS65917_ENABLE2_RES_ASSIGN 0xE >> +#define TPS65917_ENABLE2_SMPS_ASSIGN 0xF >> +#define TPS65917_ENABLE2_LDO_ASSIGN1 0x10 >> +#define TPS65917_ENABLE2_LDO_ASSIGN2 0x11 >> +#define TPS65917_REGEN2_CTRL 0x12 >> +#define TPS65917_REGEN3_CTRL 0x13 >> + >> static inline int palmas_read(struct palmas *palmas, unsigned int base, >> unsigned int reg, unsigned int *val) >> { ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 4/5] mfd: palmas: Add tps65917 support 2014-05-26 9:56 [PATCH 0/5] tps65917: Add support for for TPS65917 PMIC Keerthy ` (2 preceding siblings ...) 2014-05-26 9:56 ` [PATCH 3/5] mfd: palmas: Add tps65917 specific definitions and enums Keerthy @ 2014-05-26 9:56 ` Keerthy 2014-05-27 8:38 ` Lee Jones 2014-05-26 9:56 ` [PATCH 5/5] regulator: tps65917: Add Regulator driver for tps65917 PMIC Keerthy 4 siblings, 1 reply; 13+ messages in thread From: Keerthy @ 2014-05-26 9:56 UTC (permalink / raw) To: linux-omap; +Cc: lgirdwood, broonie, linux-kernel, sameo, lee.jones, Keerthy Add tps65917 PMIC support. tps65917 is a subset of palmas PMIC. Some of the register definitions and the interrupt mappings are different. Signed-off-by: Keerthy <j-keerthy@ti.com> --- drivers/mfd/palmas.c | 177 ++++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 172 insertions(+), 5 deletions(-) diff --git a/drivers/mfd/palmas.c b/drivers/mfd/palmas.c index d280d78..e4684cc 100644 --- a/drivers/mfd/palmas.c +++ b/drivers/mfd/palmas.c @@ -92,6 +92,133 @@ static const struct regmap_config palmas_regmap_config[PALMAS_NUM_CLIENTS] = { }, }; +static const struct regmap_irq tps65917_irqs[] = { + /* INT1 IRQs */ + [TPS65917_RESERVED1] = { + .mask = TPS65917_RESERVED, + }, + [TPS65917_PWRON_IRQ] = { + .mask = TPS65917_INT1_STATUS_PWRON, + }, + [TPS65917_LONG_PRESS_KEY_IRQ] = { + .mask = TPS65917_INT1_STATUS_LONG_PRESS_KEY, + }, + [TPS65917_RESERVED2] = { + .mask = TPS65917_RESERVED, + }, + [TPS65917_PWRDOWN_IRQ] = { + .mask = TPS65917_INT1_STATUS_PWRDOWN, + }, + [TPS65917_HOTDIE_IRQ] = { + .mask = TPS65917_INT1_STATUS_HOTDIE, + }, + [TPS65917_VSYS_MON_IRQ] = { + .mask = TPS65917_INT1_STATUS_VSYS_MON, + }, + [TPS65917_RESERVED3] = { + .mask = TPS65917_RESERVED, + }, + /* INT2 IRQs*/ + [TPS65917_RESERVED4] = { + .mask = TPS65917_RESERVED, + .reg_offset = 1, + }, + [TPS65917_OTP_ERROR_IRQ] = { + .mask = TPS65917_INT2_STATUS_OTP_ERROR, + .reg_offset = 1, + }, + [TPS65917_WDT_IRQ] = { + .mask = TPS65917_INT2_STATUS_WDT, + .reg_offset = 1, + }, + [TPS65917_RESERVED5] = { + .mask = TPS65917_RESERVED, + .reg_offset = 1, + }, + [TPS65917_RESET_IN_IRQ] = { + .mask = TPS65917_INT2_STATUS_RESET_IN, + .reg_offset = 1, + }, + [TPS65917_FSD_IRQ] = { + .mask = TPS65917_INT2_STATUS_FSD, + .reg_offset = 1, + }, + [TPS65917_SHORT_IRQ] = { + .mask = TPS65917_INT2_STATUS_SHORT, + .reg_offset = 1, + }, + [TPS65917_RESERVED6] = { + .mask = TPS65917_RESERVED, + .reg_offset = 1, + }, + /* INT3 IRQs */ + [TPS65917_GPADC_AUTO_0_IRQ] = { + .mask = TPS65917_INT3_STATUS_GPADC_AUTO_0, + .reg_offset = 2, + }, + [TPS65917_GPADC_AUTO_1_IRQ] = { + .mask = TPS65917_INT3_STATUS_GPADC_AUTO_1, + .reg_offset = 2, + }, + [TPS65917_GPADC_EOC_SW_IRQ] = { + .mask = TPS65917_INT3_STATUS_GPADC_EOC_SW, + .reg_offset = 2, + }, + [TPS65917_RESREVED6] = { + .mask = TPS65917_RESERVED6, + .reg_offset = 2, + }, + [TPS65917_RESERVED7] = { + .mask = TPS65917_RESERVED, + .reg_offset = 2, + }, + [TPS65917_RESERVED8] = { + .mask = TPS65917_RESERVED, + .reg_offset = 2, + }, + [TPS65917_RESERVED9] = { + .mask = TPS65917_RESERVED, + .reg_offset = 2, + }, + [TPS65917_VBUS_IRQ] = { + .mask = TPS65917_INT3_STATUS_VBUS, + .reg_offset = 2, + }, + /* INT4 IRQs */ + [TPS65917_GPIO_0_IRQ] = { + .mask = TPS65917_INT4_STATUS_GPIO_0, + .reg_offset = 3, + }, + [TPS65917_GPIO_1_IRQ] = { + .mask = TPS65917_INT4_STATUS_GPIO_1, + .reg_offset = 3, + }, + [TPS65917_GPIO_2_IRQ] = { + .mask = TPS65917_INT4_STATUS_GPIO_2, + .reg_offset = 3, + }, + [TPS65917_GPIO_3_IRQ] = { + .mask = TPS65917_INT4_STATUS_GPIO_3, + .reg_offset = 3, + }, + [TPS65917_GPIO_4_IRQ] = { + .mask = TPS65917_INT4_STATUS_GPIO_4, + .reg_offset = 3, + }, + [TPS65917_GPIO_5_IRQ] = { + .mask = TPS65917_INT4_STATUS_GPIO_5, + .reg_offset = 3, + }, + [TPS65917_GPIO_6_IRQ] = { + .mask = TPS65917_INT4_STATUS_GPIO_6, + .reg_offset = 3, + }, + [TPS65917_RESERVED10] = { + .mask = TPS65917_RESERVED10, + .reg_offset = 3, + }, +}; + static const struct regmap_irq palmas_irqs[] = { /* INT1 IRQs */ [PALMAS_CHARG_DET_N_VBUS_OVV_IRQ] = { @@ -232,6 +359,19 @@ static struct regmap_irq_chip palmas_irq_chip = { PALMAS_INT1_MASK), }; +static struct regmap_irq_chip tps65917_irq_chip = { + .name = "tps65917", + .irqs = tps65917_irqs, + .num_irqs = ARRAY_SIZE(tps65917_irqs), + + .num_regs = 4, + .irq_reg_stride = 5, + .status_base = PALMAS_BASE_TO_REG(PALMAS_INTERRUPT_BASE, + PALMAS_INT1_STATUS), + .mask_base = PALMAS_BASE_TO_REG(PALMAS_INTERRUPT_BASE, + PALMAS_INT1_MASK), +}; + int palmas_ext_control_req_config(struct palmas *palmas, enum palmas_external_requestor_id id, int ext_ctrl, bool enable) { @@ -357,15 +497,40 @@ static void palmas_power_off(void) static unsigned int palmas_features = PALMAS_PMIC_FEATURE_SMPS10_BOOST; static unsigned int tps659038_features; +struct palmas_driver_data { + unsigned int *features; + struct regmap_irq_chip *irq_chip; +}; + +static struct palmas_driver_data palmas_data = { + .features = &palmas_features, + .irq_chip = &palmas_irq_chip, +}; + +static struct palmas_driver_data tps659038_data = { + .features = &tps659038_features, + .irq_chip = &palmas_irq_chip, +}; + +static struct palmas_driver_data tps65917_data = { + .features = &tps659038_features, + .irq_chip = &tps65917_irq_chip, +}; + static const struct of_device_id of_palmas_match_tbl[] = { { .compatible = "ti,palmas", - .data = &palmas_features, + .data = &palmas_data, }, { .compatible = "ti,tps659038", - .data = &tps659038_features, + .data = &tps659038_data, }, + { + .compatible = "ti,tps65917", + .data = &tps65917_data, + }, + { }, }; MODULE_DEVICE_TABLE(of, of_palmas_match_tbl); @@ -375,6 +540,7 @@ static int palmas_i2c_probe(struct i2c_client *i2c, { struct palmas *palmas; struct palmas_platform_data *pdata; + struct palmas_driver_data *driver_data; struct device_node *node = i2c->dev.of_node; int ret = 0, i; unsigned int reg, addr, *features; @@ -408,7 +574,8 @@ static int palmas_i2c_probe(struct i2c_client *i2c, if (!match) return -ENODATA; - features = (unsigned int *)match->data; + driver_data = (struct palmas_driver_data *)match->data; + features = (unsigned int *)driver_data->features; palmas->features = *features; for (i = 0; i < PALMAS_NUM_CLIENTS; i++) { @@ -463,8 +630,8 @@ static int palmas_i2c_probe(struct i2c_client *i2c, regmap_write(palmas->regmap[slave], addr, reg); ret = regmap_add_irq_chip(palmas->regmap[slave], palmas->irq, - IRQF_ONESHOT | pdata->irq_flags, 0, &palmas_irq_chip, - &palmas->irq_data); + IRQF_ONESHOT | pdata->irq_flags, 0, + driver_data->irq_chip, &palmas->irq_data); if (ret < 0) goto err_i2c; -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH 4/5] mfd: palmas: Add tps65917 support 2014-05-26 9:56 ` [PATCH 4/5] mfd: palmas: Add tps65917 support Keerthy @ 2014-05-27 8:38 ` Lee Jones 2014-05-27 8:39 ` Keerthy 0 siblings, 1 reply; 13+ messages in thread From: Lee Jones @ 2014-05-27 8:38 UTC (permalink / raw) To: Keerthy; +Cc: linux-omap, lgirdwood, broonie, linux-kernel, sameo On Mon, 26 May 2014, Keerthy wrote: > Add tps65917 PMIC support. tps65917 is a subset of palmas PMIC. > Some of the register definitions and the interrupt mappings > are different. > > Signed-off-by: Keerthy <j-keerthy@ti.com> > --- > drivers/mfd/palmas.c | 177 ++++++++++++++++++++++++++++++++++++++++++++++++-- Much nicer. You just saved yourself(/the subsystem) 420 lines! I have a single nit. Once it's fixed-up you can apply my: Acked-by: Lee Jones <lee.jones@linaro.org> > 1 file changed, 172 insertions(+), 5 deletions(-) > > diff --git a/drivers/mfd/palmas.c b/drivers/mfd/palmas.c > index d280d78..e4684cc 100644 > --- a/drivers/mfd/palmas.c > +++ b/drivers/mfd/palmas.c [...] > static const struct of_device_id of_palmas_match_tbl[] = { > { > .compatible = "ti,palmas", > - .data = &palmas_features, > + .data = &palmas_data, > }, > { > .compatible = "ti,tps659038", > - .data = &tps659038_features, > + .data = &tps659038_data, > }, > + { > + .compatible = "ti,tps65917", > + .data = &tps65917_data, > + }, > + Please get rid of this line. > { }, > }; > MODULE_DEVICE_TABLE(of, of_palmas_match_tbl); -- Lee Jones Linaro STMicroelectronics Landing Team Lead Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 4/5] mfd: palmas: Add tps65917 support 2014-05-27 8:38 ` Lee Jones @ 2014-05-27 8:39 ` Keerthy 0 siblings, 0 replies; 13+ messages in thread From: Keerthy @ 2014-05-27 8:39 UTC (permalink / raw) To: Lee Jones; +Cc: Keerthy, linux-omap, lgirdwood, broonie, linux-kernel, sameo On Tuesday 27 May 2014 02:08 PM, Lee Jones wrote: > On Mon, 26 May 2014, Keerthy wrote: > >> Add tps65917 PMIC support. tps65917 is a subset of palmas PMIC. >> Some of the register definitions and the interrupt mappings >> are different. >> >> Signed-off-by: Keerthy <j-keerthy@ti.com> >> --- >> drivers/mfd/palmas.c | 177 ++++++++++++++++++++++++++++++++++++++++++++++++-- > Much nicer. You just saved yourself(/the subsystem) 420 lines! > > I have a single nit. Once it's fixed-up you can apply my: > > Acked-by: Lee Jones <lee.jones@linaro.org> Thanks. > >> 1 file changed, 172 insertions(+), 5 deletions(-) >> >> diff --git a/drivers/mfd/palmas.c b/drivers/mfd/palmas.c >> index d280d78..e4684cc 100644 >> --- a/drivers/mfd/palmas.c >> +++ b/drivers/mfd/palmas.c > [...] > >> static const struct of_device_id of_palmas_match_tbl[] = { >> { >> .compatible = "ti,palmas", >> - .data = &palmas_features, >> + .data = &palmas_data, >> }, >> { >> .compatible = "ti,tps659038", >> - .data = &tps659038_features, >> + .data = &tps659038_data, >> }, >> + { >> + .compatible = "ti,tps65917", >> + .data = &tps65917_data, >> + }, >> + > Please get rid of this line. Oops. I will knock off this line and submit. >> { }, >> }; >> MODULE_DEVICE_TABLE(of, of_palmas_match_tbl); ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 5/5] regulator: tps65917: Add Regulator driver for tps65917 PMIC 2014-05-26 9:56 [PATCH 0/5] tps65917: Add support for for TPS65917 PMIC Keerthy ` (3 preceding siblings ...) 2014-05-26 9:56 ` [PATCH 4/5] mfd: palmas: Add tps65917 support Keerthy @ 2014-05-26 9:56 ` Keerthy 2014-05-26 15:00 ` Mark Brown 4 siblings, 1 reply; 13+ messages in thread From: Keerthy @ 2014-05-26 9:56 UTC (permalink / raw) To: linux-omap; +Cc: lgirdwood, broonie, linux-kernel, sameo, lee.jones, Keerthy This patch adds support for TPS65917 PMIC regulators. The regulators set consists of 5 SMPSs and 5 LDOs. The output voltages are configurable and are meant to supply power to the main processor and other components. Signed-off-by: Keerthy <j-keerthy@ti.com> --- drivers/regulator/Kconfig | 12 + drivers/regulator/Makefile | 1 + drivers/regulator/tps65917-regulator.c | 815 ++++++++++++++++++++++++++++++++ 3 files changed, 828 insertions(+) create mode 100644 drivers/regulator/tps65917-regulator.c Index: linux/drivers/regulator/Kconfig =================================================================== --- linux.orig/drivers/regulator/Kconfig 2014-05-26 15:21:12.269247638 +0530 +++ linux/drivers/regulator/Kconfig 2014-05-26 15:21:46.956121138 +0530 @@ -581,6 +581,18 @@ help This driver supports TPS65912 voltage regulator chip. +config REGULATOR_TPS65917 + tristate "TI TPS65917 PMIC Regulators" + depends on MFD_PALMAS + help + If you wish to control the regulators on the TPS65917 series of + chips say Y here. This will enable support for all the software + controllable SMPS/LDO regulators. + + The regulators available on TPS65917 series chips vary depending + on the muxing. This is handled automatically in the driver by + reading the mux info from OTP. + config REGULATOR_TPS80031 tristate "TI TPS80031/TPS80032 power regualtor driver" depends on MFD_TPS80031 Index: linux/drivers/regulator/Makefile =================================================================== --- linux.orig/drivers/regulator/Makefile 2014-05-26 15:21:12.269247638 +0530 +++ linux/drivers/regulator/Makefile 2014-05-26 15:21:46.956121138 +0530 @@ -76,6 +76,7 @@ obj-$(CONFIG_REGULATOR_TPS6586X) += tps6586x-regulator.o obj-$(CONFIG_REGULATOR_TPS65910) += tps65910-regulator.o obj-$(CONFIG_REGULATOR_TPS65912) += tps65912-regulator.o +obj-$(CONFIG_REGULATOR_TPS65917) += tps65917-regulator.o obj-$(CONFIG_REGULATOR_TPS80031) += tps80031-regulator.o obj-$(CONFIG_REGULATOR_TWL4030) += twl-regulator.o obj-$(CONFIG_REGULATOR_VEXPRESS) += vexpress.o Index: linux/drivers/regulator/tps65917-regulator.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux/drivers/regulator/tps65917-regulator.c 2014-05-26 15:22:25.994853307 +0530 @@ -0,0 +1,814 @@ +/* + * Driver for Regulator part of TPS65917 PMIC + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether expressed or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License version 2 for more details. + */ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/init.h> +#include <linux/err.h> +#include <linux/platform_device.h> +#include <linux/regulator/driver.h> +#include <linux/regulator/machine.h> +#include <linux/slab.h> +#include <linux/regmap.h> +#include <linux/mfd/palmas.h> +#include <linux/of.h> +#include <linux/of_platform.h> +#include <linux/regulator/of_regulator.h> + +static const struct regulator_linear_range smps_low_ranges[] = { + REGULATOR_LINEAR_RANGE(500000, 0x1, 0x6, 0), + REGULATOR_LINEAR_RANGE(510000, 0x7, 0x79, 10000), + REGULATOR_LINEAR_RANGE(1650000, 0x7A, 0x7f, 0), +}; + +static const struct regulator_linear_range smps_high_ranges[] = { + REGULATOR_LINEAR_RANGE(1000000, 0x1, 0x6, 0), + REGULATOR_LINEAR_RANGE(1020000, 0x7, 0x79, 20000), + REGULATOR_LINEAR_RANGE(3300000, 0x7A, 0x7f, 0), +}; + +struct regs_info { + char *name; + char *sname; + u8 vsel_addr; + u8 ctrl_addr; + int sleep_id; +}; + +static const struct regs_info tps65917_regs_info[] = { + { + .name = "SMPS1", + .sname = "smps1-in", + .vsel_addr = TPS65917_SMPS1_VOLTAGE, + .ctrl_addr = TPS65917_SMPS1_CTRL, + .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS1, + }, + { + .name = "SMPS2", + .sname = "smps2-in", + .vsel_addr = TPS65917_SMPS2_VOLTAGE, + .ctrl_addr = TPS65917_SMPS2_CTRL, + .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS2, + }, + { + .name = "SMPS3", + .sname = "smps3-in", + .vsel_addr = TPS65917_SMPS3_VOLTAGE, + .ctrl_addr = TPS65917_SMPS3_CTRL, + .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS3, + }, + { + .name = "SMPS4", + .sname = "smps4-in", + .vsel_addr = TPS65917_SMPS4_VOLTAGE, + .ctrl_addr = TPS65917_SMPS4_CTRL, + .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS4, + }, + { + .name = "SMPS5", + .sname = "smps5-in", + .vsel_addr = TPS65917_SMPS5_VOLTAGE, + .ctrl_addr = TPS65917_SMPS5_CTRL, + .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS5, + }, + { + .name = "LDO1", + .sname = "ldo1-in", + .vsel_addr = TPS65917_LDO1_VOLTAGE, + .ctrl_addr = TPS65917_LDO1_CTRL, + .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO1, + }, + { + .name = "LDO2", + .sname = "ldo2-in", + .vsel_addr = TPS65917_LDO2_VOLTAGE, + .ctrl_addr = TPS65917_LDO2_CTRL, + .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO2, + }, + { + .name = "LDO3", + .sname = "ldo3-in", + .vsel_addr = TPS65917_LDO3_VOLTAGE, + .ctrl_addr = TPS65917_LDO3_CTRL, + .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO3, + }, + { + .name = "LDO4", + .sname = "ldo4-in", + .vsel_addr = TPS65917_LDO4_VOLTAGE, + .ctrl_addr = TPS65917_LDO4_CTRL, + .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO4, + }, + { + .name = "LDO5", + .sname = "ldo5-in", + .vsel_addr = TPS65917_LDO5_VOLTAGE, + .ctrl_addr = TPS65917_LDO5_CTRL, + .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO5, + }, + { + .name = "REGEN1", + .ctrl_addr = TPS65917_REGEN1_CTRL, + .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_REGEN1, + }, + { + .name = "REGEN2", + .ctrl_addr = TPS65917_REGEN2_CTRL, + .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_REGEN2, + }, + { + .name = "REGEN3", + .ctrl_addr = TPS65917_REGEN3_CTRL, + .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_REGEN3, + }, +}; + +#define SMPS_CTRL_MODE_OFF 0x00 +#define SMPS_CTRL_MODE_ON 0x01 +#define SMPS_CTRL_MODE_ECO 0x02 +#define SMPS_CTRL_MODE_PWM 0x03 + +#define PALMAS_SMPS_NUM_VOLTAGES 122 +#define PALMAS_LDO_NUM_VOLTAGES 50 + +#define REGULATOR_SLAVE 0 + +static int tps65917_smps_read(struct palmas *palmas, unsigned int reg, + unsigned int *dest) +{ + unsigned int addr; + + addr = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE, reg); + + return regmap_read(palmas->regmap[REGULATOR_SLAVE], addr, dest); +} + +static int tps65917_smps_write(struct palmas *palmas, unsigned int reg, + unsigned int value) +{ + unsigned int addr; + + addr = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE, reg); + + return regmap_write(palmas->regmap[REGULATOR_SLAVE], addr, value); +} + +static int tps65917_ldo_read(struct palmas *palmas, unsigned int reg, + unsigned int *dest) +{ + unsigned int addr; + + addr = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE, reg); + + return regmap_read(palmas->regmap[REGULATOR_SLAVE], addr, dest); +} + +static int tps65917_ldo_write(struct palmas *palmas, unsigned int reg, + unsigned int value) +{ + unsigned int addr; + + addr = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE, reg); + + return regmap_write(palmas->regmap[REGULATOR_SLAVE], addr, value); +} + +static int tps65917_set_mode_smps(struct regulator_dev *dev, unsigned int mode) +{ + struct palmas_pmic *pmic = rdev_get_drvdata(dev); + int id = rdev_get_id(dev); + unsigned int reg; + bool rail_enable = true; + + tps65917_smps_read(pmic->palmas, tps65917_regs_info[id].ctrl_addr, + ®); + reg &= ~PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK; + + if (reg == SMPS_CTRL_MODE_OFF) + rail_enable = false; + + switch (mode) { + case REGULATOR_MODE_NORMAL: + reg |= SMPS_CTRL_MODE_ON; + break; + case REGULATOR_MODE_IDLE: + reg |= SMPS_CTRL_MODE_ECO; + break; + case REGULATOR_MODE_FAST: + reg |= SMPS_CTRL_MODE_PWM; + break; + default: + return -EINVAL; + } + + pmic->current_reg_mode[id] = reg & PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK; + if (rail_enable) + tps65917_smps_write(pmic->palmas, + tps65917_regs_info[id].ctrl_addr, reg); + return 0; +} + +static unsigned int tps65917_get_mode_smps(struct regulator_dev *dev) +{ + struct palmas_pmic *pmic = rdev_get_drvdata(dev); + int id = rdev_get_id(dev); + unsigned int reg; + + reg = pmic->current_reg_mode[id] & PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK; + + switch (reg) { + case SMPS_CTRL_MODE_ON: + return REGULATOR_MODE_NORMAL; + case SMPS_CTRL_MODE_ECO: + return REGULATOR_MODE_IDLE; + case SMPS_CTRL_MODE_PWM: + return REGULATOR_MODE_FAST; + } + + return 0; +} + +static struct regulator_ops tps65917_ops_smps = { + .is_enabled = regulator_is_enabled_regmap, + .enable = regulator_enable_regmap, + .disable = regulator_disable_regmap, + .set_mode = tps65917_set_mode_smps, + .get_mode = tps65917_get_mode_smps, + .get_voltage_sel = regulator_get_voltage_sel_regmap, + .set_voltage_sel = regulator_set_voltage_sel_regmap, + .list_voltage = regulator_list_voltage_linear_range, + .map_voltage = regulator_map_voltage_linear_range, + .set_voltage_time_sel = regulator_set_voltage_time_sel, +}; + +static struct regulator_ops tps65917_ops_ext_control_smps = { + .set_mode = tps65917_set_mode_smps, + .get_mode = tps65917_get_mode_smps, + .get_voltage_sel = regulator_get_voltage_sel_regmap, + .set_voltage_sel = regulator_set_voltage_sel_regmap, + .list_voltage = regulator_list_voltage_linear_range, + .map_voltage = regulator_map_voltage_linear_range, +}; + +static int tps65917_is_enabled_ldo(struct regulator_dev *dev) +{ + struct palmas_pmic *pmic = rdev_get_drvdata(dev); + int id = rdev_get_id(dev); + unsigned int reg; + + tps65917_ldo_read(pmic->palmas, tps65917_regs_info[id].ctrl_addr, + ®); + + reg &= TPS65917_LDO1_CTRL_STATUS; + + return !!(reg); +} + +static struct regulator_ops tps65917_ops_ldo = { + .is_enabled = tps65917_is_enabled_ldo, + .enable = regulator_enable_regmap, + .disable = regulator_disable_regmap, + .get_voltage_sel = regulator_get_voltage_sel_regmap, + .set_voltage_sel = regulator_set_voltage_sel_regmap, + .list_voltage = regulator_list_voltage_linear, + .map_voltage = regulator_map_voltage_linear, + .set_voltage_time_sel = regulator_set_voltage_time_sel, +}; + +static struct regulator_ops tps65917_ops_ext_control_ldo = { + .get_voltage_sel = regulator_get_voltage_sel_regmap, + .set_voltage_sel = regulator_set_voltage_sel_regmap, + .list_voltage = regulator_list_voltage_linear, + .map_voltage = regulator_map_voltage_linear, +}; + +static struct regulator_ops tps65917_ops_extreg = { + .is_enabled = regulator_is_enabled_regmap, + .enable = regulator_enable_regmap, + .disable = regulator_disable_regmap, +}; + +static struct regulator_ops tps65917_ops_ext_control_extreg = { +}; + +static int tps65917_regulator_config_external(struct palmas *palmas, int id, + struct palmas_reg_init *reg_init) +{ + int sleep_id = tps65917_regs_info[id].sleep_id; + int ret; + + ret = palmas_ext_control_req_config(palmas, sleep_id, + reg_init->roof_floor, true); + if (ret < 0) + dev_err(palmas->dev, + "Ext control config for regulator %d failed %d\n", + id, ret); + return ret; +} + +/* + * setup the hardware based sleep configuration of the SMPS/LDO regulators + * from the platform data. This is different to the software based control + * supported by the regulator framework as it is controlled by toggling + * pins on the PMIC such as PREQ, SYSEN, ... + */ +static int tps65917_smps_init(struct palmas *palmas, int id, + struct palmas_reg_init *reg_init) +{ + unsigned int reg; + unsigned int addr; + int ret; + + addr = tps65917_regs_info[id].ctrl_addr; + + ret = tps65917_smps_read(palmas, addr, ®); + if (ret) + return ret; + + if (reg_init->warm_reset) + reg |= PALMAS_SMPS12_CTRL_WR_S; + else + reg &= ~PALMAS_SMPS12_CTRL_WR_S; + + if (reg_init->roof_floor) + reg |= PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN; + else + reg &= ~PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN; + + reg &= ~PALMAS_SMPS12_CTRL_MODE_SLEEP_MASK; + if (reg_init->mode_sleep) + reg |= reg_init->mode_sleep << + PALMAS_SMPS12_CTRL_MODE_SLEEP_SHIFT; + + + ret = tps65917_smps_write(palmas, addr, reg); + if (ret) + return ret; + + if (tps65917_regs_info[id].vsel_addr && reg_init->vsel) { + addr = tps65917_regs_info[id].vsel_addr; + + reg = reg_init->vsel; + + ret = tps65917_smps_write(palmas, addr, reg); + if (ret) + return ret; + } + + if (reg_init->roof_floor) { + /* Enable externally controlled regulator */ + addr = tps65917_regs_info[id].ctrl_addr; + ret = tps65917_smps_read(palmas, addr, ®); + if (ret < 0) + return ret; + + if (!(reg & PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK)) { + reg |= SMPS_CTRL_MODE_ON; + ret = tps65917_smps_write(palmas, addr, reg); + if (ret < 0) + return ret; + } + return tps65917_regulator_config_external(palmas, id, + reg_init); + } + return 0; +} + +static int tps65917_ldo_init(struct palmas *palmas, int id, + struct palmas_reg_init *reg_init) +{ + unsigned int reg; + unsigned int addr; + int ret; + + addr = tps65917_regs_info[id].ctrl_addr; + + ret = tps65917_ldo_read(palmas, addr, ®); + if (ret) + return ret; + + if (reg_init->warm_reset) + reg |= TPS65917_LDO1_CTRL_WR_S; + else + reg &= ~TPS65917_LDO1_CTRL_WR_S; + + if (reg_init->mode_sleep) + reg |= TPS65917_LDO1_CTRL_MODE_SLEEP; + else + reg &= ~TPS65917_LDO1_CTRL_MODE_SLEEP; + + ret = tps65917_ldo_write(palmas, addr, reg); + if (ret) + return ret; + + if (reg_init->roof_floor) { + /* Enable externally controlled regulator */ + addr = tps65917_regs_info[id].ctrl_addr; + ret = palmas_update_bits(palmas, PALMAS_LDO_BASE, + addr, PALMAS_LDO1_CTRL_MODE_ACTIVE, + PALMAS_LDO1_CTRL_MODE_ACTIVE); + if (ret < 0) { + dev_err(palmas->dev, + "LDO Register 0x%02x update failed %d\n", + addr, ret); + return ret; + } + return tps65917_regulator_config_external(palmas, id, + reg_init); + } + return 0; +} + +static int tps65917_extreg_init(struct palmas *palmas, int id, + struct palmas_reg_init *reg_init) +{ + unsigned int addr; + int ret; + unsigned int val = 0; + + addr = tps65917_regs_info[id].ctrl_addr; + + if (reg_init->mode_sleep) + val = PALMAS_REGEN1_CTRL_MODE_SLEEP; + + ret = palmas_update_bits(palmas, PALMAS_RESOURCE_BASE, + addr, PALMAS_REGEN1_CTRL_MODE_SLEEP, val); + if (ret < 0) { + dev_err(palmas->dev, "Resource reg 0x%02x update failed %d\n", + addr, ret); + return ret; + } + + if (reg_init->roof_floor) { + /* Enable externally controlled regulator */ + addr = tps65917_regs_info[id].ctrl_addr; + ret = palmas_update_bits(palmas, PALMAS_RESOURCE_BASE, + addr, PALMAS_REGEN1_CTRL_MODE_ACTIVE, + PALMAS_REGEN1_CTRL_MODE_ACTIVE); + if (ret < 0) { + dev_err(palmas->dev, + "Resource Register 0x%02x update failed %d\n", + addr, ret); + return ret; + } + return tps65917_regulator_config_external(palmas, id, + reg_init); + } + return 0; +} + +static struct of_regulator_match tps65917_matches[] = { + { .name = "smps1", }, + { .name = "smps2", }, + { .name = "smps3", }, + { .name = "smps4", }, + { .name = "smps5", }, + { .name = "ldo1", }, + { .name = "ldo2", }, + { .name = "ldo3", }, + { .name = "ldo4", }, + { .name = "ldo5", }, + { .name = "regen1", }, + { .name = "regen2", }, + { .name = "regen3", }, + { .name = "sysen1", }, + { .name = "sysen2", }, +}; + +static void tps65917_dt_to_pdata(struct device *dev, + struct device_node *node, + struct palmas_pmic_platform_data *pdata) +{ + struct device_node *regulators; + u32 prop; + int idx, ret; + + node = of_node_get(node); + regulators = of_get_child_by_name(node, "regulators"); + if (!regulators) { + dev_info(dev, "regulator node not found\n"); + return; + } + + ret = of_regulator_match(dev, regulators, tps65917_matches, + TPS65917_NUM_REGS); + of_node_put(regulators); + if (ret < 0) { + dev_err(dev, "Error parsing regulator init data: %d\n", ret); + return; + } + + for (idx = 0; idx < TPS65917_NUM_REGS; idx++) { + if (!tps65917_matches[idx].init_data || + !tps65917_matches[idx].of_node) + continue; + + pdata->reg_data[idx] = tps65917_matches[idx].init_data; + + pdata->reg_init[idx] = devm_kzalloc(dev, + sizeof(struct palmas_reg_init), GFP_KERNEL); + + pdata->reg_init[idx]->warm_reset = + of_property_read_bool(tps65917_matches[idx].of_node, + "ti,warm-reset"); + + ret = of_property_read_u32(tps65917_matches[idx].of_node, + "ti,roof-floor", &prop); + /* EINVAL: Property not found */ + if (ret != -EINVAL) { + int econtrol; + + /* use default value, when no value is specified */ + econtrol = PALMAS_EXT_CONTROL_NSLEEP; + if (!ret) { + switch (prop) { + case 1: + econtrol = PALMAS_EXT_CONTROL_ENABLE1; + break; + case 2: + econtrol = PALMAS_EXT_CONTROL_ENABLE2; + break; + case 3: + econtrol = PALMAS_EXT_CONTROL_NSLEEP; + break; + default: + WARN_ON(1); + dev_warn(dev, + "%s: Invalid roof-floor option: %u\n", + tps65917_matches[idx].name, prop); + break; + } + } + pdata->reg_init[idx]->roof_floor = econtrol; + } + + ret = of_property_read_u32(tps65917_matches[idx].of_node, + "ti,mode-sleep", &prop); + if (!ret) + pdata->reg_init[idx]->mode_sleep = prop; + + ret = of_property_read_bool(tps65917_matches[idx].of_node, + "ti,smps-range"); + if (ret) + pdata->reg_init[idx]->vsel = + PALMAS_SMPS12_VOLTAGE_RANGE; + } +} + +static int tps65917_regulators_probe(struct platform_device *pdev) +{ + struct palmas *palmas = dev_get_drvdata(pdev->dev.parent); + struct palmas_pmic_platform_data *pdata; + struct device_node *node = pdev->dev.of_node; + struct regulator_dev *rdev; + struct regulator_config config = { }; + struct palmas_pmic *pmic; + struct palmas_reg_init *reg_init; + int id = 0, ret; + unsigned int addr, reg; + + pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); + + if (!pdata) + return -ENOMEM; + + tps65917_dt_to_pdata(&pdev->dev, node, pdata); + + pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL); + if (!pmic) + return -ENOMEM; + + pmic->dev = &pdev->dev; + pmic->palmas = palmas; + palmas->pmic = pmic; + platform_set_drvdata(pdev, pmic); + + ret = tps65917_smps_read(palmas, PALMAS_SMPS_CTRL, ®); + if (ret) + return ret; + + if (reg & TPS65917_SMPS_CTRL_SMPS1_SMPS12_EN) + pmic->smps12 = 1; + + config.regmap = palmas->regmap[REGULATOR_SLAVE]; + config.dev = &pdev->dev; + config.driver_data = pmic; + + for (id = 0; id < TPS65917_REG_LDO1; id++) { + /* + * Miss out regulators which are not available due + * to slaving configurations. + */ + pmic->desc[id].n_linear_ranges = 3; + if ((id == TPS65917_REG_SMPS2) && pmic->smps12) + continue; + + /* Initialise sleep/init values from platform data */ + if (pdata && pdata->reg_init[id]) { + reg_init = pdata->reg_init[id]; + ret = tps65917_smps_init(palmas, id, reg_init); + if (ret) + return ret; + } else { + reg_init = NULL; + } + + /* Register the regulators */ + pmic->desc[id].name = tps65917_regs_info[id].name; + pmic->desc[id].id = id; + + /* + * Read and store the RANGE bit for later use + * This must be done before regulator is probed, + * otherwise we error in probe with unsupportable + * ranges. Read the current smps mode for later use. + */ + addr = tps65917_regs_info[id].vsel_addr; + + ret = tps65917_smps_read(pmic->palmas, addr, ®); + if (ret) + return ret; + if (reg & TPS65917_SMPS1_VOLTAGE_RANGE) + pmic->range[id] = 1; + + if (pmic->range[id]) + pmic->desc[id].linear_ranges = smps_high_ranges; + else + pmic->desc[id].linear_ranges = smps_low_ranges; + + + if (reg_init && reg_init->roof_floor) + pmic->desc[id].ops = + &tps65917_ops_ext_control_smps; + else + pmic->desc[id].ops = &tps65917_ops_smps; + pmic->desc[id].n_voltages = PALMAS_SMPS_NUM_VOLTAGES; + pmic->desc[id].vsel_reg = + PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE, + tps65917_regs_info[id].vsel_addr); + pmic->desc[id].vsel_mask = + PALMAS_SMPS12_VOLTAGE_VSEL_MASK; + + pmic->desc[id].ramp_delay = 2500; + + /* Read the smps mode for later use. */ + addr = tps65917_regs_info[id].ctrl_addr; + ret = tps65917_smps_read(pmic->palmas, addr, ®); + if (ret) + return ret; + pmic->current_reg_mode[id] = reg & + PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK; + + pmic->desc[id].type = REGULATOR_VOLTAGE; + pmic->desc[id].owner = THIS_MODULE; + + if (pdata) + config.init_data = pdata->reg_data[id]; + else + config.init_data = NULL; + + pmic->desc[id].supply_name = tps65917_regs_info[id].sname; + config.of_node = tps65917_matches[id].of_node; + + rdev = devm_regulator_register(&pdev->dev, &pmic->desc[id], + &config); + if (IS_ERR(rdev)) { + dev_err(&pdev->dev, + "failed to register %s regulator\n", + pdev->name); + return PTR_ERR(rdev); + } + + /* Save regulator for cleanup */ + pmic->rdev[id] = rdev; + } + + /* Start this loop from the id left from previous loop */ + for (; id < TPS65917_NUM_REGS; id++) { + if (pdata && pdata->reg_init[id]) + reg_init = pdata->reg_init[id]; + else + reg_init = NULL; + + /* Miss out regulators which are not available due + * to alternate functions. + */ + + /* Register the regulators */ + pmic->desc[id].name = tps65917_regs_info[id].name; + pmic->desc[id].id = id; + pmic->desc[id].type = REGULATOR_VOLTAGE; + pmic->desc[id].owner = THIS_MODULE; + + if (id < TPS65917_REG_REGEN1) { + pmic->desc[id].n_voltages = PALMAS_LDO_NUM_VOLTAGES; + if (reg_init && reg_init->roof_floor) + pmic->desc[id].ops = + &tps65917_ops_ext_control_ldo; + else + pmic->desc[id].ops = &tps65917_ops_ldo; + pmic->desc[id].min_uV = 900000; + pmic->desc[id].uV_step = 50000; + pmic->desc[id].linear_min_sel = 1; + pmic->desc[id].enable_time = 500; + pmic->desc[id].vsel_reg = + PALMAS_BASE_TO_REG(PALMAS_LDO_BASE, + tps65917_regs_info[id].vsel_addr); + pmic->desc[id].vsel_mask = + PALMAS_LDO1_VOLTAGE_VSEL_MASK; + pmic->desc[id].enable_reg = + PALMAS_BASE_TO_REG(PALMAS_LDO_BASE, + tps65917_regs_info[id].ctrl_addr); + pmic->desc[id].enable_mask = + PALMAS_LDO1_CTRL_MODE_ACTIVE; + /* + * To be confirmed. Discussion on going with PMIC Team. + * It is of the order of ~60mV/uS. + */ + pmic->desc[id].ramp_delay = 2500; + } else { + pmic->desc[id].n_voltages = 1; + if (reg_init && reg_init->roof_floor) + pmic->desc[id].ops = + &tps65917_ops_ext_control_extreg; + else + pmic->desc[id].ops = &tps65917_ops_extreg; + pmic->desc[id].enable_reg = + PALMAS_BASE_TO_REG(PALMAS_RESOURCE_BASE, + tps65917_regs_info[id].ctrl_addr); + pmic->desc[id].enable_mask = + PALMAS_REGEN1_CTRL_MODE_ACTIVE; + } + + if (pdata) + config.init_data = pdata->reg_data[id]; + else + config.init_data = NULL; + + pmic->desc[id].supply_name = tps65917_regs_info[id].sname; + config.of_node = tps65917_matches[id].of_node; + + rdev = devm_regulator_register(&pdev->dev, &pmic->desc[id], + &config); + if (IS_ERR(rdev)) { + dev_err(&pdev->dev, + "failed to register %s regulator\n", + pdev->name); + return PTR_ERR(rdev); + } + + /* Save regulator for cleanup */ + pmic->rdev[id] = rdev; + + /* Initialise sleep/init values from platform data */ + if (pdata) { + reg_init = pdata->reg_init[id]; + if (reg_init) { + if (id < TPS65917_REG_REGEN1) + ret = tps65917_ldo_init(palmas, + id, reg_init); + else + ret = tps65917_extreg_init(palmas, + id, reg_init); + if (ret) + return ret; + } + } + } + + return 0; +} + +static struct of_device_id of_tps65917_match_tbl[] = { + { .compatible = "ti,tps65917-pmic", }, + { }, +}; + +static struct platform_driver tps65917_driver = { + .driver = { + .name = "tps65917-pmic", + .of_match_table = of_match_ptr(of_tps65917_match_tbl), + .owner = THIS_MODULE, + }, + .probe = tps65917_regulators_probe, +}; + +module_platform_driver(tps65917_driver); + +MODULE_AUTHOR("J Keerthy <j-keerthy@ti.com>"); +MODULE_DESCRIPTION("TPS65917 voltage regulator driver"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:tps65917-pmic"); +MODULE_DEVICE_TABLE(of, of_tps65917_match_tbl); ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 5/5] regulator: tps65917: Add Regulator driver for tps65917 PMIC 2014-05-26 9:56 ` [PATCH 5/5] regulator: tps65917: Add Regulator driver for tps65917 PMIC Keerthy @ 2014-05-26 15:00 ` Mark Brown 2014-05-27 3:22 ` Keerthy 0 siblings, 1 reply; 13+ messages in thread From: Mark Brown @ 2014-05-26 15:00 UTC (permalink / raw) To: Keerthy; +Cc: linux-omap, lgirdwood, linux-kernel, sameo, lee.jones [-- Attachment #1: Type: text/plain, Size: 488 bytes --] On Mon, May 26, 2014 at 03:26:37PM +0530, Keerthy wrote: > This patch adds support for TPS65917 PMIC regulators. > > The regulators set consists of 5 SMPSs and 5 LDOs. The output > voltages are configurable and are meant to supply power to the > main processor and other components. This appears to look *very* like the Palmas driver, should it not be sharing code with that? If it were just data tables it'd be less of a concern but there's quite a bit of actual code here. [-- Attachment #2: Digital signature --] [-- Type: application/pgp-signature, Size: 836 bytes --] ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 5/5] regulator: tps65917: Add Regulator driver for tps65917 PMIC 2014-05-26 15:00 ` Mark Brown @ 2014-05-27 3:22 ` Keerthy 2014-05-27 8:30 ` Lee Jones 0 siblings, 1 reply; 13+ messages in thread From: Keerthy @ 2014-05-27 3:22 UTC (permalink / raw) To: Mark Brown; +Cc: Keerthy, linux-omap, lgirdwood, linux-kernel, sameo, lee.jones Hi Mark, On Monday 26 May 2014 08:30 PM, Mark Brown wrote: > On Mon, May 26, 2014 at 03:26:37PM +0530, Keerthy wrote: >> This patch adds support for TPS65917 PMIC regulators. >> >> The regulators set consists of 5 SMPSs and 5 LDOs. The output >> voltages are configurable and are meant to supply power to the >> main processor and other components. > This appears to look *very* like the Palmas driver, should it not be > sharing code with that? If it were just data tables it'd be less of a > concern but there's quite a bit of actual code here. Yes it is. The difference is in the entire register space of the regulators between the two. There are other differences in how the ramp delay is configured and SMPS ordering. The difference is also a bit in the programming sequence. I agree that largely it is Palmas based. I did not want to add more checks in the probe of the palmas driver. Hence came up with a new one. Coming to sharing the code, can we have 2 drivers which share the common functions with separate data and specific functions? I just simply do not want to add anything more to the palmas driver probe function. Kind Regards, Keerthy ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 5/5] regulator: tps65917: Add Regulator driver for tps65917 PMIC 2014-05-27 3:22 ` Keerthy @ 2014-05-27 8:30 ` Lee Jones 0 siblings, 0 replies; 13+ messages in thread From: Lee Jones @ 2014-05-27 8:30 UTC (permalink / raw) To: Keerthy; +Cc: Mark Brown, Keerthy, linux-omap, lgirdwood, linux-kernel, sameo > >>This patch adds support for TPS65917 PMIC regulators. > >> > >>The regulators set consists of 5 SMPSs and 5 LDOs. The output > >>voltages are configurable and are meant to supply power to the > >>main processor and other components. > >This appears to look *very* like the Palmas driver, should it not be > >sharing code with that? If it were just data tables it'd be less of a > >concern but there's quite a bit of actual code here. > Yes it is. The difference is in the entire register space of the regulators > between the two. There are other differences in how the ramp delay > is configured and SMPS ordering. The difference is also a bit in the > programming > sequence. I agree that largely it is Palmas based. I did not want to > add more > checks in the probe of the palmas driver. Hence came up with a new one. > > Coming to sharing the code, can we have 2 drivers which share the common > functions with separate data and specific functions? Yes, that is what the match functionality is for. Once you know which driver you're dealing with, you can call specific initialisation functions and/or supplement generic generic data structures with device specific ones. > I just simply do not want to add anything more to the palmas driver > probe function. -- Lee Jones Linaro STMicroelectronics Landing Team Lead Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2014-05-27 8:43 UTC | newest] Thread overview: 13+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2014-05-26 9:56 [PATCH 0/5] tps65917: Add support for for TPS65917 PMIC Keerthy 2014-05-26 9:56 ` [PATCH 1/5] mfd: Add DT bindings for tps65917 PMIC Keerthy 2014-05-26 9:56 ` [PATCH 2/5] Regulators: Add TPS65917 Bindings Keerthy 2014-05-26 9:56 ` [PATCH 3/5] mfd: palmas: Add tps65917 specific definitions and enums Keerthy 2014-05-27 8:41 ` Lee Jones 2014-05-27 8:43 ` Keerthy 2014-05-26 9:56 ` [PATCH 4/5] mfd: palmas: Add tps65917 support Keerthy 2014-05-27 8:38 ` Lee Jones 2014-05-27 8:39 ` Keerthy 2014-05-26 9:56 ` [PATCH 5/5] regulator: tps65917: Add Regulator driver for tps65917 PMIC Keerthy 2014-05-26 15:00 ` Mark Brown 2014-05-27 3:22 ` Keerthy 2014-05-27 8:30 ` Lee Jones
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