[PATCH 0/2] clk: ti: Fix up error checks in set_rate (and div 0 error)

[PATCH 0/2] clk: ti: Fix up error checks in set_rate (and div 0 error)

[Nishanth Menon]

Hi,
The following patches are based on v3.17-rc1
Prior to this series: http://slexy.org/view/s20QH6PW4x (notice the /0 div error spam at initial boot log)
After this series: http://slexy.org/view/s20tPNXPf4

Nishanth Menon (2):
  clk: ti: divider: Provide error check for incoming parameters in
    set_rate
  clk: ti: dra7-atl: Provide error check for incoming parameters in
    set_rate

 drivers/clk/ti/clk-dra7-atl.c |    6 +++++-
 drivers/clk/ti/divider.c      |    7 ++++++-
 2 files changed, 11 insertions(+), 2 deletions(-)

-- 
1.7.9.5

[PATCH 1/2] clk: ti: divider: Provide error check for incoming parameters in set_rate

[Nishanth Menon]

Check for valid parameters in check rate. Else, we end up getting errors
like:
[    0.000000] Division by zero in kernel.
[    0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.17.0-rc1 #1
[    0.000000] [<c0015160>] (unwind_backtrace) from [<c0011978>] (show_stack+0x10/0x14)
[    0.000000] [<c0011978>] (show_stack) from [<c055f5f4>] (dump_stack+0x78/0x94)
[    0.000000] [<c055f5f4>] (dump_stack) from [<c02e17cc>] (Ldiv0+0x8/0x10)
[    0.000000] [<c02e17cc>] (Ldiv0) from [<c047d228>] (ti_clk_divider_set_rate+0x14/0x14c)
[    0.000000] [<c047d228>] (ti_clk_divider_set_rate) from [<c047a938>] (clk_change_rate+0x138/0x180)
[    0.000000] [<c047a938>] (clk_change_rate) from [<c047a908>] (clk_change_rate+0x108/0x180)

This occurs as part of the inital clock tree update of child clock nodes
where new_rate could be 0 for non functional clocks.

Fixes: b4761198bfaf296 ("CLK: ti: add support for ti divider-clock")
Signed-off-by: Nishanth Menon <nm@ti.com>
---
 drivers/clk/ti/divider.c |    7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/ti/divider.c b/drivers/clk/ti/divider.c
index e6aa10d..a837f70 100644
--- a/drivers/clk/ti/divider.c
+++ b/drivers/clk/ti/divider.c
@@ -211,11 +211,16 @@ static long ti_clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
 static int ti_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
 				   unsigned long parent_rate)
 {
-	struct clk_divider *divider = to_clk_divider(hw);
+	struct clk_divider *divider;
 	unsigned int div, value;
 	unsigned long flags = 0;
 	u32 val;
 
+	if (!hw || !rate)
+		return -EINVAL;
+
+	divider = to_clk_divider(hw);
+
 	div = DIV_ROUND_UP(parent_rate, rate);
 	value = _get_val(divider, div);
 
-- 
1.7.9.5

[PATCH 2/2] clk: ti: dra7-atl: Provide error check for incoming parameters in set_rate

[Nishanth Menon]

Check for valid parameters in check rate. Else, we end up getting
errors.

This occurs as part of the inital clock tree update of child clock
nodes where new_rate could be 0 for non functional clocks.

Fixes: 9ac33b0ce81fa48 (" CLK: TI: Driver for DRA7 ATL (Audio Tracking Logic)")
Signed-off-by: Nishanth Menon <nm@ti.com>
---
 drivers/clk/ti/clk-dra7-atl.c |    6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/ti/clk-dra7-atl.c b/drivers/clk/ti/clk-dra7-atl.c
index 4a65b41..af29359 100644
--- a/drivers/clk/ti/clk-dra7-atl.c
+++ b/drivers/clk/ti/clk-dra7-atl.c
@@ -139,9 +139,13 @@ static long atl_clk_round_rate(struct clk_hw *hw, unsigned long rate,
 static int atl_clk_set_rate(struct clk_hw *hw, unsigned long rate,
 			    unsigned long parent_rate)
 {
-	struct dra7_atl_desc *cdesc = to_atl_desc(hw);
+	struct dra7_atl_desc *cdesc;
 	u32 divider;
 
+	if (!hw || !rate)
+		return -EINVAL;
+
+	cdesc = to_atl_desc(hw);
 	divider = ((parent_rate + rate / 2) / rate) - 1;
 	if (divider > DRA7_ATL_DIVIDER_MASK)
 		divider = DRA7_ATL_DIVIDER_MASK;
-- 
1.7.9.5

Re: [PATCH 0/2] clk: ti: Fix up error checks in set_rate (and div 0 error)

[Tero Kristo]

On 08/18/2014 07:56 PM, Nishanth Menon wrote:
> Hi,
> The following patches are based on v3.17-rc1
> Prior to this series: http://slexy.org/view/s20QH6PW4x (notice the /0 div error spam at initial boot log)
> After this series: http://slexy.org/view/s20tPNXPf4

Yeah, valid findings. However, you did not root-cause the problem, just 
added a bandaid for the most obvious errors. I will queue these patches 
for 3.17-rc fixes anyway, but will post an actual fix in a bit.

-Tero

>
> Nishanth Menon (2):
>    clk: ti: divider: Provide error check for incoming parameters in
>      set_rate
>    clk: ti: dra7-atl: Provide error check for incoming parameters in
>      set_rate
>
>   drivers/clk/ti/clk-dra7-atl.c |    6 +++++-
>   drivers/clk/ti/divider.c      |    7 ++++++-
>   2 files changed, 11 insertions(+), 2 deletions(-)
>

Re: [PATCH 0/2] clk: ti: Fix up error checks in set_rate (and div 0 error)

[Nishanth Menon]

On Thu, Aug 21, 2014 at 8:44 AM, Tero Kristo <t-kristo@ti.com> wrote:
> On 08/18/2014 07:56 PM, Nishanth Menon wrote:
>>
>> Hi,
>> The following patches are based on v3.17-rc1
>> Prior to this series: http://slexy.org/view/s20QH6PW4x (notice the /0 div
>> error spam at initial boot log)
>> After this series: http://slexy.org/view/s20tPNXPf4
>
>
> Yeah, valid findings. However, you did not root-cause the problem, just
> added a bandaid for the most obvious errors.

Yep, it does seem that omap3_noncore_dpll_set_rate had the same
bandaid as well :).. but checks did make sense..

> I will queue these patches for 3.17-rc fixes anyway, but will post an actual fix in a bit.

Thanks for rootcausing.

---
Regards,
Nishanth Menon