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From: Kishon Vijay Abraham I <kishon@ti.com>
To: grygorii.strashko@linaro.org, Tony Lindgren <tony@atomide.com>,
	Paul Walmsley <paul@pwsan.com>,
	linux-omap@vger.kernel.org
Cc: sumit.semwal@linaro.org, linux-arm-kernel@lists.infradead.org,
	Nishanth Menon <nm@ti.com>
Subject: Re: [PATCH] ARM: dra7xx: hwmod: drop .modulemode from pcie1/2 hwmods
Date: Mon, 9 Feb 2015 14:20:49 +0530	[thread overview]
Message-ID: <54D874E9.1040302@ti.com> (raw)
In-Reply-To: <1422978684-4826-1-git-send-email-grygorii.strashko@linaro.org>

Hi,

On Tuesday 03 February 2015 09:21 PM, grygorii.strashko@linaro.org wrote:
> From: Grygorii Strashko <grygorii.strashko@linaro.org>
> 
> Now DRA7xx pcie1/2 hwmods define PRCM configuration as following:
>   .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
>   .rstctrl_offs = DRA7XX_RM_L3INIT_RSTCTRL_OFFSET,
>   .modulemode   = MODULEMODE_SWCTRL,
> which is completely wrong because DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET
> is clockdomain ctrl register and NOT module ctrl register.
> And they have diffrent allowed values for bits[0,1]:
> CLKTRCTRL         MODULEMODE                                  
> 0x0: NO_SLEEP     0x0: Module is disabled by SW.              
> 0x1: SW_SLEEP     0x1: Module is managed automatically by HW  
> 0x2: SW_WKUP      0x2: Module is explicitly enabled.          
> 0x3: HW_AUTO      0x3: Reserved  
> 
> As result, following message can be seen during suspend:
>   "omap_hwmod: pcie1: _wait_target_disable failed"
> 
> Fix it by removing .modulemode from pcie1/2 hwmods and, in that
> way, prevent clockdomain ctrl register writing from HWMOD core.

Looks correct except for one change.

Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
> 
> Signed-off-by: Grygorii Strashko <Grygorii.Strashko@linaro.org>
> ---
> 
> More over, it looks like pcie1/2 hwmods are fake and have to be dropped at all.
> The real HWMODs are PCIESS1/2.

Not sure I get this. You mean "dra7xx_pcie1_hwmod" should be replaced with
"dra7xx_pciess1_hwmod"? Or you mean an entire new hwmod is missing?

Please note we still have to enable the clock domain and main clock. We've also
purposefully omitted sysconfig from hwmod data since pcie reset
(RM_PCIESS_RSTCTRL) should be done before accessing the syconfig register and
the infrastructure for that is currently not present.

> Unfortunatelly, not all information on PCIE is public, so
> I could be wrong here.
> ---
>  arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 2 --
>  1 file changed, 2 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> index ffd6604..a428b2d 100644
> --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> @@ -1478,7 +1478,6 @@ static struct omap_hwmod dra7xx_pcie1_hwmod = {
>  	.prcm = {
>  		.omap4 = {
>  			.clkctrl_offs	= DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
> -			.modulemode	= MODULEMODE_SWCTRL,

I think the entire .prcm can be removed here.
>  		},
>  	},
>  };
> @@ -1492,7 +1491,6 @@ static struct omap_hwmod dra7xx_pcie2_hwmod = {
>  	.prcm = {
>  		.omap4 = {
>  			.clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
> -			.modulemode   = MODULEMODE_SWCTRL,
>  		},
>  	},
>  };
> 

Thanks
Kishon
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  reply	other threads:[~2015-02-09  8:51 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-02-03 15:51 [PATCH] ARM: dra7xx: hwmod: drop .modulemode from pcie1/2 hwmods grygorii.strashko
2015-02-09  8:50 ` Kishon Vijay Abraham I [this message]
2015-02-09 10:28   ` Grygorii.Strashko@linaro.org
2015-02-09 13:24     ` Kishon Vijay Abraham I
2015-02-09 14:52       ` Grygorii.Strashko@linaro.org
2015-02-12  6:43         ` Kishon Vijay Abraham I
2015-02-12  8:35           ` Grygorii.Strashko@linaro.org
2015-02-12 15:08             ` Paul Walmsley
2015-02-12 16:24               ` Grygorii.Strashko@linaro.org
2015-02-12 16:27                 ` Paul Walmsley
2015-02-12 16:45                   ` Paul Walmsley
2015-02-13 14:15                     ` Kishon Vijay Abraham I

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