[PATCH 0/2] CLK: TI: add dpll_clksel_mac_clk node

[PATCH 0/2] CLK: TI: add dpll_clksel_mac_clk node

[Keerthy]

The series adds the missing clock node needed for cpsw.

Keerthy (2):
  CLK: TI: add dpll_clksel_mac_clk node
  ARM: dts: am4372: Set the default clock rate for dpll_clksel_mac_clk
    clock

 arch/arm/boot/dts/am4372.dtsi        | 7 +++++--
 arch/arm/boot/dts/am43xx-clocks.dtsi | 9 +++++++++
 drivers/clk/ti/clk-43xx.c            | 1 +
 3 files changed, 15 insertions(+), 2 deletions(-)

-- 
1.9.1

[PATCH 1/2] CLK: TI: AM437X: add dpll_clksel_mac_clk node

[Keerthy]

The patch adds the missing dpll_clksel_mac_clk clock node.

Signed-off-by: Keerthy <j-keerthy@ti.com>
---
 arch/arm/boot/dts/am43xx-clocks.dtsi | 9 +++++++++
 drivers/clk/ti/clk-43xx.c            | 1 +
 2 files changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi
index d0c0dfa..cc88728 100644
--- a/arch/arm/boot/dts/am43xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am43xx-clocks.dtsi
@@ -486,6 +486,15 @@
 		reg = <0x4238>;
 	};
 
+	dpll_clksel_mac_clk: dpll_clksel_mac_clk {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_core_m5_ck>;
+		reg = <0x4234>;
+		ti,bit-shift = <2>;
+		ti,dividers = <2>, <5>;
+	};
+
 	clk_32k_mosc_ck: clk_32k_mosc_ck {
 		#clock-cells = <0>;
 		compatible = "fixed-clock";
diff --git a/drivers/clk/ti/clk-43xx.c b/drivers/clk/ti/clk-43xx.c
index 3795fce..7549b87 100644
--- a/drivers/clk/ti/clk-43xx.c
+++ b/drivers/clk/ti/clk-43xx.c
@@ -71,6 +71,7 @@ static struct ti_dt_clk am43xx_clks[] = {
 	DT_CLK(NULL, "clk_24mhz", "clk_24mhz"),
 	DT_CLK(NULL, "cpsw_125mhz_gclk", "cpsw_125mhz_gclk"),
 	DT_CLK(NULL, "cpsw_cpts_rft_clk", "cpsw_cpts_rft_clk"),
+	DT_CLK(NULL, "dpll_clksel_mac_clk", "dpll_clksel_mac_clk"),
 	DT_CLK(NULL, "gpio0_dbclk_mux_ck", "gpio0_dbclk_mux_ck"),
 	DT_CLK(NULL, "gpio0_dbclk", "gpio0_dbclk"),
 	DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"),
-- 
1.9.1

[PATCH 2/2] ARM: dts: am4372: Set the default clock rate for dpll_clksel_mac_clk clock

[Keerthy]

cpsw needs the clock to be running at 50MHz in kernel. Hence setting
the default rate.

Signed-off-by: Keerthy <j-keerthy@ti.com>
---
 arch/arm/boot/dts/am4372.dtsi | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index c80a3e2..1680602 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -521,8 +521,11 @@
 			#address-cells = <1>;
 			#size-cells = <1>;
 			ti,hwmods = "cpgmac0";
-			clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
-			clock-names = "fck", "cpts";
+			clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>,
+				 <&dpll_clksel_mac_clk>;
+			clock-names = "fck", "cpts", "50mclk";
+			assigned-clocks = <&dpll_clksel_mac_clk>;
+			assigned-clock-rates = <50000000>;
 			status = "disabled";
 			cpdma_channels = <8>;
 			ale_entries = <1024>;
-- 
1.9.1

Re: [PATCH 0/2] CLK: TI: add dpll_clksel_mac_clk node

[Mugunthan V N]

On Thursday 18 June 2015 01:31 PM, Keerthy wrote:
> The series adds the missing clock node needed for cpsw.
> 
> Keerthy (2):
>   CLK: TI: add dpll_clksel_mac_clk node
>   ARM: dts: am4372: Set the default clock rate for dpll_clksel_mac_clk
>     clock
> 
>  arch/arm/boot/dts/am4372.dtsi        | 7 +++++--
>  arch/arm/boot/dts/am43xx-clocks.dtsi | 9 +++++++++
>  drivers/clk/ti/clk-43xx.c            | 1 +
>  3 files changed, 15 insertions(+), 2 deletions(-)
> 

Tested-by: Mugunthan V N <mugunthanvnm@ti.com>

Regards
Mugunthan V N

Re: [PATCH 0/2] CLK: TI: add dpll_clksel_mac_clk node

[Keerthy]

On Thursday 18 June 2015 02:36 PM, Mugunthan V N wrote:
> On Thursday 18 June 2015 01:31 PM, Keerthy wrote:
>> The series adds the missing clock node needed for cpsw.
>>
>> Keerthy (2):
>>    CLK: TI: add dpll_clksel_mac_clk node
>>    ARM: dts: am4372: Set the default clock rate for dpll_clksel_mac_clk
>>      clock
>>
>>   arch/arm/boot/dts/am4372.dtsi        | 7 +++++--
>>   arch/arm/boot/dts/am43xx-clocks.dtsi | 9 +++++++++
>>   drivers/clk/ti/clk-43xx.c            | 1 +
>>   3 files changed, 15 insertions(+), 2 deletions(-)
>>
>
> Tested-by: Mugunthan V N <mugunthanvnm@ti.com>

Thanks Mugunthan.

A gentle ping on this series.

Regards,
Keerthy
>
> Regards
> Mugunthan V N
>

Re: [PATCH 0/2] CLK: TI: add dpll_clksel_mac_clk node

[Tony Lindgren]

* Keerthy <a0393675@ti.com> [150625 06:48]:
> 
> On Thursday 18 June 2015 02:36 PM, Mugunthan V N wrote:
> >On Thursday 18 June 2015 01:31 PM, Keerthy wrote:
> >>The series adds the missing clock node needed for cpsw.
> >>
> >>Keerthy (2):
> >>   CLK: TI: add dpll_clksel_mac_clk node
> >>   ARM: dts: am4372: Set the default clock rate for dpll_clksel_mac_clk
> >>     clock
> >>
> >>  arch/arm/boot/dts/am4372.dtsi        | 7 +++++--
> >>  arch/arm/boot/dts/am43xx-clocks.dtsi | 9 +++++++++
> >>  drivers/clk/ti/clk-43xx.c            | 1 +
> >>  3 files changed, 15 insertions(+), 2 deletions(-)
> >>
> >
> >Tested-by: Mugunthan V N <mugunthanvnm@ti.com>
> 
> Thanks Mugunthan.
> 
> A gentle ping on this series.

Tero, care to review this series?

Regards,

Tony

Re: [PATCH 0/2] CLK: TI: add dpll_clksel_mac_clk node

[Tero Kristo]

On 07/14/2015 02:06 PM, Tony Lindgren wrote:
> * Keerthy <a0393675@ti.com> [150625 06:48]:
>>
>> On Thursday 18 June 2015 02:36 PM, Mugunthan V N wrote:
>>> On Thursday 18 June 2015 01:31 PM, Keerthy wrote:
>>>> The series adds the missing clock node needed for cpsw.
>>>>
>>>> Keerthy (2):
>>>>    CLK: TI: add dpll_clksel_mac_clk node
>>>>    ARM: dts: am4372: Set the default clock rate for dpll_clksel_mac_clk
>>>>      clock
>>>>
>>>>   arch/arm/boot/dts/am4372.dtsi        | 7 +++++--
>>>>   arch/arm/boot/dts/am43xx-clocks.dtsi | 9 +++++++++
>>>>   drivers/clk/ti/clk-43xx.c            | 1 +
>>>>   3 files changed, 15 insertions(+), 2 deletions(-)
>>>>
>>>
>>> Tested-by: Mugunthan V N <mugunthanvnm@ti.com>
>>
>> Thanks Mugunthan.
>>
>> A gentle ping on this series.
>
> Tero, care to review this series?

Acked-by: Tero Kristo <t-kristo@ti.com>

I guess this should go through your tree as this is mostly dts changes?

-Tero

>
> Regards,
>
> Tony
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Re: [PATCH 0/2] CLK: TI: add dpll_clksel_mac_clk node

[Tony Lindgren]

* Tero Kristo <t-kristo@ti.com> [150714 06:30]:
> On 07/14/2015 02:06 PM, Tony Lindgren wrote:
> >* Keerthy <a0393675@ti.com> [150625 06:48]:
> >>
> >>On Thursday 18 June 2015 02:36 PM, Mugunthan V N wrote:
> >>>On Thursday 18 June 2015 01:31 PM, Keerthy wrote:
> >>>>The series adds the missing clock node needed for cpsw.
> >>>>
> >>>>Keerthy (2):
> >>>>   CLK: TI: add dpll_clksel_mac_clk node
> >>>>   ARM: dts: am4372: Set the default clock rate for dpll_clksel_mac_clk
> >>>>     clock
> >>>>
> >>>>  arch/arm/boot/dts/am4372.dtsi        | 7 +++++--
> >>>>  arch/arm/boot/dts/am43xx-clocks.dtsi | 9 +++++++++
> >>>>  drivers/clk/ti/clk-43xx.c            | 1 +
> >>>>  3 files changed, 15 insertions(+), 2 deletions(-)
> >>>>
> >>>
> >>>Tested-by: Mugunthan V N <mugunthanvnm@ti.com>
> >>
> >>Thanks Mugunthan.
> >>
> >>A gentle ping on this series.
> >
> >Tero, care to review this series?
> 
> Acked-by: Tero Kristo <t-kristo@ti.com>
> 
> I guess this should go through your tree as this is mostly dts changes?

Actually I don't have anything coming for the clock dtsi files for
v4.3 merge window, so it's best that you queue these. For the dts
changes, please feel free to add:

Acked-by: Tony Lindgren <tony@atomide.com>