From mboxrd@z Thu Jan 1 00:00:00 1970 From: Roger Quadros Subject: Re: [PATCH v2 3/3] ARM: dts: dra7: Add syscon-pllreset syscon to SATA PHY Date: Wed, 15 Jul 2015 16:47:50 +0300 Message-ID: <55A66486.9000609@ti.com> References: <1433236242-26172-1-git-send-email-rogerq@ti.com> <1433236242-26172-4-git-send-email-rogerq@ti.com> <55A64253.100@ti.com> <20150715120745.GE17550@atomide.com> Mime-Version: 1.0 Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20150715120745.GE17550@atomide.com> Sender: linux-kernel-owner@vger.kernel.org To: Tony Lindgren , Kishon Vijay Abraham I Cc: nm@ti.com, nsekhar@ti.com, balbi@ti.com, grygorii.strashko@ti.com, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, Tero Kristo List-Id: linux-omap@vger.kernel.org Hi, On 15/07/15 15:07, Tony Lindgren wrote: > * Kishon Vijay Abraham I [150715 04:24]: >> Hi Roger, >> >> On Tuesday 02 June 2015 02:40 PM, Roger Quadros wrote: >>> This register is required to be passed to the SATA PHY driver >>> to workaround errata i783 (SATA Lockup After SATA DPLL Unlock/Relock). >>> >>> Signed-off-by: Roger Quadros >>> Signed-off-by: Sekhar Nori >>> --- >>> arch/arm/boot/dts/dra7.dtsi | 1 + >>> 1 file changed, 1 insertion(+) >>> >>> diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi >>> index f03a091..260f300 100644 >>> --- a/arch/arm/boot/dts/dra7.dtsi >>> +++ b/arch/arm/boot/dts/dra7.dtsi >>> @@ -1135,6 +1135,7 @@ >>> ctrl-module = <&omap_control_sata>; >>> clocks = <&sys_clkin1>, <&sata_ref_clk>; >>> clock-names = "sysclk", "refclk"; >>> + syscon-pllreset = <&dra7_ctrl_core 0x3fc>; >> >> I think all users of syscon should be made child node of scm_conf. Tony and >> Tero, is that right? It can't be child of scm_conf as the address is outside it's range. Looks like I have to add a new child to scm node that maps beyond the dra7_pmx_core padconf address range. >> >> If so, then we might have to modify the driver too. > > Yeah there should not be much need to use syscon outside scm_conf > area and for I2C devices. If there's some other misc register area > in dra7 in addition to scm_conf then it might make sense to use it. > > But in general, for the SCM registers, just a normal loadable kernel > driver module doing of_ioremap on a dedicated range of registers is > always a better option :) > Lets take for example this register CTRL_CORE_SMA_SW_0. It has the SATA PLL_SOFT_RESET bit, EMIF1/2 gating control bits and ISOLATE bit. I don't see this fitting in any driver except the syscon approach. cheers, -roger