From mboxrd@z Thu Jan  1 00:00:00 1970
From: Peter Ujfalusi <peter.ujfalusi@ti.com>
Subject: Re: [PATCH v4 20/25] dmaengine: edma: Simplify the interrupt handling
Date: Wed, 14 Oct 2015 14:16:06 +0300
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On 10/14/2015 02:12 PM, Peter Ujfalusi wrote:
>>> +		} else if (edma_read(ecc, EDMA_QEMR)) {
>>> +			dev_dbg(ecc->dev, "QEMR %02x\n",
>>> +				edma_read(ecc, EDMA_QEMR));
>>> +			for (i =3D 0; i < 8; i++) {
>>> +				if (edma_read(ecc, EDMA_QEMR) & BIT(i)) {
>>> +					/* Clear the corresponding IPR bits */
>>> +					edma_write(ecc, EDMA_QEMCR, BIT(i));
>>> +					edma_shadow0_write(ecc, SH_QSECR,
>>> +							   BIT(i));
>>> +
>>> +					/* NOTE:  not reported!! */
>>
>> what does this mean?
>=20
> For QEMR and CCERR registers the Linux driver only acks the event, bu=
t do not
> do anything.
> In Linux we are not using the qDMA of the eDMA3 and there is not much=
 we can
> do when the CCERR happens.
> Hrm, probably moving the CCERR print to dev_err() might be useful, bu=
t again I
> have not seen this happen. But if it does, we need to come up with so=
mething
> to avoid it. Basically repartition the use of Transfer Controllers, b=
ut this
> can not be done with this stack. An upcoming series will give us ways=
 to fine
> tune the use of TCs.

In the interrupt handler simplification patch I move the CCERR to dev_w=
arn()
so I leave it like this for this patch - as the function has been just =
moved
down in the code to be able to call the actual handler of the events.

--=20
P=E9ter