* [PATCH 0/4] RX51: SDRAM settings changes @ 2009-10-26 16:15 Tero Kristo 2009-10-26 16:15 ` [PATCH 1/4] RX51: Add SDRAM configs for different OPPs Tero Kristo 2009-10-26 18:50 ` [PATCH 0/4] RX51: SDRAM settings changes Kevin Hilman 0 siblings, 2 replies; 7+ messages in thread From: Tero Kristo @ 2009-10-26 16:15 UTC (permalink / raw) To: linux-omap From: Tero Kristo <tero.kristo@nokia.com> Following patch set fixes a few issues with current RX51 board SDRAM settings. Applies on top of PM branch. -Tero ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 1/4] RX51: Add SDRAM configs for different OPPs 2009-10-26 16:15 [PATCH 0/4] RX51: SDRAM settings changes Tero Kristo @ 2009-10-26 16:15 ` Tero Kristo 2009-10-26 16:15 ` [PATCH 2/4] RX51: SDRAM: Cleanup the init code Tero Kristo 2009-10-26 18:50 ` [PATCH 0/4] RX51: SDRAM settings changes Kevin Hilman 1 sibling, 1 reply; 7+ messages in thread From: Tero Kristo @ 2009-10-26 16:15 UTC (permalink / raw) To: linux-omap From: Tero Kristo <tero.kristo@nokia.com> This modification is needed by DVFS. Signed-off-by: Tero Kristo <tero.kristo@nokia.com> Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com> --- arch/arm/mach-omap2/board-rx51-sdram.c | 84 ++++++++++++++++++-------------- 1 files changed, 47 insertions(+), 37 deletions(-) diff --git a/arch/arm/mach-omap2/board-rx51-sdram.c b/arch/arm/mach-omap2/board-rx51-sdram.c index 6f1f33c..78cd5ed 100644 --- a/arch/arm/mach-omap2/board-rx51-sdram.c +++ b/arch/arm/mach-omap2/board-rx51-sdram.c @@ -44,7 +44,7 @@ struct sdram_info { }; -struct omap_sdrc_params rx51_sdrc_params[2]; +struct omap_sdrc_params rx51_sdrc_params[4]; static const struct sdram_timings rx51_timings[] = { { @@ -118,30 +118,28 @@ static unsigned long get_l3_rate(void) return get_core_rate() / (l & 0x03); } - - -static unsigned long sdrc_get_fclk_period(void) +static unsigned long sdrc_get_fclk_period(long rate) { /* In picoseconds */ - return 1000000000 / get_l3_rate(); + return 1000000000 / rate; } -static unsigned int sdrc_ps_to_ticks(unsigned int time_ps) +static unsigned int sdrc_ps_to_ticks(unsigned int time_ps, long rate) { unsigned long tick_ps; /* Calculate in picosecs to yield more exact results */ - tick_ps = sdrc_get_fclk_period(); + tick_ps = sdrc_get_fclk_period(rate); return (time_ps + tick_ps - 1) / tick_ps; } #undef DEBUG #ifdef DEBUG static int set_sdrc_timing_regval(u32 *regval, int st_bit, int end_bit, - int time, const char *name) + int time, long rate, const char *name) #else static int set_sdrc_timing_regval(u32 *regval, int st_bit, int end_bit, - int time) + int time, long rate) #endif { int ticks, mask, nr_bits; @@ -149,7 +147,7 @@ static int set_sdrc_timing_regval(u32 *regval, int st_bit, int end_bit, if (time == 0) ticks = 0; else - ticks = sdrc_ps_to_ticks(time); + ticks = sdrc_ps_to_ticks(time, rate); nr_bits = end_bit - st_bit + 1; if (ticks >= 1 << nr_bits) return -1; @@ -158,42 +156,46 @@ static int set_sdrc_timing_regval(u32 *regval, int st_bit, int end_bit, *regval |= ticks << st_bit; #ifdef DEBUG printk("SDRC %s: %i ticks %i ns\n", name, ticks, - (unsigned int)sdrc_get_fclk_period() * ticks / 1000); + (unsigned int)sdrc_get_fclk_period(rate) * ticks / + 1000); #endif return 0; } #ifdef DEBUG -#define SDRC_SET_ONE(reg, st, end, field) \ - if (set_sdrc_timing_regval((reg), (st), (end), rx51_timings->field, #field) < 0) \ - err = -1 +#define SDRC_SET_ONE(reg, st, end, field, rate) \ + if (set_sdrc_timing_regval((reg), (st), (end), \ + rx51_timings->field, (rate), #field) < 0) \ + err = -1; #else -#define SDRC_SET_ONE(reg, st, end, field) \ - if (set_sdrc_timing_regval((reg), (st), (end), rx51_timings->field) < 0) \ - err = -1 +#define SDRC_SET_ONE(reg, st, end, field, rate) \ + if (set_sdrc_timing_regval((reg), (st), (end), \ + rx51_timings->field, (rate)) < 0) \ + err = -1; #endif -struct omap_sdrc_params *rx51_get_sdram_timings(void) +static int sdrc_timings(int id, long rate) { u32 ticks_per_ms; u32 rfr, l; - u32 actim_ctrla, actim_ctrlb; + u32 actim_ctrla = 0, actim_ctrlb = 0; u32 rfr_ctrl; int err = 0; + long l3_rate = rate / 1000; - SDRC_SET_ONE(&actim_ctrla, 0, 4, tDAL); - SDRC_SET_ONE(&actim_ctrla, 6, 8, tDPL); - SDRC_SET_ONE(&actim_ctrla, 9, 11, tRRD); - SDRC_SET_ONE(&actim_ctrla, 12, 14, tRCD); - SDRC_SET_ONE(&actim_ctrla, 15, 17, tRP); - SDRC_SET_ONE(&actim_ctrla, 18, 21, tRAS); - SDRC_SET_ONE(&actim_ctrla, 22, 26, tRC); - SDRC_SET_ONE(&actim_ctrla, 27, 31, tRFC); + SDRC_SET_ONE(&actim_ctrla, 0, 4, tDAL, l3_rate); + SDRC_SET_ONE(&actim_ctrla, 6, 8, tDPL, l3_rate); + SDRC_SET_ONE(&actim_ctrla, 9, 11, tRRD, l3_rate); + SDRC_SET_ONE(&actim_ctrla, 12, 14, tRCD, l3_rate); + SDRC_SET_ONE(&actim_ctrla, 15, 17, tRP, l3_rate); + SDRC_SET_ONE(&actim_ctrla, 18, 21, tRAS, l3_rate); + SDRC_SET_ONE(&actim_ctrla, 22, 26, tRC, l3_rate); + SDRC_SET_ONE(&actim_ctrla, 27, 31, tRFC, l3_rate); - SDRC_SET_ONE(&actim_ctrlb, 0, 7, tXSR); + SDRC_SET_ONE(&actim_ctrlb, 0, 7, tXSR, l3_rate); - ticks_per_ms = sdrc_ps_to_ticks(1000000000); + ticks_per_ms = sdrc_ps_to_ticks(1000000000, l3_rate); rfr = rx51_timings[0].tREF * ticks_per_ms / (1 << rx51_info.row_lines); if (rfr > 65535 + 50) rfr = 65535; @@ -203,16 +205,24 @@ struct omap_sdrc_params *rx51_get_sdram_timings(void) l = rfr << 8; rfr_ctrl = l | 0x3; /* autorefresh, reload counter with 8xARCV */ - rx51_sdrc_params[0].rate = 133333333; - rx51_sdrc_params[0].actim_ctrla = actim_ctrla; - rx51_sdrc_params[0].actim_ctrlb = actim_ctrlb; - rx51_sdrc_params[0].rfr_ctrl = rfr_ctrl; - rx51_sdrc_params[0].mr = 0x32; + rx51_sdrc_params[id].rate = rate; + rx51_sdrc_params[id].actim_ctrla = actim_ctrla; + rx51_sdrc_params[id].actim_ctrlb = actim_ctrlb; + rx51_sdrc_params[id].rfr_ctrl = rfr_ctrl; + rx51_sdrc_params[id].mr = 0x32; + + rx51_sdrc_params[id + 1].rate = 0; - rx51_sdrc_params[1].rate = 0; + return err; +} + +struct omap_sdrc_params *rx51_get_sdram_timings(void) +{ + int err; - if (err < 0) - return NULL; + err = sdrc_timings(0, 41500000); + err = sdrc_timings(1, 83000000); + err |= sdrc_timings(2, 166000000); return &rx51_sdrc_params[0]; } -- 1.5.4.3 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 2/4] RX51: SDRAM: Cleanup the init code 2009-10-26 16:15 ` [PATCH 1/4] RX51: Add SDRAM configs for different OPPs Tero Kristo @ 2009-10-26 16:15 ` Tero Kristo 2009-10-26 16:15 ` [PATCH 3/4] RX51: SDRC: change timing values to follow generic memory requirements Tero Kristo 0 siblings, 1 reply; 7+ messages in thread From: Tero Kristo @ 2009-10-26 16:15 UTC (permalink / raw) To: linux-omap From: Tero Kristo <tero.kristo@nokia.com> Removed a few unused functions + macro definitions + variables from the code. Signed-off-by: Tero Kristo <tero.kristo@nokia.com> --- arch/arm/mach-omap2/board-rx51-sdram.c | 51 -------------------------------- 1 files changed, 0 insertions(+), 51 deletions(-) diff --git a/arch/arm/mach-omap2/board-rx51-sdram.c b/arch/arm/mach-omap2/board-rx51-sdram.c index 78cd5ed..b5d1c55 100644 --- a/arch/arm/mach-omap2/board-rx51-sdram.c +++ b/arch/arm/mach-omap2/board-rx51-sdram.c @@ -67,57 +67,6 @@ static const struct sdram_info rx51_info = { .row_lines = 13, }; -#define CM_BASE 0x48004000 - -#define CM_CLKSEL_CORE 0x0a40 -#define CM_CLKSEL1_PLL 0x0d40 - -#define PRM_CLKSEL 0x48306d40 -#define PRM_CLKSRC_CTRL 0x48307270 - -static u32 cm_base = CM_BASE; - -static inline u32 cm_read_reg(int idx) -{ - return *(u32 *)OMAP2_L4_IO_ADDRESS(cm_base + idx); -} - -static const unsigned long sys_clk_rate_table[] = { - 12000, 13000, 19200, 26000, 38400, 16800 -}; - -static unsigned long get_sys_clk_rate(void) -{ - unsigned long rate; - - rate = sys_clk_rate_table[*(u32 *)OMAP2_L4_IO_ADDRESS(PRM_CLKSEL) & 0x07]; - if (((*(u32 *)OMAP2_L4_IO_ADDRESS(PRM_CLKSRC_CTRL) >> 6) & 0x03) == 0x02) - rate /= 2; - return rate; -} - -static unsigned long get_core_rate(void) -{ - unsigned long rate; - u32 l; - - l = cm_read_reg(CM_CLKSEL1_PLL); - rate = get_sys_clk_rate(); - rate *= ((l >> 16) & 0x7ff); - rate /= ((l >> 8) & 0x7f) + 1; - rate /= (l >> 27) & 0x1f; - - return rate; -} - -static unsigned long get_l3_rate(void) -{ - u32 l; - - l = cm_read_reg(CM_CLKSEL_CORE); - return get_core_rate() / (l & 0x03); -} - static unsigned long sdrc_get_fclk_period(long rate) { /* In picoseconds */ -- 1.5.4.3 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 3/4] RX51: SDRC: change timing values to follow generic memory requirements 2009-10-26 16:15 ` [PATCH 2/4] RX51: SDRAM: Cleanup the init code Tero Kristo @ 2009-10-26 16:15 ` Tero Kristo 2009-10-26 16:15 ` [PATCH 4/4] RX51: Fix SDRAM RFR timings calculation Tero Kristo 0 siblings, 1 reply; 7+ messages in thread From: Tero Kristo @ 2009-10-26 16:15 UTC (permalink / raw) To: linux-omap; +Cc: Onkalo Samu.P From: Onkalo Samu.P <samu.p.onkalo@nokia.com> Current memory parameters are slightly off-spec. Also, a couple of unused functions removed from code. Signed-off-by: Samu Onkalo <samu.p.onkalo@nokia.com> --- arch/arm/mach-omap2/board-rx51-sdram.c | 130 ++++++++++++++++++++++---------- 1 files changed, 91 insertions(+), 39 deletions(-) diff --git a/arch/arm/mach-omap2/board-rx51-sdram.c b/arch/arm/mach-omap2/board-rx51-sdram.c index b5d1c55..237b898 100644 --- a/arch/arm/mach-omap2/board-rx51-sdram.c +++ b/arch/arm/mach-omap2/board-rx51-sdram.c @@ -1,5 +1,5 @@ /* - * SDRC register values for the Samsung K4X1G323PC + * SDRC register values for RX51 * * Copyright (C) 2008 Nokia Corporation * @@ -23,7 +23,7 @@ #include <mach/sdrc.h> -/* In picoseconds, except for tREF */ +/* In picoseconds, except for tREF (ns), tXP, tCKE, tWTR (clks) */ struct sdram_timings { u32 casl; u32 tDAL; @@ -36,7 +36,11 @@ struct sdram_timings { u32 tRFC; u32 tXSR; - u32 tREF; /* in ms */ + u32 tREF; /* in ns */ + + u32 tXP; + u32 tCKE; + u32 tWTR; }; struct sdram_info { @@ -49,22 +53,22 @@ struct omap_sdrc_params rx51_sdrc_params[4]; static const struct sdram_timings rx51_timings[] = { { .casl = 3, - .tDAL = 15000 + 18000, + .tDAL = 33000, .tDPL = 15000, .tRRD = 12000, - .tRCD = 18000, + .tRCD = 22500, .tRP = 18000, .tRAS = 42000, .tRC = 66000, - .tRFC = 97500, - .tXSR = 120000, + .tRFC = 138000, + .tXSR = 200000, - .tREF = 64, - }, -}; + .tREF = 7800, -static const struct sdram_info rx51_info = { - .row_lines = 13, + .tXP = 2, + .tCKE = 2, + .tWTR = 2 + }, }; static unsigned long sdrc_get_fclk_period(long rate) @@ -85,18 +89,14 @@ static unsigned int sdrc_ps_to_ticks(unsigned int time_ps, long rate) #undef DEBUG #ifdef DEBUG static int set_sdrc_timing_regval(u32 *regval, int st_bit, int end_bit, - int time, long rate, const char *name) + int ticks, long rate, const char *name) #else static int set_sdrc_timing_regval(u32 *regval, int st_bit, int end_bit, - int time, long rate) + int ticks) #endif { - int ticks, mask, nr_bits; + int mask, nr_bits; - if (time == 0) - ticks = 0; - else - ticks = sdrc_ps_to_ticks(time, rate); nr_bits = end_bit - st_bit + 1; if (ticks >= 1 << nr_bits) return -1; @@ -104,7 +104,7 @@ static int set_sdrc_timing_regval(u32 *regval, int st_bit, int end_bit, *regval &= ~(mask << st_bit); *regval |= ticks << st_bit; #ifdef DEBUG - printk("SDRC %s: %i ticks %i ns\n", name, ticks, + printk(KERN_INFO "SDRC %s: %i ticks %i ns\n", name, ticks, (unsigned int)sdrc_get_fclk_period(rate) * ticks / 1000); #endif @@ -113,46 +113,98 @@ static int set_sdrc_timing_regval(u32 *regval, int st_bit, int end_bit, } #ifdef DEBUG -#define SDRC_SET_ONE(reg, st, end, field, rate) \ - if (set_sdrc_timing_regval((reg), (st), (end), \ +#define SDRC_SET_ONE(reg, st, end, field, rate) \ + if (set_sdrc_timing_regval((reg), (st), (end), \ rx51_timings->field, (rate), #field) < 0) \ err = -1; #else -#define SDRC_SET_ONE(reg, st, end, field, rate) \ - if (set_sdrc_timing_regval((reg), (st), (end), \ - rx51_timings->field, (rate)) < 0) \ +#define SDRC_SET_ONE(reg, st, end, field, rate) \ + if (set_sdrc_timing_regval((reg), (st), (end), \ + rx51_timings->field, (rate)) < 0) \ + err = -1; +#endif + +#ifdef DEBUG +static int set_sdrc_timing_regval_ps(u32 *regval, int st_bit, int end_bit, + int time, long rate, const char *name) +#else +static int set_sdrc_timing_regval_ps(u32 *regval, int st_bit, int end_bit, + int time, long rate) +#endif +{ + int ticks, ret; + ret = 0; + + if (time == 0) + ticks = 0; + else + ticks = sdrc_ps_to_ticks(time, rate); + +#ifdef DEBUG + ret = set_sdrc_timing_regval(regval, st_bit, end_bit, ticks, + rate, name); +#else + ret = set_sdrc_timing_regval(regval, st_bit, end_bit, ticks); +#endif + + return ret; +} + +#ifdef DEBUG +#define SDRC_SET_ONE_PS(reg, st, end, field, rate) \ + if (set_sdrc_timing_regval_ps((reg), (st), (end), \ + rx51_timings->field, \ + (rate), #field) < 0) \ + err = -1; + +#else +#define SDRC_SET_ONE_PS(reg, st, end, field, rate) \ + if (set_sdrc_timing_regval_ps((reg), (st), (end), \ + rx51_timings->field, (rate)) < 0) \ err = -1; #endif static int sdrc_timings(int id, long rate) { - u32 ticks_per_ms; + u32 ticks_per_us; u32 rfr, l; u32 actim_ctrla = 0, actim_ctrlb = 0; u32 rfr_ctrl; int err = 0; long l3_rate = rate / 1000; - SDRC_SET_ONE(&actim_ctrla, 0, 4, tDAL, l3_rate); - SDRC_SET_ONE(&actim_ctrla, 6, 8, tDPL, l3_rate); - SDRC_SET_ONE(&actim_ctrla, 9, 11, tRRD, l3_rate); - SDRC_SET_ONE(&actim_ctrla, 12, 14, tRCD, l3_rate); - SDRC_SET_ONE(&actim_ctrla, 15, 17, tRP, l3_rate); - SDRC_SET_ONE(&actim_ctrla, 18, 21, tRAS, l3_rate); - SDRC_SET_ONE(&actim_ctrla, 22, 26, tRC, l3_rate); - SDRC_SET_ONE(&actim_ctrla, 27, 31, tRFC, l3_rate); +#ifdef DEBUG + printk(KERN_INFO "SDRC CLK rate: %i MHz\n", (int)l3_rate/1000); +#endif + + SDRC_SET_ONE_PS(&actim_ctrla, 0, 4, tDAL, l3_rate); + SDRC_SET_ONE_PS(&actim_ctrla, 6, 8, tDPL, l3_rate); + SDRC_SET_ONE_PS(&actim_ctrla, 9, 11, tRRD, l3_rate); + SDRC_SET_ONE_PS(&actim_ctrla, 12, 14, tRCD, l3_rate); + SDRC_SET_ONE_PS(&actim_ctrla, 15, 17, tRP, l3_rate); + SDRC_SET_ONE_PS(&actim_ctrla, 18, 21, tRAS, l3_rate); + SDRC_SET_ONE_PS(&actim_ctrla, 22, 26, tRC, l3_rate); + SDRC_SET_ONE_PS(&actim_ctrla, 27, 31, tRFC, l3_rate); - SDRC_SET_ONE(&actim_ctrlb, 0, 7, tXSR, l3_rate); + SDRC_SET_ONE_PS(&actim_ctrlb, 0, 7, tXSR, l3_rate); - ticks_per_ms = sdrc_ps_to_ticks(1000000000, l3_rate); - rfr = rx51_timings[0].tREF * ticks_per_ms / (1 << rx51_info.row_lines); + SDRC_SET_ONE(&actim_ctrlb, 8, 10, tXP, l3_rate); + SDRC_SET_ONE(&actim_ctrlb, 12, 14, tCKE, l3_rate); + SDRC_SET_ONE(&actim_ctrlb, 16, 17, tWTR, l3_rate); + + ticks_per_us = sdrc_ps_to_ticks(1000000, l3_rate); + rfr = rx51_timings[0].tREF * ticks_per_us / 1000; if (rfr > 65535 + 50) rfr = 65535; else rfr -= 50; +#ifdef DEBUG + printk(KERN_INFO "SDRC tREF: %i ticks\n", rfr); +#endif + l = rfr << 8; - rfr_ctrl = l | 0x3; /* autorefresh, reload counter with 8xARCV */ + rfr_ctrl = l | 0x1; /* autorefresh, reload counter with 1xARCV */ rx51_sdrc_params[id].rate = rate; rx51_sdrc_params[id].actim_ctrla = actim_ctrla; @@ -170,7 +222,7 @@ struct omap_sdrc_params *rx51_get_sdram_timings(void) int err; err = sdrc_timings(0, 41500000); - err = sdrc_timings(1, 83000000); + err |= sdrc_timings(1, 83000000); err |= sdrc_timings(2, 166000000); return &rx51_sdrc_params[0]; -- 1.5.4.3 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 4/4] RX51: Fix SDRAM RFR timings calculation 2009-10-26 16:15 ` [PATCH 3/4] RX51: SDRC: change timing values to follow generic memory requirements Tero Kristo @ 2009-10-26 16:15 ` Tero Kristo 0 siblings, 0 replies; 7+ messages in thread From: Tero Kristo @ 2009-10-26 16:15 UTC (permalink / raw) To: linux-omap; +Cc: Kalle Jokiniemi From: Kalle Jokiniemi <kalle.jokiniemi@digia.com> sdrc_ps_to_ticks introduced some unnecessary rounding error to SDRC_RFR value calculation. Fixed by adding 10^3 more accuracy before division and skipping the sdrc_ps_to_ticks call. Problem-reported-by: Jukka S. Laitinen <jukka.s.laitinen@nokia.com> Signed-off-by: Kalle Jokiniemi <kalle.jokiniemi@digia.com> --- arch/arm/mach-omap2/board-rx51-sdram.c | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-omap2/board-rx51-sdram.c b/arch/arm/mach-omap2/board-rx51-sdram.c index 237b898..f3b9917 100644 --- a/arch/arm/mach-omap2/board-rx51-sdram.c +++ b/arch/arm/mach-omap2/board-rx51-sdram.c @@ -166,7 +166,7 @@ static int set_sdrc_timing_regval_ps(u32 *regval, int st_bit, int end_bit, static int sdrc_timings(int id, long rate) { - u32 ticks_per_us; + u32 ticks_per_ms; u32 rfr, l; u32 actim_ctrla = 0, actim_ctrlb = 0; u32 rfr_ctrl; @@ -192,8 +192,8 @@ static int sdrc_timings(int id, long rate) SDRC_SET_ONE(&actim_ctrlb, 12, 14, tCKE, l3_rate); SDRC_SET_ONE(&actim_ctrlb, 16, 17, tWTR, l3_rate); - ticks_per_us = sdrc_ps_to_ticks(1000000, l3_rate); - rfr = rx51_timings[0].tREF * ticks_per_us / 1000; + ticks_per_ms = l3_rate; + rfr = rx51_timings[0].tREF * ticks_per_ms / 1000000; if (rfr > 65535 + 50) rfr = 65535; else -- 1.5.4.3 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 0/4] RX51: SDRAM settings changes 2009-10-26 16:15 [PATCH 0/4] RX51: SDRAM settings changes Tero Kristo 2009-10-26 16:15 ` [PATCH 1/4] RX51: Add SDRAM configs for different OPPs Tero Kristo @ 2009-10-26 18:50 ` Kevin Hilman 2009-10-27 12:48 ` Tero.Kristo 1 sibling, 1 reply; 7+ messages in thread From: Kevin Hilman @ 2009-10-26 18:50 UTC (permalink / raw) To: Tero Kristo; +Cc: linux-omap Tero Kristo <tero.kristo@nokia.com> writes: > From: Tero Kristo <tero.kristo@nokia.com> > > Following patch set fixes a few issues with current RX51 board SDRAM settings. > Applies on top of PM branch. > Tero, Can you resend this series against the master branch? There is no reason this should be carried in the PM branch anymore. You'll have to add to your series the patch to add the board-rx51-sdram.c file, which I currently carry in the PM branch. Then, for the PM branch, we just need a small patch to add the various rate tables in the call to init_common_hw until DVFS stuff is upstream. Kevin ^ permalink raw reply [flat|nested] 7+ messages in thread
* RE: [PATCH 0/4] RX51: SDRAM settings changes 2009-10-26 18:50 ` [PATCH 0/4] RX51: SDRAM settings changes Kevin Hilman @ 2009-10-27 12:48 ` Tero.Kristo 0 siblings, 0 replies; 7+ messages in thread From: Tero.Kristo @ 2009-10-27 12:48 UTC (permalink / raw) To: khilman; +Cc: linux-omap >-----Original Message----- >From: ext Kevin Hilman [mailto:khilman@deeprootsystems.com] >Sent: 26 October, 2009 20:50 >To: Kristo Tero (Nokia-D/Tampere) >Cc: linux-omap@vger.kernel.org >Subject: Re: [PATCH 0/4] RX51: SDRAM settings changes > >Tero Kristo <tero.kristo@nokia.com> writes: > >> From: Tero Kristo <tero.kristo@nokia.com> >> >> Following patch set fixes a few issues with current RX51 >board SDRAM settings. >> Applies on top of PM branch. >> > >Tero, > >Can you resend this series against the master branch? There >is no reason >this should be carried in the PM branch anymore. > >You'll have to add to your series the patch to add the >board-rx51-sdram.c file, which I currently carry in the PM branch. > >Then, for the PM branch, we just need a small patch to add the various >rate tables in the call to init_common_hw until DVFS stuff is >upstream. Ok, I have now done this. I also combined the series into one patch as it will generate a new file and I don't see any need to clutter git-log with several patches to currently non-existent file. Sending out now. -Tero ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2009-10-27 12:48 UTC | newest] Thread overview: 7+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2009-10-26 16:15 [PATCH 0/4] RX51: SDRAM settings changes Tero Kristo 2009-10-26 16:15 ` [PATCH 1/4] RX51: Add SDRAM configs for different OPPs Tero Kristo 2009-10-26 16:15 ` [PATCH 2/4] RX51: SDRAM: Cleanup the init code Tero Kristo 2009-10-26 16:15 ` [PATCH 3/4] RX51: SDRC: change timing values to follow generic memory requirements Tero Kristo 2009-10-26 16:15 ` [PATCH 4/4] RX51: Fix SDRAM RFR timings calculation Tero Kristo 2009-10-26 18:50 ` [PATCH 0/4] RX51: SDRAM settings changes Kevin Hilman 2009-10-27 12:48 ` Tero.Kristo
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