* [PATCH 00/17] OMAP3: Base support for VDD2 DVFS
@ 2009-01-09 15:45 Tero Kristo
2009-01-09 15:45 ` [PATCH 01/17] ARM: MMU: add a Non-cacheable Normal executable memory type Tero Kristo
2009-01-13 17:13 ` [PATCH 00/17] OMAP3: Base support for VDD2 DVFS Kevin Hilman
0 siblings, 2 replies; 19+ messages in thread
From: Tero Kristo @ 2009-01-09 15:45 UTC (permalink / raw)
To: linux-omap
Resending this set against the latest PM branch. This set provides base
SDRC + SRAM + clock framework support for VDD2 DVFS control. Main reasoning
for this set is that when VDD2 clock is changed, memory clocking changes also
and you need to be rather careful when you are doing this.
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH 01/17] ARM: MMU: add a Non-cacheable Normal executable memory type
2009-01-09 15:45 [PATCH 00/17] OMAP3: Base support for VDD2 DVFS Tero Kristo
@ 2009-01-09 15:45 ` Tero Kristo
2009-01-09 15:45 ` [PATCH 02/17] OMAP3 SRAM: mark OCM RAM as Non-cacheable Normal memory Tero Kristo
2009-01-13 17:13 ` [PATCH 00/17] OMAP3: Base support for VDD2 DVFS Kevin Hilman
1 sibling, 1 reply; 19+ messages in thread
From: Tero Kristo @ 2009-01-09 15:45 UTC (permalink / raw)
To: linux-omap; +Cc: Paul Walmsley
From: Paul Walmsley <paul@pwsan.com>
Add a Non-cacheable Normal ARM executable memory type,
MT_MEMORY_NONCACHED. This is needed for the OMAP3 SDRAM clock change
code, which must run from SRAM. The SRAM must be marked as
non-cacheable memory to avoid dirty cache line writebacks to SDRAM
while the SDRAM controller is paused.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
arch/arm/include/asm/mach/map.h | 1 +
arch/arm/mm/mmu.c | 23 +++++++++++++++++++++++
2 files changed, 24 insertions(+), 0 deletions(-)
diff --git a/arch/arm/include/asm/mach/map.h b/arch/arm/include/asm/mach/map.h
index 39d949b..58cf91f 100644
--- a/arch/arm/include/asm/mach/map.h
+++ b/arch/arm/include/asm/mach/map.h
@@ -26,6 +26,7 @@ struct map_desc {
#define MT_HIGH_VECTORS 8
#define MT_MEMORY 9
#define MT_ROM 10
+#define MT_MEMORY_NONCACHED 11
#ifdef CONFIG_MMU
extern void iotable_init(struct map_desc *, int);
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 7f36c82..9ad6413 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -242,6 +242,10 @@ static struct mem_type mem_types[] = {
.prot_sect = PMD_TYPE_SECT,
.domain = DOMAIN_KERNEL,
},
+ [MT_MEMORY_NONCACHED] = {
+ .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
+ .domain = DOMAIN_KERNEL,
+ },
};
const struct mem_type *get_mem_type(unsigned int type)
@@ -405,9 +409,28 @@ static void __init build_mem_type_table(void)
kern_pgprot |= L_PTE_SHARED;
vecs_pgprot |= L_PTE_SHARED;
mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
+ mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
#endif
}
+ /*
+ * Non-cacheable Normal - intended for memory areas that must
+ * not cause cache line evictions when used
+ */
+ if (cpu_arch >= CPU_ARCH_ARMv6) {
+ if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
+ /* Non-cacheable Normal is XCB = 001 */
+ mem_types[MT_MEMORY_NONCACHED].prot_sect |=
+ PMD_SECT_BUFFERED;
+ } else {
+ /* For both ARMv6 and non-TEX-remapping ARMv7 */
+ mem_types[MT_MEMORY_NONCACHED].prot_sect |=
+ PMD_SECT_TEX(1);
+ }
+ } else {
+ mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE;
+ }
+
for (i = 0; i < 16; i++) {
unsigned long v = pgprot_val(protection_map[i]);
protection_map[i] = __pgprot(v | user_pgprot);
--
1.5.4.3
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 02/17] OMAP3 SRAM: mark OCM RAM as Non-cacheable Normal memory
2009-01-09 15:45 ` [PATCH 01/17] ARM: MMU: add a Non-cacheable Normal executable memory type Tero Kristo
@ 2009-01-09 15:45 ` Tero Kristo
2009-01-09 15:45 ` [PATCH 03/17] OMAP3 SRAM: add ARM barriers to omap3_sram_configure_core_dpll Tero Kristo
0 siblings, 1 reply; 19+ messages in thread
From: Tero Kristo @ 2009-01-09 15:45 UTC (permalink / raw)
To: linux-omap; +Cc: Paul Walmsley
From: Paul Walmsley <paul@pwsan.com>
Mark the SRAM (aka OCM RAM) as Non-cacheable Normal memory[1]. This
is to prevent the ARM from evicting existing cache lines to SDRAM
while code is executing from the SRAM. Necessary since one of the
primary uses for the SRAM is to hold the code and data for the CORE
DPLL M2 divider reprogramming code, which must execute while the SDRC
is idled. If the ARM attempts to write cache lines back to the while
the SRAM code is running, the ARM will stall[2].
TI deals with this problem in the CDP kernel by marking the SRAM as
Strongly-ordered memory.
Tero Kristo <tero.kristo@nokia.com> caught a bug in an earlier version of
this patch - thanks Tero.
...
1. ARMv7 ARM (DDI 0406A) pp. A3-30, A3-31, B3-32.
2. Private communication with Richard Woodruff <r-woodruff2@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Tero Kristo <tero.kristo@nokia.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
---
arch/arm/plat-omap/sram.c | 9 +++++++++
1 files changed, 9 insertions(+), 0 deletions(-)
mode change 100755 => 100644 arch/arm/plat-omap/sram.c
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
old mode 100755
new mode 100644
index 9946f82..5c0d463
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -207,6 +207,15 @@ void __init omap_map_sram(void)
base = OMAP3_SRAM_PA;
base = ROUND_DOWN(base, PAGE_SIZE);
omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
+
+ /*
+ * SRAM must be marked as non-cached on OMAP3 since the
+ * CORE DPLL M2 divider change code (in SRAM) runs with the
+ * SDRAM controller disabled, and if it is marked cached,
+ * the ARM may attempt to write cache lines back to SDRAM
+ * which will cause the system to hang.
+ */
+ omap_sram_io_desc[0].type = MT_MEMORY_NONCACHED;
}
omap_sram_io_desc[0].length = 1024 * 1024; /* Use section desc */
--
1.5.4.3
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 03/17] OMAP3 SRAM: add ARM barriers to omap3_sram_configure_core_dpll
2009-01-09 15:45 ` [PATCH 02/17] OMAP3 SRAM: mark OCM RAM as Non-cacheable Normal memory Tero Kristo
@ 2009-01-09 15:45 ` Tero Kristo
2009-01-09 15:45 ` [PATCH 04/17] OMAP3 clock: add interconnect barriers to CORE DPLL M2 change Tero Kristo
0 siblings, 1 reply; 19+ messages in thread
From: Tero Kristo @ 2009-01-09 15:45 UTC (permalink / raw)
To: linux-omap; +Cc: Paul Walmsley
From: Paul Walmsley <paul@pwsan.com>
Add more barriers in the SRAM CORE DPLL M2 divider change code.
- Add a DSB SY after the function's entry point to flush all cached
and buffered writes and wait for the interconnect to claim that they
have completed[1]. The idea here is to force all delayed write
traffic going to the SDRAM to at least post to the L3 interconnect
before continuing. If these writes are allowed to occur after the
SDRC is idled, the writes will not be acknowledged and the ARM will
stall.
Note that in this case, it does not matter if the writes actually
complete to the SDRAM - it is only necessary for the writes to leave
the ARM itself. If the writes are posted by the interconnect when
the SDRC goes into idle, the writes will be delayed until the SDRC
returns from idle[2]. If the SDRC is in the middle of a write when
it is requested to enter idle, the SDRC will not acknowledge the
idle request until the writes complete to the SDRAM.[3]
The old-style DMB in sdram_in_selfrefresh is now superfluous, so,
remove it.
- Add an ISB before the function's exit point to prevent the ARM from
speculatively executing into SDRAM before the SDRAM is enabled[4].
...
1. ARMv7 ARM (DDI 0406A) A3-47, A3-48.
2. Private communication with Richard Woodruff <r-woodruff2@ti.com>.
3. Private communication with Richard Woodruff <r-woodruff2@ti.com>.
4. ARMv7 ARM (DDI 0406A) A3-48.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
---
arch/arm/mach-omap2/sram34xx.S | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
index 2c71461..f4a356d 100644
--- a/arch/arm/mach-omap2/sram34xx.S
+++ b/arch/arm/mach-omap2/sram34xx.S
@@ -43,6 +43,7 @@
*/
ENTRY(omap3_sram_configure_core_dpll)
stmfd sp!, {r1-r12, lr} @ store regs to stack
+ dsb @ flush buffered writes to interconnect
cmp r3, #0x2
blne configure_sdrc
cmp r3, #0x2
@@ -58,6 +59,7 @@ ENTRY(omap3_sram_configure_core_dpll)
blne wait_dll_lock
cmp r3, #0x1
blne configure_sdrc
+ isb @ prevent speculative exec past here
mov r0, #0 @ return value
ldmfd sp!, {r1-r12, pc} @ restore regs and return
unlock_dll:
@@ -73,8 +75,6 @@ lock_dll:
str r5, [r4]
bx lr
sdram_in_selfrefresh:
- mov r5, #0x0 @ Move 0 to R5
- mcr p15, 0, r5, c7, c10, 5 @ memory barrier
ldr r4, omap3_sdrc_power @ read the SDRC_POWER register
ldr r5, [r4] @ read the contents of SDRC_POWER
orr r5, r5, #0x40 @ enable self refresh on idle req
--
1.5.4.3
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 04/17] OMAP3 clock: add interconnect barriers to CORE DPLL M2 change
2009-01-09 15:45 ` [PATCH 03/17] OMAP3 SRAM: add ARM barriers to omap3_sram_configure_core_dpll Tero Kristo
@ 2009-01-09 15:45 ` Tero Kristo
2009-01-09 15:45 ` [PATCH 05/17] OMAP3 SRAM: clear the SDRC PWRENA bit during SDRC frequency change Tero Kristo
0 siblings, 1 reply; 19+ messages in thread
From: Tero Kristo @ 2009-01-09 15:45 UTC (permalink / raw)
To: linux-omap; +Cc: Paul Walmsley
From: Paul Walmsley <paul@pwsan.com>
Where necessary, add interconnect barriers to force posted writes to
complete before continuing.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
arch/arm/mach-omap2/sram34xx.S | 9 ++++++---
1 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
index f4a356d..8d524f3 100644
--- a/arch/arm/mach-omap2/sram34xx.S
+++ b/arch/arm/mach-omap2/sram34xx.S
@@ -66,22 +66,23 @@ unlock_dll:
ldr r4, omap3_sdrc_dlla_ctrl
ldr r5, [r4]
orr r5, r5, #0x4
- str r5, [r4]
+ str r5, [r4] @ (no OCP barrier needed)
bx lr
lock_dll:
ldr r4, omap3_sdrc_dlla_ctrl
ldr r5, [r4]
bic r5, r5, #0x4
- str r5, [r4]
+ str r5, [r4] @ (no OCP barrier needed)
bx lr
sdram_in_selfrefresh:
ldr r4, omap3_sdrc_power @ read the SDRC_POWER register
ldr r5, [r4] @ read the contents of SDRC_POWER
orr r5, r5, #0x40 @ enable self refresh on idle req
str r5, [r4] @ write back to SDRC_POWER register
+ ldr r5, [r4] @ posted-write barrier for SDRC
ldr r4, omap3_cm_iclken1_core @ read the CM_ICLKEN1_CORE reg
ldr r5, [r4]
- bic r5, r5, #0x2 @ disable iclk bit for SRDC
+ bic r5, r5, #0x2 @ disable iclk bit for SDRC
str r5, [r4]
wait_sdrc_idle:
ldr r4, omap3_cm_idlest1_core
@@ -97,6 +98,7 @@ configure_core_dpll:
and r5, r5, r6
orr r5, r5, r3, lsl #0x1B @ r3 contains the M2 val
str r5, [r4]
+ ldr r5, [r4] @ posted-write barrier for CM
mov r5, #0x800 @ wait for the clock to stabilise
cmp r3, #2
bne wait_clk_stable
@@ -152,6 +154,7 @@ configure_sdrc:
str r1, [r4]
ldr r4, omap3_sdrc_actim_ctrlb
str r2, [r4]
+ ldr r2, [r4] @ posted-write barrier for SDRC
bx lr
omap3_sdrc_power:
--
1.5.4.3
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 05/17] OMAP3 SRAM: clear the SDRC PWRENA bit during SDRC frequency change
2009-01-09 15:45 ` [PATCH 04/17] OMAP3 clock: add interconnect barriers to CORE DPLL M2 change Tero Kristo
@ 2009-01-09 15:45 ` Tero Kristo
2009-01-09 15:45 ` [PATCH 06/17] OMAP3 SDRC: Add 166MHz, 83MHz SDRC settings for the BeagleBoard Tero Kristo
0 siblings, 1 reply; 19+ messages in thread
From: Tero Kristo @ 2009-01-09 15:45 UTC (permalink / raw)
To: linux-omap; +Cc: Paul Walmsley
From: Paul Walmsley <paul@pwsan.com>
Clear the SDRC_POWER.PWRENA bit before putting the SDRAM into self-refresh
mode. This prevents the SDRC from attempting to power off the SDRAM,
which can cause the system to hang.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
arch/arm/mach-omap2/sram34xx.S | 7 ++++---
1 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
index 8d524f3..9a45415 100644
--- a/arch/arm/mach-omap2/sram34xx.S
+++ b/arch/arm/mach-omap2/sram34xx.S
@@ -77,7 +77,9 @@ lock_dll:
sdram_in_selfrefresh:
ldr r4, omap3_sdrc_power @ read the SDRC_POWER register
ldr r5, [r4] @ read the contents of SDRC_POWER
+ mov r9, r5 @ keep a copy of SDRC_POWER bits
orr r5, r5, #0x40 @ enable self refresh on idle req
+ bic r5, r5, #0x4 @ clear PWDENA
str r5, [r4] @ write back to SDRC_POWER register
ldr r5, [r4] @ posted-write barrier for SDRC
ldr r4, omap3_cm_iclken1_core @ read the CM_ICLKEN1_CORE reg
@@ -128,10 +130,9 @@ wait_sdrc_idle1:
and r5, r5, #0x2
cmp r5, #0
bne wait_sdrc_idle1
+restore_sdrc_power_val:
ldr r4, omap3_sdrc_power
- ldr r5, [r4]
- bic r5, r5, #0x40
- str r5, [r4]
+ str r9, [r4] @ restore SDRC_POWER, no barrier needed
bx lr
wait_dll_lock:
ldr r4, omap3_sdrc_dlla_status
--
1.5.4.3
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 06/17] OMAP3 SDRC: Add 166MHz, 83MHz SDRC settings for the BeagleBoard
2009-01-09 15:45 ` [PATCH 05/17] OMAP3 SRAM: clear the SDRC PWRENA bit during SDRC frequency change Tero Kristo
@ 2009-01-09 15:45 ` Tero Kristo
2009-01-09 15:45 ` [PATCH 07/17] OMAP3 SDRC: initialize SDRC_POWER at boot Tero Kristo
0 siblings, 1 reply; 19+ messages in thread
From: Tero Kristo @ 2009-01-09 15:45 UTC (permalink / raw)
To: linux-omap; +Cc: Paul Walmsley
From: Paul Walmsley <paul@pwsan.com>
The BeagleBoard u-boot uses DPLL3 settings that result in 83000000 /
166000000 Hz clock rates for the SDRC, rather than the derated DPLL3
settings used by earlier bootloaders.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h | 22 +++++++++++++++++---
1 files changed, 18 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h b/arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h
index ef35415..b6c1db3 100644
--- a/arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h
+++ b/arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h
@@ -20,34 +20,48 @@
/* XXX Using ARE = 0x1 (no autorefresh burst) -- can this be changed? */
static struct omap_sdrc_params mt46h32m32lf6_sdrc_params[] = {
[0] = {
- .rate = 165941176,
+ .rate = 166000000,
.actim_ctrla = 0x9a9db4c6,
.actim_ctrlb = 0x00011217,
.rfr_ctrl = 0x0004dc01,
.mr = 0x00000032,
},
[1] = {
+ .rate = 165941176,
+ .actim_ctrla = 0x9a9db4c6,
+ .actim_ctrlb = 0x00011217,
+ .rfr_ctrl = 0x0004dc01,
+ .mr = 0x00000032,
+ },
+ [2] = {
.rate = 133333333,
.actim_ctrla = 0x7a19b485,
.actim_ctrlb = 0x00011213,
.rfr_ctrl = 0x0003de01,
.mr = 0x00000032,
},
- [2] = {
+ [3] = {
+ .rate = 83000000,
+ .actim_ctrla = 0x51512283,
+ .actim_ctrlb = 0x0001120c,
+ .rfr_ctrl = 0x00025501,
+ .mr = 0x00000032,
+ },
+ [4] = {
.rate = 82970588,
.actim_ctrla = 0x51512283,
.actim_ctrlb = 0x0001120c,
.rfr_ctrl = 0x00025501,
.mr = 0x00000032,
},
- [3] = {
+ [5] = {
.rate = 66666666,
.actim_ctrla = 0x410d2243,
.actim_ctrlb = 0x0001120a,
.rfr_ctrl = 0x0001d601,
.mr = 0x00000032,
},
- [4] = {
+ [6] = {
.rate = 0
},
};
--
1.5.4.3
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 07/17] OMAP3 SDRC: initialize SDRC_POWER at boot
2009-01-09 15:45 ` [PATCH 06/17] OMAP3 SDRC: Add 166MHz, 83MHz SDRC settings for the BeagleBoard Tero Kristo
@ 2009-01-09 15:45 ` Tero Kristo
2009-01-09 15:45 ` [PATCH 08/17] OMAP3 SRAM: renumber registers to make space for argument passing Tero Kristo
0 siblings, 1 reply; 19+ messages in thread
From: Tero Kristo @ 2009-01-09 15:45 UTC (permalink / raw)
To: linux-omap; +Cc: Paul Walmsley
From: Paul Walmsley <paul@pwsan.com>
Initialize SDRC_POWER to a known-good setting when the kernel boots.
Necessary since some bootloaders don't initialize SDRC_POWER properly.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
arch/arm/mach-omap2/sdrc.c | 19 ++++++++++++++++++-
1 files changed, 18 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/sdrc.c b/arch/arm/mach-omap2/sdrc.c
index 7da6587..28d9e38 100644
--- a/arch/arm/mach-omap2/sdrc.c
+++ b/arch/arm/mach-omap2/sdrc.c
@@ -37,6 +37,10 @@ static struct omap_sdrc_params *sdrc_init_params;
void __iomem *omap2_sdrc_base;
void __iomem *omap2_sms_base;
+/* SDRC_POWER register bits */
+#define SDRC_POWER_EXTCLKDIS_SHIFT 3
+#define SDRC_POWER_PWDENA_SHIFT 2
+#define SDRC_POWER_PAGEPOLICY_SHIFT 0
/**
* omap2_sdrc_get_params - return SDRC register values for a given clock rate
@@ -74,7 +78,14 @@ void __init omap2_set_globals_sdrc(struct omap_globals *omap2_globals)
omap2_sms_base = omap2_globals->sms;
}
-/* turn on smart idle modes for SDRAM scheduler and controller */
+/**
+ * omap2_sdrc_init - initialize SMS, SDRC devices on boot
+ * @sp: pointer to a null-terminated list of struct omap_sdrc_params
+ *
+ * Turn on smart idle modes for SDRAM scheduler and controller.
+ * Program a known-good configuration for the SDRC to deal with buggy
+ * bootloaders.
+ */
void __init omap2_sdrc_init(struct omap_sdrc_params *sp)
{
u32 l;
@@ -90,4 +101,10 @@ void __init omap2_sdrc_init(struct omap_sdrc_params *sp)
sdrc_write_reg(l, SDRC_SYSCONFIG);
sdrc_init_params = sp;
+
+ /* XXX Enable SRFRONIDLEREQ here also? */
+ l = (1 << SDRC_POWER_EXTCLKDIS_SHIFT) |
+ (1 << SDRC_POWER_PWDENA_SHIFT) |
+ (1 << SDRC_POWER_PAGEPOLICY_SHIFT);
+ sdrc_write_reg(l, SDRC_POWER);
}
--
1.5.4.3
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 08/17] OMAP3 SRAM: renumber registers to make space for argument passing
2009-01-09 15:45 ` [PATCH 07/17] OMAP3 SDRC: initialize SDRC_POWER at boot Tero Kristo
@ 2009-01-09 15:45 ` Tero Kristo
2009-01-09 15:45 ` [PATCH 09/17] OMAP3 clock: only unlock SDRC DLL if SDRC clk < 83MHz Tero Kristo
0 siblings, 1 reply; 19+ messages in thread
From: Tero Kristo @ 2009-01-09 15:45 UTC (permalink / raw)
To: linux-omap; +Cc: Paul Walmsley
From: Paul Walmsley <paul@pwsan.com>
Renumber registers in omap3_sram_configure_core_dpll() assembly code to
make space for additional parameters.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
arch/arm/mach-omap2/sram34xx.S | 114 ++++++++++++++++++++--------------------
1 files changed, 57 insertions(+), 57 deletions(-)
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
index 9a45415..35131e5 100644
--- a/arch/arm/mach-omap2/sram34xx.S
+++ b/arch/arm/mach-omap2/sram34xx.S
@@ -63,50 +63,50 @@ ENTRY(omap3_sram_configure_core_dpll)
mov r0, #0 @ return value
ldmfd sp!, {r1-r12, pc} @ restore regs and return
unlock_dll:
- ldr r4, omap3_sdrc_dlla_ctrl
- ldr r5, [r4]
- orr r5, r5, #0x4
- str r5, [r4] @ (no OCP barrier needed)
+ ldr r11, omap3_sdrc_dlla_ctrl
+ ldr r12, [r11]
+ orr r12, r12, #0x4
+ str r12, [r11] @ (no OCP barrier needed)
bx lr
lock_dll:
- ldr r4, omap3_sdrc_dlla_ctrl
- ldr r5, [r4]
- bic r5, r5, #0x4
- str r5, [r4] @ (no OCP barrier needed)
+ ldr r11, omap3_sdrc_dlla_ctrl
+ ldr r12, [r11]
+ bic r12, r12, #0x4
+ str r12, [r11] @ (no OCP barrier needed)
bx lr
sdram_in_selfrefresh:
- ldr r4, omap3_sdrc_power @ read the SDRC_POWER register
- ldr r5, [r4] @ read the contents of SDRC_POWER
- mov r9, r5 @ keep a copy of SDRC_POWER bits
- orr r5, r5, #0x40 @ enable self refresh on idle req
- bic r5, r5, #0x4 @ clear PWDENA
- str r5, [r4] @ write back to SDRC_POWER register
- ldr r5, [r4] @ posted-write barrier for SDRC
- ldr r4, omap3_cm_iclken1_core @ read the CM_ICLKEN1_CORE reg
- ldr r5, [r4]
- bic r5, r5, #0x2 @ disable iclk bit for SDRC
- str r5, [r4]
+ ldr r11, omap3_sdrc_power @ read the SDRC_POWER register
+ ldr r12, [r11] @ read the contents of SDRC_POWER
+ mov r9, r12 @ keep a copy of SDRC_POWER bits
+ orr r12, r12, #0x40 @ enable self refresh on idle req
+ bic r12, r12, #0x4 @ clear PWDENA
+ str r12, [r11] @ write back to SDRC_POWER register
+ ldr r12, [r11] @ posted-write barrier for SDRC
+ ldr r11, omap3_cm_iclken1_core @ read the CM_ICLKEN1_CORE reg
+ ldr r12, [r11]
+ bic r12, r12, #0x2 @ disable iclk bit for SDRC
+ str r12, [r11]
wait_sdrc_idle:
- ldr r4, omap3_cm_idlest1_core
- ldr r5, [r4]
- and r5, r5, #0x2 @ check for SDRC idle
- cmp r5, #2
+ ldr r11, omap3_cm_idlest1_core
+ ldr r12, [r11]
+ and r12, r12, #0x2 @ check for SDRC idle
+ cmp r12, #2
bne wait_sdrc_idle
bx lr
configure_core_dpll:
- ldr r4, omap3_cm_clksel1_pll
- ldr r5, [r4]
- ldr r6, core_m2_mask_val @ modify m2 for core dpll
- and r5, r5, r6
- orr r5, r5, r3, lsl #0x1B @ r3 contains the M2 val
- str r5, [r4]
- ldr r5, [r4] @ posted-write barrier for CM
- mov r5, #0x800 @ wait for the clock to stabilise
+ ldr r11, omap3_cm_clksel1_pll
+ ldr r12, [r11]
+ ldr r10, core_m2_mask_val @ modify m2 for core dpll
+ and r12, r12, r10
+ orr r12, r12, r3, lsl #0x1B @ r3 contains the M2 val
+ str r12, [r11]
+ ldr r12, [r11] @ posted-write barrier for CM
+ mov r12, #0x800 @ wait for the clock to stabilise
cmp r3, #2
bne wait_clk_stable
bx lr
wait_clk_stable:
- subs r5, r5, #1
+ subs r12, r12, #1
bne wait_clk_stable
nop
nop
@@ -120,42 +120,42 @@ wait_clk_stable:
nop
bx lr
enable_sdrc:
- ldr r4, omap3_cm_iclken1_core
- ldr r5, [r4]
- orr r5, r5, #0x2 @ enable iclk bit for SDRC
- str r5, [r4]
+ ldr r11, omap3_cm_iclken1_core
+ ldr r12, [r11]
+ orr r12, r12, #0x2 @ enable iclk bit for SDRC
+ str r12, [r11]
wait_sdrc_idle1:
- ldr r4, omap3_cm_idlest1_core
- ldr r5, [r4]
- and r5, r5, #0x2
- cmp r5, #0
+ ldr r11, omap3_cm_idlest1_core
+ ldr r12, [r11]
+ and r12, r12, #0x2
+ cmp r12, #0
bne wait_sdrc_idle1
restore_sdrc_power_val:
- ldr r4, omap3_sdrc_power
- str r9, [r4] @ restore SDRC_POWER, no barrier needed
+ ldr r11, omap3_sdrc_power
+ str r9, [r11] @ restore SDRC_POWER, no barrier needed
bx lr
wait_dll_lock:
- ldr r4, omap3_sdrc_dlla_status
- ldr r5, [r4]
- and r5, r5, #0x4
- cmp r5, #0x4
+ ldr r11, omap3_sdrc_dlla_status
+ ldr r12, [r11]
+ and r12, r12, #0x4
+ cmp r12, #0x4
bne wait_dll_lock
bx lr
wait_dll_unlock:
- ldr r4, omap3_sdrc_dlla_status
- ldr r5, [r4]
- and r5, r5, #0x4
- cmp r5, #0x0
+ ldr r11, omap3_sdrc_dlla_status
+ ldr r12, [r11]
+ and r12, r12, #0x4
+ cmp r12, #0x0
bne wait_dll_unlock
bx lr
configure_sdrc:
- ldr r4, omap3_sdrc_rfr_ctrl
- str r0, [r4]
- ldr r4, omap3_sdrc_actim_ctrla
- str r1, [r4]
- ldr r4, omap3_sdrc_actim_ctrlb
- str r2, [r4]
- ldr r2, [r4] @ posted-write barrier for SDRC
+ ldr r11, omap3_sdrc_rfr_ctrl
+ str r0, [r11]
+ ldr r11, omap3_sdrc_actim_ctrla
+ str r1, [r11]
+ ldr r11, omap3_sdrc_actim_ctrlb
+ str r2, [r11]
+ ldr r2, [r11] @ posted-write barrier for SDRC
bx lr
omap3_sdrc_power:
--
1.5.4.3
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 09/17] OMAP3 clock: only unlock SDRC DLL if SDRC clk < 83MHz
2009-01-09 15:45 ` [PATCH 08/17] OMAP3 SRAM: renumber registers to make space for argument passing Tero Kristo
@ 2009-01-09 15:45 ` Tero Kristo
2009-01-09 15:45 ` [PATCH 10/17] OMAP3 clock: use pr_debug() rather than pr_info() in some clock change code Tero Kristo
0 siblings, 1 reply; 19+ messages in thread
From: Tero Kristo @ 2009-01-09 15:45 UTC (permalink / raw)
To: linux-omap; +Cc: Paul Walmsley
From: Paul Walmsley <paul@pwsan.com>
According to the 34xx TRM Rev. K section 11.2.4.4.11.1 "Purpose of the
DLL/CDL Module," the SDRC delay-locked-loop can be locked at any SDRC
clock frequency from 83MHz to 166MHz. CDP code unconditionally
unlocked the DLL whenever shifting to a lower SDRC speed, but this
seems unnecessary and error-prone, as the DLL is no longer able to
compensate for process, voltage, and temperature variations. Instead,
only unlock the DLL when the SDRC clock rate would be less than 83MHz.
In situations where the DLL is unlocked, we should probably be
changing the FIXEDDELAY field, but currently we have no information on
how to calculate it.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
arch/arm/mach-omap2/clock34xx.c | 10 +++++++++-
arch/arm/mach-omap2/sram34xx.S | 13 +++++++------
arch/arm/plat-omap/include/mach/sram.h | 6 ++++--
arch/arm/plat-omap/sram.c | 7 ++++---
4 files changed, 24 insertions(+), 12 deletions(-)
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 55981dd..2e9ed66 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -74,6 +74,8 @@ static unsigned long compute_lpj(unsigned long ref, u_int div, u_int mult)
}
#endif
+#define MIN_SDRC_DLL_LOCK_FREQ 83000000
+
/**
* omap3_dpll_recalc - recalculate DPLL rate
* @clk: DPLL struct clk
@@ -485,6 +487,7 @@ static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
{
u32 new_div = 0;
+ u32 unlock_dll = 0;
unsigned long validrate, sdrcrate;
struct omap_sdrc_params *sp;
@@ -511,6 +514,11 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
if (!sp)
return -EINVAL;
+ if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) {
+ pr_debug("clock: will unlock SDRC DLL\n");
+ unlock_dll = 1;
+ }
+
pr_info("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
validrate);
pr_info("clock: SDRC timing params used: %08x %08x %08x\n",
@@ -521,7 +529,7 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
/* REVISIT: Add SDRC_MR changing to this code also */
omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla,
- sp->actim_ctrlb, new_div);
+ sp->actim_ctrlb, new_div, unlock_dll);
return 0;
}
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
index 35131e5..c080c82 100644
--- a/arch/arm/mach-omap2/sram34xx.S
+++ b/arch/arm/mach-omap2/sram34xx.S
@@ -40,22 +40,23 @@
/*
* Change frequency of core dpll
* r0 = sdrc_rfr_ctrl r1 = sdrc_actim_ctrla r2 = sdrc_actim_ctrlb r3 = M2
+ * r4 = Unlock SDRC DLL? (1 = yes, 0 = no) -- only unlock DLL for
+ * SDRC rates < 83MHz
*/
ENTRY(omap3_sram_configure_core_dpll)
stmfd sp!, {r1-r12, lr} @ store regs to stack
+ ldr r4, [sp, #52] @ pull extra args off the stack
dsb @ flush buffered writes to interconnect
cmp r3, #0x2
blne configure_sdrc
- cmp r3, #0x2
+ cmp r4, #0x1
+ bleq unlock_dll
blne lock_dll
- cmp r3, #0x1
- blne unlock_dll
bl sdram_in_selfrefresh @ put the SDRAM in self refresh
bl configure_core_dpll
bl enable_sdrc
- cmp r3, #0x1
- blne wait_dll_unlock
- cmp r3, #0x2
+ cmp r4, #0x1
+ bleq wait_dll_unlock
blne wait_dll_lock
cmp r3, #0x1
blne configure_sdrc
diff --git a/arch/arm/plat-omap/include/mach/sram.h b/arch/arm/plat-omap/include/mach/sram.h
index 0c0b45f..3f0711f 100644
--- a/arch/arm/plat-omap/include/mach/sram.h
+++ b/arch/arm/plat-omap/include/mach/sram.h
@@ -23,7 +23,8 @@ extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl,
u32 sdrc_actim_ctrla,
- u32 sdrc_actim_ctrlb, u32 m2);
+ u32 sdrc_actim_ctrlb, u32 m2,
+ u32 unlock_dll);
extern void omap3_sram_restore_context(void);
/* Do not use these */
@@ -61,7 +62,8 @@ extern unsigned long omap243x_sram_reprogram_sdrc_sz;
extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl,
u32 sdrc_actim_ctrla,
- u32 sdrc_actim_ctrlb, u32 m2);
+ u32 sdrc_actim_ctrlb, u32 m2,
+ u32 unlock_dll);
extern unsigned long omap3_sram_configure_core_dpll_sz;
#ifdef CONFIG_PM
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 5c0d463..6ecda40 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -371,16 +371,17 @@ static inline int omap243x_sram_init(void)
static u32 (*_omap3_sram_configure_core_dpll)(u32 sdrc_rfr_ctrl,
u32 sdrc_actim_ctrla,
u32 sdrc_actim_ctrlb,
- u32 m2);
+ u32 m2, u32 unlock_dll);
u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla,
- u32 sdrc_actim_ctrlb, u32 m2)
+ u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll)
{
if (!_omap3_sram_configure_core_dpll)
omap_sram_error();
return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl,
sdrc_actim_ctrla,
- sdrc_actim_ctrlb, m2);
+ sdrc_actim_ctrlb, m2,
+ unlock_dll);
}
#ifdef CONFIG_PM
--
1.5.4.3
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 10/17] OMAP3 clock: use pr_debug() rather than pr_info() in some clock change code
2009-01-09 15:45 ` [PATCH 09/17] OMAP3 clock: only unlock SDRC DLL if SDRC clk < 83MHz Tero Kristo
@ 2009-01-09 15:45 ` Tero Kristo
2009-01-09 15:45 ` [PATCH 11/17] OMAP3 clock: remove wait for DPLL3 M2 clock to stabilize Tero Kristo
0 siblings, 1 reply; 19+ messages in thread
From: Tero Kristo @ 2009-01-09 15:45 UTC (permalink / raw)
To: linux-omap; +Cc: Paul Walmsley
From: Paul Walmsley <paul@pwsan.com>
The CORE DPLL M2 frequency change code should use pr_debug(), not
pr_info(), for its debug messages. Same with
omap2_clksel_round_rate_div(). While here, convert a few printk(KERN_ERR ..
into pr_err().
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
arch/arm/mach-omap2/clock.c | 12 ++++++------
arch/arm/mach-omap2/clock34xx.c | 8 ++++----
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 224535f..612db25 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -591,8 +591,8 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
const struct clksel_rate *clkr;
u32 last_div = 0;
- printk(KERN_INFO "clock: clksel_round_rate_div: %s target_rate %ld\n",
- clk->name, target_rate);
+ pr_debug("clock: clksel_round_rate_div: %s target_rate %ld\n",
+ clk->name, target_rate);
*new_div = 1;
@@ -606,7 +606,7 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
/* Sanity check */
if (clkr->div <= last_div)
- printk(KERN_ERR "clock: clksel_rate table not sorted "
+ pr_err("clock: clksel_rate table not sorted "
"for clock %s", clk->name);
last_div = clkr->div;
@@ -618,7 +618,7 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
}
if (!clkr->div) {
- printk(KERN_ERR "clock: Could not find divisor for target "
+ pr_err("clock: Could not find divisor for target "
"rate %ld for clock %s parent %s\n", target_rate,
clk->name, clk->parent->name);
return ~0;
@@ -626,8 +626,8 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
*new_div = clkr->div;
- printk(KERN_INFO "clock: new_div = %d, new_rate = %ld\n", *new_div,
- (clk->parent->rate / clkr->div));
+ pr_debug("clock: new_div = %d, new_rate = %ld\n", *new_div,
+ (clk->parent->rate / clkr->div));
return (clk->parent->rate / clkr->div);
}
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 2e9ed66..febbf0a 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -519,10 +519,10 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
unlock_dll = 1;
}
- pr_info("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
- validrate);
- pr_info("clock: SDRC timing params used: %08x %08x %08x\n",
- sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb);
+ pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
+ validrate);
+ pr_debug("clock: SDRC timing params used: %08x %08x %08x\n",
+ sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb);
/* REVISIT: SRAM code doesn't support other M2 divisors yet */
WARN_ON(new_div != 1 && new_div != 2);
--
1.5.4.3
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 11/17] OMAP3 clock: remove wait for DPLL3 M2 clock to stabilize
2009-01-09 15:45 ` [PATCH 10/17] OMAP3 clock: use pr_debug() rather than pr_info() in some clock change code Tero Kristo
@ 2009-01-09 15:45 ` Tero Kristo
2009-01-09 15:45 ` [PATCH 12/17] OMAP3 clock: initialize SDRC timings at kernel start Tero Kristo
0 siblings, 1 reply; 19+ messages in thread
From: Tero Kristo @ 2009-01-09 15:45 UTC (permalink / raw)
To: linux-omap; +Cc: Paul Walmsley
From: Paul Walmsley <paul@pwsan.com>
The original CDP kernel that this code comes from waited for 0x800
loops after switching the CORE DPLL M2 divider. This does not appear
to be necessary.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
arch/arm/mach-omap2/sram34xx.S | 3 ---
1 files changed, 0 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
index c080c82..84781a6 100644
--- a/arch/arm/mach-omap2/sram34xx.S
+++ b/arch/arm/mach-omap2/sram34xx.S
@@ -102,9 +102,6 @@ configure_core_dpll:
orr r12, r12, r3, lsl #0x1B @ r3 contains the M2 val
str r12, [r11]
ldr r12, [r11] @ posted-write barrier for CM
- mov r12, #0x800 @ wait for the clock to stabilise
- cmp r3, #2
- bne wait_clk_stable
bx lr
wait_clk_stable:
subs r12, r12, #1
--
1.5.4.3
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 12/17] OMAP3 clock: initialize SDRC timings at kernel start
2009-01-09 15:45 ` [PATCH 11/17] OMAP3 clock: remove wait for DPLL3 M2 clock to stabilize Tero Kristo
@ 2009-01-09 15:45 ` Tero Kristo
2009-01-09 15:45 ` [PATCH 13/17] OMAP3 clock: add a short delay when lowering CORE clk rate Tero Kristo
0 siblings, 1 reply; 19+ messages in thread
From: Tero Kristo @ 2009-01-09 15:45 UTC (permalink / raw)
To: linux-omap; +Cc: Paul Walmsley
From: Paul Walmsley <paul@pwsan.com>
On the OMAP3, initialize SDRC timings when the kernel boots. This ensures
that the kernel is running with known, optimized SDRC timings, rather than
whatever was configured by the bootloader.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
arch/arm/mach-omap2/clock34xx.c | 3 ---
arch/arm/mach-omap2/io.c | 36 ++++++++++++++++++++++++++++++++++++
2 files changed, 36 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index febbf0a..7770553 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -497,9 +497,6 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
if (clk != &dpll3_m2_ck)
return -EINVAL;
- if (rate == clk->rate)
- return 0;
-
validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
if (validrate != rate)
return -EINVAL;
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 5b529ae..6fb6c29 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -19,6 +19,7 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
+#include <linux/clk.h>
#include <asm/tlb.h>
@@ -198,6 +199,38 @@ void __init omap2_map_common_io(void)
omapfb_reserve_sdram();
}
+/*
+ * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
+ *
+ * Sets the CORE DPLL3 M2 divider to the same value that it's at
+ * currently. This has the effect of setting the SDRC SDRAM AC timing
+ * registers to the values currently defined by the kernel. Currently
+ * only defined for OMAP3; will return 0 if called on OMAP2. Returns
+ * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
+ * or passes along the return value of clk_set_rate().
+ */
+static int __init _omap2_init_reprogram_sdrc(void)
+{
+ struct clk *dpll3_m2_ck;
+ int v = -EINVAL;
+
+ if (!cpu_is_omap34xx())
+ return 0;
+
+ dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
+ if (!dpll3_m2_ck)
+ return -EINVAL;
+
+ pr_info("Reprogramming SDRC\n");
+ v = clk_set_rate(dpll3_m2_ck, clk_get_rate(dpll3_m2_ck));
+ if (v)
+ pr_err("dpll3_m2_clk rate change failed: %d\n", v);
+
+ clk_put(dpll3_m2_ck);
+
+ return v;
+}
+
void __init omap2_init_common_hw(struct omap_sdrc_params *sp,
struct omap_opp *mpu_opps,
struct omap_opp *dsp_opps,
@@ -212,5 +245,8 @@ void __init omap2_init_common_hw(struct omap_sdrc_params *sp,
omap2_clk_init();
omap_pm_if_init();
omap2_sdrc_init(sp);
+
+ _omap2_init_reprogram_sdrc();
+
gpmc_init();
}
--
1.5.4.3
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 13/17] OMAP3 clock: add a short delay when lowering CORE clk rate
2009-01-09 15:45 ` [PATCH 12/17] OMAP3 clock: initialize SDRC timings at kernel start Tero Kristo
@ 2009-01-09 15:45 ` Tero Kristo
2009-01-09 15:45 ` [PATCH 14/17] OMAP3 clock/SDRC: program SDRC_MR register during SDRC clock change Tero Kristo
0 siblings, 1 reply; 19+ messages in thread
From: Tero Kristo @ 2009-01-09 15:45 UTC (permalink / raw)
To: linux-omap; +Cc: Paul Walmsley
From: Paul Walmsley <paul@pwsan.com>
When changing the SDRAM clock from 166MHz to 83MHz via the CORE DPLL M2
divider, add a short delay before returning to SDRAM to allow the SDRC
time to stabilize. Without this delay, the system is prone to random
panics upon re-entering SDRAM.
This time delay varies based on MPU frequency. At 500MHz MPU frequency at
room temperature, 64 loops seems to work okay; so add another 32 loops for
environmental and process variation.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
arch/arm/mach-omap2/clock34xx.c | 30 ++++++++++++++++++++++++++++--
arch/arm/mach-omap2/sram34xx.S | 20 +++++++++-----------
arch/arm/plat-omap/include/mach/sram.h | 4 ++--
arch/arm/plat-omap/sram.c | 8 +++++---
4 files changed, 44 insertions(+), 18 deletions(-)
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 7770553..48148de 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -76,6 +76,20 @@ static unsigned long compute_lpj(unsigned long ref, u_int div, u_int mult)
#define MIN_SDRC_DLL_LOCK_FREQ 83000000
+#define CYCLES_PER_MHZ 1000000
+
+/* Scale factor for fixed-point arith in omap3_core_dpll_m2_set_rate() */
+#define SDRC_MPURATE_SCALE 8
+
+/* 2^SDRC_MPURATE_BASE_SHIFT: MPU MHz that SDRC_MPURATE_LOOPS is defined for */
+#define SDRC_MPURATE_BASE_SHIFT 9
+
+/*
+ * SDRC_MPURATE_LOOPS: Number of MPU loops to execute at
+ * 2^MPURATE_BASE_SHIFT MHz for SDRC to stabilize
+ */
+#define SDRC_MPURATE_LOOPS 96
+
/**
* omap3_dpll_recalc - recalculate DPLL rate
* @clk: DPLL struct clk
@@ -488,7 +502,8 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
{
u32 new_div = 0;
u32 unlock_dll = 0;
- unsigned long validrate, sdrcrate;
+ u32 c;
+ unsigned long validrate, sdrcrate, mpurate;
struct omap_sdrc_params *sp;
if (!clk || !rate)
@@ -516,6 +531,17 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
unlock_dll = 1;
}
+ /*
+ * XXX This only needs to be done when the CPU frequency changes
+ */
+ mpurate = arm_fck.rate / CYCLES_PER_MHZ;
+ c = (mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT;
+ c += 1; /* for safety */
+ c *= SDRC_MPURATE_LOOPS;
+ c >>= SDRC_MPURATE_SCALE;
+ if (c == 0)
+ c = 1;
+
pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
validrate);
pr_debug("clock: SDRC timing params used: %08x %08x %08x\n",
@@ -526,7 +552,7 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
/* REVISIT: Add SDRC_MR changing to this code also */
omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla,
- sp->actim_ctrlb, new_div, unlock_dll);
+ sp->actim_ctrlb, new_div, unlock_dll, c);
return 0;
}
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
index 84781a6..8d4a88c 100644
--- a/arch/arm/mach-omap2/sram34xx.S
+++ b/arch/arm/mach-omap2/sram34xx.S
@@ -42,10 +42,14 @@
* r0 = sdrc_rfr_ctrl r1 = sdrc_actim_ctrla r2 = sdrc_actim_ctrlb r3 = M2
* r4 = Unlock SDRC DLL? (1 = yes, 0 = no) -- only unlock DLL for
* SDRC rates < 83MHz
+ * r5 = number of MPU cycles to wait for SDRC to stabilize after
+ * reprogramming the SDRC when switching to a slower MPU speed
+ *
*/
ENTRY(omap3_sram_configure_core_dpll)
stmfd sp!, {r1-r12, lr} @ store regs to stack
ldr r4, [sp, #52] @ pull extra args off the stack
+ ldr r5, [sp, #56] @ load extra args from the stack
dsb @ flush buffered writes to interconnect
cmp r3, #0x2
blne configure_sdrc
@@ -59,7 +63,11 @@ ENTRY(omap3_sram_configure_core_dpll)
bleq wait_dll_unlock
blne wait_dll_lock
cmp r3, #0x1
- blne configure_sdrc
+ beq return_to_sdram
+ bl configure_sdrc
+ mov r12, r5 @ if slowing, wait for SDRC to stabilize
+ bl wait_clk_stable
+return_to_sdram:
isb @ prevent speculative exec past here
mov r0, #0 @ return value
ldmfd sp!, {r1-r12, pc} @ restore regs and return
@@ -106,16 +114,6 @@ configure_core_dpll:
wait_clk_stable:
subs r12, r12, #1
bne wait_clk_stable
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
bx lr
enable_sdrc:
ldr r11, omap3_cm_iclken1_core
diff --git a/arch/arm/plat-omap/include/mach/sram.h b/arch/arm/plat-omap/include/mach/sram.h
index 3f0711f..37c13a0 100644
--- a/arch/arm/plat-omap/include/mach/sram.h
+++ b/arch/arm/plat-omap/include/mach/sram.h
@@ -24,7 +24,7 @@ extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl,
u32 sdrc_actim_ctrla,
u32 sdrc_actim_ctrlb, u32 m2,
- u32 unlock_dll);
+ u32 unlock_dll, u32 f);
extern void omap3_sram_restore_context(void);
/* Do not use these */
@@ -63,7 +63,7 @@ extern unsigned long omap243x_sram_reprogram_sdrc_sz;
extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl,
u32 sdrc_actim_ctrla,
u32 sdrc_actim_ctrlb, u32 m2,
- u32 unlock_dll);
+ u32 unlock_dll, u32 f);
extern unsigned long omap3_sram_configure_core_dpll_sz;
#ifdef CONFIG_PM
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 6ecda40..dc762d4 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -371,9 +371,11 @@ static inline int omap243x_sram_init(void)
static u32 (*_omap3_sram_configure_core_dpll)(u32 sdrc_rfr_ctrl,
u32 sdrc_actim_ctrla,
u32 sdrc_actim_ctrlb,
- u32 m2, u32 unlock_dll);
+ u32 m2, u32 unlock_dll,
+ u32 f);
u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla,
- u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll)
+ u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll,
+ u32 f)
{
if (!_omap3_sram_configure_core_dpll)
omap_sram_error();
@@ -381,7 +383,7 @@ u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla,
return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl,
sdrc_actim_ctrla,
sdrc_actim_ctrlb, m2,
- unlock_dll);
+ unlock_dll, f);
}
#ifdef CONFIG_PM
--
1.5.4.3
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 14/17] OMAP3 clock/SDRC: program SDRC_MR register during SDRC clock change
2009-01-09 15:45 ` [PATCH 13/17] OMAP3 clock: add a short delay when lowering CORE clk rate Tero Kristo
@ 2009-01-09 15:45 ` Tero Kristo
2009-01-09 15:45 ` [PATCH 15/17] OMAP3 SRAM: add more comments on the SRAM code Tero Kristo
0 siblings, 1 reply; 19+ messages in thread
From: Tero Kristo @ 2009-01-09 15:45 UTC (permalink / raw)
To: linux-omap; +Cc: Paul Walmsley
From: Paul Walmsley <paul@pwsan.com>
Program the SDRC_MR_0 register as well during SDRC clock changes.
This register allows selection of the memory CAS latency. Some SDRAM
chips, such as the Qimonda HYB18M512160AF6, have a lower CAS latency
at lower clock rates.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
arch/arm/mach-omap2/clock34xx.c | 4 ++--
arch/arm/mach-omap2/sram34xx.S | 8 +++++++-
arch/arm/plat-omap/include/mach/sram.h | 4 ++--
arch/arm/plat-omap/sram.c | 6 +++---
4 files changed, 14 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 48148de..4d86ea6 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -550,9 +550,9 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
/* REVISIT: SRAM code doesn't support other M2 divisors yet */
WARN_ON(new_div != 1 && new_div != 2);
- /* REVISIT: Add SDRC_MR changing to this code also */
omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla,
- sp->actim_ctrlb, new_div, unlock_dll, c);
+ sp->actim_ctrlb, new_div, unlock_dll, c,
+ sp->mr);
return 0;
}
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
index 8d4a88c..d13f1cc 100644
--- a/arch/arm/mach-omap2/sram34xx.S
+++ b/arch/arm/mach-omap2/sram34xx.S
@@ -44,12 +44,14 @@
* SDRC rates < 83MHz
* r5 = number of MPU cycles to wait for SDRC to stabilize after
* reprogramming the SDRC when switching to a slower MPU speed
+ * r6 = SDRC_MR_0 register value
*
*/
ENTRY(omap3_sram_configure_core_dpll)
stmfd sp!, {r1-r12, lr} @ store regs to stack
ldr r4, [sp, #52] @ pull extra args off the stack
ldr r5, [sp, #56] @ load extra args from the stack
+ ldr r6, [sp, #60] @ load extra args from the stack
dsb @ flush buffered writes to interconnect
cmp r3, #0x2
blne configure_sdrc
@@ -151,7 +153,9 @@ configure_sdrc:
str r1, [r11]
ldr r11, omap3_sdrc_actim_ctrlb
str r2, [r11]
- ldr r2, [r11] @ posted-write barrier for SDRC
+ ldr r11, omap3_sdrc_mr_0
+ str r6, [r11]
+ ldr r6, [r11] @ posted-write barrier for SDRC
bx lr
omap3_sdrc_power:
@@ -168,6 +172,8 @@ omap3_sdrc_actim_ctrla:
.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0)
omap3_sdrc_actim_ctrlb:
.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0)
+omap3_sdrc_mr_0:
+ .word OMAP34XX_SDRC_REGADDR(SDRC_MR_0)
omap3_sdrc_dlla_status:
.word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
omap3_sdrc_dlla_ctrl:
diff --git a/arch/arm/plat-omap/include/mach/sram.h b/arch/arm/plat-omap/include/mach/sram.h
index 37c13a0..6800975 100644
--- a/arch/arm/plat-omap/include/mach/sram.h
+++ b/arch/arm/plat-omap/include/mach/sram.h
@@ -24,7 +24,7 @@ extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl,
u32 sdrc_actim_ctrla,
u32 sdrc_actim_ctrlb, u32 m2,
- u32 unlock_dll, u32 f);
+ u32 unlock_dll, u32 f, u32 sdrc_mr);
extern void omap3_sram_restore_context(void);
/* Do not use these */
@@ -63,7 +63,7 @@ extern unsigned long omap243x_sram_reprogram_sdrc_sz;
extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl,
u32 sdrc_actim_ctrla,
u32 sdrc_actim_ctrlb, u32 m2,
- u32 unlock_dll, u32 f);
+ u32 unlock_dll, u32 f, u32 sdrc_mr);
extern unsigned long omap3_sram_configure_core_dpll_sz;
#ifdef CONFIG_PM
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index dc762d4..d7aeff8 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -372,10 +372,10 @@ static u32 (*_omap3_sram_configure_core_dpll)(u32 sdrc_rfr_ctrl,
u32 sdrc_actim_ctrla,
u32 sdrc_actim_ctrlb,
u32 m2, u32 unlock_dll,
- u32 f);
+ u32 f, u32 sdrc_mr);
u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla,
u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll,
- u32 f)
+ u32 f, u32 sdrc_mr)
{
if (!_omap3_sram_configure_core_dpll)
omap_sram_error();
@@ -383,7 +383,7 @@ u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla,
return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl,
sdrc_actim_ctrla,
sdrc_actim_ctrlb, m2,
- unlock_dll, f);
+ unlock_dll, f, sdrc_mr);
}
#ifdef CONFIG_PM
--
1.5.4.3
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 15/17] OMAP3 SRAM: add more comments on the SRAM code
2009-01-09 15:45 ` [PATCH 14/17] OMAP3 clock/SDRC: program SDRC_MR register during SDRC clock change Tero Kristo
@ 2009-01-09 15:45 ` Tero Kristo
2009-01-09 15:45 ` [PATCH 16/17] OMAP3 SRAM: convert SRAM code to use macros rather than magic numbers Tero Kristo
0 siblings, 1 reply; 19+ messages in thread
From: Tero Kristo @ 2009-01-09 15:45 UTC (permalink / raw)
To: linux-omap; +Cc: Paul Walmsley
From: Paul Walmsley <paul@pwsan.com>
Clean up comments and copyrights on the CORE DPLL3 M2 divider change code.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
arch/arm/mach-omap2/sram34xx.S | 45 +++++++++++++++++++++------------------
1 files changed, 24 insertions(+), 21 deletions(-)
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
index d13f1cc..37a1e1f 100644
--- a/arch/arm/mach-omap2/sram34xx.S
+++ b/arch/arm/mach-omap2/sram34xx.S
@@ -3,13 +3,12 @@
*
* Omap3 specific functions that need to be run in internal SRAM
*
- * (C) Copyright 2007
- * Texas Instruments Inc.
- * Rajendra Nayak <rnayak@ti.com>
+ * Copyright (C) 2004, 2007, 2008 Texas Instruments, Inc.
+ * Copyright (C) 2008 Nokia Corporation
*
- * (C) Copyright 2004
- * Texas Instruments, <www.ti.com>
+ * Rajendra Nayak <rnayak@ti.com>
* Richard Woodruff <r-woodruff2@ti.com>
+ * Paul Walmsley
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@@ -38,13 +37,16 @@
.text
/*
- * Change frequency of core dpll
- * r0 = sdrc_rfr_ctrl r1 = sdrc_actim_ctrla r2 = sdrc_actim_ctrlb r3 = M2
- * r4 = Unlock SDRC DLL? (1 = yes, 0 = no) -- only unlock DLL for
+ * omap3_sram_configure_core_dpll - change DPLL3 M2 divider
+ * r0 = new SDRC_RFR_CTRL register contents
+ * r1 = new SDRC_ACTIM_CTRLA register contents
+ * r2 = new SDRC_ACTIM_CTRLB register contents
+ * r3 = new M2 divider setting (only 1 and 2 supported right now)
+ * r4 = unlock SDRC DLL? (1 = yes, 0 = no). Only unlock DLL for
* SDRC rates < 83MHz
* r5 = number of MPU cycles to wait for SDRC to stabilize after
* reprogramming the SDRC when switching to a slower MPU speed
- * r6 = SDRC_MR_0 register value
+ * r6 = new SDRC_MR_0 register value
*
*/
ENTRY(omap3_sram_configure_core_dpll)
@@ -53,22 +55,22 @@ ENTRY(omap3_sram_configure_core_dpll)
ldr r5, [sp, #56] @ load extra args from the stack
ldr r6, [sp, #60] @ load extra args from the stack
dsb @ flush buffered writes to interconnect
- cmp r3, #0x2
- blne configure_sdrc
- cmp r4, #0x1
+ cmp r3, #0x2 @ if increasing SDRC clk rate,
+ blne configure_sdrc @ program the SDRC regs early (for RFR)
+ cmp r4, #0x1 @ set the intended DLL state
bleq unlock_dll
blne lock_dll
- bl sdram_in_selfrefresh @ put the SDRAM in self refresh
- bl configure_core_dpll
- bl enable_sdrc
- cmp r4, #0x1
+ bl sdram_in_selfrefresh @ put SDRAM in self refresh, idle SDRC
+ bl configure_core_dpll @ change the DPLL3 M2 divider
+ bl enable_sdrc @ take SDRC out of idle
+ cmp r4, #0x1 @ wait for DLL status to change
bleq wait_dll_unlock
blne wait_dll_lock
- cmp r3, #0x1
- beq return_to_sdram
- bl configure_sdrc
- mov r12, r5 @ if slowing, wait for SDRC to stabilize
- bl wait_clk_stable
+ cmp r3, #0x1 @ if increasing SDRC clk rate,
+ beq return_to_sdram @ return to SDRAM code, otherwise,
+ bl configure_sdrc @ reprogram SDRC regs now
+ mov r12, r5
+ bl wait_clk_stable @ wait for SDRC to stabilize
return_to_sdram:
isb @ prevent speculative exec past here
mov r0, #0 @ return value
@@ -93,6 +95,7 @@ sdram_in_selfrefresh:
bic r12, r12, #0x4 @ clear PWDENA
str r12, [r11] @ write back to SDRC_POWER register
ldr r12, [r11] @ posted-write barrier for SDRC
+idle_sdrc:
ldr r11, omap3_cm_iclken1_core @ read the CM_ICLKEN1_CORE reg
ldr r12, [r11]
bic r12, r12, #0x2 @ disable iclk bit for SDRC
--
1.5.4.3
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 16/17] OMAP3 SRAM: convert SRAM code to use macros rather than magic numbers
2009-01-09 15:45 ` [PATCH 15/17] OMAP3 SRAM: add more comments on the SRAM code Tero Kristo
@ 2009-01-09 15:45 ` Tero Kristo
2009-01-09 15:45 ` [PATCH 17/17] OMAP3: Add support for DPLL3 divisor values higher than 2 Tero Kristo
0 siblings, 1 reply; 19+ messages in thread
From: Tero Kristo @ 2009-01-09 15:45 UTC (permalink / raw)
To: linux-omap; +Cc: Paul Walmsley
From: Paul Walmsley <paul@pwsan.com>
Convert omap3_sram_configure_core_dpll() to use macros rather than
magic numbers.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
arch/arm/mach-omap2/sram34xx.S | 53 ++++++++++++++++++++++++++++-----------
1 files changed, 38 insertions(+), 15 deletions(-)
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
index 37a1e1f..16eb4ef 100644
--- a/arch/arm/mach-omap2/sram34xx.S
+++ b/arch/arm/mach-omap2/sram34xx.S
@@ -36,6 +36,29 @@
.text
+/* r4 parameters */
+#define SDRC_NO_UNLOCK_DLL 0x0
+#define SDRC_UNLOCK_DLL 0x1
+
+/* SDRC_DLLA_CTRL bit settings */
+#define DLLIDLE_MASK 0x4
+
+/* SDRC_DLLA_STATUS bit settings */
+#define LOCKSTATUS_MASK 0x4
+
+/* SDRC_POWER bit settings */
+#define SRFRONIDLEREQ_MASK 0x40
+#define PWDENA_MASK 0x4
+
+/* CM_IDLEST1_CORE bit settings */
+#define ST_SDRC_MASK 0x2
+
+/* CM_ICLKEN1_CORE bit settings */
+#define EN_SDRC_MASK 0x2
+
+/* CM_CLKSEL1_PLL bit settings */
+#define CORE_DPLL_CLKOUT_DIV_SHIFT 0x1b
+
/*
* omap3_sram_configure_core_dpll - change DPLL3 M2 divider
* r0 = new SDRC_RFR_CTRL register contents
@@ -57,13 +80,13 @@ ENTRY(omap3_sram_configure_core_dpll)
dsb @ flush buffered writes to interconnect
cmp r3, #0x2 @ if increasing SDRC clk rate,
blne configure_sdrc @ program the SDRC regs early (for RFR)
- cmp r4, #0x1 @ set the intended DLL state
+ cmp r4, #SDRC_UNLOCK_DLL @ set the intended DLL state
bleq unlock_dll
blne lock_dll
bl sdram_in_selfrefresh @ put SDRAM in self refresh, idle SDRC
bl configure_core_dpll @ change the DPLL3 M2 divider
bl enable_sdrc @ take SDRC out of idle
- cmp r4, #0x1 @ wait for DLL status to change
+ cmp r4, #SDRC_UNLOCK_DLL @ wait for DLL status to change
bleq wait_dll_unlock
blne wait_dll_lock
cmp r3, #0x1 @ if increasing SDRC clk rate,
@@ -78,33 +101,33 @@ return_to_sdram:
unlock_dll:
ldr r11, omap3_sdrc_dlla_ctrl
ldr r12, [r11]
- orr r12, r12, #0x4
+ orr r12, r12, #DLLIDLE_MASK
str r12, [r11] @ (no OCP barrier needed)
bx lr
lock_dll:
ldr r11, omap3_sdrc_dlla_ctrl
ldr r12, [r11]
- bic r12, r12, #0x4
+ bic r12, r12, #DLLIDLE_MASK
str r12, [r11] @ (no OCP barrier needed)
bx lr
sdram_in_selfrefresh:
ldr r11, omap3_sdrc_power @ read the SDRC_POWER register
ldr r12, [r11] @ read the contents of SDRC_POWER
mov r9, r12 @ keep a copy of SDRC_POWER bits
- orr r12, r12, #0x40 @ enable self refresh on idle req
- bic r12, r12, #0x4 @ clear PWDENA
+ orr r12, r12, #SRFRONIDLEREQ_MASK @ enable self refresh on idle
+ bic r12, r12, #PWDENA_MASK @ clear PWDENA
str r12, [r11] @ write back to SDRC_POWER register
ldr r12, [r11] @ posted-write barrier for SDRC
idle_sdrc:
ldr r11, omap3_cm_iclken1_core @ read the CM_ICLKEN1_CORE reg
ldr r12, [r11]
- bic r12, r12, #0x2 @ disable iclk bit for SDRC
+ bic r12, r12, #EN_SDRC_MASK @ disable iclk bit for SDRC
str r12, [r11]
wait_sdrc_idle:
ldr r11, omap3_cm_idlest1_core
ldr r12, [r11]
- and r12, r12, #0x2 @ check for SDRC idle
- cmp r12, #2
+ and r12, r12, #ST_SDRC_MASK @ check for SDRC idle
+ cmp r12, #ST_SDRC_MASK
bne wait_sdrc_idle
bx lr
configure_core_dpll:
@@ -112,7 +135,7 @@ configure_core_dpll:
ldr r12, [r11]
ldr r10, core_m2_mask_val @ modify m2 for core dpll
and r12, r12, r10
- orr r12, r12, r3, lsl #0x1B @ r3 contains the M2 val
+ orr r12, r12, r3, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT
str r12, [r11]
ldr r12, [r11] @ posted-write barrier for CM
bx lr
@@ -123,12 +146,12 @@ wait_clk_stable:
enable_sdrc:
ldr r11, omap3_cm_iclken1_core
ldr r12, [r11]
- orr r12, r12, #0x2 @ enable iclk bit for SDRC
+ orr r12, r12, #EN_SDRC_MASK @ enable iclk bit for SDRC
str r12, [r11]
wait_sdrc_idle1:
ldr r11, omap3_cm_idlest1_core
ldr r12, [r11]
- and r12, r12, #0x2
+ and r12, r12, #ST_SDRC_MASK
cmp r12, #0
bne wait_sdrc_idle1
restore_sdrc_power_val:
@@ -138,14 +161,14 @@ restore_sdrc_power_val:
wait_dll_lock:
ldr r11, omap3_sdrc_dlla_status
ldr r12, [r11]
- and r12, r12, #0x4
- cmp r12, #0x4
+ and r12, r12, #LOCKSTATUS_MASK
+ cmp r12, #LOCKSTATUS_MASK
bne wait_dll_lock
bx lr
wait_dll_unlock:
ldr r11, omap3_sdrc_dlla_status
ldr r12, [r11]
- and r12, r12, #0x4
+ and r12, r12, #LOCKSTATUS_MASK
cmp r12, #0x0
bne wait_dll_unlock
bx lr
--
1.5.4.3
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 17/17] OMAP3: Add support for DPLL3 divisor values higher than 2
2009-01-09 15:45 ` [PATCH 16/17] OMAP3 SRAM: convert SRAM code to use macros rather than magic numbers Tero Kristo
@ 2009-01-09 15:45 ` Tero Kristo
0 siblings, 0 replies; 19+ messages in thread
From: Tero Kristo @ 2009-01-09 15:45 UTC (permalink / raw)
To: linux-omap
Previously only 1 and 2 was supported. This is needed for DVFS VDD2 control.
Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
---
arch/arm/mach-omap2/clock34xx.c | 9 +++------
arch/arm/mach-omap2/sram34xx.S | 8 +++++---
arch/arm/plat-omap/include/mach/sram.h | 6 ++++--
arch/arm/plat-omap/sram.c | 6 +++---
4 files changed, 15 insertions(+), 14 deletions(-)
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 4d86ea6..b565ee6 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -518,9 +518,9 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
sdrcrate = sdrc_ick.rate;
if (rate > clk->rate)
- sdrcrate <<= ((rate / clk->rate) - 1);
+ sdrcrate <<= ((rate / clk->rate) >> 1);
else
- sdrcrate >>= ((clk->rate / rate) - 1);
+ sdrcrate >>= ((clk->rate / rate) >> 1);
sp = omap2_sdrc_get_params(sdrcrate);
if (!sp)
@@ -547,12 +547,9 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
pr_debug("clock: SDRC timing params used: %08x %08x %08x\n",
sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb);
- /* REVISIT: SRAM code doesn't support other M2 divisors yet */
- WARN_ON(new_div != 1 && new_div != 2);
-
omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla,
sp->actim_ctrlb, new_div, unlock_dll, c,
- sp->mr);
+ sp->mr, rate > clk->rate);
return 0;
}
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
index 16eb4ef..487fa86 100644
--- a/arch/arm/mach-omap2/sram34xx.S
+++ b/arch/arm/mach-omap2/sram34xx.S
@@ -70,6 +70,7 @@
* r5 = number of MPU cycles to wait for SDRC to stabilize after
* reprogramming the SDRC when switching to a slower MPU speed
* r6 = new SDRC_MR_0 register value
+ * r7 = increasing SDRC rate? (1 = yes, 0 = no)
*
*/
ENTRY(omap3_sram_configure_core_dpll)
@@ -77,9 +78,10 @@ ENTRY(omap3_sram_configure_core_dpll)
ldr r4, [sp, #52] @ pull extra args off the stack
ldr r5, [sp, #56] @ load extra args from the stack
ldr r6, [sp, #60] @ load extra args from the stack
+ ldr r7, [sp, #64] @ load extra args from the stack
dsb @ flush buffered writes to interconnect
- cmp r3, #0x2 @ if increasing SDRC clk rate,
- blne configure_sdrc @ program the SDRC regs early (for RFR)
+ cmp r7, #1 @ if increasing SDRC clk rate,
+ bleq configure_sdrc @ program the SDRC regs early (for RFR)
cmp r4, #SDRC_UNLOCK_DLL @ set the intended DLL state
bleq unlock_dll
blne lock_dll
@@ -89,7 +91,7 @@ ENTRY(omap3_sram_configure_core_dpll)
cmp r4, #SDRC_UNLOCK_DLL @ wait for DLL status to change
bleq wait_dll_unlock
blne wait_dll_lock
- cmp r3, #0x1 @ if increasing SDRC clk rate,
+ cmp r7, #1 @ if increasing SDRC clk rate,
beq return_to_sdram @ return to SDRAM code, otherwise,
bl configure_sdrc @ reprogram SDRC regs now
mov r12, r5
diff --git a/arch/arm/plat-omap/include/mach/sram.h b/arch/arm/plat-omap/include/mach/sram.h
index 6800975..ad0a600 100644
--- a/arch/arm/plat-omap/include/mach/sram.h
+++ b/arch/arm/plat-omap/include/mach/sram.h
@@ -24,7 +24,8 @@ extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl,
u32 sdrc_actim_ctrla,
u32 sdrc_actim_ctrlb, u32 m2,
- u32 unlock_dll, u32 f, u32 sdrc_mr);
+ u32 unlock_dll, u32 f, u32 sdrc_mr,
+ u32 inc);
extern void omap3_sram_restore_context(void);
/* Do not use these */
@@ -63,7 +64,8 @@ extern unsigned long omap243x_sram_reprogram_sdrc_sz;
extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl,
u32 sdrc_actim_ctrla,
u32 sdrc_actim_ctrlb, u32 m2,
- u32 unlock_dll, u32 f, u32 sdrc_mr);
+ u32 unlock_dll, u32 f, u32 sdrc_mr,
+ u32 inc);
extern unsigned long omap3_sram_configure_core_dpll_sz;
#ifdef CONFIG_PM
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index d7aeff8..a2e60e7 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -372,10 +372,10 @@ static u32 (*_omap3_sram_configure_core_dpll)(u32 sdrc_rfr_ctrl,
u32 sdrc_actim_ctrla,
u32 sdrc_actim_ctrlb,
u32 m2, u32 unlock_dll,
- u32 f, u32 sdrc_mr);
+ u32 f, u32 sdrc_mr, u32 inc);
u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla,
u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll,
- u32 f, u32 sdrc_mr)
+ u32 f, u32 sdrc_mr, u32 inc)
{
if (!_omap3_sram_configure_core_dpll)
omap_sram_error();
@@ -383,7 +383,7 @@ u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla,
return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl,
sdrc_actim_ctrla,
sdrc_actim_ctrlb, m2,
- unlock_dll, f, sdrc_mr);
+ unlock_dll, f, sdrc_mr, inc);
}
#ifdef CONFIG_PM
--
1.5.4.3
^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [PATCH 00/17] OMAP3: Base support for VDD2 DVFS
2009-01-09 15:45 [PATCH 00/17] OMAP3: Base support for VDD2 DVFS Tero Kristo
2009-01-09 15:45 ` [PATCH 01/17] ARM: MMU: add a Non-cacheable Normal executable memory type Tero Kristo
@ 2009-01-13 17:13 ` Kevin Hilman
1 sibling, 0 replies; 19+ messages in thread
From: Kevin Hilman @ 2009-01-13 17:13 UTC (permalink / raw)
To: Tero Kristo; +Cc: linux-omap
Tero Kristo <tero.kristo@nokia.com> writes:
> Resending this set against the latest PM branch. This set provides base
> SDRC + SRAM + clock framework support for VDD2 DVFS control. Main reasoning
> for this set is that when VDD2 clock is changed, memory clocking changes also
> and you need to be rather careful when you are doing this.
Pulling this into PM branch for more testing.
BUT.... this series has few (if any) dependencies on other PM branch
code. I would like to se this rebased against l-o and submitted for
direct merge.
Kevin
^ permalink raw reply [flat|nested] 19+ messages in thread
end of thread, other threads:[~2009-01-13 17:13 UTC | newest]
Thread overview: 19+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2009-01-09 15:45 [PATCH 00/17] OMAP3: Base support for VDD2 DVFS Tero Kristo
2009-01-09 15:45 ` [PATCH 01/17] ARM: MMU: add a Non-cacheable Normal executable memory type Tero Kristo
2009-01-09 15:45 ` [PATCH 02/17] OMAP3 SRAM: mark OCM RAM as Non-cacheable Normal memory Tero Kristo
2009-01-09 15:45 ` [PATCH 03/17] OMAP3 SRAM: add ARM barriers to omap3_sram_configure_core_dpll Tero Kristo
2009-01-09 15:45 ` [PATCH 04/17] OMAP3 clock: add interconnect barriers to CORE DPLL M2 change Tero Kristo
2009-01-09 15:45 ` [PATCH 05/17] OMAP3 SRAM: clear the SDRC PWRENA bit during SDRC frequency change Tero Kristo
2009-01-09 15:45 ` [PATCH 06/17] OMAP3 SDRC: Add 166MHz, 83MHz SDRC settings for the BeagleBoard Tero Kristo
2009-01-09 15:45 ` [PATCH 07/17] OMAP3 SDRC: initialize SDRC_POWER at boot Tero Kristo
2009-01-09 15:45 ` [PATCH 08/17] OMAP3 SRAM: renumber registers to make space for argument passing Tero Kristo
2009-01-09 15:45 ` [PATCH 09/17] OMAP3 clock: only unlock SDRC DLL if SDRC clk < 83MHz Tero Kristo
2009-01-09 15:45 ` [PATCH 10/17] OMAP3 clock: use pr_debug() rather than pr_info() in some clock change code Tero Kristo
2009-01-09 15:45 ` [PATCH 11/17] OMAP3 clock: remove wait for DPLL3 M2 clock to stabilize Tero Kristo
2009-01-09 15:45 ` [PATCH 12/17] OMAP3 clock: initialize SDRC timings at kernel start Tero Kristo
2009-01-09 15:45 ` [PATCH 13/17] OMAP3 clock: add a short delay when lowering CORE clk rate Tero Kristo
2009-01-09 15:45 ` [PATCH 14/17] OMAP3 clock/SDRC: program SDRC_MR register during SDRC clock change Tero Kristo
2009-01-09 15:45 ` [PATCH 15/17] OMAP3 SRAM: add more comments on the SRAM code Tero Kristo
2009-01-09 15:45 ` [PATCH 16/17] OMAP3 SRAM: convert SRAM code to use macros rather than magic numbers Tero Kristo
2009-01-09 15:45 ` [PATCH 17/17] OMAP3: Add support for DPLL3 divisor values higher than 2 Tero Kristo
2009-01-13 17:13 ` [PATCH 00/17] OMAP3: Base support for VDD2 DVFS Kevin Hilman
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox