[PATCH 0/5] extra module resets to ensure full-chip idle

[PATCH 0/5] extra module resets to ensure full-chip idle

[Kevin Hilman]

Various bootloaders have been known to leave modules in a state
which prevents full-chip retention.  This series forces
MMC, IVA2 and D2D/modem into known reset/idle states so that
the OMAP3 can hit full-chip idle.

Tested on OMAP3 Beagle, and custom OMAP3 hardware.

NOTE: this is similar to the set I posted for the PM branch
      but this series is rebased onto linux-omap and includes
      the MMC reset.

Kevin Hilman (5):
  OMAP3: PM: HSMMC: force MMC module reset on boot
  OMAP3: PM: Force IVA2 into idle during bootup
  OMAP3: PM: Add D2D clocks and auto-idle setup to PRCM init
  OMAP3: PM: D2D clockdomain supports SW supervised transitions
  OMAP3: PM: Ensure modem is reset during PRCM init

 arch/arm/mach-omap2/clock34xx.h           |   37 +++++++++++++-
 arch/arm/mach-omap2/clockdomains.h        |    2 +-
 arch/arm/mach-omap2/cm-regbits-34xx.h     |   14 +++++
 arch/arm/mach-omap2/devices.c             |   76 +++++++++++++++++++++++++++++
 arch/arm/mach-omap2/pm34xx.c              |   65 ++++++++++++++++++++++++-
 arch/arm/plat-omap/include/mach/control.h |    5 ++
 6 files changed, 195 insertions(+), 4 deletions(-)

[PATCH 1/5] OMAP3: PM: HSMMC: force MMC module reset on boot

[Kevin Hilman]

The bootloader may leave the MMC in a state which prevents hitting
retention.  Even when MMC is not compiled in, each MMC module needs to
be forced into reset.

Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
---
 arch/arm/mach-omap2/devices.c |   76 +++++++++++++++++++++++++++++++++++++++++
 1 files changed, 76 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 241e418..196de4e 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -14,6 +14,7 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
+#include <linux/clk.h>
 
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
@@ -358,6 +359,80 @@ static inline void omap_init_sha1_md5(void) { }
 
 /*-------------------------------------------------------------------------*/
 
+#ifdef CONFIG_ARCH_OMAP3
+
+#define MMCHS1				(L4_34XX_BASE + 0x9C000)
+#define MMCHS2				(L4_34XX_BASE + 0xB4000)
+#define MMCHS3				(L4_34XX_BASE + 0xAD000)
+#define MAX_MMC				3
+#define MMCHS_SYSCONFIG			0x0010
+#define MMCHS_SYSCONFIG_SWRESET		(1 << 1)
+#define MMCHS_SYSSTATUS			0x0014
+#define MMCHS_SYSSTATUS_RESETDONE	(1 << 0)
+
+static struct platform_device dummy_pdev = {
+	.dev = {
+		.bus = &platform_bus_type,
+	},
+};
+
+/**
+ * omap_hsmmc_reset() - Full reset of each HS-MMC controller
+ *
+ * Ensure that each MMC controller is fully reset.  Controllers
+ * left in an unknown state (by bootloaer) may prevent retention
+ * or OFF-mode.  This is especially important in cases where the
+ * MMC driver is not enabled, _or_ built as a module.
+ *
+ * In order for reset to work, interface, functional and debounce
+ * clocks must be enabled.  The debounce clock comes from func_32k_clk
+ * and is not under SW control, so we only enable i- and f-clocks.
+ **/
+static void __init omap_hsmmc_reset(void)
+{
+	u32 i, base[MAX_MMC] = {MMCHS1, MMCHS2, MMCHS3};
+
+	for (i = 0; i < MAX_MMC; i++) {
+		u32 v;
+		struct clk *iclk, *fclk;
+		struct device *dev = &dummy_pdev.dev;
+
+		dummy_pdev.id = i;
+		iclk = clk_get(dev, "mmchs_ick");
+		if (iclk && clk_enable(iclk))
+			iclk = NULL;
+
+		fclk = clk_get(dev, "mmchs_fck");
+		if (fclk && clk_enable(fclk))
+			fclk = NULL;
+
+		if (!iclk || !fclk) {
+			printk(KERN_WARNING
+			       "%s: Unable to enable clocks for MMC%d, "
+			       "cannot reset.\n",  __func__, i);
+			break;
+		}
+
+		omap_writel(MMCHS_SYSCONFIG_SWRESET, base[i] + MMCHS_SYSCONFIG);
+		v = omap_readl(base[i] + MMCHS_SYSSTATUS);
+		while (!(omap_readl(base[i] + MMCHS_SYSSTATUS) &
+			 MMCHS_SYSSTATUS_RESETDONE))
+			cpu_relax();
+
+		if (fclk) {
+			clk_disable(fclk);
+			clk_put(fclk);
+		}
+		if (iclk) {
+			clk_disable(iclk);
+			clk_put(iclk);
+		}
+	}
+}
+#else
+static inline void omap_hsmmc_reset(void) {}
+#endif
+
 #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \
 	defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
 
@@ -477,6 +552,7 @@ static int __init omap2_init_devices(void)
 	/* please keep these calls, and their implementations above,
 	 * in alphabetical order so they're easier to sort through.
 	 */
+	omap_hsmmc_reset();
 	omap_init_camera();
 	omap_init_mbox();
 	omap_init_mcspi();
-- 
1.6.0.3

[PATCH 2/5] OMAP3: PM: Force IVA2 into idle during bootup

[Kevin Hilman]

Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
---
 arch/arm/mach-omap2/pm34xx.c              |   55 +++++++++++++++++++++++++++++
 arch/arm/plat-omap/include/mach/control.h |    5 +++
 2 files changed, 60 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 9f5a544..5166fbd 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -29,6 +29,7 @@
 #include <mach/pm.h>
 #include <mach/clockdomain.h>
 #include <mach/powerdomain.h>
+#include <mach/control.h>
 
 #include "cm.h"
 #include "cm-regbits-34xx.h"
@@ -363,6 +364,58 @@ static struct platform_suspend_ops omap_pm_ops = {
 	.valid		= suspend_valid_only_mem,
 };
 
+
+/**
+ * omap3_iva_idle(): ensure IVA is in idle so it can be put into
+ *                   retention
+ *
+ * In cases where IVA2 is activated by bootcode, it may prevent
+ * full-chip retention or off-mode because it is not idle.  This
+ * function forces the IVA2 into idle state so it can go
+ * into retention/off and thus allow full-chip retention/off.
+ *
+ **/
+static void __init omap3_iva_idle(void)
+{
+	struct clk *iva2_ck;
+
+	iva2_ck = clk_get(NULL, "iva2_fclk");
+	if (!iva2_ck) {
+		pr_err("Unable to get IVA2 fclk: cannot force idle.\n");
+		return;
+	}
+
+	/* Disable IVA2 clock */
+	clk_disable(iva2_ck);
+
+	/* Reset IVA2 */
+	prm_write_mod_reg(OMAP3430_RST1_IVA2 |
+			  OMAP3430_RST2_IVA2 |
+			  OMAP3430_RST3_IVA2,
+			  OMAP3430_IVA2_MOD, RM_RSTCTRL);
+
+	/* Enable IVA2 clock */
+	clk_enable(iva2_ck);
+
+	/* Set IVA2 boot mode to 'idle' */
+	omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
+			 OMAP343X_CONTROL_IVA2_BOOTMOD);
+
+	/* Un-reset IVA2 */
+	prm_write_mod_reg(0, OMAP3430_IVA2_MOD, RM_RSTCTRL);
+
+	/* Disable IVA2 clocks */
+	clk_disable(iva2_ck);
+
+	/* Reset IVA2 */
+	prm_write_mod_reg(OMAP3430_RST1_IVA2 |
+			  OMAP3430_RST2_IVA2 |
+			  OMAP3430_RST3_IVA2,
+			  OMAP3430_IVA2_MOD, RM_RSTCTRL);
+
+	clk_put(iva2_ck);
+}
+
 static void __init prcm_setup_regs(void)
 {
 	/* XXX Reset all wkdeps. This should be done when initializing
@@ -515,6 +568,8 @@ static void __init prcm_setup_regs(void)
 	 * it is selected to mpu wakeup goup */
 	prm_write_mod_reg(OMAP3430_IO_EN | OMAP3430_WKUP_EN,
 			OCP_MOD, OMAP2_PRM_IRQENABLE_MPU_OFFSET);
+
+	omap3_iva_idle();
 }
 
 static int __init pwrdms_setup(struct powerdomain *pwrdm)
diff --git a/arch/arm/plat-omap/include/mach/control.h b/arch/arm/plat-omap/include/mach/control.h
index ee3c39e..b51f7fd 100644
--- a/arch/arm/plat-omap/include/mach/control.h
+++ b/arch/arm/plat-omap/include/mach/control.h
@@ -208,6 +208,11 @@
 #define OMAP2_PBIASLITEPWRDNZ0		(1 << 1)
 #define OMAP2_PBIASLITEVMODE0		(1 << 0)
 
+/* CONTROL_IVA2_BOOTMOD bits */
+#define OMAP3_IVA2_BOOTMOD_SHIFT	0
+#define OMAP3_IVA2_BOOTMOD_MASK		(0xf << 0)
+#define OMAP3_IVA2_BOOTMOD_IDLE		(0x1 << 0)
+
 #ifndef __ASSEMBLY__
 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
 extern void __iomem *omap_ctrl_base_get(void);
-- 
1.6.0.3

[PATCH 3/5] OMAP3: PM: Add D2D clocks and auto-idle setup to PRCM init

[Kevin Hilman]

Add D2D clocks (modem_fck, sad2d_ick, mad2d_ick) to clock framework,
and also ensure that auto-idle bits are set for these clocks during
PRCM init.

Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
---
 arch/arm/mach-omap2/clock34xx.h       |   37 +++++++++++++++++++++++++++++++-
 arch/arm/mach-omap2/cm-regbits-34xx.h |   14 ++++++++++++
 arch/arm/mach-omap2/pm34xx.c          |    4 ++-
 3 files changed, 52 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index 0b95fcb..78504ce 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -1330,6 +1330,38 @@ static struct clk d2d_26m_fck = {
 	.recalc		= &followparent_recalc,
 };
 
+static struct clk modem_fck = {
+	.name		= "modem_fck",
+	.parent		= &sys_ck,
+	.prcm_mod	= CORE_MOD,
+	.enable_reg	= CM_FCLKEN1,
+	.enable_bit	= OMAP3430_EN_MODEM_SHIFT,
+	.flags		= CLOCK_IN_OMAP343X,
+	.clkdm		= { .name = "d2d_clkdm" },
+	.recalc		= &followparent_recalc,
+};
+
+static struct clk sad2d_ick = {
+	.name		= "sad2d_ick",
+	.parent		= &sys_ck,
+	.prcm_mod	= CORE_MOD,
+	.enable_reg	= CM_ICLKEN1,
+	.enable_bit	= OMAP3430_EN_SAD2D_SHIFT,
+	.flags		= CLOCK_IN_OMAP343X,
+	.clkdm		= { .name = "d2d_clkdm" },
+	.recalc		= &followparent_recalc,
+};
+
+static struct clk mad2d_ick = {
+	.name		= "mad2d_ick",
+	.parent		= &sys_ck,
+	.prcm_mod	= CORE_MOD,
+	.enable_reg	= CM_ICLKEN3,
+	.enable_bit	= OMAP3430_EN_MAD2D_SHIFT,
+	.flags		= CLOCK_IN_OMAP343X,
+	.clkdm		= { .name = "d2d_clkdm" },
+	.recalc		= &followparent_recalc,
+};
 static const struct clksel omap343x_gpt_clksel[] = {
 	{ .parent = &omap_32k_fck, .rates = gpt_32k_rates },
 	{ .parent = &sys_ck,	   .rates = gpt_sys_rates },
@@ -2241,8 +2273,6 @@ static struct clk usb_l4_ick = {
 	.recalc		= &omap2_clksel_recalc,
 };
 
-/* XXX MDM_INTC_ICK, SAD2D_ICK ?? */
-
 /* SECURITY_L4_ICK2 based clocks */
 
 static struct clk security_l4_ick2 = {
@@ -3460,6 +3490,9 @@ static struct clk *onchip_34xx_clks[] __initdata = {
 	&sgx_fck,
 	&sgx_ick,
 	&d2d_26m_fck,
+	&modem_fck,
+	&sad2d_ick,
+	&mad2d_ick,
 	&gpt10_fck,
 	&gpt11_fck,
 	&cpefuse_fck,
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h
index 6f3f5a3..6923deb 100644
--- a/arch/arm/mach-omap2/cm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
@@ -145,6 +145,8 @@
 #define OMAP3430_CLKACTIVITY_MPU_MASK			(1 << 0)
 
 /* CM_FCLKEN1_CORE specific bits */
+#define OMAP3430_EN_MODEM				(1 << 31)
+#define OMAP3430_EN_MODEM_SHIFT				31
 
 /* CM_ICLKEN1_CORE specific bits */
 #define OMAP3430_EN_ICR					(1 << 29)
@@ -161,6 +163,8 @@
 #define OMAP3430_EN_MAILBOXES_SHIFT			7
 #define OMAP3430_EN_OMAPCTRL				(1 << 6)
 #define OMAP3430_EN_OMAPCTRL_SHIFT			6
+#define OMAP3430_EN_SAD2D				(1 << 3)
+#define OMAP3430_EN_SAD2D_SHIFT				3
 #define OMAP3430_EN_SDRC				(1 << 1)
 #define OMAP3430_EN_SDRC_SHIFT				1
 
@@ -176,6 +180,10 @@
 #define OMAP3430_EN_DES1				(1 << 0)
 #define OMAP3430_EN_DES1_SHIFT				0
 
+/* CM_ICLKEN3_CORE */
+#define OMAP3430_EN_MAD2D_SHIFT				3
+#define OMAP3430_EN_MAD2D				(1 << 3)
+
 /* CM_FCLKEN3_CORE specific bits */
 #define OMAP3430ES2_EN_TS_SHIFT				1
 #define OMAP3430ES2_EN_TS_MASK				(1 << 1)
@@ -231,6 +239,8 @@
 #define OMAP3430ES2_ST_CPEFUSE_MASK			(1 << 0)
 
 /* CM_AUTOIDLE1_CORE */
+#define OMAP3430_AUTO_MODEM				(1 << 31)
+#define OMAP3430_AUTO_MODEM_SHIFT			31
 #define OMAP3430ES2_AUTO_MMC3				(1 << 30)
 #define OMAP3430ES2_AUTO_MMC3_SHIFT			30
 #define OMAP3430ES2_AUTO_ICR				(1 << 29)
@@ -287,6 +297,8 @@
 #define OMAP3430_AUTO_HSOTGUSB_SHIFT			4
 #define OMAP3430ES1_AUTO_D2D				(1 << 3)
 #define OMAP3430ES1_AUTO_D2D_SHIFT			3
+#define OMAP3430_AUTO_SAD2D				(1 << 3)
+#define OMAP3430_AUTO_SAD2D_SHIFT			3
 #define OMAP3430_AUTO_SSI				(1 << 0)
 #define OMAP3430_AUTO_SSI_SHIFT				0
 
@@ -308,6 +320,8 @@
 #define	OMAP3430ES2_AUTO_USBTLL				(1 << 2)
 #define OMAP3430ES2_AUTO_USBTLL_SHIFT			2
 #define OMAP3430ES2_AUTO_USBTLL_MASK			(1 << 2)
+#define OMAP3430_AUTO_MAD2D_SHIFT			3
+#define OMAP3430_AUTO_MAD2D				(1 << 3)
 
 /* CM_CLKSEL_CORE */
 #define OMAP3430_CLKSEL_SSI_SHIFT			8
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 5166fbd..7c5577a 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -437,6 +437,7 @@ static void __init prcm_setup_regs(void)
 	 * Note that in the long run this should be done by clockfw
 	 */
 	cm_write_mod_reg(
+		OMAP3430_AUTO_MODEM |
 		OMAP3430ES2_AUTO_MMC3 |
 		OMAP3430ES2_AUTO_ICR |
 		OMAP3430_AUTO_AES2 |
@@ -464,7 +465,7 @@ static void __init prcm_setup_regs(void)
 		OMAP3430_AUTO_OMAPCTRL |
 		OMAP3430ES1_AUTO_FSHOSTUSB |
 		OMAP3430_AUTO_HSOTGUSB |
-		OMAP3430ES1_AUTO_D2D | /* This is es1 only */
+		OMAP3430_AUTO_SAD2D |
 		OMAP3430_AUTO_SSI,
 		CORE_MOD, CM_AUTOIDLE1);
 
@@ -478,6 +479,7 @@ static void __init prcm_setup_regs(void)
 
 	if (omap_rev() > OMAP3430_REV_ES1_0) {
 		cm_write_mod_reg(
+			OMAP3430_AUTO_MAD2D |
 			OMAP3430ES2_AUTO_USBTLL,
 			CORE_MOD, CM_AUTOIDLE3);
 	}
-- 
1.6.0.3

[PATCH 4/5] OMAP3: PM: D2D clockdomain supports SW supervised transitions

[Kevin Hilman]

Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
---
 arch/arm/mach-omap2/clockdomains.h |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/clockdomains.h b/arch/arm/mach-omap2/clockdomains.h
index bafa650..49a5774 100644
--- a/arch/arm/mach-omap2/clockdomains.h
+++ b/arch/arm/mach-omap2/clockdomains.h
@@ -198,7 +198,7 @@ static struct clockdomain sgx_clkdm = {
 static struct clockdomain d2d_clkdm = {
 	.name		= "d2d_clkdm",
 	.pwrdm		= { .name = "core_pwrdm" },
-	.flags		= CLKDM_CAN_HWSUP,
+	.flags		= CLKDM_CAN_HWSUP_SWSUP,
 	.clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK,
 	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
-- 
1.6.0.3

[PATCH 5/5] OMAP3: PM: Ensure modem is reset during PRCM init

[Kevin Hilman]

Rogue bootloaders may enable the modem and thus keep the
D2D power- and clock-domains from going into retention.
Reset modem on boot to be sure it is in known state.

Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
---
 arch/arm/mach-omap2/pm34xx.c |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 7c5577a..e22a11f 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -418,6 +418,12 @@ static void __init omap3_iva_idle(void)
 
 static void __init prcm_setup_regs(void)
 {
+	/* reset modem */
+	prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON |
+			  OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST,
+			  CORE_MOD, RM_RSTCTRL);
+	prm_write_mod_reg(0, CORE_MOD, RM_RSTCTRL);
+
 	/* XXX Reset all wkdeps. This should be done when initializing
 	 * powerdomains */
 	prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
-- 
1.6.0.3

Re: [PATCH 1/5] OMAP3: PM: HSMMC: force MMC module reset on boot

[Tony Lindgren]

* Kevin Hilman <khilman@deeprootsystems.com> [081126 16:07]:
> The bootloader may leave the MMC in a state which prevents hitting
> retention.  Even when MMC is not compiled in, each MMC module needs to
> be forced into reset.
> 
> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
> ---
>  arch/arm/mach-omap2/devices.c |   76 +++++++++++++++++++++++++++++++++++++++++
>  1 files changed, 76 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
> index 241e418..196de4e 100644
> --- a/arch/arm/mach-omap2/devices.c
> +++ b/arch/arm/mach-omap2/devices.c
> @@ -14,6 +14,7 @@
>  #include <linux/init.h>
>  #include <linux/platform_device.h>
>  #include <linux/io.h>
> +#include <linux/clk.h>
>  
>  #include <mach/hardware.h>
>  #include <asm/mach-types.h>
> @@ -358,6 +359,80 @@ static inline void omap_init_sha1_md5(void) { }
>  
>  /*-------------------------------------------------------------------------*/
>  
> +#ifdef CONFIG_ARCH_OMAP3
> +
> +#define MMCHS1				(L4_34XX_BASE + 0x9C000)
> +#define MMCHS2				(L4_34XX_BASE + 0xB4000)
> +#define MMCHS3				(L4_34XX_BASE + 0xAD000)

These are already in plat-omap/include/mach/mmc.h, how about just
include it? Then you can have a switch statement like we already have
for omap2_init_mmc?

> +#define MAX_MMC				3

This too

> +#define MMCHS_SYSCONFIG			0x0010
> +#define MMCHS_SYSCONFIG_SWRESET		(1 << 1)
> +#define MMCHS_SYSSTATUS			0x0014
> +#define MMCHS_SYSSTATUS_RESETDONE	(1 << 0)
> +
> +static struct platform_device dummy_pdev = {
> +	.dev = {
> +		.bus = &platform_bus_type,
> +	},
> +};
> +
> +/**
> + * omap_hsmmc_reset() - Full reset of each HS-MMC controller
> + *
> + * Ensure that each MMC controller is fully reset.  Controllers
> + * left in an unknown state (by bootloaer) may prevent retention
> + * or OFF-mode.  This is especially important in cases where the
> + * MMC driver is not enabled, _or_ built as a module.

Should say bootloader above :)

Regards,

Tony


> + * In order for reset to work, interface, functional and debounce
> + * clocks must be enabled.  The debounce clock comes from func_32k_clk
> + * and is not under SW control, so we only enable i- and f-clocks.
> + **/
> +static void __init omap_hsmmc_reset(void)
> +{
> +	u32 i, base[MAX_MMC] = {MMCHS1, MMCHS2, MMCHS3};
> +
> +	for (i = 0; i < MAX_MMC; i++) {
> +		u32 v;
> +		struct clk *iclk, *fclk;
> +		struct device *dev = &dummy_pdev.dev;
> +
> +		dummy_pdev.id = i;
> +		iclk = clk_get(dev, "mmchs_ick");
> +		if (iclk && clk_enable(iclk))
> +			iclk = NULL;
> +
> +		fclk = clk_get(dev, "mmchs_fck");
> +		if (fclk && clk_enable(fclk))
> +			fclk = NULL;
> +
> +		if (!iclk || !fclk) {
> +			printk(KERN_WARNING
> +			       "%s: Unable to enable clocks for MMC%d, "
> +			       "cannot reset.\n",  __func__, i);
> +			break;
> +		}
> +
> +		omap_writel(MMCHS_SYSCONFIG_SWRESET, base[i] + MMCHS_SYSCONFIG);
> +		v = omap_readl(base[i] + MMCHS_SYSSTATUS);
> +		while (!(omap_readl(base[i] + MMCHS_SYSSTATUS) &
> +			 MMCHS_SYSSTATUS_RESETDONE))
> +			cpu_relax();
> +
> +		if (fclk) {
> +			clk_disable(fclk);
> +			clk_put(fclk);
> +		}
> +		if (iclk) {
> +			clk_disable(iclk);
> +			clk_put(iclk);
> +		}
> +	}
> +}
> +#else
> +static inline void omap_hsmmc_reset(void) {}
> +#endif
> +
>  #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \
>  	defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
>  
> @@ -477,6 +552,7 @@ static int __init omap2_init_devices(void)
>  	/* please keep these calls, and their implementations above,
>  	 * in alphabetical order so they're easier to sort through.
>  	 */
> +	omap_hsmmc_reset();
>  	omap_init_camera();
>  	omap_init_mbox();
>  	omap_init_mcspi();
> -- 
> 1.6.0.3
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH 0/5] extra module resets to ensure full-chip idle

[Dirk Behme]

Kevin Hilman wrote:
> Various bootloaders have been known to leave modules in a state
> which prevents full-chip retention.  

Does it make sense to check if

[PATCH 1/5] OMAP3: PM: HSMMC: force MMC module reset on boot
[PATCH 2/5] OMAP3: PM: Force IVA2 into idle during bootup

can be done in U-Boot, too? If yes, I would have a look to it.

Regards

Dirk

> This series forces
> MMC, IVA2 and D2D/modem into known reset/idle states so that
> the OMAP3 can hit full-chip idle.
> 
> Tested on OMAP3 Beagle, and custom OMAP3 hardware.
> 
> NOTE: this is similar to the set I posted for the PM branch
>       but this series is rebased onto linux-omap and includes
>       the MMC reset.
> 
> Kevin Hilman (5):
>   OMAP3: PM: HSMMC: force MMC module reset on boot
>   OMAP3: PM: Force IVA2 into idle during bootup
>   OMAP3: PM: Add D2D clocks and auto-idle setup to PRCM init
>   OMAP3: PM: D2D clockdomain supports SW supervised transitions
>   OMAP3: PM: Ensure modem is reset during PRCM init
> 
>  arch/arm/mach-omap2/clock34xx.h           |   37 +++++++++++++-
>  arch/arm/mach-omap2/clockdomains.h        |    2 +-
>  arch/arm/mach-omap2/cm-regbits-34xx.h     |   14 +++++
>  arch/arm/mach-omap2/devices.c             |   76 +++++++++++++++++++++++++++++
>  arch/arm/mach-omap2/pm34xx.c              |   65 ++++++++++++++++++++++++-
>  arch/arm/plat-omap/include/mach/control.h |    5 ++
>  6 files changed, 195 insertions(+), 4 deletions(-)
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 

Re: [PATCH 0/5] extra module resets to ensure full-chip idle

[Kevin Hilman]

Dirk Behme <dirk.behme@googlemail.com> writes:

> Kevin Hilman wrote:
>> Various bootloaders have been known to leave modules in a state
>> which prevents full-chip retention.  
>
> Does it make sense to check if
>
> [PATCH 1/5] OMAP3: PM: HSMMC: force MMC module reset on boot
> [PATCH 2/5] OMAP3: PM: Force IVA2 into idle during bootup
>
> can be done in U-Boot, too? If yes, I would have a look to it.

Yes, ideally u-boot or whatever bootloader isused should 
be leaving these modules in a known reset/idle state.

However, there are many bootloaders for many platforms out there so
until there is some sort of standard on bootloaders, I think the
kernel will have to ensure this is done.

Kevin

>
>> This series forces
>> MMC, IVA2 and D2D/modem into known reset/idle states so that
>> the OMAP3 can hit full-chip idle.
>>
>> Tested on OMAP3 Beagle, and custom OMAP3 hardware.
>>
>> NOTE: this is similar to the set I posted for the PM branch
>>       but this series is rebased onto linux-omap and includes
>>       the MMC reset.
>>
>> Kevin Hilman (5):
>>   OMAP3: PM: HSMMC: force MMC module reset on boot
>>   OMAP3: PM: Force IVA2 into idle during bootup
>>   OMAP3: PM: Add D2D clocks and auto-idle setup to PRCM init
>>   OMAP3: PM: D2D clockdomain supports SW supervised transitions
>>   OMAP3: PM: Ensure modem is reset during PRCM init
>>
>>  arch/arm/mach-omap2/clock34xx.h           |   37 +++++++++++++-
>>  arch/arm/mach-omap2/clockdomains.h        |    2 +-
>>  arch/arm/mach-omap2/cm-regbits-34xx.h     |   14 +++++
>>  arch/arm/mach-omap2/devices.c             |   76 +++++++++++++++++++++++++++++
>>  arch/arm/mach-omap2/pm34xx.c              |   65 ++++++++++++++++++++++++-
>>  arch/arm/plat-omap/include/mach/control.h |    5 ++
>>  6 files changed, 195 insertions(+), 4 deletions(-)
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
>> the body of a message to majordomo@vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>>

Re: [PATCH 0/5] extra module resets to ensure full-chip idle

[Koen Kooi]

[-- Attachment #1: Type: text/plain, Size: 1628 bytes --]


Op 27 nov 2008, om 01:05 heeft Kevin Hilman het volgende geschreven:

> Various bootloaders have been known to leave modules in a state
> which prevents full-chip retention.  This series forces
> MMC, IVA2 and D2D/modem into known reset/idle states so that
> the OMAP3 can hit full-chip idle.
>
> Tested on OMAP3 Beagle, and custom OMAP3 hardware.
>
> NOTE: this is similar to the set I posted for the PM branch
>      but this series is rebased onto linux-omap and includes
>      the MMC reset.

I'm having trouble applying these against current head  
(5019ed843f3208482c64043e4052e89b3d5462a0), against which rev were  
they generated?

regards,

Koen



>
>
> Kevin Hilman (5):
>  OMAP3: PM: HSMMC: force MMC module reset on boot
>  OMAP3: PM: Force IVA2 into idle during bootup
>  OMAP3: PM: Add D2D clocks and auto-idle setup to PRCM init
>  OMAP3: PM: D2D clockdomain supports SW supervised transitions
>  OMAP3: PM: Ensure modem is reset during PRCM init
>
> arch/arm/mach-omap2/clock34xx.h           |   37 +++++++++++++-
> arch/arm/mach-omap2/clockdomains.h        |    2 +-
> arch/arm/mach-omap2/cm-regbits-34xx.h     |   14 +++++
> arch/arm/mach-omap2/devices.c             |   76 ++++++++++++++++++++ 
> +++++++++
> arch/arm/mach-omap2/pm34xx.c              |   65 ++++++++++++++++++++ 
> ++++-
> arch/arm/plat-omap/include/mach/control.h |    5 ++
> 6 files changed, 195 insertions(+), 4 deletions(-)
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux- 
> omap" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>


[-- Attachment #2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 186 bytes --]

Re: [PATCH 0/5] extra module resets to ensure full-chip idle

[Kevin Hilman]

Koen Kooi <k.kooi@student.utwente.nl> writes:

> Op 27 nov 2008, om 01:05 heeft Kevin Hilman het volgende geschreven:
>
>> Various bootloaders have been known to leave modules in a state
>> which prevents full-chip retention.  This series forces
>> MMC, IVA2 and D2D/modem into known reset/idle states so that
>> the OMAP3 can hit full-chip idle.
>>
>> Tested on OMAP3 Beagle, and custom OMAP3 hardware.
>>
>> NOTE: this is similar to the set I posted for the PM branch
>>      but this series is rebased onto linux-omap and includes
>>      the MMC reset.
>
> I'm having trouble applying these against current head
> (5019ed843f3208482c64043e4052e89b3d5462a0), against which rev were
> they generated?
>
> regards,
>
> Koen
>

Sorry...

This series applies on top of on addtional patch which I mistakenly
assumed was already in l-o.  Here it is.

Kevin

>From cbcf5c91b3e5156a9379d2312de9c9fa814bd3d8 Mon Sep 17 00:00:00 2001
From: Tero Kristo <tero.kristo@nokia.com>
Date: Wed, 26 Nov 2008 14:41:28 -0800
Subject: [PATCH] OMAP2/3 clock: fix DPLL rate calculation

Noncore dpll can enter autoidle state, in which case the rate calculation
fails.  Fixed by checking dpll mode instead of idle status.

Also, previously, the OMAP2xxx code returned the wrong value for the
DPLL rate under some conditions.  Move the CORE_CLK rate recalculation
to clock24xx.c:omap2xxx_clk_get_core_rate().

Thanks to Peter de Schrijver <peter.de-schrijver@nokia.com> for help
debugging and Kevin Hilman <khilman@deeprootsystems.com> for reporting
the OMAP2 build problems with an earlier version of this patch.

Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Peter de Schrijver <peter.de-schrijver@nokia.com>
---
 arch/arm/mach-omap2/clock.c             |   29 ++++++++++++++--------
 arch/arm/mach-omap2/clock.h             |    5 ++++
 arch/arm/mach-omap2/clock24xx.c         |   39 ++++++++++++++++++++----------
 arch/arm/mach-omap2/clock24xx.h         |    4 +-
 arch/arm/mach-omap2/sdrc2xxx.c          |    2 +
 arch/arm/plat-omap/include/mach/clock.h |   13 +++-------
 6 files changed, 57 insertions(+), 35 deletions(-)

diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 42af286..54255fe 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -71,9 +71,15 @@
 #define DPLL_FINT_UNDERFLOW		-1
 #define DPLL_FINT_INVALID		-2
 
-/* Some OMAP2xxx CM_CLKSEL_PLL.ST_CORE_CLK bits - for omap2_get_dpll_rate() */
-#define ST_CORE_CLK_REF			0x1
-#define ST_CORE_CLK_32K			0x3
+/* OMAP2xxx CM_CLKEN_PLL.EN_DPLL bits - for omap2_get_dpll_rate() */
+#define OMAP2XXX_EN_DPLL_LPBYPASS		0x1
+#define OMAP2XXX_EN_DPLL_FRBYPASS		0x2
+#define OMAP2XXX_EN_DPLL_LOCKED			0x3
+
+/* OMAP3xxx CM_CLKEN_PLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
+#define OMAP3XXX_EN_DPLL_LPBYPASS		0x5
+#define OMAP3XXX_EN_DPLL_FRBYPASS		0x6
+#define OMAP3XXX_EN_DPLL_LOCKED			0x7
 
 /* Bitmask to isolate the register type of clk.enable_reg */
 #define PRCM_REGTYPE_MASK		0xf0
@@ -267,19 +273,20 @@ u32 omap2_get_dpll_rate(struct clk *clk)
 		return 0;
 
 	/* Return bypass rate if DPLL is bypassed */
-	v = cm_read_mod_reg(clk->prcm_mod, dd->idlest_reg);
-	v &= dd->idlest_mask;
-	v >>= __ffs(dd->idlest_mask);
+	v = cm_read_mod_reg(clk->prcm_mod, dd->control_reg);
+	v &= dd->enable_mask;
+	v >>= __ffs(dd->enable_mask);
+
 	if (cpu_is_omap24xx()) {
 
-		if (v == ST_CORE_CLK_REF)
-			return clk->parent->rate; /* sys_clk */
-		else if (v == ST_CORE_CLK_32K)
-			return 32768;
+		if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
+		    v == OMAP2XXX_EN_DPLL_FRBYPASS)
+			return clk->parent->rate;
 
 	} else if (cpu_is_omap34xx()) {
 
-		if (!v)
+		if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
+		    v == OMAP3XXX_EN_DPLL_FRBYPASS)
 			return dd->bypass_clk->rate;
 
 	}
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index bcb0c03..b7784d1 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -21,6 +21,11 @@
 /* The maximum error between a target DPLL rate and the rounded rate in Hz */
 #define DEFAULT_DPLL_RATE_TOLERANCE	50000
 
+/* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */
+#define CORE_CLK_SRC_32K		0x0
+#define CORE_CLK_SRC_DPLL		0x1
+#define CORE_CLK_SRC_DPLL_X2		0x2
+
 int omap2_clk_init(void);
 int omap2_clk_enable(struct clk *clk);
 void omap2_clk_disable(struct clk *clk);
diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c
index 32f6632..4bd21dd 100644
--- a/arch/arm/mach-omap2/clock24xx.c
+++ b/arch/arm/mach-omap2/clock24xx.c
@@ -60,19 +60,32 @@ static struct clk *sclk;
  * Omap24xx specific clock functions
  *-------------------------------------------------------------------------*/
 
-/* This actually returns the rate of core_ck, not dpll_ck. */
-static u32 omap2_get_dpll_rate_24xx(struct clk *tclk)
+/**
+ * omap2xxx_clk_get_core_rate - return the CORE_CLK rate
+ * @clk: pointer to the combined dpll_ck + core_ck (currently "dpll_ck")
+ *
+ * Returns the CORE_CLK rate.  CORE_CLK can have one of three rate
+ * sources on OMAP2xxx: the DPLL CLKOUT rate, DPLL CLKOUTX2, or 32KHz
+ * (the latter is unusual).  This currently should be called with
+ * struct clk *dpll_ck, which is a composite clock of dpll_ck and
+ * core_ck.
+ */
+static u32 omap2xxx_clk_get_core_rate(struct clk *clk)
 {
-	long long dpll_clk;
-	u8 amult;
+	long long core_clk;
+	u32 v;
 
-	dpll_clk = omap2_get_dpll_rate(tclk);
+	core_clk = omap2_get_dpll_rate(clk);
 
-	amult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
-	amult &= OMAP24XX_CORE_CLK_SRC_MASK;
-	dpll_clk *= amult;
+	v = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
+	v &= OMAP24XX_CORE_CLK_SRC_MASK;
+
+	if (v == CORE_CLK_SRC_32K)
+		core_clk = 32768;
+	else
+		core_clk *= v;
 
-	return dpll_clk;
+	return core_clk;
 }
 
 static int omap2_enable_osc_ck(struct clk *clk)
@@ -164,7 +177,7 @@ static long omap2_dpllcore_round_rate(unsigned long target_rate)
 
 static void omap2_dpllcore_recalc(struct clk *clk)
 {
-	clk->rate = omap2_get_dpll_rate_24xx(clk);
+	clk->rate = omap2xxx_clk_get_core_rate(clk);
 
 	propagate_rate(clk);
 }
@@ -179,7 +192,7 @@ static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
 	int ret = -EINVAL;
 
 	local_irq_save(flags);
-	cur_rate = omap2_get_dpll_rate_24xx(&dpll_ck);
+	cur_rate = omap2xxx_clk_get_core_rate(&dpll_ck);
 	mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
 	mult &= OMAP24XX_CORE_CLK_SRC_MASK;
 
@@ -319,7 +332,7 @@ static int omap2_select_table_rate(struct clk *clk, unsigned long rate)
 	}
 
 	curr_prcm_set = prcm;
-	cur_rate = omap2_get_dpll_rate_24xx(&dpll_ck);
+	cur_rate = omap2xxx_clk_get_core_rate(&dpll_ck);
 
 	if (prcm->dpll_speed == cur_rate / 2) {
 		omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
@@ -535,7 +548,7 @@ int __init omap2_clk_init(void)
 	}
 
 	/* Check the MPU rate set by bootloader */
-	clkrate = omap2_get_dpll_rate_24xx(&dpll_ck);
+	clkrate = omap2xxx_clk_get_core_rate(&dpll_ck);
 	for (prcm = rate_table; prcm->mpu_speed; prcm++) {
 		if (!(prcm->flags & cpu_mask))
 			continue;
diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h
index 724bcb0..929a257 100644
--- a/arch/arm/mach-omap2/clock24xx.h
+++ b/arch/arm/mach-omap2/clock24xx.h
@@ -673,8 +673,8 @@ static struct dpll_data dpll_dd = {
 	.mult_div1_reg		= CM_CLKSEL1,
 	.mult_mask		= OMAP24XX_DPLL_MULT_MASK,
 	.div1_mask		= OMAP24XX_DPLL_DIV_MASK,
-	.idlest_reg		= CM_IDLEST,
-	.idlest_mask		= OMAP24XX_ST_CORE_CLK_MASK,
+	.control_reg		= CM_CLKEN,
+	.enable_mask		= OMAP24XX_EN_DPLL_MASK,
 	.max_multiplier		= 1024,
 	.min_divider		= 1,
 	.max_divider		= 16,
diff --git a/arch/arm/mach-omap2/sdrc2xxx.c b/arch/arm/mach-omap2/sdrc2xxx.c
index 0723e59..479dc8c 100644
--- a/arch/arm/mach-omap2/sdrc2xxx.c
+++ b/arch/arm/mach-omap2/sdrc2xxx.c
@@ -28,6 +28,8 @@
 #include <mach/clock.h>
 #include <mach/sram.h>
 
+#include "clock.h"
+
 #include "prm.h"
 
 #include <mach/sdrc.h>
diff --git a/arch/arm/plat-omap/include/mach/clock.h b/arch/arm/plat-omap/include/mach/clock.h
index 4eef580..e793616 100644
--- a/arch/arm/plat-omap/include/mach/clock.h
+++ b/arch/arm/plat-omap/include/mach/clock.h
@@ -42,14 +42,14 @@ struct dpll_data {
 	u8			min_divider;
 	u8			max_divider;
 	u32			max_tolerance;
-	u16			idlest_reg;
-	u32			idlest_mask;
 	struct clk		*bypass_clk;
+	u16			control_reg;
+	u32			enable_mask;
 #  if defined(CONFIG_ARCH_OMAP3)
+	u16			idlest_reg;
+	u32			idlest_mask;
 	u32			freqsel_mask;
 	u8			modes;
-	u16			control_reg;
-	u32			enable_mask;
 	u8			auto_recal_bit;
 	u8			recal_en_bit;
 	u8			recal_st_bit;
@@ -175,9 +175,4 @@ extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
 #define CLK_REG_IN_PRM		(1 << 0)
 #define CLK_REG_IN_SCM		(1 << 1)
 
-/* CM_CLKSEL2_PLL.CORE_CLK_SRC options (24XX) */
-#define CORE_CLK_SRC_32K		0
-#define CORE_CLK_SRC_DPLL		1
-#define CORE_CLK_SRC_DPLL_X2		2
-
 #endif
-- 
1.6.0.3

Re: [PATCH 0/5] extra module resets to ensure full-chip idle

[Paul Walmsley]

On Sat, 29 Nov 2008, Kevin Hilman wrote:

> This series applies on top of on addtional patch which I mistakenly
> assumed was already in l-o.  Here it is.

Just FYI, there's an updated version of this patch - following shortly...

- Paul