[PATCH] OMAP3: PM: Fix the pwrdm_enable/disable_hdwr_sar funcs

[PATCH] OMAP3: PM: Fix the pwrdm_enable/disable_hdwr_sar funcs

[Rajendra Nayak]

The pwrdm_enable_hdwr_sar/pwrdm_disable_hdwr_sar do not
actually set/reset the SAVEANDRESTORE bit in the PWSTCTRL
register but modify some other bit instead.
This happens due to the OMAP3430ES2_SAVEANDRESTORE_SHIFT
being defined as (1 << 4) instead of just 4.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
---
 arch/arm/mach-omap2/prm-regbits-34xx.h |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h
index 06fee29..d4ea370 100644
--- a/arch/arm/mach-omap2/prm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-34xx.h
@@ -411,7 +411,7 @@
 /* PM_PREPWSTST_CAM specific bits */
 
 /* PM_PWSTCTRL_USBHOST specific bits */
-#define OMAP3430ES2_SAVEANDRESTORE_SHIFT		(1 << 4)
+#define OMAP3430ES2_SAVEANDRESTORE_SHIFT		4
 
 /* RM_RSTST_PER specific bits */
 
-- 
1.5.4.7

Re: [PATCH] OMAP3: PM: Fix the pwrdm_enable/disable_hdwr_sar funcs

[Kevin Hilman]

Rajendra Nayak <rnayak@ti.com> writes:

> The pwrdm_enable_hdwr_sar/pwrdm_disable_hdwr_sar do not
> actually set/reset the SAVEANDRESTORE bit in the PWSTCTRL
> register but modify some other bit instead.
> This happens due to the OMAP3430ES2_SAVEANDRESTORE_SHIFT
> being defined as (1 << 4) instead of just 4.
>
> Signed-off-by: Rajendra Nayak <rnayak@ti.com>

Thanks, pushing to PM branch.

I'll wait to hear from Kalle if we can revert his previous patch
for this.

Kevin

> ---
>  arch/arm/mach-omap2/prm-regbits-34xx.h |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h
> index 06fee29..d4ea370 100644
> --- a/arch/arm/mach-omap2/prm-regbits-34xx.h
> +++ b/arch/arm/mach-omap2/prm-regbits-34xx.h
> @@ -411,7 +411,7 @@
>  /* PM_PREPWSTST_CAM specific bits */
>  
>  /* PM_PWSTCTRL_USBHOST specific bits */
> -#define OMAP3430ES2_SAVEANDRESTORE_SHIFT		(1 << 4)
> +#define OMAP3430ES2_SAVEANDRESTORE_SHIFT		4
>  
>  /* RM_RSTST_PER specific bits */
>  
> -- 
> 1.5.4.7
>
> --
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Re: [PATCH] OMAP3: PM: Fix the pwrdm_enable/disable_hdwr_sar funcs

[Paul Walmsley]

On Fri, 5 Jun 2009, Kevin Hilman wrote:

> Rajendra Nayak <rnayak@ti.com> writes:
> 
> > The pwrdm_enable_hdwr_sar/pwrdm_disable_hdwr_sar do not
> > actually set/reset the SAVEANDRESTORE bit in the PWSTCTRL
> > register but modify some other bit instead.
> > This happens due to the OMAP3430ES2_SAVEANDRESTORE_SHIFT
> > being defined as (1 << 4) instead of just 4.
> >
> > Signed-off-by: Rajendra Nayak <rnayak@ti.com>
> 
> Thanks, pushing to PM branch.
> 
> I'll wait to hear from Kalle if we can revert his previous patch
> for this.

I think Kalle covered this one already:

http://patchwork.kernel.org/patch/15586/

- Paul

> 
> Kevin
> 
> > ---
> >  arch/arm/mach-omap2/prm-regbits-34xx.h |    2 +-
> >  1 files changed, 1 insertions(+), 1 deletions(-)
> >
> > diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h
> > index 06fee29..d4ea370 100644
> > --- a/arch/arm/mach-omap2/prm-regbits-34xx.h
> > +++ b/arch/arm/mach-omap2/prm-regbits-34xx.h
> > @@ -411,7 +411,7 @@
> >  /* PM_PREPWSTST_CAM specific bits */
> >  
> >  /* PM_PWSTCTRL_USBHOST specific bits */
> > -#define OMAP3430ES2_SAVEANDRESTORE_SHIFT		(1 << 4)
> > +#define OMAP3430ES2_SAVEANDRESTORE_SHIFT		4
> >  
> >  /* RM_RSTST_PER specific bits */
> >  
> > -- 
> > 1.5.4.7
> >
> > --
> > To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> > the body of a message to majordomo@vger.kernel.org
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> 

Re: [PATCH] OMAP3: PM: Fix the pwrdm_enable/disable_hdwr_sar funcs

[Kevin Hilman]

Paul Walmsley <paul@pwsan.com> writes:

> On Fri, 5 Jun 2009, Kevin Hilman wrote:
>
>> Rajendra Nayak <rnayak@ti.com> writes:
>> 
>> > The pwrdm_enable_hdwr_sar/pwrdm_disable_hdwr_sar do not
>> > actually set/reset the SAVEANDRESTORE bit in the PWSTCTRL
>> > register but modify some other bit instead.
>> > This happens due to the OMAP3430ES2_SAVEANDRESTORE_SHIFT
>> > being defined as (1 << 4) instead of just 4.
>> >
>> > Signed-off-by: Rajendra Nayak <rnayak@ti.com>
>> 
>> Thanks, pushing to PM branch.
>> 
>> I'll wait to hear from Kalle if we can revert his previous patch
>> for this.
>
> I think Kalle covered this one already:
>
> http://patchwork.kernel.org/patch/15586/

... but was missing from PM branch.  Remedied now.

But we also have a patch in the PM branch[1] which disables the
USBHOST SAR by removing the HAS_HDWR_SAR flag for the pwrdm.

I'm gessing/hoping that fixing this shift value allows us to
revert that patch and am hoping for some confirmation from 
Kalle.

Kevin

[1]  http://git.kernel.org/?p=linux/kernel/git/khilman/linux-omap-pm.git;a=commit;h=942fc93ce6b5ec7999f7864f6bb088cc8f308f45

VS: [PATCH] OMAP3: PM: Fix the pwrdm_enable/disable_hdwr_sar funcs

[Jokiniemi Kalle]

________________________________________
Lähettäjä: Kevin Hilman [khilman@deeprootsystems.com]
Lähetetty: 6. kesäkuuta 2009 1:53
Vastaanottaja: Paul Walmsley
Kopio: Rajendra Nayak; Jokiniemi Kalle; linux-omap@vger.kernel.org
Aihe: Re: [PATCH] OMAP3: PM: Fix the pwrdm_enable/disable_hdwr_sar funcs

Paul Walmsley <paul@pwsan.com> writes:

>> On Fri, 5 Jun 2009, Kevin Hilman wrote:
>>
>>> Rajendra Nayak <rnayak@ti.com> writes:
>>>
>>> > The pwrdm_enable_hdwr_sar/pwrdm_disable_hdwr_sar do not
>>> > actually set/reset the SAVEANDRESTORE bit in the PWSTCTRL
>>> > register but modify some other bit instead.
>>> > This happens due to the OMAP3430ES2_SAVEANDRESTORE_SHIFT
>>> > being defined as (1 << 4) instead of just 4.
>>> >
>>> > Signed-off-by: Rajendra Nayak <rnayak@ti.com>
>>>
>>> Thanks, pushing to PM branch.
>>>
>>> I'll wait to hear from Kalle if we can revert his previous patch
>>> for this.
>>
>> I think Kalle covered this one already:
>>
>> http://patchwork.kernel.org/patch/15586/
>
> ... but was missing from PM branch.  Remedied now.
>
> But we also have a patch in the PM branch[1] which disables the
> USBHOST SAR by removing the HAS_HDWR_SAR flag for the pwrdm.
>
> I'm gessing/hoping that fixing this shift value allows us to
> revert that patch and am hoping for some confirmation from
> Kalle.

The above shift fix enabled both USBHOST and USBTLL saverestores.
Unfortunately, the USBHOST saverestore seems to cause the USBHOST
power domain to hang in active state after toggling
/sys/power/enable_off_mode 0 -> 1-> 0. This was observed at least
on RX-51. Haven't tested this on other hardware though. USBTLL
saverestore works ok on ES3.1 and later devices.

I think the conclusion from discussion with Richard W. was that using
SW triggered power domain state transition for USBHOST would make
the USBHOST SAR work. The problem with just disabling USBHOST
SAR is that it leaves ES3.0 devices open for the dreaded "cold reset
issue" (as USBTLL SAR won't work on ES3.0).

We are currently using all ES3.1 devices, so there is no push to get a
better fix for this. If anyone wants to take a shot at the problem, feel
free to do so.

- Kalle

>
> Kevin
>
> [1]  http://git.kernel.org/?p=linux/kernel/git/khilman/linux-omap-pm.git;a=commit;h=942fc93ce6b5ec7999f7864f6bb088cc8f308f45
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