[RFC] OMAP3: GPIO: Enable debounce clock only when debounce is enabled

[RFC] OMAP3: GPIO: Enable debounce clock only when debounce is enabled

[Jouni Hogander]

This patch changes gpio "driver" to enable debounce clock for
gpio-bank only when debounce is enabled for some gpio in that bank.

This patch obsoletes "PM: Dynamic GPIO clock handling" patch. Nasty
side effect is that gpios in per domain aren't capable to generate
wake-up if per domain is in sleep state. Anyway keeping dbcks enabled
all the time isn't either good way to workaround this problem. For
this we need to use iopad wake-up. Currently enabling iopad wakeup
mechanism for gpio pads is left for bootloader or kernel (depending
which one does the configuration)

Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com>
---
 arch/arm/plat-omap/gpio.c |   26 +++++++++++++++++---------
 1 files changed, 17 insertions(+), 9 deletions(-)

diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index 0e74103..da164d8 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -152,6 +152,9 @@ struct gpio_bank {
 	u32 level_mask;
 	spinlock_t lock;
 	struct gpio_chip chip;
+#if defined(CONFIG_ARCH_OMAP3)
+	struct clk *dbck
+#endif
 };
 
 #define METHOD_MPUIO		0
@@ -500,11 +503,16 @@ void omap_set_gpio_debounce(int gpio, int enable)
 	reg += OMAP24XX_GPIO_DEBOUNCE_EN;
 	val = __raw_readl(reg);
 
-	if (enable)
+	if (enable && !(val & l))
 		val |= l;
-	else
+	else if (!enable && val & l)
 		val &= ~l;
+	else
+		return;
 
+#if defined(CONFIG_ARCH_OMAP3)
+	enable ? clk_enable(bank->dbck) : clk_disable(bank->dbck);
+#endif
 	__raw_writel(val, reg);
 }
 EXPORT_SYMBOL(omap_set_gpio_debounce);
@@ -1315,7 +1323,6 @@ static struct clk * gpio5_fck;
 #endif
 
 #if defined(CONFIG_ARCH_OMAP3)
-static struct clk *gpio_fclks[OMAP34XX_NR_GPIOS];
 static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
 #endif
 
@@ -1386,12 +1393,6 @@ static int __init _omap_gpio_init(void)
 				printk(KERN_ERR "Could not get %s\n", clk_name);
 			else
 				clk_enable(gpio_iclks[i]);
-			sprintf(clk_name, "gpio%d_fck", i + 1);
-			gpio_fclks[i] = clk_get(NULL, clk_name);
-			if (IS_ERR(gpio_fclks[i]))
-				printk(KERN_ERR "Could not get %s\n", clk_name);
-			else
-				clk_enable(gpio_fclks[i]);
 		}
 	}
 #endif
@@ -1531,6 +1532,13 @@ static int __init _omap_gpio_init(void)
 		}
 		set_irq_chained_handler(bank->irq, gpio_irq_handler);
 		set_irq_data(bank->irq, bank);
+
+#if defined(CONFIG_ARCH_OMAP3)
+		sprintf(clk_name, "gpio%d_fck", i + 1);
+		bank->dbck = clk_get(NULL, clk_name);
+		if (IS_ERR(bank->dbck))
+			printk(KERN_ERR "Could not get %s\n", clk_name);
+#endif
 	}
 
 	/* Enable system clock for GPIO module.
-- 
1.5.5

Re: [RFC] OMAP3: GPIO: Enable debounce clock only when debounce is enabled

[Daniel Stone]

[-- Attachment #1: Type: text/plain, Size: 1291 bytes --]

On Fri, Sep 12, 2008 at 01:51:38PM +0300, ext Jouni Hogander wrote:
> This patch changes gpio "driver" to enable debounce clock for
> gpio-bank only when debounce is enabled for some gpio in that bank.
> 
> This patch obsoletes "PM: Dynamic GPIO clock handling" patch. Nasty
> side effect is that gpios in per domain aren't capable to generate
> wake-up if per domain is in sleep state. Anyway keeping dbcks enabled
> all the time isn't either good way to workaround this problem. For
> this we need to use iopad wake-up. Currently enabling iopad wakeup
> mechanism for gpio pads is left for bootloader or kernel (depending
> which one does the configuration)
> 
> Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com>
> ---
>  arch/arm/plat-omap/gpio.c |   26 +++++++++++++++++---------
>  1 files changed, 17 insertions(+), 9 deletions(-)
> 
> diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
> index 0e74103..da164d8 100644
> --- a/arch/arm/plat-omap/gpio.c
> +++ b/arch/arm/plat-omap/gpio.c
> @@ -152,6 +152,9 @@ struct gpio_bank {
>  	u32 level_mask;
>  	spinlock_t lock;
>  	struct gpio_chip chip;
> +#if defined(CONFIG_ARCH_OMAP3)
> +	struct clk *dbck
                        ^
                        ;
> +#endif

Cheers,
Daniel

[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 197 bytes --]

Re: [RFC] OMAP3: GPIO: Enable debounce clock only when debounce is enabled

[Paul Walmsley]

Hello Jouni,

On Fri, 12 Sep 2008, Jouni Hogander wrote:

> This patch changes gpio "driver" to enable debounce clock for
> gpio-bank only when debounce is enabled for some gpio in that bank.
> 
> This patch obsoletes "PM: Dynamic GPIO clock handling" patch. Nasty
> side effect is that gpios in per domain aren't capable to generate
> wake-up if per domain is in sleep state. Anyway keeping dbcks enabled
> all the time isn't either good way to workaround this problem. For
> this we need to use iopad wake-up. Currently enabling iopad wakeup
> mechanism for gpio pads is left for bootloader or kernel (depending
> which one does the configuration)

nice resolution to this issue!  Besides Daniel's change, also it would be 
good to rename the "functional" clocks in the clock tree to indicate that 
these are debounce clocks.  Perhaps to GPIOx_DBCLK?


- Paul

[PATCH] OMAP3: GPIO: Enable debounce clock only when debounce is enabled

[Jouni Hogander]

This patch changes gpio "driver" to enable debounce clock for
gpio-bank only when debounce is enabled for some gpio in that bank.

Gpio functional clocks are also renamed in clock tree, gpioX_fck ->
gpioX_dbck.

This patch triggers problem with gpio wake-up and Omap3. Gpios in PER
domain aren't capable to generate wake-up if PER domain is in sleep
state. For this iopad wake-up should be used and needed pad
configuration should be done. Enabling iopad wake-up for gpio pads is
left for bootloader or omap mux configuration in kernel.

Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com>
---
 arch/arm/mach-omap2/clock34xx.h |   36 ++++++++++++++++++------------------
 arch/arm/plat-omap/gpio.c       |   26 +++++++++++++++++---------
 2 files changed, 35 insertions(+), 27 deletions(-)

diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index 674c204..1ba4ea9 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -2335,8 +2335,8 @@ static struct clk wkup_32k_fck = {
 	.recalc		= &followparent_recalc,
 };
 
-static struct clk gpio1_fck = {
-	.name		= "gpio1_fck",
+static struct clk gpio1_dbck = {
+	.name		= "gpio1_dbck",
 	.parent		= &wkup_32k_fck,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_GPIO1_SHIFT,
@@ -2582,8 +2582,8 @@ static struct clk per_32k_alwon_fck = {
 	.recalc		= &followparent_recalc,
 };
 
-static struct clk gpio6_fck = {
-	.name		= "gpio6_fck",
+static struct clk gpio6_dbck = {
+	.name		= "gpio6_dbck",
 	.parent		= &per_32k_alwon_fck,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_GPIO6_SHIFT,
@@ -2592,8 +2592,8 @@ static struct clk gpio6_fck = {
 	.recalc		= &followparent_recalc,
 };
 
-static struct clk gpio5_fck = {
-	.name		= "gpio5_fck",
+static struct clk gpio5_dbck = {
+	.name		= "gpio5_dbck",
 	.parent		= &per_32k_alwon_fck,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_GPIO5_SHIFT,
@@ -2602,8 +2602,8 @@ static struct clk gpio5_fck = {
 	.recalc		= &followparent_recalc,
 };
 
-static struct clk gpio4_fck = {
-	.name		= "gpio4_fck",
+static struct clk gpio4_dbck = {
+	.name		= "gpio4_dbck",
 	.parent		= &per_32k_alwon_fck,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_GPIO4_SHIFT,
@@ -2612,8 +2612,8 @@ static struct clk gpio4_fck = {
 	.recalc		= &followparent_recalc,
 };
 
-static struct clk gpio3_fck = {
-	.name		= "gpio3_fck",
+static struct clk gpio3_dbck = {
+	.name		= "gpio3_dbck",
 	.parent		= &per_32k_alwon_fck,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_GPIO3_SHIFT,
@@ -2622,8 +2622,8 @@ static struct clk gpio3_fck = {
 	.recalc		= &followparent_recalc,
 };
 
-static struct clk gpio2_fck = {
-	.name		= "gpio2_fck",
+static struct clk gpio2_dbck = {
+	.name		= "gpio2_dbck",
 	.parent		= &per_32k_alwon_fck,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_GPIO2_SHIFT,
@@ -3225,7 +3225,7 @@ static struct clk *onchip_34xx_clks[] __initdata = {
 	&usim_fck,
 	&gpt1_fck,
 	&wkup_32k_fck,
-	&gpio1_fck,
+	&gpio1_dbck,
 	&wdt2_fck,
 	&wkup_l4_ick,
 	&usim_ick,
@@ -3247,11 +3247,11 @@ static struct clk *onchip_34xx_clks[] __initdata = {
 	&gpt8_fck,
 	&gpt9_fck,
 	&per_32k_alwon_fck,
-	&gpio6_fck,
-	&gpio5_fck,
-	&gpio4_fck,
-	&gpio3_fck,
-	&gpio2_fck,
+	&gpio6_dbck,
+	&gpio5_dbck,
+	&gpio4_dbck,
+	&gpio3_dbck,
+	&gpio2_dbck,
 	&wdt3_fck,
 	&per_l4_ick,
 	&gpio6_ick,
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index ac55616..b4817b5 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -151,6 +151,9 @@ struct gpio_bank {
 	u32 level_mask;
 	spinlock_t lock;
 	struct gpio_chip chip;
+#if defined(CONFIG_ARCH_OMAP3)
+	struct clk *dbck;
+#endif
 };
 
 #define METHOD_MPUIO		0
@@ -483,11 +486,16 @@ void omap_set_gpio_debounce(int gpio, int enable)
 	reg += OMAP24XX_GPIO_DEBOUNCE_EN;
 	val = __raw_readl(reg);
 
-	if (enable)
+	if (enable && !(val & l))
 		val |= l;
-	else
+	else if (!enable && val & l)
 		val &= ~l;
+	else
+		return;
 
+#if defined(CONFIG_ARCH_OMAP3)
+	enable ? clk_enable(bank->dbck) : clk_disable(bank->dbck);
+#endif
 	__raw_writel(val, reg);
 }
 EXPORT_SYMBOL(omap_set_gpio_debounce);
@@ -1298,7 +1306,6 @@ static struct clk * gpio5_fck;
 #endif
 
 #if defined(CONFIG_ARCH_OMAP3)
-static struct clk *gpio_fclks[OMAP34XX_NR_GPIOS];
 static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
 #endif
 
@@ -1369,12 +1376,6 @@ static int __init _omap_gpio_init(void)
 				printk(KERN_ERR "Could not get %s\n", clk_name);
 			else
 				clk_enable(gpio_iclks[i]);
-			sprintf(clk_name, "gpio%d_fck", i + 1);
-			gpio_fclks[i] = clk_get(NULL, clk_name);
-			if (IS_ERR(gpio_fclks[i]))
-				printk(KERN_ERR "Could not get %s\n", clk_name);
-			else
-				clk_enable(gpio_fclks[i]);
 		}
 	}
 #endif
@@ -1513,6 +1514,13 @@ static int __init _omap_gpio_init(void)
 		}
 		set_irq_chained_handler(bank->irq, gpio_irq_handler);
 		set_irq_data(bank->irq, bank);
+
+#if defined(CONFIG_ARCH_OMAP3)
+		sprintf(clk_name, "gpio%d_dbck", i + 1);
+		bank->dbck = clk_get(NULL, clk_name);
+		if (IS_ERR(bank->dbck))
+			printk(KERN_ERR "Could not get %s\n", clk_name);
+#endif
 	}
 
 	/* Enable system clock for GPIO module.
-- 
1.5.5

Re: [PATCH] OMAP3: GPIO: Enable debounce clock only when debounce is enabled

[Kevin Hilman]

Jouni Hogander <jouni.hogander@nokia.com> writes:

> This patch changes gpio "driver" to enable debounce clock for
> gpio-bank only when debounce is enabled for some gpio in that bank.
>
> Gpio functional clocks are also renamed in clock tree, gpioX_fck ->
> gpioX_dbck.
>
> This patch triggers problem with gpio wake-up and Omap3. Gpios in PER
> domain aren't capable to generate wake-up if PER domain is in sleep
> state. For this iopad wake-up should be used and needed pad
> configuration should be done. Enabling iopad wake-up for gpio pads is
> left for bootloader or omap mux configuration in kernel.
>
> Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com>
> ---
>  arch/arm/mach-omap2/clock34xx.h |   36 ++++++++++++++++++------------------
>  arch/arm/plat-omap/gpio.c       |   26 +++++++++++++++++---------
>  2 files changed, 35 insertions(+), 27 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
> index 674c204..1ba4ea9 100644
> --- a/arch/arm/mach-omap2/clock34xx.h
> +++ b/arch/arm/mach-omap2/clock34xx.h
> @@ -2335,8 +2335,8 @@ static struct clk wkup_32k_fck = {
>  	.recalc		= &followparent_recalc,
>  };
>  
> -static struct clk gpio1_fck = {
> -	.name		= "gpio1_fck",
> +static struct clk gpio1_dbck = {
> +	.name		= "gpio1_dbck",
>  	.parent		= &wkup_32k_fck,
>  	.enable_reg	= _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
>  	.enable_bit	= OMAP3430_EN_GPIO1_SHIFT,
> @@ -2582,8 +2582,8 @@ static struct clk per_32k_alwon_fck = {
>  	.recalc		= &followparent_recalc,
>  };
>  
> -static struct clk gpio6_fck = {
> -	.name		= "gpio6_fck",
> +static struct clk gpio6_dbck = {
> +	.name		= "gpio6_dbck",
>  	.parent		= &per_32k_alwon_fck,
>  	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
>  	.enable_bit	= OMAP3430_EN_GPIO6_SHIFT,
> @@ -2592,8 +2592,8 @@ static struct clk gpio6_fck = {
>  	.recalc		= &followparent_recalc,
>  };
>  
> -static struct clk gpio5_fck = {
> -	.name		= "gpio5_fck",
> +static struct clk gpio5_dbck = {
> +	.name		= "gpio5_dbck",
>  	.parent		= &per_32k_alwon_fck,
>  	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
>  	.enable_bit	= OMAP3430_EN_GPIO5_SHIFT,
> @@ -2602,8 +2602,8 @@ static struct clk gpio5_fck = {
>  	.recalc		= &followparent_recalc,
>  };
>  
> -static struct clk gpio4_fck = {
> -	.name		= "gpio4_fck",
> +static struct clk gpio4_dbck = {
> +	.name		= "gpio4_dbck",
>  	.parent		= &per_32k_alwon_fck,
>  	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
>  	.enable_bit	= OMAP3430_EN_GPIO4_SHIFT,
> @@ -2612,8 +2612,8 @@ static struct clk gpio4_fck = {
>  	.recalc		= &followparent_recalc,
>  };
>  
> -static struct clk gpio3_fck = {
> -	.name		= "gpio3_fck",
> +static struct clk gpio3_dbck = {
> +	.name		= "gpio3_dbck",
>  	.parent		= &per_32k_alwon_fck,
>  	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
>  	.enable_bit	= OMAP3430_EN_GPIO3_SHIFT,
> @@ -2622,8 +2622,8 @@ static struct clk gpio3_fck = {
>  	.recalc		= &followparent_recalc,
>  };
>  
> -static struct clk gpio2_fck = {
> -	.name		= "gpio2_fck",
> +static struct clk gpio2_dbck = {
> +	.name		= "gpio2_dbck",
>  	.parent		= &per_32k_alwon_fck,
>  	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
>  	.enable_bit	= OMAP3430_EN_GPIO2_SHIFT,
> @@ -3225,7 +3225,7 @@ static struct clk *onchip_34xx_clks[] __initdata = {
>  	&usim_fck,
>  	&gpt1_fck,
>  	&wkup_32k_fck,
> -	&gpio1_fck,
> +	&gpio1_dbck,
>  	&wdt2_fck,
>  	&wkup_l4_ick,
>  	&usim_ick,
> @@ -3247,11 +3247,11 @@ static struct clk *onchip_34xx_clks[] __initdata = {
>  	&gpt8_fck,
>  	&gpt9_fck,
>  	&per_32k_alwon_fck,
> -	&gpio6_fck,
> -	&gpio5_fck,
> -	&gpio4_fck,
> -	&gpio3_fck,
> -	&gpio2_fck,
> +	&gpio6_dbck,
> +	&gpio5_dbck,
> +	&gpio4_dbck,
> +	&gpio3_dbck,
> +	&gpio2_dbck,
>  	&wdt3_fck,
>  	&per_l4_ick,
>  	&gpio6_ick,
> diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
> index ac55616..b4817b5 100644
> --- a/arch/arm/plat-omap/gpio.c
> +++ b/arch/arm/plat-omap/gpio.c
> @@ -151,6 +151,9 @@ struct gpio_bank {
>  	u32 level_mask;
>  	spinlock_t lock;
>  	struct gpio_chip chip;
> +#if defined(CONFIG_ARCH_OMAP3)
> +	struct clk *dbck;
> +#endif
>  };
>  
>  #define METHOD_MPUIO		0
> @@ -483,11 +486,16 @@ void omap_set_gpio_debounce(int gpio, int enable)
>  	reg += OMAP24XX_GPIO_DEBOUNCE_EN;
>  	val = __raw_readl(reg);
>  
> -	if (enable)
> +	if (enable && !(val & l))
>  		val |= l;
> -	else
> +	else if (!enable && val & l)
>  		val &= ~l;
> +	else
> +		return;
>  
> +#if defined(CONFIG_ARCH_OMAP3)
> +	enable ? clk_enable(bank->dbck) : clk_disable(bank->dbck);
> +#endif

For proper multi-omap support, you also need an 'if  cpu_is_34xx()' here

>  	__raw_writel(val, reg);
>  }
>  EXPORT_SYMBOL(omap_set_gpio_debounce);
> @@ -1298,7 +1306,6 @@ static struct clk * gpio5_fck;
>  #endif
>  
>  #if defined(CONFIG_ARCH_OMAP3)
> -static struct clk *gpio_fclks[OMAP34XX_NR_GPIOS];
>  static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
>  #endif
>  
> @@ -1369,12 +1376,6 @@ static int __init _omap_gpio_init(void)
>  				printk(KERN_ERR "Could not get %s\n", clk_name);
>  			else
>  				clk_enable(gpio_iclks[i]);
> -			sprintf(clk_name, "gpio%d_fck", i + 1);
> -			gpio_fclks[i] = clk_get(NULL, clk_name);
> -			if (IS_ERR(gpio_fclks[i]))
> -				printk(KERN_ERR "Could not get %s\n", clk_name);
> -			else
> -				clk_enable(gpio_fclks[i]);
>  		}
>  	}
>  #endif
> @@ -1513,6 +1514,13 @@ static int __init _omap_gpio_init(void)
>  		}
>  		set_irq_chained_handler(bank->irq, gpio_irq_handler);
>  		set_irq_data(bank->irq, bank);
> +
> +#if defined(CONFIG_ARCH_OMAP3)
> +		sprintf(clk_name, "gpio%d_dbck", i + 1);
> +		bank->dbck = clk_get(NULL, clk_name);
> +		if (IS_ERR(bank->dbck))
> +			printk(KERN_ERR "Could not get %s\n", clk_name);
> +#endif

And here.

Or, since this is init code and not performance critical, it may be a
bit cleaner to just get rid of the #ifdef and use the runtime
checking.

Kevin

>  	}
>  
>  	/* Enable system clock for GPIO module.
> -- 
> 1.5.5
>
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[PATCH] OMAP3: GPIO: Enable debounce clock only when debounce is enabled v2.

[Jouni Hogander]

This patch changes gpio "driver" to enable debounce clock for
gpio-bank only when debounce is enabled for some gpio in that bank.

Gpio functional clocks are also renamed in clock tree, gpioX_fck ->
gpioX_dbck.

This patch triggers problem with gpio wake-up and Omap3. Gpios in PER
domain aren't capable to generate wake-up if PER domain is in sleep
state. For this iopad wake-up should be used and needed pad
configuration should be done. Enabling iopad wake-up for gpio pads is
left for bootloader or omap mux configuration in kernel.

Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com>
---
 arch/arm/mach-omap2/clock34xx.h |   36 ++++++++++++++++++------------------
 arch/arm/plat-omap/gpio.c       |   29 ++++++++++++++++++++---------
 2 files changed, 38 insertions(+), 27 deletions(-)

diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index 41f91f8..b81b69b 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -2399,8 +2399,8 @@ static struct clk wkup_32k_fck = {
 	.recalc		= &followparent_recalc,
 };
 
-static struct clk gpio1_fck = {
-	.name		= "gpio1_fck",
+static struct clk gpio1_dbck = {
+	.name		= "gpio1_dbck",
 	.parent		= &wkup_32k_fck,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_GPIO1_SHIFT,
@@ -2643,8 +2643,8 @@ static struct clk per_32k_alwon_fck = {
 	.recalc		= &followparent_recalc,
 };
 
-static struct clk gpio6_fck = {
-	.name		= "gpio6_fck",
+static struct clk gpio6_dbck = {
+	.name		= "gpio6_dbck",
 	.parent		= &per_32k_alwon_fck,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_GPIO6_SHIFT,
@@ -2653,8 +2653,8 @@ static struct clk gpio6_fck = {
 	.recalc		= &followparent_recalc,
 };
 
-static struct clk gpio5_fck = {
-	.name		= "gpio5_fck",
+static struct clk gpio5_dbck = {
+	.name		= "gpio5_dbck",
 	.parent		= &per_32k_alwon_fck,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_GPIO5_SHIFT,
@@ -2663,8 +2663,8 @@ static struct clk gpio5_fck = {
 	.recalc		= &followparent_recalc,
 };
 
-static struct clk gpio4_fck = {
-	.name		= "gpio4_fck",
+static struct clk gpio4_dbck = {
+	.name		= "gpio4_dbck",
 	.parent		= &per_32k_alwon_fck,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_GPIO4_SHIFT,
@@ -2673,8 +2673,8 @@ static struct clk gpio4_fck = {
 	.recalc		= &followparent_recalc,
 };
 
-static struct clk gpio3_fck = {
-	.name		= "gpio3_fck",
+static struct clk gpio3_dbck = {
+	.name		= "gpio3_dbck",
 	.parent		= &per_32k_alwon_fck,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_GPIO3_SHIFT,
@@ -2683,8 +2683,8 @@ static struct clk gpio3_fck = {
 	.recalc		= &followparent_recalc,
 };
 
-static struct clk gpio2_fck = {
-	.name		= "gpio2_fck",
+static struct clk gpio2_dbck = {
+	.name		= "gpio2_dbck",
 	.parent		= &per_32k_alwon_fck,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_GPIO2_SHIFT,
@@ -3290,7 +3290,7 @@ static struct clk *onchip_34xx_clks[] __initdata = {
 	&usim_fck,
 	&gpt1_fck,
 	&wkup_32k_fck,
-	&gpio1_fck,
+	&gpio1_dbck,
 	&wdt2_fck,
 	&wkup_l4_ick,
 	&usim_ick,
@@ -3312,11 +3312,11 @@ static struct clk *onchip_34xx_clks[] __initdata = {
 	&gpt8_fck,
 	&gpt9_fck,
 	&per_32k_alwon_fck,
-	&gpio6_fck,
-	&gpio5_fck,
-	&gpio4_fck,
-	&gpio3_fck,
-	&gpio2_fck,
+	&gpio6_dbck,
+	&gpio5_dbck,
+	&gpio4_dbck,
+	&gpio3_dbck,
+	&gpio2_dbck,
 	&wdt3_fck,
 	&per_l4_ick,
 	&gpio6_ick,
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index ac55616..77a6d90 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -151,6 +151,9 @@ struct gpio_bank {
 	u32 level_mask;
 	spinlock_t lock;
 	struct gpio_chip chip;
+#if defined(CONFIG_ARCH_OMAP3)
+	struct clk *dbck;
+#endif
 };
 
 #define METHOD_MPUIO		0
@@ -483,11 +486,17 @@ void omap_set_gpio_debounce(int gpio, int enable)
 	reg += OMAP24XX_GPIO_DEBOUNCE_EN;
 	val = __raw_readl(reg);
 
-	if (enable)
+	if (enable && !(val & l))
 		val |= l;
-	else
+	else if (!enable && val & l)
 		val &= ~l;
+	else
+		return;
 
+#if defined(CONFIG_ARCH_OMAP3)
+	if (cpu_is_omap34xx())
+		enable ? clk_enable(bank->dbck) : clk_disable(bank->dbck);
+#endif
 	__raw_writel(val, reg);
 }
 EXPORT_SYMBOL(omap_set_gpio_debounce);
@@ -1298,7 +1307,6 @@ static struct clk * gpio5_fck;
 #endif
 
 #if defined(CONFIG_ARCH_OMAP3)
-static struct clk *gpio_fclks[OMAP34XX_NR_GPIOS];
 static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
 #endif
 
@@ -1369,12 +1377,6 @@ static int __init _omap_gpio_init(void)
 				printk(KERN_ERR "Could not get %s\n", clk_name);
 			else
 				clk_enable(gpio_iclks[i]);
-			sprintf(clk_name, "gpio%d_fck", i + 1);
-			gpio_fclks[i] = clk_get(NULL, clk_name);
-			if (IS_ERR(gpio_fclks[i]))
-				printk(KERN_ERR "Could not get %s\n", clk_name);
-			else
-				clk_enable(gpio_fclks[i]);
 		}
 	}
 #endif
@@ -1513,6 +1515,15 @@ static int __init _omap_gpio_init(void)
 		}
 		set_irq_chained_handler(bank->irq, gpio_irq_handler);
 		set_irq_data(bank->irq, bank);
+
+#if defined(CONFIG_ARCH_OMAP3)
+		if (cpu_is_omap34xx()) {
+			sprintf(clk_name, "gpio%d_dbck", i + 1);
+			bank->dbck = clk_get(NULL, clk_name);
+			if (IS_ERR(bank->dbck))
+				printk(KERN_ERR "Could not get %s\n", clk_name);
+		}
+#endif
 	}
 
 	/* Enable system clock for GPIO module.
-- 
1.5.5

Re: [PATCH] OMAP3: GPIO: Enable debounce clock only when debounce is enabled v2.

[Paul Walmsley]

Hi Jouni,

sorry to make you rework this again, but:

On Tue, 16 Sep 2008, Jouni Hogander wrote:

> This patch changes gpio "driver" to enable debounce clock for
> gpio-bank only when debounce is enabled for some gpio in that bank.

>  
> +#if defined(CONFIG_ARCH_OMAP3)
> +	if (cpu_is_omap34xx())
> +		enable ? clk_enable(bank->dbck) : clk_disable(bank->dbck);
> +#endif

the #ifdefs here are unnecessary, since the preprocessor will reduce 
cpu_is_omap34xx() to a constant for single-OMAP builds..

> @@ -1513,6 +1515,15 @@ static int __init _omap_gpio_init(void)
>  		}
>  		set_irq_chained_handler(bank->irq, gpio_irq_handler);
>  		set_irq_data(bank->irq, bank);
> +
> +#if defined(CONFIG_ARCH_OMAP3)
> +		if (cpu_is_omap34xx()) {
> +			sprintf(clk_name, "gpio%d_dbck", i + 1);
> +			bank->dbck = clk_get(NULL, clk_name);
> +			if (IS_ERR(bank->dbck))
> +				printk(KERN_ERR "Could not get %s\n", clk_name);
> +		}
> +#endif

as above.


- Paul

Re: [PATCH] OMAP3: GPIO: Enable debounce clock only when debounce is enabled v2.

[Högander Jouni]

"ext Paul Walmsley" <paul@pwsan.com> writes:

> Hi Jouni,
>
> sorry to make you rework this again, but:
>
> On Tue, 16 Sep 2008, Jouni Hogander wrote:
>
>> This patch changes gpio "driver" to enable debounce clock for
>> gpio-bank only when debounce is enabled for some gpio in that bank.
>
>>  
>> +#if defined(CONFIG_ARCH_OMAP3)
>> +	if (cpu_is_omap34xx())
>> +		enable ? clk_enable(bank->dbck) : clk_disable(bank->dbck);
>> +#endif
>
> the #ifdefs here are unnecessary, since the preprocessor will reduce 
> cpu_is_omap34xx() to a constant for single-OMAP builds..

NP. Maybe I can learn this multi/single OMAP thing:)

If I remove these ifdefs then I should remove also these:

#if defined(CONFIG_ARCH_OMAP3)
	struct clk *dbck;
#endif

Is that ok?

>
>> @@ -1513,6 +1515,15 @@ static int __init _omap_gpio_init(void)
>>  		}
>>  		set_irq_chained_handler(bank->irq, gpio_irq_handler);
>>  		set_irq_data(bank->irq, bank);
>> +
>> +#if defined(CONFIG_ARCH_OMAP3)
>> +		if (cpu_is_omap34xx()) {
>> +			sprintf(clk_name, "gpio%d_dbck", i + 1);
>> +			bank->dbck = clk_get(NULL, clk_name);
>> +			if (IS_ERR(bank->dbck))
>> +				printk(KERN_ERR "Could not get %s\n", clk_name);
>> +		}
>> +#endif
>
> as above.
>
>
> - Paul
>
>

-- 
Jouni Högander

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Re: [PATCH] OMAP3: GPIO: Enable debounce clock only when debounce is enabled v2.

[Paul Walmsley]

[-- Attachment #1: Type: TEXT/PLAIN, Size: 278 bytes --]

Hello Jouni, 

On Tue, 16 Sep 2008, Högander Jouni wrote:

> If I remove these ifdefs then I should remove also these:
> 
> #if defined(CONFIG_ARCH_OMAP3)
> 	struct clk *dbck;
> #endif

Missed that one.  Yes, it looks fine to me to remove the ifdefs there.


- Paul

[PATCH] OMAP3: GPIO: Enable debounce clock only when debounce is enabled v3.

[Jouni Hogander]

This patch changes gpio "driver" to enable debounce clock for
gpio-bank only when debounce is enabled for some gpio in that bank.

Gpio functional clocks are also renamed in clock tree, gpioX_fck ->
gpioX_dbck.

This patch triggers problem with gpio wake-up and Omap3. Gpios in PER
domain aren't capable to generate wake-up if PER domain is in sleep
state. For this iopad wake-up should be used and needed pad
configuration should be done. Enabling iopad wake-up for gpio pads is
left for bootloader or omap mux configuration in kernel.

Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com>
---
 arch/arm/mach-omap2/clock34xx.h |   36 ++++++++++++++++++------------------
 arch/arm/plat-omap/gpio.c       |   26 +++++++++++++++-----------
 2 files changed, 33 insertions(+), 29 deletions(-)

diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index 41f91f8..b81b69b 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -2399,8 +2399,8 @@ static struct clk wkup_32k_fck = {
 	.recalc		= &followparent_recalc,
 };
 
-static struct clk gpio1_fck = {
-	.name		= "gpio1_fck",
+static struct clk gpio1_dbck = {
+	.name		= "gpio1_dbck",
 	.parent		= &wkup_32k_fck,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_GPIO1_SHIFT,
@@ -2643,8 +2643,8 @@ static struct clk per_32k_alwon_fck = {
 	.recalc		= &followparent_recalc,
 };
 
-static struct clk gpio6_fck = {
-	.name		= "gpio6_fck",
+static struct clk gpio6_dbck = {
+	.name		= "gpio6_dbck",
 	.parent		= &per_32k_alwon_fck,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_GPIO6_SHIFT,
@@ -2653,8 +2653,8 @@ static struct clk gpio6_fck = {
 	.recalc		= &followparent_recalc,
 };
 
-static struct clk gpio5_fck = {
-	.name		= "gpio5_fck",
+static struct clk gpio5_dbck = {
+	.name		= "gpio5_dbck",
 	.parent		= &per_32k_alwon_fck,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_GPIO5_SHIFT,
@@ -2663,8 +2663,8 @@ static struct clk gpio5_fck = {
 	.recalc		= &followparent_recalc,
 };
 
-static struct clk gpio4_fck = {
-	.name		= "gpio4_fck",
+static struct clk gpio4_dbck = {
+	.name		= "gpio4_dbck",
 	.parent		= &per_32k_alwon_fck,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_GPIO4_SHIFT,
@@ -2673,8 +2673,8 @@ static struct clk gpio4_fck = {
 	.recalc		= &followparent_recalc,
 };
 
-static struct clk gpio3_fck = {
-	.name		= "gpio3_fck",
+static struct clk gpio3_dbck = {
+	.name		= "gpio3_dbck",
 	.parent		= &per_32k_alwon_fck,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_GPIO3_SHIFT,
@@ -2683,8 +2683,8 @@ static struct clk gpio3_fck = {
 	.recalc		= &followparent_recalc,
 };
 
-static struct clk gpio2_fck = {
-	.name		= "gpio2_fck",
+static struct clk gpio2_dbck = {
+	.name		= "gpio2_dbck",
 	.parent		= &per_32k_alwon_fck,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_GPIO2_SHIFT,
@@ -3290,7 +3290,7 @@ static struct clk *onchip_34xx_clks[] __initdata = {
 	&usim_fck,
 	&gpt1_fck,
 	&wkup_32k_fck,
-	&gpio1_fck,
+	&gpio1_dbck,
 	&wdt2_fck,
 	&wkup_l4_ick,
 	&usim_ick,
@@ -3312,11 +3312,11 @@ static struct clk *onchip_34xx_clks[] __initdata = {
 	&gpt8_fck,
 	&gpt9_fck,
 	&per_32k_alwon_fck,
-	&gpio6_fck,
-	&gpio5_fck,
-	&gpio4_fck,
-	&gpio3_fck,
-	&gpio2_fck,
+	&gpio6_dbck,
+	&gpio5_dbck,
+	&gpio4_dbck,
+	&gpio3_dbck,
+	&gpio2_dbck,
 	&wdt3_fck,
 	&per_l4_ick,
 	&gpio6_ick,
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index ac55616..2d63023 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -151,6 +151,7 @@ struct gpio_bank {
 	u32 level_mask;
 	spinlock_t lock;
 	struct gpio_chip chip;
+	struct clk *dbck;
 };
 
 #define METHOD_MPUIO		0
@@ -483,10 +484,15 @@ void omap_set_gpio_debounce(int gpio, int enable)
 	reg += OMAP24XX_GPIO_DEBOUNCE_EN;
 	val = __raw_readl(reg);
 
-	if (enable)
+	if (enable && !(val & l))
 		val |= l;
-	else
+	else if (!enable && val & l)
 		val &= ~l;
+	else
+		return;
+
+	if (cpu_is_omap34xx())
+		enable ? clk_enable(bank->dbck) : clk_disable(bank->dbck);
 
 	__raw_writel(val, reg);
 }
@@ -1298,7 +1304,6 @@ static struct clk * gpio5_fck;
 #endif
 
 #if defined(CONFIG_ARCH_OMAP3)
-static struct clk *gpio_fclks[OMAP34XX_NR_GPIOS];
 static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
 #endif
 
@@ -1312,9 +1317,7 @@ static int __init _omap_gpio_init(void)
 	int i;
 	int gpio = 0;
 	struct gpio_bank *bank;
-#if defined(CONFIG_ARCH_OMAP3)
 	char clk_name[11];
-#endif
 
 	initialized = 1;
 
@@ -1369,12 +1372,6 @@ static int __init _omap_gpio_init(void)
 				printk(KERN_ERR "Could not get %s\n", clk_name);
 			else
 				clk_enable(gpio_iclks[i]);
-			sprintf(clk_name, "gpio%d_fck", i + 1);
-			gpio_fclks[i] = clk_get(NULL, clk_name);
-			if (IS_ERR(gpio_fclks[i]))
-				printk(KERN_ERR "Could not get %s\n", clk_name);
-			else
-				clk_enable(gpio_fclks[i]);
 		}
 	}
 #endif
@@ -1513,6 +1510,13 @@ static int __init _omap_gpio_init(void)
 		}
 		set_irq_chained_handler(bank->irq, gpio_irq_handler);
 		set_irq_data(bank->irq, bank);
+
+		if (cpu_is_omap34xx()) {
+			sprintf(clk_name, "gpio%d_dbck", i + 1);
+			bank->dbck = clk_get(NULL, clk_name);
+			if (IS_ERR(bank->dbck))
+				printk(KERN_ERR "Could not get %s\n", clk_name);
+		}
 	}
 
 	/* Enable system clock for GPIO module.
-- 
1.5.5

Re: [PATCH] OMAP3: GPIO: Enable debounce clock only when debounce is enabled v3.

[Paul Walmsley]

On Tue, 16 Sep 2008, Jouni Hogander wrote:

> This patch changes gpio "driver" to enable debounce clock for
> gpio-bank only when debounce is enabled for some gpio in that bank.
> 
> Gpio functional clocks are also renamed in clock tree, gpioX_fck ->
> gpioX_dbck.
> 
> This patch triggers problem with gpio wake-up and Omap3. Gpios in PER
> domain aren't capable to generate wake-up if PER domain is in sleep
> state. For this iopad wake-up should be used and needed pad
> configuration should be done. Enabling iopad wake-up for gpio pads is
> left for bootloader or omap mux configuration in kernel.
> 
> Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com>

Acked-by: Paul Walmsley <paul@pwsan.com>


- Paul

Re: [PATCH] OMAP3: GPIO: Enable debounce clock only when debounce is enabled v3.

[Tony Lindgren]

* Paul Walmsley <paul@booyaka.com> [080916 16:02]:
> On Tue, 16 Sep 2008, Jouni Hogander wrote:
> 
> > This patch changes gpio "driver" to enable debounce clock for
> > gpio-bank only when debounce is enabled for some gpio in that bank.
> > 
> > Gpio functional clocks are also renamed in clock tree, gpioX_fck ->
> > gpioX_dbck.
> > 
> > This patch triggers problem with gpio wake-up and Omap3. Gpios in PER
> > domain aren't capable to generate wake-up if PER domain is in sleep
> > state. For this iopad wake-up should be used and needed pad
> > configuration should be done. Enabling iopad wake-up for gpio pads is
> > left for bootloader or omap mux configuration in kernel.
> > 
> > Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com>
> 
> Acked-by: Paul Walmsley <paul@pwsan.com>

Pushing today.

Tony