* [PATCH v2 11/18] GPIO: OMAP: Clean set_gpio_triggering function
2011-06-15 4:23 [PATCH v2 10/18] GPIO: OMAP: Remove hardcoded offsets in ctxt save/restore Tarun Kanti DebBarma
@ 2011-06-15 4:23 ` Tarun Kanti DebBarma
2011-06-16 17:40 ` Kevin Hilman
2011-06-15 4:23 ` [PATCH v2 12/18] GPIO: OMAP: Clean omap_gpio_mod_init function Tarun Kanti DebBarma
` (6 subsequent siblings)
7 siblings, 1 reply; 23+ messages in thread
From: Tarun Kanti DebBarma @ 2011-06-15 4:23 UTC (permalink / raw)
To: linux-omap; +Cc: khilman, santosh.shilimkar, tony
From: Charulatha V <charu@ti.com>
Getting rid of ifdefs within the function by adding register offset intctrl
and associating OMAPXXXX_GPIO_INT_CONTROL in respective SoC specific files.
Signed-off-by: Charulatha V <charu@ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
---
arch/arm/mach-omap1/gpio15xx.c | 2 +
arch/arm/mach-omap1/gpio16xx.c | 3 +
arch/arm/mach-omap1/gpio7xx.c | 2 +
arch/arm/mach-omap2/gpio.c | 4 +
arch/arm/plat-omap/include/plat/gpio.h | 3 +
drivers/gpio/gpio-omap.c | 124 +++++++++-----------------------
6 files changed, 47 insertions(+), 91 deletions(-)
diff --git a/arch/arm/mach-omap1/gpio15xx.c b/arch/arm/mach-omap1/gpio15xx.c
index e8a3bd9..fd2fe8f 100644
--- a/arch/arm/mach-omap1/gpio15xx.c
+++ b/arch/arm/mach-omap1/gpio15xx.c
@@ -42,6 +42,7 @@ static struct omap_gpio_reg_offs omap15xx_mpuio_regs = {
.irqstatus = OMAP_MPUIO_GPIO_INT,
.irqenable = OMAP_MPUIO_GPIO_MASKIT,
.irqenable_inv = true,
+ .irqctrl = OMAP_MPUIO_GPIO_INT_EDGE,
};
static struct __initdata omap_gpio_platform_data omap15xx_mpu_gpio_config = {
@@ -83,6 +84,7 @@ static struct omap_gpio_reg_offs omap15xx_gpio_regs = {
.irqstatus = OMAP1510_GPIO_INT_STATUS,
.irqenable = OMAP1510_GPIO_INT_MASK,
.irqenable_inv = true,
+ .irqctrl = OMAP1510_GPIO_INT_CONTROL,
};
static struct __initdata omap_gpio_platform_data omap15xx_gpio_config = {
diff --git a/arch/arm/mach-omap1/gpio16xx.c b/arch/arm/mach-omap1/gpio16xx.c
index d1da7c8..4677ea5 100644
--- a/arch/arm/mach-omap1/gpio16xx.c
+++ b/arch/arm/mach-omap1/gpio16xx.c
@@ -45,6 +45,7 @@ static struct omap_gpio_reg_offs omap16xx_mpuio_regs = {
.irqstatus = OMAP_MPUIO_GPIO_INT,
.irqenable = OMAP_MPUIO_GPIO_MASKIT,
.irqenable_inv = true,
+ .irqctrl = OMAP_MPUIO_GPIO_INT_EDGE,
};
static struct __initdata omap_gpio_platform_data omap16xx_mpu_gpio_config = {
@@ -93,6 +94,8 @@ static struct omap_gpio_reg_offs omap16xx_gpio_regs = {
.wkup_status = OMAP1610_GPIO_WAKEUPENABLE,
.wkup_clear = OMAP1610_GPIO_CLEAR_WAKEUPENA,
.wkup_set = OMAP1610_GPIO_SET_WAKEUPENA,
+ .edgectrl1 = OMAP1610_GPIO_EDGE_CTRL1,
+ .edgectrl2 = OMAP1610_GPIO_EDGE_CTRL2,
};
static struct __initdata omap_gpio_platform_data omap16xx_gpio1_config = {
diff --git a/arch/arm/mach-omap1/gpio7xx.c b/arch/arm/mach-omap1/gpio7xx.c
index f5d5572..6e439ff 100644
--- a/arch/arm/mach-omap1/gpio7xx.c
+++ b/arch/arm/mach-omap1/gpio7xx.c
@@ -47,6 +47,7 @@ static struct omap_gpio_reg_offs omap7xx_mpuio_regs = {
.irqstatus = OMAP_MPUIO_GPIO_INT / 2,
.irqenable = OMAP_MPUIO_GPIO_MASKIT / 2,
.irqenable_inv = true,
+ .irqctrl = OMAP_MPUIO_GPIO_INT_EDGE / 2,
};
static struct __initdata omap_gpio_platform_data omap7xx_mpu_gpio_config = {
@@ -88,6 +89,7 @@ static struct omap_gpio_reg_offs omap7xx_gpio_regs = {
.irqstatus = OMAP7XX_GPIO_INT_STATUS,
.irqenable = OMAP7XX_GPIO_INT_MASK,
.irqenable_inv = true,
+ .irqctrl = OMAP7XX_GPIO_INT_CONTROL,
};
static struct __initdata omap_gpio_platform_data omap7xx_gpio1_config = {
diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c
index 0a8f637..3c96855 100644
--- a/arch/arm/mach-omap2/gpio.c
+++ b/arch/arm/mach-omap2/gpio.c
@@ -83,6 +83,10 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
return -ENOMEM;
}
+ pdata->regs->irqctrl = USHRT_MAX;
+ pdata->regs->edgectrl1 = USHRT_MAX;
+ pdata->regs->edgectrl2 = USHRT_MAX;
+
switch (oh->class->rev) {
case 0:
if (id == 1)
diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h
index 32b862a..c0a92ea 100644
--- a/arch/arm/plat-omap/include/plat/gpio.h
+++ b/arch/arm/plat-omap/include/plat/gpio.h
@@ -197,6 +197,9 @@ struct omap_gpio_reg_offs {
u16 leveldetect1;
u16 risingdetect;
u16 fallingdetect;
+ u16 irqctrl;
+ u16 edgectrl1;
+ u16 edgectrl2;
bool irqenable_inv;
};
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 1551017..7609ce4 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -196,35 +196,24 @@ static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
__raw_writel(val, reg);
}
-#ifdef CONFIG_ARCH_OMAP2PLUS
-static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
+static inline void set_gpio_trigger(struct gpio_bank *bank, int gpio,
int trigger)
{
void __iomem *base = bank->base;
u32 gpio_bit = 1 << gpio;
- if (cpu_is_omap44xx()) {
- MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit,
- trigger & IRQ_TYPE_LEVEL_LOW);
- MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit,
- trigger & IRQ_TYPE_LEVEL_HIGH);
- MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit,
- trigger & IRQ_TYPE_EDGE_RISING);
- MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit,
- trigger & IRQ_TYPE_EDGE_FALLING);
- } else {
- MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
+ MOD_REG_BIT(bank->regs->leveldetect0, gpio_bit,
trigger & IRQ_TYPE_LEVEL_LOW);
- MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
+ MOD_REG_BIT(bank->regs->leveldetect1, gpio_bit,
trigger & IRQ_TYPE_LEVEL_HIGH);
- MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
+ MOD_REG_BIT(bank->regs->risingdetect, gpio_bit,
trigger & IRQ_TYPE_EDGE_RISING);
- MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
+ MOD_REG_BIT(bank->regs->fallingdetect, gpio_bit,
trigger & IRQ_TYPE_EDGE_FALLING);
- }
+
if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
if (cpu_is_omap44xx()) {
- MOD_REG_BIT(OMAP4_GPIO_IRQWAKEN0, gpio_bit,
+ MOD_REG_BIT(bank->regs->wkup_status, gpio_bit,
trigger != 0);
} else {
/*
@@ -233,10 +222,10 @@ static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
*/
if (trigger & IRQ_TYPE_EDGE_BOTH)
__raw_writel(1 << gpio, bank->base
- + OMAP24XX_GPIO_SETWKUENA);
+ + bank->regs->wkup_set);
else
__raw_writel(1 << gpio, bank->base
- + OMAP24XX_GPIO_CLEARWKUENA);
+ + bank->regs->wkup_clear);
}
}
/* This part needs to be executed always for OMAP34xx */
@@ -257,7 +246,6 @@ static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
__raw_readl(bank->base + bank->regs->leveldetect0) |
__raw_readl(bank->base + bank->regs->leveldetect1);
}
-#endif
#ifdef CONFIG_ARCH_OMAP1
/*
@@ -269,23 +257,10 @@ static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
void __iomem *reg = bank->base;
u32 l = 0;
- switch (bank->method) {
- case METHOD_MPUIO:
- reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
- break;
-#ifdef CONFIG_ARCH_OMAP15XX
- case METHOD_GPIO_1510:
- reg += OMAP1510_GPIO_INT_CONTROL;
- break;
-#endif
-#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
- case METHOD_GPIO_7XX:
- reg += OMAP7XX_GPIO_INT_CONTROL;
- break;
-#endif
- default:
+ if (!bank->regs->irqctrl)
return;
- }
+
+ reg += bank->regs->irqctrl;
l = __raw_readl(reg);
if ((l >> gpio) & 1)
@@ -302,24 +277,11 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
void __iomem *reg = bank->base;
u32 l = 0;
- switch (bank->method) {
-#ifdef CONFIG_ARCH_OMAP1
- case METHOD_MPUIO:
- reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
- l = __raw_readl(reg);
- if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
- bank->toggle_mask |= 1 << gpio;
- if (trigger & IRQ_TYPE_EDGE_RISING)
- l |= 1 << gpio;
- else if (trigger & IRQ_TYPE_EDGE_FALLING)
- l &= ~(1 << gpio);
- else
- goto bad;
- break;
-#endif
-#ifdef CONFIG_ARCH_OMAP15XX
- case METHOD_GPIO_1510:
- reg += OMAP1510_GPIO_INT_CONTROL;
+ if (bank->regs->leveldetect0 && bank->regs->wkup_status) {
+ set_gpio_trigger(bank, gpio, trigger);
+ } else if (bank->regs->irqctrl) {
+ reg += bank->regs->irqctrl;
+
l = __raw_readl(reg);
if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
bank->toggle_mask |= 1 << gpio;
@@ -328,15 +290,16 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
else if (trigger & IRQ_TYPE_EDGE_FALLING)
l &= ~(1 << gpio);
else
- goto bad;
- break;
-#endif
-#ifdef CONFIG_ARCH_OMAP16XX
- case METHOD_GPIO_1610:
+ return -EINVAL;
+
+ __raw_writel(l, reg);
+
+ } else if (bank->regs->edgectrl1) {
if (gpio & 0x08)
- reg += OMAP1610_GPIO_EDGE_CTRL2;
+ reg += bank->regs->edgectrl2;
else
- reg += OMAP1610_GPIO_EDGE_CTRL1;
+ reg += bank->regs->edgectrl1;
+
gpio &= 0x07;
l = __raw_readl(reg);
l &= ~(3 << (gpio << 1));
@@ -344,40 +307,19 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
l |= 2 << (gpio << 1);
if (trigger & IRQ_TYPE_EDGE_FALLING)
l |= 1 << (gpio << 1);
+
if (trigger)
/* Enable wake-up during idle for dynamic tick */
- __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
+ __raw_writel(1 << gpio, bank->base
+ + bank->regs->wkup_set);
else
- __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
- break;
-#endif
-#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
- case METHOD_GPIO_7XX:
- reg += OMAP7XX_GPIO_INT_CONTROL;
- l = __raw_readl(reg);
- if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
- bank->toggle_mask |= 1 << gpio;
- if (trigger & IRQ_TYPE_EDGE_RISING)
- l |= 1 << gpio;
- else if (trigger & IRQ_TYPE_EDGE_FALLING)
- l &= ~(1 << gpio);
- else
- goto bad;
- break;
-#endif
-#ifdef CONFIG_ARCH_OMAP2PLUS
- case METHOD_GPIO_24XX:
- case METHOD_GPIO_44XX:
- set_24xx_gpio_triggering(bank, gpio, trigger);
- return 0;
-#endif
- default:
- goto bad;
+ __raw_writel(1 << gpio, bank->base
+ + bank->regs->wkup_clear);
+
+ __raw_writel(l, reg);
}
- __raw_writel(l, reg);
+
return 0;
-bad:
- return -EINVAL;
}
static int gpio_irq_type(struct irq_data *d, unsigned type)
--
1.6.0.4
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [PATCH v2 11/18] GPIO: OMAP: Clean set_gpio_triggering function
2011-06-15 4:23 ` [PATCH v2 11/18] GPIO: OMAP: Clean set_gpio_triggering function Tarun Kanti DebBarma
@ 2011-06-16 17:40 ` Kevin Hilman
2011-06-17 5:16 ` DebBarma, Tarun Kanti
0 siblings, 1 reply; 23+ messages in thread
From: Kevin Hilman @ 2011-06-16 17:40 UTC (permalink / raw)
To: Tarun Kanti DebBarma; +Cc: linux-omap, santosh.shilimkar, tony
Tarun Kanti DebBarma <tarun.kanti@ti.com> writes:
> From: Charulatha V <charu@ti.com>
>
> Getting rid of ifdefs within the function by adding register offset intctrl
> and associating OMAPXXXX_GPIO_INT_CONTROL in respective SoC specific files.
>
> Signed-off-by: Charulatha V <charu@ti.com>
> Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
[...]
> diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c
> index 0a8f637..3c96855 100644
> --- a/arch/arm/mach-omap2/gpio.c
> +++ b/arch/arm/mach-omap2/gpio.c
> @@ -83,6 +83,10 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
> return -ENOMEM;
> }
>
> + pdata->regs->irqctrl = USHRT_MAX;
> + pdata->regs->edgectrl1 = USHRT_MAX;
> + pdata->regs->edgectrl2 = USHRT_MAX;
As with all the other undefined values, please use zero.
The driver check is checking for non-zero values which would be true
with USHRT_MAX. You don't happen to see this because of the OMAP1 #ifdef.
[...]
> if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
> if (cpu_is_omap44xx()) {
> - MOD_REG_BIT(OMAP4_GPIO_IRQWAKEN0, gpio_bit,
> + MOD_REG_BIT(bank->regs->wkup_status, gpio_bit,
> trigger != 0);
> } else {
> /*
> @@ -233,10 +222,10 @@ static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
> */
> if (trigger & IRQ_TYPE_EDGE_BOTH)
> __raw_writel(1 << gpio, bank->base
> - + OMAP24XX_GPIO_SETWKUENA);
> + + bank->regs->wkup_set);
> else
> __raw_writel(1 << gpio, bank->base
> - + OMAP24XX_GPIO_CLEARWKUENA);
> + + bank->regs->wkup_clear);
> }
Probably should be done in an additional patch, but the cpu_is_44xx()
above could be removed too.
The 44xx TRM recommends using the wkup_status only (not using set/clear
registers) and the same could be done for the other SoCs.
Kevin
^ permalink raw reply [flat|nested] 23+ messages in thread* RE: [PATCH v2 11/18] GPIO: OMAP: Clean set_gpio_triggering function
2011-06-16 17:40 ` Kevin Hilman
@ 2011-06-17 5:16 ` DebBarma, Tarun Kanti
0 siblings, 0 replies; 23+ messages in thread
From: DebBarma, Tarun Kanti @ 2011-06-17 5:16 UTC (permalink / raw)
To: Hilman, Kevin
Cc: linux-omap@vger.kernel.org, Shilimkar, Santosh, tony@atomide.com
> -----Original Message-----
> From: Hilman, Kevin
> Sent: Thursday, June 16, 2011 11:11 PM
> To: DebBarma, Tarun Kanti
> Cc: linux-omap@vger.kernel.org; Shilimkar, Santosh; tony@atomide.com
> Subject: Re: [PATCH v2 11/18] GPIO: OMAP: Clean set_gpio_triggering
> function
>
> Tarun Kanti DebBarma <tarun.kanti@ti.com> writes:
>
> > From: Charulatha V <charu@ti.com>
> >
> > Getting rid of ifdefs within the function by adding register offset
> intctrl
> > and associating OMAPXXXX_GPIO_INT_CONTROL in respective SoC specific
> files.
> >
> > Signed-off-by: Charulatha V <charu@ti.com>
> > Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
>
> [...]
>
> > diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c
> > index 0a8f637..3c96855 100644
> > --- a/arch/arm/mach-omap2/gpio.c
> > +++ b/arch/arm/mach-omap2/gpio.c
> > @@ -83,6 +83,10 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh,
> void *unused)
> > return -ENOMEM;
> > }
> >
> > + pdata->regs->irqctrl = USHRT_MAX;
> > + pdata->regs->edgectrl1 = USHRT_MAX;
> > + pdata->regs->edgectrl2 = USHRT_MAX;
>
> As with all the other undefined values, please use zero.
Yes.
>
> The driver check is checking for non-zero values which would be true
> with USHRT_MAX. You don't happen to see this because of the OMAP1 #ifdef.
Ok, I will change.
>
> [...]
>
> > if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
> > if (cpu_is_omap44xx()) {
> > - MOD_REG_BIT(OMAP4_GPIO_IRQWAKEN0, gpio_bit,
> > + MOD_REG_BIT(bank->regs->wkup_status, gpio_bit,
> > trigger != 0);
> > } else {
> > /*
> > @@ -233,10 +222,10 @@ static inline void set_24xx_gpio_triggering(struct
> gpio_bank *bank, int gpio,
> > */
> > if (trigger & IRQ_TYPE_EDGE_BOTH)
> > __raw_writel(1 << gpio, bank->base
> > - + OMAP24XX_GPIO_SETWKUENA);
> > + + bank->regs->wkup_set);
> > else
> > __raw_writel(1 << gpio, bank->base
> > - + OMAP24XX_GPIO_CLEARWKUENA);
> > + + bank->regs->wkup_clear);
> > }
>
> Probably should be done in an additional patch, but the cpu_is_44xx()
> above could be removed too.
>
> The 44xx TRM recommends using the wkup_status only (not using set/clear
> registers) and the same could be done for the other SoCs.
Ok, I will change for other SoC's as well.
--
Tarun
>
> Kevin
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 12/18] GPIO: OMAP: Clean omap_gpio_mod_init function
2011-06-15 4:23 [PATCH v2 10/18] GPIO: OMAP: Remove hardcoded offsets in ctxt save/restore Tarun Kanti DebBarma
2011-06-15 4:23 ` [PATCH v2 11/18] GPIO: OMAP: Clean set_gpio_triggering function Tarun Kanti DebBarma
@ 2011-06-15 4:23 ` Tarun Kanti DebBarma
2011-06-16 17:49 ` Kevin Hilman
2011-06-15 4:23 ` [PATCH v2 13/18] GPIO: OMAP15xx: Use pinctrl offset instead of macro Tarun Kanti DebBarma
` (5 subsequent siblings)
7 siblings, 1 reply; 23+ messages in thread
From: Tarun Kanti DebBarma @ 2011-06-15 4:23 UTC (permalink / raw)
To: linux-omap; +Cc: khilman, santosh.shilimkar, tony
From: Charulatha V <charu@ti.com>
With register offsets now defined for respective OMAP versions we can get rid
of cpu_class_* checks. In addition, organized common initialization for the
different OMAP silicon versions.
Signed-off-by: Charulatha V <charu@ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
---
arch/arm/mach-omap1/gpio16xx.c | 1 +
arch/arm/plat-omap/include/plat/gpio.h | 2 +
drivers/gpio/gpio-omap.c | 121 +++++++++++++++++++++-----------
3 files changed, 84 insertions(+), 40 deletions(-)
diff --git a/arch/arm/mach-omap1/gpio16xx.c b/arch/arm/mach-omap1/gpio16xx.c
index 4677ea5..efd9275 100644
--- a/arch/arm/mach-omap1/gpio16xx.c
+++ b/arch/arm/mach-omap1/gpio16xx.c
@@ -96,6 +96,7 @@ static struct omap_gpio_reg_offs omap16xx_gpio_regs = {
.wkup_set = OMAP1610_GPIO_SET_WAKEUPENA,
.edgectrl1 = OMAP1610_GPIO_EDGE_CTRL1,
.edgectrl2 = OMAP1610_GPIO_EDGE_CTRL2,
+ .sysconfig = OMAP1610_GPIO_SYSCONFIG,
};
static struct __initdata omap_gpio_platform_data omap16xx_gpio1_config = {
diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h
index c0a92ea..30db400 100644
--- a/arch/arm/plat-omap/include/plat/gpio.h
+++ b/arch/arm/plat-omap/include/plat/gpio.h
@@ -200,6 +200,8 @@ struct omap_gpio_reg_offs {
u16 irqctrl;
u16 edgectrl1;
u16 edgectrl2;
+ /* Not applicable for OMAP2+ as hwmod layer takes care of sysconfig */
+ u16 sysconfig;
bool irqenable_inv;
};
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 53f2ea6..89d1ea5 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -887,47 +887,94 @@ static void __init omap_gpio_show_rev(struct gpio_bank *bank)
*/
static struct lock_class_key gpio_lock_class;
-/* TODO: Cleanup cpu_is_* checks */
static void omap_gpio_mod_init(struct gpio_bank *bank)
{
- if (cpu_class_is_omap2()) {
- if (cpu_is_omap44xx()) {
- __raw_writel(0xffffffff, bank->base +
- OMAP4_GPIO_IRQSTATUSCLR0);
- __raw_writel(0x00000000, bank->base +
- OMAP4_GPIO_DEBOUNCENABLE);
- /* Initialize interface clk ungated, module enabled */
- __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
- } else if (cpu_is_omap34xx()) {
- __raw_writel(0x00000000, bank->base +
- OMAP24XX_GPIO_IRQENABLE1);
- __raw_writel(0xffffffff, bank->base +
- OMAP24XX_GPIO_IRQSTATUS1);
- __raw_writel(0x00000000, bank->base +
- OMAP24XX_GPIO_DEBOUNCE_EN);
+ if (bank->width == 32) {
+ u32 clr_all = 0; /* clear all the bits */
+ u32 set_all = 0xFFFFFFFF; /* set all the bits */
+
+ if (bank_is_mpuio(bank)) {
+ __raw_writel(set_all, bank->base +
+ bank->regs->irqenable);
+
+ if (bank->suspend_support)
+ mpuio_init(bank);
+ return;
+ }
+
+ if (bank->regs->ctrl)
/* Initialize interface clk ungated, module enabled */
- __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
+ __raw_writel(clr_all, bank->base + bank->regs->ctrl);
+
+ if (bank->regs->clr_irqenable) {
+ __raw_writel(set_all, bank->base +
+ bank->regs->clr_irqenable);
+ } else if (bank->regs->irqenable) {
+ u32 i;
+
+ if (bank->regs->irqenable_inv)
+ i = set_all;
+ else
+ i = clr_all;
+
+ __raw_writel(i, bank->base + bank->regs->irqenable);
}
- } else if (cpu_class_is_omap1()) {
- if (bank_is_mpuio(bank) && bank->suspend_support) {
- __raw_writew(0xffff, bank->base +
- OMAP_MPUIO_GPIO_MASKIT / bank->stride);
- mpuio_init(bank);
+
+ if (bank->regs->irqstatus) {
+ u32 i;
+
+ if (bank->regs->irqenable_inv)
+ i = clr_all;
+ else
+ i = set_all;
+
+ __raw_writel(i, bank->base + bank->regs->irqstatus);
}
- if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
- __raw_writew(0xffff, bank->base
- + OMAP1510_GPIO_INT_MASK);
- __raw_writew(0x0000, bank->base
- + OMAP1510_GPIO_INT_STATUS);
+
+ if (bank->regs->debounce_en)
+ __raw_writel(clr_all, bank->base +
+ bank->regs->debounce_en);
+
+ } else if (bank->width == 16) {
+ u16 clr_all = 0; /* clear all the bits */
+ u16 set_all = 0xFFFF; /* set all the bits */
+
+ if (bank_is_mpuio(bank)) {
+ __raw_writew(set_all, bank->base +
+ bank->regs->irqenable);
+
+ if (bank->suspend_support)
+ mpuio_init(bank);
+
+ return;
}
- if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
- __raw_writew(0x0000, bank->base
- + OMAP1610_GPIO_IRQENABLE1);
- __raw_writew(0xffff, bank->base
- + OMAP1610_GPIO_IRQSTATUS1);
- __raw_writew(0x0014, bank->base
- + OMAP1610_GPIO_SYSCONFIG);
+
+ if (bank->regs->irqenable) {
+ u16 i;
+
+ if (bank->regs->irqenable_inv)
+ i = set_all;
+ else
+ i = clr_all;
+
+ __raw_writew(i, bank->base + bank->regs->irqenable);
+ }
+
+ if (bank->regs->irqstatus) {
+ u32 i;
+
+ if (bank->regs->irqenable_inv)
+ i = clr_all;
+ else
+ i = set_all;
+
+ __raw_writew(i, bank->base + bank->regs->irqstatus);
+ }
+
+ if (bank->regs->sysconfig) {
+ /* set wakeup-enable and smart-idle */
+ __raw_writew(0x14, bank->base + bank->regs->sysconfig);
/*
* Enable system clock for GPIO module.
@@ -936,12 +983,6 @@ static void omap_gpio_mod_init(struct gpio_bank *bank)
omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04,
ULPD_CAM_CLK_CTRL);
}
- if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
- __raw_writel(0xffffffff, bank->base
- + OMAP7XX_GPIO_INT_MASK);
- __raw_writel(0x00000000, bank->base
- + OMAP7XX_GPIO_INT_STATUS);
- }
}
}
--
1.6.0.4
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [PATCH v2 12/18] GPIO: OMAP: Clean omap_gpio_mod_init function
2011-06-15 4:23 ` [PATCH v2 12/18] GPIO: OMAP: Clean omap_gpio_mod_init function Tarun Kanti DebBarma
@ 2011-06-16 17:49 ` Kevin Hilman
2011-06-17 5:11 ` DebBarma, Tarun Kanti
2011-06-27 10:48 ` DebBarma, Tarun Kanti
0 siblings, 2 replies; 23+ messages in thread
From: Kevin Hilman @ 2011-06-16 17:49 UTC (permalink / raw)
To: Tarun Kanti DebBarma; +Cc: linux-omap, santosh.shilimkar, tony
Tarun Kanti DebBarma <tarun.kanti@ti.com> writes:
> From: Charulatha V <charu@ti.com>
>
> With register offsets now defined for respective OMAP versions we can get rid
> of cpu_class_* checks. In addition, organized common initialization for the
> different OMAP silicon versions.
>
> Signed-off-by: Charulatha V <charu@ti.com>
> Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
Since the SYSCONFIG register settings are OMAP1-only and init-time only,
they could be done in the OMAP1-specific init functions.
Also, this could be quite a bit more compact by not duplicating code for
both bank widths. Instead, create some local function pointers for 16
or 32-bit register access, and assign them based on bank width.
Kevin
> ---
> arch/arm/mach-omap1/gpio16xx.c | 1 +
> arch/arm/plat-omap/include/plat/gpio.h | 2 +
> drivers/gpio/gpio-omap.c | 121 +++++++++++++++++++++-----------
> 3 files changed, 84 insertions(+), 40 deletions(-)
>
> diff --git a/arch/arm/mach-omap1/gpio16xx.c b/arch/arm/mach-omap1/gpio16xx.c
> index 4677ea5..efd9275 100644
> --- a/arch/arm/mach-omap1/gpio16xx.c
> +++ b/arch/arm/mach-omap1/gpio16xx.c
> @@ -96,6 +96,7 @@ static struct omap_gpio_reg_offs omap16xx_gpio_regs = {
> .wkup_set = OMAP1610_GPIO_SET_WAKEUPENA,
> .edgectrl1 = OMAP1610_GPIO_EDGE_CTRL1,
> .edgectrl2 = OMAP1610_GPIO_EDGE_CTRL2,
> + .sysconfig = OMAP1610_GPIO_SYSCONFIG,
> };
>
> static struct __initdata omap_gpio_platform_data omap16xx_gpio1_config = {
> diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h
> index c0a92ea..30db400 100644
> --- a/arch/arm/plat-omap/include/plat/gpio.h
> +++ b/arch/arm/plat-omap/include/plat/gpio.h
> @@ -200,6 +200,8 @@ struct omap_gpio_reg_offs {
> u16 irqctrl;
> u16 edgectrl1;
> u16 edgectrl2;
> + /* Not applicable for OMAP2+ as hwmod layer takes care of sysconfig */
> + u16 sysconfig;
>
> bool irqenable_inv;
> };
> diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
> index 53f2ea6..89d1ea5 100644
> --- a/drivers/gpio/gpio-omap.c
> +++ b/drivers/gpio/gpio-omap.c
> @@ -887,47 +887,94 @@ static void __init omap_gpio_show_rev(struct gpio_bank *bank)
> */
> static struct lock_class_key gpio_lock_class;
>
> -/* TODO: Cleanup cpu_is_* checks */
> static void omap_gpio_mod_init(struct gpio_bank *bank)
> {
> - if (cpu_class_is_omap2()) {
> - if (cpu_is_omap44xx()) {
> - __raw_writel(0xffffffff, bank->base +
> - OMAP4_GPIO_IRQSTATUSCLR0);
> - __raw_writel(0x00000000, bank->base +
> - OMAP4_GPIO_DEBOUNCENABLE);
> - /* Initialize interface clk ungated, module enabled */
> - __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
> - } else if (cpu_is_omap34xx()) {
> - __raw_writel(0x00000000, bank->base +
> - OMAP24XX_GPIO_IRQENABLE1);
> - __raw_writel(0xffffffff, bank->base +
> - OMAP24XX_GPIO_IRQSTATUS1);
> - __raw_writel(0x00000000, bank->base +
> - OMAP24XX_GPIO_DEBOUNCE_EN);
> + if (bank->width == 32) {
> + u32 clr_all = 0; /* clear all the bits */
> + u32 set_all = 0xFFFFFFFF; /* set all the bits */
> +
> + if (bank_is_mpuio(bank)) {
> + __raw_writel(set_all, bank->base +
> + bank->regs->irqenable);
> +
> + if (bank->suspend_support)
> + mpuio_init(bank);
>
> + return;
> + }
> +
> + if (bank->regs->ctrl)
> /* Initialize interface clk ungated, module enabled */
> - __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
> + __raw_writel(clr_all, bank->base + bank->regs->ctrl);
> +
> + if (bank->regs->clr_irqenable) {
> + __raw_writel(set_all, bank->base +
> + bank->regs->clr_irqenable);
> + } else if (bank->regs->irqenable) {
> + u32 i;
> +
> + if (bank->regs->irqenable_inv)
> + i = set_all;
> + else
> + i = clr_all;
> +
> + __raw_writel(i, bank->base + bank->regs->irqenable);
> }
> - } else if (cpu_class_is_omap1()) {
> - if (bank_is_mpuio(bank) && bank->suspend_support) {
> - __raw_writew(0xffff, bank->base +
> - OMAP_MPUIO_GPIO_MASKIT / bank->stride);
> - mpuio_init(bank);
> +
> + if (bank->regs->irqstatus) {
> + u32 i;
> +
> + if (bank->regs->irqenable_inv)
> + i = clr_all;
> + else
> + i = set_all;
> +
> + __raw_writel(i, bank->base + bank->regs->irqstatus);
> }
> - if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
> - __raw_writew(0xffff, bank->base
> - + OMAP1510_GPIO_INT_MASK);
> - __raw_writew(0x0000, bank->base
> - + OMAP1510_GPIO_INT_STATUS);
> +
> + if (bank->regs->debounce_en)
> + __raw_writel(clr_all, bank->base +
> + bank->regs->debounce_en);
> +
> + } else if (bank->width == 16) {
> + u16 clr_all = 0; /* clear all the bits */
> + u16 set_all = 0xFFFF; /* set all the bits */
> +
> + if (bank_is_mpuio(bank)) {
> + __raw_writew(set_all, bank->base +
> + bank->regs->irqenable);
> +
> + if (bank->suspend_support)
> + mpuio_init(bank);
> +
> + return;
> }
> - if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
> - __raw_writew(0x0000, bank->base
> - + OMAP1610_GPIO_IRQENABLE1);
> - __raw_writew(0xffff, bank->base
> - + OMAP1610_GPIO_IRQSTATUS1);
> - __raw_writew(0x0014, bank->base
> - + OMAP1610_GPIO_SYSCONFIG);
> +
> + if (bank->regs->irqenable) {
> + u16 i;
> +
> + if (bank->regs->irqenable_inv)
> + i = set_all;
> + else
> + i = clr_all;
> +
> + __raw_writew(i, bank->base + bank->regs->irqenable);
> + }
> +
> + if (bank->regs->irqstatus) {
> + u32 i;
> +
> + if (bank->regs->irqenable_inv)
> + i = clr_all;
> + else
> + i = set_all;
> +
> + __raw_writew(i, bank->base + bank->regs->irqstatus);
> + }
> +
> + if (bank->regs->sysconfig) {
> + /* set wakeup-enable and smart-idle */
> + __raw_writew(0x14, bank->base + bank->regs->sysconfig);
>
> /*
> * Enable system clock for GPIO module.
> @@ -936,12 +983,6 @@ static void omap_gpio_mod_init(struct gpio_bank *bank)
> omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04,
> ULPD_CAM_CLK_CTRL);
> }
> - if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
> - __raw_writel(0xffffffff, bank->base
> - + OMAP7XX_GPIO_INT_MASK);
> - __raw_writel(0x00000000, bank->base
> - + OMAP7XX_GPIO_INT_STATUS);
> - }
> }
> }
^ permalink raw reply [flat|nested] 23+ messages in thread* RE: [PATCH v2 12/18] GPIO: OMAP: Clean omap_gpio_mod_init function
2011-06-16 17:49 ` Kevin Hilman
@ 2011-06-17 5:11 ` DebBarma, Tarun Kanti
2011-06-27 10:48 ` DebBarma, Tarun Kanti
1 sibling, 0 replies; 23+ messages in thread
From: DebBarma, Tarun Kanti @ 2011-06-17 5:11 UTC (permalink / raw)
To: Hilman, Kevin
Cc: linux-omap@vger.kernel.org, Shilimkar, Santosh, tony@atomide.com
> -----Original Message-----
> From: Hilman, Kevin
> Sent: Thursday, June 16, 2011 11:19 PM
> To: DebBarma, Tarun Kanti
> Cc: linux-omap@vger.kernel.org; Shilimkar, Santosh; tony@atomide.com
> Subject: Re: [PATCH v2 12/18] GPIO: OMAP: Clean omap_gpio_mod_init
> function
>
> Tarun Kanti DebBarma <tarun.kanti@ti.com> writes:
>
> > From: Charulatha V <charu@ti.com>
> >
> > With register offsets now defined for respective OMAP versions we can
> get rid
> > of cpu_class_* checks. In addition, organized common initialization for
> the
> > different OMAP silicon versions.
> >
> > Signed-off-by: Charulatha V <charu@ti.com>
> > Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
>
> Since the SYSCONFIG register settings are OMAP1-only and init-time only,
> they could be done in the OMAP1-specific init functions.
Right, I will change.
>
> Also, this could be quite a bit more compact by not duplicating code for
> both bank widths. Instead, create some local function pointers for 16
> or 32-bit register access, and assign them based on bank width.
Sounds good! I will do that.
--
Tarun
>
> Kevin
>
> > ---
> > arch/arm/mach-omap1/gpio16xx.c | 1 +
> > arch/arm/plat-omap/include/plat/gpio.h | 2 +
> > drivers/gpio/gpio-omap.c | 121 +++++++++++++++++++++----
> -------
> > 3 files changed, 84 insertions(+), 40 deletions(-)
> >
> > diff --git a/arch/arm/mach-omap1/gpio16xx.c b/arch/arm/mach-
> omap1/gpio16xx.c
> > index 4677ea5..efd9275 100644
> > --- a/arch/arm/mach-omap1/gpio16xx.c
> > +++ b/arch/arm/mach-omap1/gpio16xx.c
> > @@ -96,6 +96,7 @@ static struct omap_gpio_reg_offs omap16xx_gpio_regs =
> {
> > .wkup_set = OMAP1610_GPIO_SET_WAKEUPENA,
> > .edgectrl1 = OMAP1610_GPIO_EDGE_CTRL1,
> > .edgectrl2 = OMAP1610_GPIO_EDGE_CTRL2,
> > + .sysconfig = OMAP1610_GPIO_SYSCONFIG,
> > };
> >
> > static struct __initdata omap_gpio_platform_data omap16xx_gpio1_config
> = {
> > diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-
> omap/include/plat/gpio.h
> > index c0a92ea..30db400 100644
> > --- a/arch/arm/plat-omap/include/plat/gpio.h
> > +++ b/arch/arm/plat-omap/include/plat/gpio.h
> > @@ -200,6 +200,8 @@ struct omap_gpio_reg_offs {
> > u16 irqctrl;
> > u16 edgectrl1;
> > u16 edgectrl2;
> > + /* Not applicable for OMAP2+ as hwmod layer takes care of sysconfig
> */
> > + u16 sysconfig;
> >
> > bool irqenable_inv;
> > };
> > diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
> > index 53f2ea6..89d1ea5 100644
> > --- a/drivers/gpio/gpio-omap.c
> > +++ b/drivers/gpio/gpio-omap.c
> > @@ -887,47 +887,94 @@ static void __init omap_gpio_show_rev(struct
> gpio_bank *bank)
> > */
> > static struct lock_class_key gpio_lock_class;
> >
> > -/* TODO: Cleanup cpu_is_* checks */
> > static void omap_gpio_mod_init(struct gpio_bank *bank)
> > {
> > - if (cpu_class_is_omap2()) {
> > - if (cpu_is_omap44xx()) {
> > - __raw_writel(0xffffffff, bank->base +
> > - OMAP4_GPIO_IRQSTATUSCLR0);
> > - __raw_writel(0x00000000, bank->base +
> > - OMAP4_GPIO_DEBOUNCENABLE);
> > - /* Initialize interface clk ungated, module enabled */
> > - __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
> > - } else if (cpu_is_omap34xx()) {
> > - __raw_writel(0x00000000, bank->base +
> > - OMAP24XX_GPIO_IRQENABLE1);
> > - __raw_writel(0xffffffff, bank->base +
> > - OMAP24XX_GPIO_IRQSTATUS1);
> > - __raw_writel(0x00000000, bank->base +
> > - OMAP24XX_GPIO_DEBOUNCE_EN);
> > + if (bank->width == 32) {
> > + u32 clr_all = 0; /* clear all the bits */
> > + u32 set_all = 0xFFFFFFFF; /* set all the bits */
> > +
> > + if (bank_is_mpuio(bank)) {
> > + __raw_writel(set_all, bank->base +
> > + bank->regs->irqenable);
> > +
> > + if (bank->suspend_support)
> > + mpuio_init(bank);
> >
> > + return;
> > + }
> > +
> > + if (bank->regs->ctrl)
> > /* Initialize interface clk ungated, module enabled */
> > - __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
> > + __raw_writel(clr_all, bank->base + bank->regs->ctrl);
> > +
> > + if (bank->regs->clr_irqenable) {
> > + __raw_writel(set_all, bank->base +
> > + bank->regs->clr_irqenable);
> > + } else if (bank->regs->irqenable) {
> > + u32 i;
> > +
> > + if (bank->regs->irqenable_inv)
> > + i = set_all;
> > + else
> > + i = clr_all;
> > +
> > + __raw_writel(i, bank->base + bank->regs->irqenable);
> > }
> > - } else if (cpu_class_is_omap1()) {
> > - if (bank_is_mpuio(bank) && bank->suspend_support) {
> > - __raw_writew(0xffff, bank->base +
> > - OMAP_MPUIO_GPIO_MASKIT / bank->stride);
> > - mpuio_init(bank);
> > +
> > + if (bank->regs->irqstatus) {
> > + u32 i;
> > +
> > + if (bank->regs->irqenable_inv)
> > + i = clr_all;
> > + else
> > + i = set_all;
> > +
> > + __raw_writel(i, bank->base + bank->regs->irqstatus);
> > }
> > - if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
> > - __raw_writew(0xffff, bank->base
> > - + OMAP1510_GPIO_INT_MASK);
> > - __raw_writew(0x0000, bank->base
> > - + OMAP1510_GPIO_INT_STATUS);
> > +
> > + if (bank->regs->debounce_en)
> > + __raw_writel(clr_all, bank->base +
> > + bank->regs->debounce_en);
> > +
> > + } else if (bank->width == 16) {
> > + u16 clr_all = 0; /* clear all the bits */
> > + u16 set_all = 0xFFFF; /* set all the bits */
> > +
> > + if (bank_is_mpuio(bank)) {
> > + __raw_writew(set_all, bank->base +
> > + bank->regs->irqenable);
> > +
> > + if (bank->suspend_support)
> > + mpuio_init(bank);
> > +
> > + return;
> > }
> > - if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
> > - __raw_writew(0x0000, bank->base
> > - + OMAP1610_GPIO_IRQENABLE1);
> > - __raw_writew(0xffff, bank->base
> > - + OMAP1610_GPIO_IRQSTATUS1);
> > - __raw_writew(0x0014, bank->base
> > - + OMAP1610_GPIO_SYSCONFIG);
> > +
> > + if (bank->regs->irqenable) {
> > + u16 i;
> > +
> > + if (bank->regs->irqenable_inv)
> > + i = set_all;
> > + else
> > + i = clr_all;
> > +
> > + __raw_writew(i, bank->base + bank->regs->irqenable);
> > + }
> > +
> > + if (bank->regs->irqstatus) {
> > + u32 i;
> > +
> > + if (bank->regs->irqenable_inv)
> > + i = clr_all;
> > + else
> > + i = set_all;
> > +
> > + __raw_writew(i, bank->base + bank->regs->irqstatus);
> > + }
> > +
> > + if (bank->regs->sysconfig) {
> > + /* set wakeup-enable and smart-idle */
> > + __raw_writew(0x14, bank->base + bank->regs->sysconfig);
> >
> > /*
> > * Enable system clock for GPIO module.
> > @@ -936,12 +983,6 @@ static void omap_gpio_mod_init(struct gpio_bank
> *bank)
> > omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04,
> > ULPD_CAM_CLK_CTRL);
> > }
> > - if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
> > - __raw_writel(0xffffffff, bank->base
> > - + OMAP7XX_GPIO_INT_MASK);
> > - __raw_writel(0x00000000, bank->base
> > - + OMAP7XX_GPIO_INT_STATUS);
> > - }
> > }
> > }
^ permalink raw reply [flat|nested] 23+ messages in thread* RE: [PATCH v2 12/18] GPIO: OMAP: Clean omap_gpio_mod_init function
2011-06-16 17:49 ` Kevin Hilman
2011-06-17 5:11 ` DebBarma, Tarun Kanti
@ 2011-06-27 10:48 ` DebBarma, Tarun Kanti
2011-06-27 23:06 ` Kevin Hilman
1 sibling, 1 reply; 23+ messages in thread
From: DebBarma, Tarun Kanti @ 2011-06-27 10:48 UTC (permalink / raw)
To: Hilman, Kevin
Cc: linux-omap@vger.kernel.org, Shilimkar, Santosh, tony@atomide.com
Kevin,
[...]
> >
> > With register offsets now defined for respective OMAP versions we can
> get rid
> > of cpu_class_* checks. In addition, organized common initialization for
> the
> > different OMAP silicon versions.
> >
> > Signed-off-by: Charulatha V <charu@ti.com>
> > Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
>
> Since the SYSCONFIG register settings are OMAP1-only and init-time only,
> they could be done in the OMAP1-specific init functions.
BTW, I needed some more clarifications here...
The omap_gpio_mod_init() is called only once from _probe().
So, does it make sense to have a separate init function?
If yes, I have to call __init omap1_gpio_mod_init() from _probe() again.
This is because I need the bank information supplied to it.
Let me know if this is a fair understanding. Thanks.
--
Tarun
>
> Also, this could be quite a bit more compact by not duplicating code for
> both bank widths. Instead, create some local function pointers for 16
> or 32-bit register access, and assign them based on bank width.
>
> Kevin
>
[...]
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 12/18] GPIO: OMAP: Clean omap_gpio_mod_init function
2011-06-27 10:48 ` DebBarma, Tarun Kanti
@ 2011-06-27 23:06 ` Kevin Hilman
0 siblings, 0 replies; 23+ messages in thread
From: Kevin Hilman @ 2011-06-27 23:06 UTC (permalink / raw)
To: DebBarma, Tarun Kanti
Cc: linux-omap@vger.kernel.org, Shilimkar, Santosh, tony@atomide.com
"DebBarma, Tarun Kanti" <tarun.kanti@ti.com> writes:
> Kevin,
> [...]
>> >
>> > With register offsets now defined for respective OMAP versions we can
>> get rid
>> > of cpu_class_* checks. In addition, organized common initialization for
>> the
>> > different OMAP silicon versions.
>> >
>> > Signed-off-by: Charulatha V <charu@ti.com>
>> > Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
>>
>> Since the SYSCONFIG register settings are OMAP1-only and init-time only,
>> they could be done in the OMAP1-specific init functions.
> BTW, I needed some more clarifications here...
> The omap_gpio_mod_init() is called only once from _probe().
> So, does it make sense to have a separate init function?
> If yes, I have to call __init omap1_gpio_mod_init() from _probe() again.
> This is because I need the bank information supplied to it.
What I was thinking is something like the patch below (16xx only for
example, but would need to be done for other OMAP1 also). This patch
will obviously not work, but read the comment in the patch to make it work.
Kevin
diff --git a/arch/arm/mach-omap1/gpio16xx.c b/arch/arm/mach-omap1/gpio16xx.c
index c69b3b1..1d34a4c 100644
--- a/arch/arm/mach-omap1/gpio16xx.c
+++ b/arch/arm/mach-omap1/gpio16xx.c
@@ -218,8 +218,12 @@ static int __init omap16xx_gpio_init(void)
if (!cpu_is_omap16xx())
return -EINVAL;
- for (i = 0; i < ARRAY_SIZE(omap16xx_gpio_dev); i++)
+ for (i = 0; i < ARRAY_SIZE(omap16xx_gpio_dev); i++) {
+ u32 base = 0; /* get base from device's struct resource */
+
+ __raw_writew(0x0014, base + OMAP1610_GPIO_SYSCONFIG);
platform_device_register(omap16xx_gpio_dev[i]);
+ }
gpio_bank_count = ARRAY_SIZE(omap16xx_gpio_dev);
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v2 13/18] GPIO: OMAP15xx: Use pinctrl offset instead of macro
2011-06-15 4:23 [PATCH v2 10/18] GPIO: OMAP: Remove hardcoded offsets in ctxt save/restore Tarun Kanti DebBarma
2011-06-15 4:23 ` [PATCH v2 11/18] GPIO: OMAP: Clean set_gpio_triggering function Tarun Kanti DebBarma
2011-06-15 4:23 ` [PATCH v2 12/18] GPIO: OMAP: Clean omap_gpio_mod_init function Tarun Kanti DebBarma
@ 2011-06-15 4:23 ` Tarun Kanti DebBarma
2011-06-15 4:23 ` [PATCH v2 14/18] GPIO: OMAP: Fix use of readl/readw to access isr_reg Tarun Kanti DebBarma
` (4 subsequent siblings)
7 siblings, 0 replies; 23+ messages in thread
From: Tarun Kanti DebBarma @ 2011-06-15 4:23 UTC (permalink / raw)
To: linux-omap; +Cc: khilman, santosh.shilimkar, tony
From: Charulatha V <charu@ti.com>
Use regs->pinctrl field instead of using the macro OMAP1510_GPIO_PIN_CONTROL
Signed-off-by: Charulatha V <charu@ti.com>
---
arch/arm/mach-omap1/gpio15xx.c | 1 +
arch/arm/plat-omap/include/plat/gpio.h | 1 +
drivers/gpio/gpio-omap.c | 8 +++-----
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-omap1/gpio15xx.c b/arch/arm/mach-omap1/gpio15xx.c
index fd2fe8f..020725f 100644
--- a/arch/arm/mach-omap1/gpio15xx.c
+++ b/arch/arm/mach-omap1/gpio15xx.c
@@ -85,6 +85,7 @@ static struct omap_gpio_reg_offs omap15xx_gpio_regs = {
.irqenable = OMAP1510_GPIO_INT_MASK,
.irqenable_inv = true,
.irqctrl = OMAP1510_GPIO_INT_CONTROL,
+ .pinctrl = OMAP1510_GPIO_PIN_CONTROL,
};
static struct __initdata omap_gpio_platform_data omap15xx_gpio_config = {
diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h
index 30db400..8f85700 100644
--- a/arch/arm/plat-omap/include/plat/gpio.h
+++ b/arch/arm/plat-omap/include/plat/gpio.h
@@ -202,6 +202,7 @@ struct omap_gpio_reg_offs {
u16 edgectrl2;
/* Not applicable for OMAP2+ as hwmod layer takes care of sysconfig */
u16 sysconfig;
+ u16 pinctrl;
bool irqenable_inv;
};
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 89d1ea5..c6987f2 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -507,15 +507,13 @@ static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
*/
_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
-#ifdef CONFIG_ARCH_OMAP15XX
- if (bank->method == METHOD_GPIO_1510) {
- void __iomem *reg;
+ if (bank->regs->pinctrl) {
+ void __iomem *reg = bank->base + bank->regs->pinctrl;
/* Claim the pin for MPU */
- reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
__raw_writel(__raw_readl(reg) | (1 << offset), reg);
}
-#endif
+
if (bank->regs->ctrl && !bank->mod_usage) {
void __iomem *reg = bank->base + bank->regs->ctrl;
u32 ctrl;
--
1.6.0.4
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v2 14/18] GPIO: OMAP: Fix use of readl/readw to access isr_reg
2011-06-15 4:23 [PATCH v2 10/18] GPIO: OMAP: Remove hardcoded offsets in ctxt save/restore Tarun Kanti DebBarma
` (2 preceding siblings ...)
2011-06-15 4:23 ` [PATCH v2 13/18] GPIO: OMAP15xx: Use pinctrl offset instead of macro Tarun Kanti DebBarma
@ 2011-06-15 4:23 ` Tarun Kanti DebBarma
2011-06-16 17:53 ` Kevin Hilman
2011-06-16 17:57 ` Kevin Hilman
2011-06-15 4:23 ` [PATCH v2 15/18] GPIO: OMAP: Remove bank->method & METHOD_* macros Tarun Kanti DebBarma
` (3 subsequent siblings)
7 siblings, 2 replies; 23+ messages in thread
From: Tarun Kanti DebBarma @ 2011-06-15 4:23 UTC (permalink / raw)
To: linux-omap; +Cc: khilman, santosh.shilimkar, tony
From: Charulatha V <charu@ti.com>
In gpio_irq_handler, isr register is always accessed as 32 bit register and only
for OMAP15xx the first 16 MSBs are masked. Correct this by using the appropriate
readl/readw registers as per the bank width.
Signed-off-by: Charulatha V <charu@ti.com>
---
drivers/gpio/gpio-omap.c | 8 +++++---
1 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index c6987f2..01b568f 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -590,10 +590,12 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
u32 enabled;
enabled = _get_gpio_irqbank_mask(bank);
- isr_saved = isr = __raw_readl(isr_reg) & enabled;
- if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
- isr &= 0x0000ffff;
+ if (bank->width == 32)
+ isr = __raw_readl(isr_reg) & enabled;
+ else if (bank->width == 16)
+ isr = (__raw_readw(isr_reg) & enabled) & 0x0000ffff;
+ isr_saved = isr;
if (bank->regs->leveldetect0)
level_mask = bank->level_mask & enabled;
--
1.6.0.4
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [PATCH v2 14/18] GPIO: OMAP: Fix use of readl/readw to access isr_reg
2011-06-15 4:23 ` [PATCH v2 14/18] GPIO: OMAP: Fix use of readl/readw to access isr_reg Tarun Kanti DebBarma
@ 2011-06-16 17:53 ` Kevin Hilman
2011-06-17 5:07 ` DebBarma, Tarun Kanti
2011-06-16 17:57 ` Kevin Hilman
1 sibling, 1 reply; 23+ messages in thread
From: Kevin Hilman @ 2011-06-16 17:53 UTC (permalink / raw)
To: Tarun Kanti DebBarma; +Cc: linux-omap, santosh.shilimkar, tony
Tarun Kanti DebBarma <tarun.kanti@ti.com> writes:
> From: Charulatha V <charu@ti.com>
>
> In gpio_irq_handler, isr register is always accessed as 32 bit register and only
> for OMAP15xx the first 16 MSBs are masked. Correct this by using the appropriate
> readl/readw registers as per the bank width.
>
> Signed-off-by: Charulatha V <charu@ti.com>
> ---
> drivers/gpio/gpio-omap.c | 8 +++++---
> 1 files changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
> index c6987f2..01b568f 100644
> --- a/drivers/gpio/gpio-omap.c
> +++ b/drivers/gpio/gpio-omap.c
> @@ -590,10 +590,12 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
> u32 enabled;
>
> enabled = _get_gpio_irqbank_mask(bank);
> - isr_saved = isr = __raw_readl(isr_reg) & enabled;
>
> - if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
> - isr &= 0x0000ffff;
> + if (bank->width == 32)
> + isr = __raw_readl(isr_reg) & enabled;
> + else if (bank->width == 16)
> + isr = (__raw_readw(isr_reg) & enabled) & 0x0000ffff;
Minor nit: is the '& 0xffff' really needed. The 'enabled' mask is
already masked using the bank width.
Kevin
> + isr_saved = isr;
>
> if (bank->regs->leveldetect0)
> level_mask = bank->level_mask & enabled;
^ permalink raw reply [flat|nested] 23+ messages in thread
* RE: [PATCH v2 14/18] GPIO: OMAP: Fix use of readl/readw to access isr_reg
2011-06-16 17:53 ` Kevin Hilman
@ 2011-06-17 5:07 ` DebBarma, Tarun Kanti
0 siblings, 0 replies; 23+ messages in thread
From: DebBarma, Tarun Kanti @ 2011-06-17 5:07 UTC (permalink / raw)
To: Hilman, Kevin
Cc: linux-omap@vger.kernel.org, Shilimkar, Santosh, tony@atomide.com
> -----Original Message-----
> From: Hilman, Kevin
> Sent: Thursday, June 16, 2011 11:24 PM
> To: DebBarma, Tarun Kanti
> Cc: linux-omap@vger.kernel.org; Shilimkar, Santosh; tony@atomide.com
> Subject: Re: [PATCH v2 14/18] GPIO: OMAP: Fix use of readl/readw to access
> isr_reg
>
> Tarun Kanti DebBarma <tarun.kanti@ti.com> writes:
>
> > From: Charulatha V <charu@ti.com>
> >
> > In gpio_irq_handler, isr register is always accessed as 32 bit register
> and only
> > for OMAP15xx the first 16 MSBs are masked. Correct this by using the
> appropriate
> > readl/readw registers as per the bank width.
> >
> > Signed-off-by: Charulatha V <charu@ti.com>
> > ---
> > drivers/gpio/gpio-omap.c | 8 +++++---
> > 1 files changed, 5 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
> > index c6987f2..01b568f 100644
> > --- a/drivers/gpio/gpio-omap.c
> > +++ b/drivers/gpio/gpio-omap.c
> > @@ -590,10 +590,12 @@ static void gpio_irq_handler(unsigned int irq,
> struct irq_desc *desc)
> > u32 enabled;
> >
> > enabled = _get_gpio_irqbank_mask(bank);
> > - isr_saved = isr = __raw_readl(isr_reg) & enabled;
> >
> > - if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
> > - isr &= 0x0000ffff;
> > + if (bank->width == 32)
> > + isr = __raw_readl(isr_reg) & enabled;
> > + else if (bank->width == 16)
> > + isr = (__raw_readw(isr_reg) & enabled) & 0x0000ffff;
>
> Minor nit: is the '& 0xffff' really needed. The 'enabled' mask is
> already masked using the bank width.
Right, that's you pointed out. Thanks.
--
Tarun
>
> Kevin
>
> > + isr_saved = isr;
> >
> > if (bank->regs->leveldetect0)
> > level_mask = bank->level_mask & enabled;
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 14/18] GPIO: OMAP: Fix use of readl/readw to access isr_reg
2011-06-15 4:23 ` [PATCH v2 14/18] GPIO: OMAP: Fix use of readl/readw to access isr_reg Tarun Kanti DebBarma
2011-06-16 17:53 ` Kevin Hilman
@ 2011-06-16 17:57 ` Kevin Hilman
2011-06-17 5:05 ` DebBarma, Tarun Kanti
1 sibling, 1 reply; 23+ messages in thread
From: Kevin Hilman @ 2011-06-16 17:57 UTC (permalink / raw)
To: Tarun Kanti DebBarma; +Cc: linux-omap, santosh.shilimkar, tony
Tarun Kanti DebBarma <tarun.kanti@ti.com> writes:
> From: Charulatha V <charu@ti.com>
>
> In gpio_irq_handler, isr register is always accessed as 32 bit register and only
> for OMAP15xx the first 16 MSBs are masked. Correct this by using the appropriate
> readl/readw registers as per the bank width.
>
> Signed-off-by: Charulatha V <charu@ti.com>
> ---
> drivers/gpio/gpio-omap.c | 8 +++++---
> 1 files changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
> index c6987f2..01b568f 100644
> --- a/drivers/gpio/gpio-omap.c
> +++ b/drivers/gpio/gpio-omap.c
> @@ -590,10 +590,12 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
> u32 enabled;
>
> enabled = _get_gpio_irqbank_mask(bank);
> - isr_saved = isr = __raw_readl(isr_reg) & enabled;
>
> - if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
> - isr &= 0x0000ffff;
> + if (bank->width == 32)
> + isr = __raw_readl(isr_reg) & enabled;
> + else if (bank->width == 16)
> + isr = (__raw_readw(isr_reg) & enabled) & 0x0000ffff;
> + isr_saved = isr;
Come to think of it, even when bank->width is 16, all the OMAP1
registers are 4-byte aligned, so just use a 4-byte read. The 'enabled'
mask is already taking care to mask for bank width.
Kevin
^ permalink raw reply [flat|nested] 23+ messages in thread
* RE: [PATCH v2 14/18] GPIO: OMAP: Fix use of readl/readw to access isr_reg
2011-06-16 17:57 ` Kevin Hilman
@ 2011-06-17 5:05 ` DebBarma, Tarun Kanti
0 siblings, 0 replies; 23+ messages in thread
From: DebBarma, Tarun Kanti @ 2011-06-17 5:05 UTC (permalink / raw)
To: Hilman, Kevin
Cc: linux-omap@vger.kernel.org, Shilimkar, Santosh, tony@atomide.com
> -----Original Message-----
> From: Hilman, Kevin
> Sent: Thursday, June 16, 2011 11:28 PM
> To: DebBarma, Tarun Kanti
> Cc: linux-omap@vger.kernel.org; Shilimkar, Santosh; tony@atomide.com
> Subject: Re: [PATCH v2 14/18] GPIO: OMAP: Fix use of readl/readw to access
> isr_reg
>
> Tarun Kanti DebBarma <tarun.kanti@ti.com> writes:
>
> > From: Charulatha V <charu@ti.com>
> >
> > In gpio_irq_handler, isr register is always accessed as 32 bit register
> and only
> > for OMAP15xx the first 16 MSBs are masked. Correct this by using the
> appropriate
> > readl/readw registers as per the bank width.
> >
> > Signed-off-by: Charulatha V <charu@ti.com>
> > ---
> > drivers/gpio/gpio-omap.c | 8 +++++---
> > 1 files changed, 5 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
> > index c6987f2..01b568f 100644
> > --- a/drivers/gpio/gpio-omap.c
> > +++ b/drivers/gpio/gpio-omap.c
> > @@ -590,10 +590,12 @@ static void gpio_irq_handler(unsigned int irq,
> struct irq_desc *desc)
> > u32 enabled;
> >
> > enabled = _get_gpio_irqbank_mask(bank);
> > - isr_saved = isr = __raw_readl(isr_reg) & enabled;
> >
> > - if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
> > - isr &= 0x0000ffff;
> > + if (bank->width == 32)
> > + isr = __raw_readl(isr_reg) & enabled;
> > + else if (bank->width == 16)
> > + isr = (__raw_readw(isr_reg) & enabled) & 0x0000ffff;
> > + isr_saved = isr;
>
> Come to think of it, even when bank->width is 16, all the OMAP1
> registers are 4-byte aligned, so just use a 4-byte read. The 'enabled'
> mask is already taking care to mask for bank width.
Yes, that makes sense. I will change.
--
Tarun
--
>
> Kevin
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 15/18] GPIO: OMAP: Remove bank->method & METHOD_* macros
2011-06-15 4:23 [PATCH v2 10/18] GPIO: OMAP: Remove hardcoded offsets in ctxt save/restore Tarun Kanti DebBarma
` (3 preceding siblings ...)
2011-06-15 4:23 ` [PATCH v2 14/18] GPIO: OMAP: Fix use of readl/readw to access isr_reg Tarun Kanti DebBarma
@ 2011-06-15 4:23 ` Tarun Kanti DebBarma
2011-06-15 4:23 ` [PATCH v2 16/18] GPIO: OMAP: Fix bankwidth for OMAP7xx MPUIO Tarun Kanti DebBarma
` (2 subsequent siblings)
7 siblings, 0 replies; 23+ messages in thread
From: Tarun Kanti DebBarma @ 2011-06-15 4:23 UTC (permalink / raw)
To: linux-omap; +Cc: khilman, santosh.shilimkar, tony
From: Charulatha V <charu@ti.com>
The only bank->type (method) used in the OMAP GPIO driver is MPUIO type as they
need to be handled separately. Identify the same using a flag and remove all
METHOD_* macros.
Signed-off-by: Charulatha V <charu@ti.com>
---
arch/arm/mach-omap1/gpio15xx.c | 3 +--
arch/arm/mach-omap1/gpio16xx.c | 6 +-----
arch/arm/mach-omap1/gpio7xx.c | 8 +-------
arch/arm/mach-omap2/gpio.c | 2 --
arch/arm/plat-omap/include/plat/gpio.h | 9 +--------
drivers/gpio/gpio-omap.c | 18 ++++++------------
6 files changed, 10 insertions(+), 36 deletions(-)
diff --git a/arch/arm/mach-omap1/gpio15xx.c b/arch/arm/mach-omap1/gpio15xx.c
index 020725f..c51593c 100644
--- a/arch/arm/mach-omap1/gpio15xx.c
+++ b/arch/arm/mach-omap1/gpio15xx.c
@@ -47,7 +47,7 @@ static struct omap_gpio_reg_offs omap15xx_mpuio_regs = {
static struct __initdata omap_gpio_platform_data omap15xx_mpu_gpio_config = {
.virtual_irq_start = IH_MPUIO_BASE,
- .bank_type = METHOD_MPUIO,
+ .is_mpuio = true,
.bank_width = 16,
.bank_stride = 1,
.regs = &omap15xx_mpuio_regs,
@@ -90,7 +90,6 @@ static struct omap_gpio_reg_offs omap15xx_gpio_regs = {
static struct __initdata omap_gpio_platform_data omap15xx_gpio_config = {
.virtual_irq_start = IH_GPIO_BASE,
- .bank_type = METHOD_GPIO_1510,
.bank_width = 16,
.regs = &omap15xx_gpio_regs,
};
diff --git a/arch/arm/mach-omap1/gpio16xx.c b/arch/arm/mach-omap1/gpio16xx.c
index efd9275..6b90fad 100644
--- a/arch/arm/mach-omap1/gpio16xx.c
+++ b/arch/arm/mach-omap1/gpio16xx.c
@@ -50,7 +50,7 @@ static struct omap_gpio_reg_offs omap16xx_mpuio_regs = {
static struct __initdata omap_gpio_platform_data omap16xx_mpu_gpio_config = {
.virtual_irq_start = IH_MPUIO_BASE,
- .bank_type = METHOD_MPUIO,
+ .is_mpuio = true,
.bank_width = 16,
.bank_stride = 1,
.suspend_support = true,
@@ -101,7 +101,6 @@ static struct omap_gpio_reg_offs omap16xx_gpio_regs = {
static struct __initdata omap_gpio_platform_data omap16xx_gpio1_config = {
.virtual_irq_start = IH_GPIO_BASE,
- .bank_type = METHOD_GPIO_1610,
.bank_width = 16,
.suspend_support = true,
.regs = &omap16xx_gpio_regs,
@@ -132,7 +131,6 @@ static struct __initdata resource omap16xx_gpio2_resources[] = {
static struct __initdata omap_gpio_platform_data omap16xx_gpio2_config = {
.virtual_irq_start = IH_GPIO_BASE + 16,
- .bank_type = METHOD_GPIO_1610,
.bank_width = 16,
.suspend_support = true,
.regs = &omap16xx_gpio_regs,
@@ -163,7 +161,6 @@ static struct __initdata resource omap16xx_gpio3_resources[] = {
static struct __initdata omap_gpio_platform_data omap16xx_gpio3_config = {
.virtual_irq_start = IH_GPIO_BASE + 32,
- .bank_type = METHOD_GPIO_1610,
.bank_width = 16,
.suspend_support = true,
.regs = &omap16xx_gpio_regs,
@@ -194,7 +191,6 @@ static struct __initdata resource omap16xx_gpio4_resources[] = {
static struct __initdata omap_gpio_platform_data omap16xx_gpio4_config = {
.virtual_irq_start = IH_GPIO_BASE + 48,
- .bank_type = METHOD_GPIO_1610,
.bank_width = 16,
.suspend_support = true,
.regs = &omap16xx_gpio_regs,
diff --git a/arch/arm/mach-omap1/gpio7xx.c b/arch/arm/mach-omap1/gpio7xx.c
index 6e439ff..91a7691 100644
--- a/arch/arm/mach-omap1/gpio7xx.c
+++ b/arch/arm/mach-omap1/gpio7xx.c
@@ -52,8 +52,8 @@ static struct omap_gpio_reg_offs omap7xx_mpuio_regs = {
static struct __initdata omap_gpio_platform_data omap7xx_mpu_gpio_config = {
.virtual_irq_start = IH_MPUIO_BASE,
- .bank_type = METHOD_MPUIO,
.bank_width = 32,
+ .is_mpuio = true,
.bank_stride = 2,
.regs = &omap7xx_mpuio_regs,
};
@@ -94,7 +94,6 @@ static struct omap_gpio_reg_offs omap7xx_gpio_regs = {
static struct __initdata omap_gpio_platform_data omap7xx_gpio1_config = {
.virtual_irq_start = IH_GPIO_BASE,
- .bank_type = METHOD_GPIO_7XX,
.bank_width = 32,
.regs = &omap7xx_gpio_regs,
};
@@ -124,7 +123,6 @@ static struct __initdata resource omap7xx_gpio2_resources[] = {
static struct __initdata omap_gpio_platform_data omap7xx_gpio2_config = {
.virtual_irq_start = IH_GPIO_BASE + 32,
- .bank_type = METHOD_GPIO_7XX,
.bank_width = 32,
.regs = &omap7xx_gpio_regs,
};
@@ -154,7 +152,6 @@ static struct __initdata resource omap7xx_gpio3_resources[] = {
static struct __initdata omap_gpio_platform_data omap7xx_gpio3_config = {
.virtual_irq_start = IH_GPIO_BASE + 64,
- .bank_type = METHOD_GPIO_7XX,
.bank_width = 32,
.regs = &omap7xx_gpio_regs,
};
@@ -184,7 +181,6 @@ static struct __initdata resource omap7xx_gpio4_resources[] = {
static struct __initdata omap_gpio_platform_data omap7xx_gpio4_config = {
.virtual_irq_start = IH_GPIO_BASE + 96,
- .bank_type = METHOD_GPIO_7XX,
.bank_width = 32,
.regs = &omap7xx_gpio_regs,
};
@@ -214,7 +210,6 @@ static struct __initdata resource omap7xx_gpio5_resources[] = {
static struct __initdata omap_gpio_platform_data omap7xx_gpio5_config = {
.virtual_irq_start = IH_GPIO_BASE + 128,
- .bank_type = METHOD_GPIO_7XX,
.bank_width = 32,
.regs = &omap7xx_gpio_regs,
};
@@ -244,7 +239,6 @@ static struct __initdata resource omap7xx_gpio6_resources[] = {
static struct __initdata omap_gpio_platform_data omap7xx_gpio6_config = {
.virtual_irq_start = IH_GPIO_BASE + 160,
- .bank_type = METHOD_GPIO_7XX,
.bank_width = 32,
.regs = &omap7xx_gpio_regs,
};
diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c
index 3c96855..a6ecd00 100644
--- a/arch/arm/mach-omap2/gpio.c
+++ b/arch/arm/mach-omap2/gpio.c
@@ -98,7 +98,6 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
/* fall through */
case 1:
- pdata->bank_type = METHOD_GPIO_24XX;
pdata->regs->revision = OMAP24XX_GPIO_REVISION;
pdata->regs->direction = OMAP24XX_GPIO_OE;
pdata->regs->datain = OMAP24XX_GPIO_DATAIN;
@@ -123,7 +122,6 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
pdata->regs->fallingdetect = OMAP24XX_GPIO_FALLINGDETECT;
break;
case 2:
- pdata->bank_type = METHOD_GPIO_44XX;
pdata->regs->revision = OMAP4_GPIO_REVISION;
pdata->regs->direction = OMAP4_GPIO_OE;
pdata->regs->datain = OMAP4_GPIO_DATAIN;
diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h
index 8f85700..804a55f 100644
--- a/arch/arm/plat-omap/include/plat/gpio.h
+++ b/arch/arm/plat-omap/include/plat/gpio.h
@@ -162,13 +162,6 @@
IH_MPUIO_BASE + ((nr) & 0x0f) : \
IH_GPIO_BASE + (nr))
-#define METHOD_MPUIO 0
-#define METHOD_GPIO_1510 1
-#define METHOD_GPIO_1610 2
-#define METHOD_GPIO_7XX 3
-#define METHOD_GPIO_24XX 5
-#define METHOD_GPIO_44XX 6
-
struct omap_gpio_dev_attr {
int bank_width; /* GPIO bank width */
bool dbck_flag; /* dbck required or not - True for OMAP3&4 */
@@ -209,12 +202,12 @@ struct omap_gpio_reg_offs {
struct omap_gpio_platform_data {
u16 virtual_irq_start;
- int bank_type;
int bank_width; /* GPIO bank width */
int bank_stride; /* Only needed for omap1 MPUIO */
bool suspend_support; /* Bank supports suspend/resume operations or not */
bool dbck_flag; /* dbck required or not - True for OMAP3&4 */
bool loses_context; /* whether the bank would ever lose context */
+ bool is_mpuio; /* whether the bank is of type MPUIO */
u32 non_wakeup_gpios;
struct omap_gpio_reg_offs *regs;
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 01b568f..36532de 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -49,7 +49,6 @@ struct gpio_bank {
void __iomem *base;
u16 irq;
u16 virtual_irq_start;
- int method;
u32 suspend_wakeup;
u32 saved_wakeup;
u32 non_wakeup_gpios;
@@ -66,6 +65,7 @@ struct gpio_bank {
u32 mod_usage;
u32 dbck_enable_mask;
struct device *dev;
+ bool is_mpuio;
bool dbck_flag;
bool loses_context;
bool suspend_support;
@@ -706,8 +706,6 @@ static struct irq_chip gpio_irq_chip = {
};
/*---------------------------------------------------------------------*/
-#define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
-
static int omap_mpuio_suspend_noirq(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
@@ -771,10 +769,6 @@ static inline void mpuio_init(struct gpio_bank *bank)
/*---------------------------------------------------------------------*/
-/* REVISIT these are stupid implementations! replace by ones that
- * don't switch on METHOD_* and which mostly avoid spinlocks
- */
-
static int gpio_input(struct gpio_chip *chip, unsigned offset)
{
struct gpio_bank *bank;
@@ -893,7 +887,7 @@ static void omap_gpio_mod_init(struct gpio_bank *bank)
u32 clr_all = 0; /* clear all the bits */
u32 set_all = 0xFFFFFFFF; /* set all the bits */
- if (bank_is_mpuio(bank)) {
+ if (bank->is_mpuio) {
__raw_writel(set_all, bank->base +
bank->regs->irqenable);
@@ -940,7 +934,7 @@ static void omap_gpio_mod_init(struct gpio_bank *bank)
u16 clr_all = 0; /* clear all the bits */
u16 set_all = 0xFFFF; /* set all the bits */
- if (bank_is_mpuio(bank)) {
+ if (bank->is_mpuio) {
__raw_writew(set_all, bank->base +
bank->regs->irqenable);
@@ -1028,7 +1022,7 @@ static void __devinit omap_gpio_chip_init(struct gpio_bank *bank)
bank->chip.set_debounce = gpio_debounce;
bank->chip.set = gpio_set;
bank->chip.to_irq = gpio_2irq;
- if (bank_is_mpuio(bank)) {
+ if (bank->is_mpuio) {
bank->chip.label = "mpuio";
if (bank->suspend_support)
bank->chip.dev = &omap_mpuio_device.dev;
@@ -1046,7 +1040,7 @@ static void __devinit omap_gpio_chip_init(struct gpio_bank *bank)
j < bank->virtual_irq_start + bank->width; j++) {
irq_set_lockdep_class(j, &gpio_lock_class);
irq_set_chip_data(j, bank);
- if (bank_is_mpuio(bank)) {
+ if (bank->is_mpuio) {
omap_mpuio_alloc_gc(bank, j, bank->width);
} else {
irq_set_chip(j, &gpio_irq_chip);
@@ -1090,11 +1084,11 @@ static int __devinit omap_gpio_probe(struct platform_device *pdev)
pdata = pdev->dev.platform_data;
bank->virtual_irq_start = pdata->virtual_irq_start;
- bank->method = pdata->bank_type;
bank->dev = &pdev->dev;
bank->dbck_flag = pdata->dbck_flag;
bank->stride = pdata->bank_stride;
bank->width = pdata->bank_width;
+ bank->is_mpuio = pdata->is_mpuio;
bank->suspend_support = pdata->suspend_support;
bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
bank->loses_context = pdata->loses_context;
--
1.6.0.4
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v2 16/18] GPIO: OMAP: Fix bankwidth for OMAP7xx MPUIO
2011-06-15 4:23 [PATCH v2 10/18] GPIO: OMAP: Remove hardcoded offsets in ctxt save/restore Tarun Kanti DebBarma
` (4 preceding siblings ...)
2011-06-15 4:23 ` [PATCH v2 15/18] GPIO: OMAP: Remove bank->method & METHOD_* macros Tarun Kanti DebBarma
@ 2011-06-15 4:23 ` Tarun Kanti DebBarma
2011-06-15 4:23 ` [PATCH v2 17/18] GPIO: OMAP: Use PM runtime framework Tarun Kanti DebBarma
2011-06-15 4:23 ` [PATCH v2 18/18] GPIO: OMAP2+: Clean prepare_for_idle and resume_after_idle Tarun Kanti DebBarma
7 siblings, 0 replies; 23+ messages in thread
From: Tarun Kanti DebBarma @ 2011-06-15 4:23 UTC (permalink / raw)
To: linux-omap; +Cc: khilman, santosh.shilimkar, tony
From: Charulatha V <charu@ti.com>
In all OMAP1 SoCs, the MPUIO bank width is 16 bits. But, in OMAP7xx,
it is wrongly initialised to 32. Fix this.
Signed-off-by: Charulatha V <charu@ti.com>
---
arch/arm/mach-omap1/gpio7xx.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap1/gpio7xx.c b/arch/arm/mach-omap1/gpio7xx.c
index 91a7691..65949c8 100644
--- a/arch/arm/mach-omap1/gpio7xx.c
+++ b/arch/arm/mach-omap1/gpio7xx.c
@@ -52,8 +52,8 @@ static struct omap_gpio_reg_offs omap7xx_mpuio_regs = {
static struct __initdata omap_gpio_platform_data omap7xx_mpu_gpio_config = {
.virtual_irq_start = IH_MPUIO_BASE,
- .bank_width = 32,
.is_mpuio = true,
+ .bank_width = 16,
.bank_stride = 2,
.regs = &omap7xx_mpuio_regs,
};
--
1.6.0.4
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v2 17/18] GPIO: OMAP: Use PM runtime framework
2011-06-15 4:23 [PATCH v2 10/18] GPIO: OMAP: Remove hardcoded offsets in ctxt save/restore Tarun Kanti DebBarma
` (5 preceding siblings ...)
2011-06-15 4:23 ` [PATCH v2 16/18] GPIO: OMAP: Fix bankwidth for OMAP7xx MPUIO Tarun Kanti DebBarma
@ 2011-06-15 4:23 ` Tarun Kanti DebBarma
2011-06-16 18:03 ` Kevin Hilman
2011-06-15 4:23 ` [PATCH v2 18/18] GPIO: OMAP2+: Clean prepare_for_idle and resume_after_idle Tarun Kanti DebBarma
7 siblings, 1 reply; 23+ messages in thread
From: Tarun Kanti DebBarma @ 2011-06-15 4:23 UTC (permalink / raw)
To: linux-omap; +Cc: khilman, santosh.shilimkar, tony
From: Charulatha V <charu@ti.com>
Call runtime pm APIs pm_runtime_get_sync() and pm_runtime_put_sync()
for enabling/disabling clocks appropriately. Remove syscore_ops and
instead use dev_pm_ops now.
Signed-off-by: Charulatha V <charu@ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
---
drivers/gpio/gpio-omap.c | 100 ++++++++++++++++++++++++++++++++++++---------
1 files changed, 80 insertions(+), 20 deletions(-)
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index ea984fd..f5bb469 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -80,6 +80,8 @@ struct gpio_bank {
struct omap_gpio_reg_offs *regs;
};
+static void omap_gpio_mod_init(struct gpio_bank *bank);
+
#define GPIO_INDEX(bank, gpio) (gpio % bank->width)
#define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio))
#define GPIO_MOD_CTRL_BIT BIT(0)
@@ -492,6 +494,22 @@ static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
unsigned long flags;
+ /*
+ * If this is the first gpio_request for the bank,
+ * enable the bank module.
+ */
+ if (!bank->mod_usage) {
+ if (IS_ERR_VALUE(pm_runtime_get_sync(bank->dev) < 0)) {
+ dev_err(bank->dev, "%s: GPIO bank %d "
+ "pm_runtime_get_sync failed\n",
+ __func__, bank->id);
+ return -EINVAL;
+ }
+
+ /* Initialize the gpio bank registers to init time value */
+ omap_gpio_mod_init(bank);
+ }
+
spin_lock_irqsave(&bank->lock, flags);
/* Set trigger to none. You need to enable the desired trigger with
@@ -548,6 +566,18 @@ static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
_reset_gpio(bank, bank->chip.base + offset);
spin_unlock_irqrestore(&bank->lock, flags);
+
+ /*
+ * If this is the last gpio to be freed in the bank,
+ * disable the bank module.
+ */
+ if (!bank->mod_usage) {
+ if (IS_ERR_VALUE(pm_runtime_put_sync(bank->dev) < 0)) {
+ dev_err(bank->dev, "%s: GPIO bank %d "
+ "pm_runtime_put_sync failed\n",
+ __func__, bank->id);
+ }
+ }
}
/*
@@ -572,6 +602,9 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
chained_irq_enter(chip, desc);
bank = irq_get_handler_data(irq);
+
+ pm_runtime_get_sync(bank->dev);
+
isr_reg = bank->base + bank->regs->irqstatus;
if (WARN_ON(!isr_reg))
@@ -640,6 +673,8 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
exit:
if (!unmasked)
chained_irq_exit(chip, desc);
+
+ pm_runtime_put_sync(bank->dev);
}
static void gpio_irq_shutdown(struct irq_data *d)
@@ -1120,12 +1155,25 @@ static int __devinit omap_gpio_probe(struct platform_device *pdev)
}
pm_runtime_enable(bank->dev);
- pm_runtime_get_sync(bank->dev);
+ pm_runtime_irq_safe(bank->dev);
+ if (IS_ERR_VALUE(pm_runtime_get_sync(bank->dev) < 0)) {
+ dev_err(bank->dev, "%s: GPIO bank %d pm_runtime_get_sync "
+ "failed\n", __func__, bank->id);
+ iounmap(bank->base);
+ return -EINVAL;
+ }
omap_gpio_mod_init(bank);
omap_gpio_chip_init(bank);
omap_gpio_show_rev(bank);
+ if (IS_ERR_VALUE(pm_runtime_put_sync(bank->dev) < 0)) {
+ dev_err(bank->dev, "%s: GPIO bank %d pm_runtime_put_sync "
+ "failed\n", __func__, bank->id);
+ iounmap(bank->base);
+ return -EINVAL;
+ }
+
list_add_tail(&bank->node, &omap_gpio_list);
return ret;
@@ -1136,7 +1184,7 @@ err_exit:
return ret;
}
-static int omap_gpio_suspend(void)
+static int omap_gpio_suspend(struct device *dev)
{
struct gpio_bank *bank;
@@ -1163,7 +1211,7 @@ static int omap_gpio_suspend(void)
return 0;
}
-static void omap_gpio_resume(void)
+static int omap_gpio_resume(struct device *dev)
{
struct gpio_bank *bank;
@@ -1173,7 +1221,7 @@ static void omap_gpio_resume(void)
unsigned long flags;
if (!bank->suspend_support)
- return;
+ return 0;
wake_clear = bank->base + bank->regs->wkup_clear;
wake_set = bank->base + bank->regs->wkup_set;
@@ -1183,12 +1231,18 @@ static void omap_gpio_resume(void)
__raw_writel(bank->saved_wakeup, wake_set);
spin_unlock_irqrestore(&bank->lock, flags);
}
+ return 0;
}
-static struct syscore_ops omap_gpio_syscore_ops = {
- .suspend = omap_gpio_suspend,
- .resume = omap_gpio_resume,
-};
+static int omap_gpio_pm_runtime_suspend(struct device *dev)
+{
+ return 0;
+}
+
+static int omap_gpio_pm_runtime_resume(struct device *dev)
+{
+ return 0;
+}
#ifdef CONFIG_ARCH_OMAP2PLUS
@@ -1212,6 +1266,11 @@ void omap2_gpio_prepare_for_idle(int off_mode)
if (!off_mode)
continue;
+ if (IS_ERR_VALUE(pm_runtime_put_sync(bank->dev) < 0))
+ dev_err(bank->dev, "%s: GPIO bank %d "
+ "pm_runtime_put_sync failed\n",
+ __func__, bank->id);
+
/* If going to OFF, remove triggering for all
* non-wakeup GPIOs. Otherwise spurious IRQs will be
* generated. See OMAP2420 Errata item 1.101. */
@@ -1252,6 +1311,11 @@ void omap2_gpio_resume_after_idle(void)
if (!bank->loses_context)
continue;
+ if (IS_ERR_VALUE(pm_runtime_get_sync(bank->dev) < 0))
+ dev_err(bank->dev, "%s: GPIO bank %d "
+ "pm_runtime_get_sync failed\n",
+ __func__, bank->id);
+
for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
clk_enable(bank->dbck);
@@ -1366,10 +1430,18 @@ void omap_gpio_restore_context(struct gpio_bank *bank)
}
#endif
+static const struct dev_pm_ops gpio_pm_ops = {
+ .runtime_suspend = omap_gpio_pm_runtime_suspend,
+ .runtime_resume = omap_gpio_pm_runtime_resume,
+ .suspend = omap_gpio_suspend,
+ .resume = omap_gpio_resume,
+};
+
static struct platform_driver omap_gpio_driver = {
.probe = omap_gpio_probe,
.driver = {
.name = "omap_gpio",
+ .pm = &gpio_pm_ops,
},
};
@@ -1384,15 +1456,3 @@ static int __init omap_gpio_drv_reg(void)
}
postcore_initcall(omap_gpio_drv_reg);
-static int __init omap_gpio_sysinit(void)
-{
-
-#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
- if (cpu_is_omap16xx() || cpu_class_is_omap2())
- register_syscore_ops(&omap_gpio_syscore_ops);
-#endif
-
- return 0;
-}
-
-arch_initcall(omap_gpio_sysinit);
--
1.6.0.4
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [PATCH v2 17/18] GPIO: OMAP: Use PM runtime framework
2011-06-15 4:23 ` [PATCH v2 17/18] GPIO: OMAP: Use PM runtime framework Tarun Kanti DebBarma
@ 2011-06-16 18:03 ` Kevin Hilman
2011-06-17 5:00 ` DebBarma, Tarun Kanti
0 siblings, 1 reply; 23+ messages in thread
From: Kevin Hilman @ 2011-06-16 18:03 UTC (permalink / raw)
To: Tarun Kanti DebBarma; +Cc: linux-omap, santosh.shilimkar, tony
Tarun Kanti DebBarma <tarun.kanti@ti.com> writes:
> From: Charulatha V <charu@ti.com>
>
> Call runtime pm APIs pm_runtime_get_sync() and pm_runtime_put_sync()
> for enabling/disabling clocks appropriately. Remove syscore_ops and
> instead use dev_pm_ops now.
>
> Signed-off-by: Charulatha V <charu@ti.com>
> Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
Approach is fine. some minor comments below..
> ---
> drivers/gpio/gpio-omap.c | 100 ++++++++++++++++++++++++++++++++++++---------
> 1 files changed, 80 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
> index ea984fd..f5bb469 100644
> --- a/drivers/gpio/gpio-omap.c
> +++ b/drivers/gpio/gpio-omap.c
> @@ -80,6 +80,8 @@ struct gpio_bank {
> struct omap_gpio_reg_offs *regs;
> };
>
> +static void omap_gpio_mod_init(struct gpio_bank *bank);
> +
> #define GPIO_INDEX(bank, gpio) (gpio % bank->width)
> #define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio))
> #define GPIO_MOD_CTRL_BIT BIT(0)
> @@ -492,6 +494,22 @@ static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
> struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
> unsigned long flags;
>
> + /*
> + * If this is the first gpio_request for the bank,
> + * enable the bank module.
> + */
> + if (!bank->mod_usage) {
> + if (IS_ERR_VALUE(pm_runtime_get_sync(bank->dev) < 0)) {
> + dev_err(bank->dev, "%s: GPIO bank %d "
> + "pm_runtime_get_sync failed\n",
> + __func__, bank->id);
> + return -EINVAL;
> + }
> +
> + /* Initialize the gpio bank registers to init time value */
> + omap_gpio_mod_init(bank);
> + }
> +
> spin_lock_irqsave(&bank->lock, flags);
>
> /* Set trigger to none. You need to enable the desired trigger with
> @@ -548,6 +566,18 @@ static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
>
> _reset_gpio(bank, bank->chip.base + offset);
> spin_unlock_irqrestore(&bank->lock, flags);
> +
> + /*
> + * If this is the last gpio to be freed in the bank,
> + * disable the bank module.
> + */
> + if (!bank->mod_usage) {
> + if (IS_ERR_VALUE(pm_runtime_put_sync(bank->dev) < 0)) {
> + dev_err(bank->dev, "%s: GPIO bank %d "
> + "pm_runtime_put_sync failed\n",
> + __func__, bank->id);
> + }
> + }
> }
>
> /*
> @@ -572,6 +602,9 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
> chained_irq_enter(chip, desc);
>
> bank = irq_get_handler_data(irq);
> +
> + pm_runtime_get_sync(bank->dev);
> +
> isr_reg = bank->base + bank->regs->irqstatus;
>
> if (WARN_ON(!isr_reg))
> @@ -640,6 +673,8 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
> exit:
> if (!unmasked)
> chained_irq_exit(chip, desc);
> +
> + pm_runtime_put_sync(bank->dev);
> }
>
> static void gpio_irq_shutdown(struct irq_data *d)
> @@ -1120,12 +1155,25 @@ static int __devinit omap_gpio_probe(struct platform_device *pdev)
> }
>
> pm_runtime_enable(bank->dev);
> - pm_runtime_get_sync(bank->dev);
> + pm_runtime_irq_safe(bank->dev);
> + if (IS_ERR_VALUE(pm_runtime_get_sync(bank->dev) < 0)) {
> + dev_err(bank->dev, "%s: GPIO bank %d pm_runtime_get_sync "
> + "failed\n", __func__, bank->id);
> + iounmap(bank->base);
> + return -EINVAL;
> + }
>
> omap_gpio_mod_init(bank);
> omap_gpio_chip_init(bank);
> omap_gpio_show_rev(bank);
>
> + if (IS_ERR_VALUE(pm_runtime_put_sync(bank->dev) < 0)) {
> + dev_err(bank->dev, "%s: GPIO bank %d pm_runtime_put_sync "
> + "failed\n", __func__, bank->id);
> + iounmap(bank->base);
> + return -EINVAL;
> + }
> +
> list_add_tail(&bank->node, &omap_gpio_list);
>
> return ret;
> @@ -1136,7 +1184,7 @@ err_exit:
> return ret;
> }
>
> -static int omap_gpio_suspend(void)
> +static int omap_gpio_suspend(struct device *dev)
> {
> struct gpio_bank *bank;
>
> @@ -1163,7 +1211,7 @@ static int omap_gpio_suspend(void)
> return 0;
> }
>
> -static void omap_gpio_resume(void)
> +static int omap_gpio_resume(struct device *dev)
> {
> struct gpio_bank *bank;
>
> @@ -1173,7 +1221,7 @@ static void omap_gpio_resume(void)
> unsigned long flags;
>
> if (!bank->suspend_support)
> - return;
> + return 0;
>
> wake_clear = bank->base + bank->regs->wkup_clear;
> wake_set = bank->base + bank->regs->wkup_set;
> @@ -1183,12 +1231,18 @@ static void omap_gpio_resume(void)
> __raw_writel(bank->saved_wakeup, wake_set);
> spin_unlock_irqrestore(&bank->lock, flags);
> }
> + return 0;
> }
>
> -static struct syscore_ops omap_gpio_syscore_ops = {
> - .suspend = omap_gpio_suspend,
> - .resume = omap_gpio_resume,
> -};
> +static int omap_gpio_pm_runtime_suspend(struct device *dev)
Please drop the 'pm_' in these function names.
> +{
> + return 0;
> +}
> +
> +static int omap_gpio_pm_runtime_resume(struct device *dev)
> +{
> + return 0;
> +}
Actually, empty functions should not even be added. Just add them in
the patch that uses them.
Kevin
^ permalink raw reply [flat|nested] 23+ messages in thread* RE: [PATCH v2 17/18] GPIO: OMAP: Use PM runtime framework
2011-06-16 18:03 ` Kevin Hilman
@ 2011-06-17 5:00 ` DebBarma, Tarun Kanti
0 siblings, 0 replies; 23+ messages in thread
From: DebBarma, Tarun Kanti @ 2011-06-17 5:00 UTC (permalink / raw)
To: Hilman, Kevin
Cc: linux-omap@vger.kernel.org, Shilimkar, Santosh, tony@atomide.com
> -----Original Message-----
> From: Hilman, Kevin
> Sent: Thursday, June 16, 2011 11:33 PM
> To: DebBarma, Tarun Kanti
> Cc: linux-omap@vger.kernel.org; Shilimkar, Santosh; tony@atomide.com
> Subject: Re: [PATCH v2 17/18] GPIO: OMAP: Use PM runtime framework
>
> Tarun Kanti DebBarma <tarun.kanti@ti.com> writes:
>
> > From: Charulatha V <charu@ti.com>
> >
> > Call runtime pm APIs pm_runtime_get_sync() and pm_runtime_put_sync()
> > for enabling/disabling clocks appropriately. Remove syscore_ops and
> > instead use dev_pm_ops now.
> >
> > Signed-off-by: Charulatha V <charu@ti.com>
> > Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
>
> Approach is fine. some minor comments below..
>
> > ---
> > drivers/gpio/gpio-omap.c | 100 ++++++++++++++++++++++++++++++++++++---
> ------
> > 1 files changed, 80 insertions(+), 20 deletions(-)
> >
> > diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
> > index ea984fd..f5bb469 100644
> > --- a/drivers/gpio/gpio-omap.c
> > +++ b/drivers/gpio/gpio-omap.c
> > @@ -80,6 +80,8 @@ struct gpio_bank {
> > struct omap_gpio_reg_offs *regs;
> > };
> >
> > +static void omap_gpio_mod_init(struct gpio_bank *bank);
> > +
> > #define GPIO_INDEX(bank, gpio) (gpio % bank->width)
> > #define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio))
> > #define GPIO_MOD_CTRL_BIT BIT(0)
> > @@ -492,6 +494,22 @@ static int omap_gpio_request(struct gpio_chip
> *chip, unsigned offset)
> > struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
> > unsigned long flags;
> >
> > + /*
> > + * If this is the first gpio_request for the bank,
> > + * enable the bank module.
> > + */
> > + if (!bank->mod_usage) {
> > + if (IS_ERR_VALUE(pm_runtime_get_sync(bank->dev) < 0)) {
> > + dev_err(bank->dev, "%s: GPIO bank %d "
> > + "pm_runtime_get_sync failed\n",
> > + __func__, bank->id);
> > + return -EINVAL;
> > + }
> > +
> > + /* Initialize the gpio bank registers to init time value */
> > + omap_gpio_mod_init(bank);
> > + }
> > +
> > spin_lock_irqsave(&bank->lock, flags);
> >
> > /* Set trigger to none. You need to enable the desired trigger with
> > @@ -548,6 +566,18 @@ static void omap_gpio_free(struct gpio_chip *chip,
> unsigned offset)
> >
> > _reset_gpio(bank, bank->chip.base + offset);
> > spin_unlock_irqrestore(&bank->lock, flags);
> > +
> > + /*
> > + * If this is the last gpio to be freed in the bank,
> > + * disable the bank module.
> > + */
> > + if (!bank->mod_usage) {
> > + if (IS_ERR_VALUE(pm_runtime_put_sync(bank->dev) < 0)) {
> > + dev_err(bank->dev, "%s: GPIO bank %d "
> > + "pm_runtime_put_sync failed\n",
> > + __func__, bank->id);
> > + }
> > + }
> > }
> >
> > /*
> > @@ -572,6 +602,9 @@ static void gpio_irq_handler(unsigned int irq,
> struct irq_desc *desc)
> > chained_irq_enter(chip, desc);
> >
> > bank = irq_get_handler_data(irq);
> > +
> > + pm_runtime_get_sync(bank->dev);
> > +
> > isr_reg = bank->base + bank->regs->irqstatus;
> >
> > if (WARN_ON(!isr_reg))
> > @@ -640,6 +673,8 @@ static void gpio_irq_handler(unsigned int irq,
> struct irq_desc *desc)
> > exit:
> > if (!unmasked)
> > chained_irq_exit(chip, desc);
> > +
> > + pm_runtime_put_sync(bank->dev);
> > }
> >
> > static void gpio_irq_shutdown(struct irq_data *d)
> > @@ -1120,12 +1155,25 @@ static int __devinit omap_gpio_probe(struct
> platform_device *pdev)
> > }
> >
> > pm_runtime_enable(bank->dev);
> > - pm_runtime_get_sync(bank->dev);
> > + pm_runtime_irq_safe(bank->dev);
> > + if (IS_ERR_VALUE(pm_runtime_get_sync(bank->dev) < 0)) {
> > + dev_err(bank->dev, "%s: GPIO bank %d pm_runtime_get_sync "
> > + "failed\n", __func__, bank->id);
> > + iounmap(bank->base);
> > + return -EINVAL;
> > + }
> >
> > omap_gpio_mod_init(bank);
> > omap_gpio_chip_init(bank);
> > omap_gpio_show_rev(bank);
> >
> > + if (IS_ERR_VALUE(pm_runtime_put_sync(bank->dev) < 0)) {
> > + dev_err(bank->dev, "%s: GPIO bank %d pm_runtime_put_sync "
> > + "failed\n", __func__, bank->id);
> > + iounmap(bank->base);
> > + return -EINVAL;
> > + }
> > +
> > list_add_tail(&bank->node, &omap_gpio_list);
> >
> > return ret;
> > @@ -1136,7 +1184,7 @@ err_exit:
> > return ret;
> > }
> >
> > -static int omap_gpio_suspend(void)
> > +static int omap_gpio_suspend(struct device *dev)
> > {
> > struct gpio_bank *bank;
> >
> > @@ -1163,7 +1211,7 @@ static int omap_gpio_suspend(void)
> > return 0;
> > }
> >
> > -static void omap_gpio_resume(void)
> > +static int omap_gpio_resume(struct device *dev)
> > {
> > struct gpio_bank *bank;
> >
> > @@ -1173,7 +1221,7 @@ static void omap_gpio_resume(void)
> > unsigned long flags;
> >
> > if (!bank->suspend_support)
> > - return;
> > + return 0;
> >
> > wake_clear = bank->base + bank->regs->wkup_clear;
> > wake_set = bank->base + bank->regs->wkup_set;
> > @@ -1183,12 +1231,18 @@ static void omap_gpio_resume(void)
> > __raw_writel(bank->saved_wakeup, wake_set);
> > spin_unlock_irqrestore(&bank->lock, flags);
> > }
> > + return 0;
> > }
> >
> > -static struct syscore_ops omap_gpio_syscore_ops = {
> > - .suspend = omap_gpio_suspend,
> > - .resume = omap_gpio_resume,
> > -};
> > +static int omap_gpio_pm_runtime_suspend(struct device *dev)
>
> Please drop the 'pm_' in these function names.
OK.
>
> > +{
> > + return 0;
> > +}
> > +
> > +static int omap_gpio_pm_runtime_resume(struct device *dev)
> > +{
> > + return 0;
> > +}
>
> Actually, empty functions should not even be added. Just add them in
> the patch that uses them.
OK.
--
Tarun
>
> Kevin
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 18/18] GPIO: OMAP2+: Clean prepare_for_idle and resume_after_idle
2011-06-15 4:23 [PATCH v2 10/18] GPIO: OMAP: Remove hardcoded offsets in ctxt save/restore Tarun Kanti DebBarma
` (6 preceding siblings ...)
2011-06-15 4:23 ` [PATCH v2 17/18] GPIO: OMAP: Use PM runtime framework Tarun Kanti DebBarma
@ 2011-06-15 4:23 ` Tarun Kanti DebBarma
2011-06-16 18:10 ` Kevin Hilman
7 siblings, 1 reply; 23+ messages in thread
From: Tarun Kanti DebBarma @ 2011-06-15 4:23 UTC (permalink / raw)
To: linux-omap; +Cc: khilman, santosh.shilimkar, tony
Simplify omap2_gpio_prepare_for_idle() and omap2_gpio_resume_after_idle()
by moving most of the stuff to *_pm_runtime_suspend() and *_pm_runtime_resume().
Also, omap_gpio_suspend() and omap_gpio_resume() optimized to operate per
GPIO bank instead of operating on entire list every time.
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
Signed-off-by: Charulatha V <charu@ti.com>
---
drivers/gpio/gpio-omap.c | 306 ++++++++++++++++++++++++----------------------
1 files changed, 159 insertions(+), 147 deletions(-)
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index f5bb469..320a169 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -1154,6 +1154,8 @@ static int __devinit omap_gpio_probe(struct platform_device *pdev)
goto err_free;
}
+ platform_set_drvdata(pdev, bank);
+
pm_runtime_enable(bank->dev);
pm_runtime_irq_safe(bank->dev);
if (IS_ERR_VALUE(pm_runtime_get_sync(bank->dev) < 0)) {
@@ -1186,116 +1188,199 @@ err_exit:
static int omap_gpio_suspend(struct device *dev)
{
- struct gpio_bank *bank;
+ struct platform_device *pdev = to_platform_device(dev);
+ struct gpio_bank *bank = platform_get_drvdata(pdev);
+ void __iomem *wake_status;
+ void __iomem *wake_clear;
+ void __iomem *wake_set;
+ unsigned long flags;
- list_for_each_entry(bank, &omap_gpio_list, node) {
- void __iomem *wake_status;
- void __iomem *wake_clear;
- void __iomem *wake_set;
- unsigned long flags;
-
- if (!bank->suspend_support)
- return 0;
-
- wake_status = bank->base + bank->regs->wkup_status;
- wake_clear = bank->base + bank->regs->wkup_clear;
- wake_set = bank->base + bank->regs->wkup_set;
-
- spin_lock_irqsave(&bank->lock, flags);
- bank->saved_wakeup = __raw_readl(wake_status);
- __raw_writel(0xffffffff, wake_clear);
- __raw_writel(bank->suspend_wakeup, wake_set);
- spin_unlock_irqrestore(&bank->lock, flags);
- }
+ if (!bank->suspend_support)
+ return 0;
+
+ wake_status = bank->base + bank->regs->wkup_status;
+ wake_clear = bank->base + bank->regs->wkup_clear;
+ wake_set = bank->base + bank->regs->wkup_set;
+
+ pm_runtime_get_sync(dev);
+
+ spin_lock_irqsave(&bank->lock, flags);
+ bank->saved_wakeup = __raw_readl(wake_status);
+ __raw_writel(0xffffffff, wake_clear);
+ __raw_writel(bank->suspend_wakeup, wake_set);
+ spin_unlock_irqrestore(&bank->lock, flags);
+
+ pm_runtime_put_sync(dev);
return 0;
}
static int omap_gpio_resume(struct device *dev)
{
- struct gpio_bank *bank;
+ struct platform_device *pdev = to_platform_device(dev);
+ struct gpio_bank *bank = platform_get_drvdata(pdev);
+ void __iomem *wake_clear;
+ void __iomem *wake_set;
+ unsigned long flags;
- list_for_each_entry(bank, &omap_gpio_list, node) {
- void __iomem *wake_clear;
- void __iomem *wake_set;
- unsigned long flags;
+ if (!bank->suspend_support)
+ return 0;
- if (!bank->suspend_support)
- return 0;
+ wake_clear = bank->base + bank->regs->wkup_clear;
+ wake_set = bank->base + bank->regs->wkup_set;
- wake_clear = bank->base + bank->regs->wkup_clear;
- wake_set = bank->base + bank->regs->wkup_set;
+ pm_runtime_get_sync(dev);
+
+ spin_lock_irqsave(&bank->lock, flags);
+ __raw_writel(0xffffffff, wake_clear);
+ __raw_writel(bank->saved_wakeup, wake_set);
+ spin_unlock_irqrestore(&bank->lock, flags);
+
+ pm_runtime_put_sync(dev);
- spin_lock_irqsave(&bank->lock, flags);
- __raw_writel(0xffffffff, wake_clear);
- __raw_writel(bank->saved_wakeup, wake_set);
- spin_unlock_irqrestore(&bank->lock, flags);
- }
return 0;
}
+#ifdef CONFIG_ARCH_OMAP2PLUS
+static void omap_gpio_save_context(struct gpio_bank *bank);
+static void omap_gpio_restore_context(struct gpio_bank *bank);
+#endif
+
static int omap_gpio_pm_runtime_suspend(struct device *dev)
{
+#ifdef CONFIG_ARCH_OMAP2PLUS
+ struct platform_device *pdev = to_platform_device(dev);
+ struct gpio_bank *bank = platform_get_drvdata(pdev);
+ u32 l1 = 0, l2 = 0;
+ int j;
+
+ for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
+ clk_disable(bank->dbck);
+
+ /* If going to OFF, remove triggering for all
+ * non-wakeup GPIOs. Otherwise spurious IRQs will be
+ * generated. See OMAP2420 Errata item 1.101. */
+ if (!(bank->enabled_non_wakeup_gpios))
+ goto save_gpio_ctx;
+
+ bank->saved_datain = __raw_readl(bank->base +
+ bank->regs->datain);
+ l1 = __raw_readl(bank->base + bank->regs->fallingdetect);
+ l2 = __raw_readl(bank->base + bank->regs->risingdetect);
+
+ bank->saved_fallingdetect = l1;
+ bank->saved_risingdetect = l2;
+ l1 &= ~bank->enabled_non_wakeup_gpios;
+ l2 &= ~bank->enabled_non_wakeup_gpios;
+
+ __raw_writel(l1, bank->base + bank->regs->fallingdetect);
+ __raw_writel(l2, bank->base + bank->regs->risingdetect);
+
+save_gpio_ctx:
+ if (bank->get_context_loss_count)
+ bank->ctx_loss_count = bank->get_context_loss_count(bank->dev);
+ omap_gpio_save_context(bank);
+#endif
return 0;
}
static int omap_gpio_pm_runtime_resume(struct device *dev)
{
+#ifdef CONFIG_ARCH_OMAP2PLUS
+ struct platform_device *pdev = to_platform_device(dev);
+ struct gpio_bank *bank = platform_get_drvdata(pdev);
+ u32 ctx_lost_cnt_after;
+ u32 l = 0, gen, gen0, gen1;
+ int j;
+
+ for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
+ clk_enable(bank->dbck);
+
+ if (bank->get_context_loss_count) {
+ ctx_lost_cnt_after =
+ bank->get_context_loss_count(bank->dev);
+ if (ctx_lost_cnt_after != bank->ctx_loss_count)
+ omap_gpio_restore_context(bank);
+ }
+
+ if (!(bank->enabled_non_wakeup_gpios))
+ return 0;
+
+ __raw_writel(bank->saved_fallingdetect,
+ bank->base + bank->regs->fallingdetect);
+ __raw_writel(bank->saved_risingdetect,
+ bank->base + bank->regs->risingdetect);
+ l = __raw_readl(bank->base + bank->regs->datain);
+
+ /* Check if any of the non-wakeup interrupt GPIOs have changed
+ * state. If so, generate an IRQ by software. This is
+ * horribly racy, but it's the best we can do to work around
+ * this silicon bug. */
+ l ^= bank->saved_datain;
+ l &= bank->enabled_non_wakeup_gpios;
+
+ /*
+ * No need to generate IRQs for the rising edge for gpio IRQs
+ * configured with falling edge only; and vice versa.
+ */
+ gen0 = l & bank->saved_fallingdetect;
+ gen0 &= bank->saved_datain;
+ gen1 = l & bank->saved_risingdetect;
+ gen1 &= ~(bank->saved_datain);
+
+ /* FIXME: Consider GPIO IRQs with level detections properly! */
+ gen = l & (~(bank->saved_fallingdetect) &
+ ~(bank->saved_risingdetect));
+ /* Consider all GPIO IRQs needed to be updated */
+ gen |= gen0 | gen1;
+
+ if (gen) {
+ u32 old0, old1;
+
+ old0 = __raw_readl(bank->base +
+ bank->regs->leveldetect0);
+ old1 = __raw_readl(bank->base +
+ bank->regs->leveldetect1);
+
+ __raw_writel(old0, bank->base +
+ bank->regs->leveldetect0);
+ __raw_writel(old1, bank->base +
+ bank->regs->leveldetect1);
+ if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
+ old0 |= gen;
+ old1 |= gen;
+ }
+
+ if (cpu_is_omap44xx()) {
+ old0 |= l;
+ old1 |= l;
+ }
+ __raw_writel(old0, bank->base +
+ bank->regs->leveldetect0);
+ __raw_writel(old1, bank->base +
+ bank->regs->leveldetect1);
+ }
+#endif
return 0;
}
#ifdef CONFIG_ARCH_OMAP2PLUS
-static void omap_gpio_save_context(struct gpio_bank *bank);
-static void omap_gpio_restore_context(struct gpio_bank *bank);
-
void omap2_gpio_prepare_for_idle(int off_mode)
{
struct gpio_bank *bank;
- list_for_each_entry(bank, &omap_gpio_list, node) {
- u32 l1 = 0, l2 = 0;
- int j;
-
- if (!bank->loses_context)
- continue;
-
- for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
- clk_disable(bank->dbck);
+ if (!off_mode)
+ return;
- if (!off_mode)
+ list_for_each_entry(bank, &omap_gpio_list, node) {
+ if (!bank->mod_usage || !bank->loses_context)
continue;
if (IS_ERR_VALUE(pm_runtime_put_sync(bank->dev) < 0))
dev_err(bank->dev, "%s: GPIO bank %d "
"pm_runtime_put_sync failed\n",
__func__, bank->id);
-
- /* If going to OFF, remove triggering for all
- * non-wakeup GPIOs. Otherwise spurious IRQs will be
- * generated. See OMAP2420 Errata item 1.101. */
- if (!(bank->enabled_non_wakeup_gpios))
- goto save_gpio_ctx;
-
- bank->saved_datain = __raw_readl(bank->base +
- bank->regs->datain);
- l1 = __raw_readl(bank->base + bank->regs->fallingdetect);
- l2 = __raw_readl(bank->base + bank->regs->risingdetect);
-
- bank->saved_fallingdetect = l1;
- bank->saved_risingdetect = l2;
- l1 &= ~bank->enabled_non_wakeup_gpios;
- l2 &= ~bank->enabled_non_wakeup_gpios;
-
- __raw_writel(l1, bank->base + bank->regs->fallingdetect);
- __raw_writel(l2, bank->base + bank->regs->risingdetect);
-
-save_gpio_ctx:
- if (bank->get_context_loss_count)
- bank->ctx_loss_count =
- bank->get_context_loss_count(bank->dev);
-
- omap_gpio_save_context(bank);
}
}
@@ -1304,86 +1389,13 @@ void omap2_gpio_resume_after_idle(void)
struct gpio_bank *bank;
list_for_each_entry(bank, &omap_gpio_list, node) {
- u32 ctx_lost_cnt_after;
- u32 l = 0, gen, gen0, gen1;
- int j;
-
- if (!bank->loses_context)
+ if (!bank->mod_usage || !bank->loses_context)
continue;
if (IS_ERR_VALUE(pm_runtime_get_sync(bank->dev) < 0))
dev_err(bank->dev, "%s: GPIO bank %d "
"pm_runtime_get_sync failed\n",
__func__, bank->id);
-
- for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
- clk_enable(bank->dbck);
-
- if (bank->get_context_loss_count) {
- ctx_lost_cnt_after =
- bank->get_context_loss_count(bank->dev);
- if (ctx_lost_cnt_after != bank->ctx_loss_count)
- omap_gpio_restore_context(bank);
- }
-
- if (!(bank->enabled_non_wakeup_gpios))
- continue;
-
- __raw_writel(bank->saved_fallingdetect,
- bank->base + bank->regs->fallingdetect);
- __raw_writel(bank->saved_risingdetect,
- bank->base + bank->regs->risingdetect);
- l = __raw_readl(bank->base + bank->regs->datain);
-
- /* Check if any of the non-wakeup interrupt GPIOs have changed
- * state. If so, generate an IRQ by software. This is
- * horribly racy, but it's the best we can do to work around
- * this silicon bug. */
- l ^= bank->saved_datain;
- l &= bank->enabled_non_wakeup_gpios;
-
- /*
- * No need to generate IRQs for the rising edge for gpio IRQs
- * configured with falling edge only; and vice versa.
- */
- gen0 = l & bank->saved_fallingdetect;
- gen0 &= bank->saved_datain;
-
- gen1 = l & bank->saved_risingdetect;
- gen1 &= ~(bank->saved_datain);
-
- /* FIXME: Consider GPIO IRQs with level detections properly! */
- gen = l & (~(bank->saved_fallingdetect) &
- ~(bank->saved_risingdetect));
- /* Consider all GPIO IRQs needed to be updated */
- gen |= gen0 | gen1;
-
- if (gen) {
- u32 old0, old1;
-
- old0 = __raw_readl(bank->base +
- bank->regs->leveldetect0);
- old1 = __raw_readl(bank->base +
- bank->regs->leveldetect1);
-
- __raw_writel(old0, bank->base +
- bank->regs->leveldetect0);
- __raw_writel(old1, bank->base +
- bank->regs->leveldetect1);
- if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
- old0 |= gen;
- old1 |= gen;
- }
-
- if (cpu_is_omap44xx()) {
- old0 |= l;
- old1 |= l;
- }
- __raw_writel(old0, bank->base +
- bank->regs->leveldetect0);
- __raw_writel(old1, bank->base +
- bank->regs->leveldetect1);
- }
}
}
--
1.6.0.4
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [PATCH v2 18/18] GPIO: OMAP2+: Clean prepare_for_idle and resume_after_idle
2011-06-15 4:23 ` [PATCH v2 18/18] GPIO: OMAP2+: Clean prepare_for_idle and resume_after_idle Tarun Kanti DebBarma
@ 2011-06-16 18:10 ` Kevin Hilman
2011-06-17 4:57 ` DebBarma, Tarun Kanti
0 siblings, 1 reply; 23+ messages in thread
From: Kevin Hilman @ 2011-06-16 18:10 UTC (permalink / raw)
To: Tarun Kanti DebBarma; +Cc: linux-omap, santosh.shilimkar, tony
Tarun Kanti DebBarma <tarun.kanti@ti.com> writes:
> Simplify omap2_gpio_prepare_for_idle() and omap2_gpio_resume_after_idle()
> by moving most of the stuff to *_pm_runtime_suspend() and *_pm_runtime_resume().
> Also, omap_gpio_suspend() and omap_gpio_resume() optimized to operate per
> GPIO bank instead of operating on entire list every time.
This second part should be a separate patch.
> Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
> Signed-off-by: Charulatha V <charu@ti.com>
[...]
>
> +#ifdef CONFIG_ARCH_OMAP2PLUS
> +static void omap_gpio_save_context(struct gpio_bank *bank);
> +static void omap_gpio_restore_context(struct gpio_bank *bank);
> +#endif
> +
> static int omap_gpio_pm_runtime_suspend(struct device *dev)
> {
> +#ifdef CONFIG_ARCH_OMAP2PLUS
c.f. #ifdefs are ugly in Documentation/SubmittingPatches
Just wrap all of these funcions: runtime PM, save/restore context,
prepare/resume from idle inside the #ifdef. Then have an else
clause with NULL versions of the runtime PM functions.
Kevin
^ permalink raw reply [flat|nested] 23+ messages in thread* RE: [PATCH v2 18/18] GPIO: OMAP2+: Clean prepare_for_idle and resume_after_idle
2011-06-16 18:10 ` Kevin Hilman
@ 2011-06-17 4:57 ` DebBarma, Tarun Kanti
0 siblings, 0 replies; 23+ messages in thread
From: DebBarma, Tarun Kanti @ 2011-06-17 4:57 UTC (permalink / raw)
To: Hilman, Kevin
Cc: linux-omap@vger.kernel.org, Shilimkar, Santosh, tony@atomide.com
[...]
>
> > Simplify omap2_gpio_prepare_for_idle() and
> omap2_gpio_resume_after_idle()
> > by moving most of the stuff to *_pm_runtime_suspend() and
> *_pm_runtime_resume().
> > Also, omap_gpio_suspend() and omap_gpio_resume() optimized to operate
> per
> > GPIO bank instead of operating on entire list every time.
>
> This second part should be a separate patch.
OK.
>
> > Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
> > Signed-off-by: Charulatha V <charu@ti.com>
>
> [...]
>
> >
> > +#ifdef CONFIG_ARCH_OMAP2PLUS
> > +static void omap_gpio_save_context(struct gpio_bank *bank);
> > +static void omap_gpio_restore_context(struct gpio_bank *bank);
> > +#endif
> > +
> > static int omap_gpio_pm_runtime_suspend(struct device *dev)
> > {
> > +#ifdef CONFIG_ARCH_OMAP2PLUS
>
> c.f. #ifdefs are ugly in Documentation/SubmittingPatches
>
> Just wrap all of these funcions: runtime PM, save/restore context,
> prepare/resume from idle inside the #ifdef. Then have an else
> clause with NULL versions of the runtime PM functions.
OK.
--
Tarun
>
> Kevin
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