PM: OMAP3 HS/EMU off-mode support

PM: OMAP3 HS/EMU off-mode support

[Tero Kristo]

This patchset provides off-mode support for OMAP3 HS/EMU devices. Due to
secure environment in these devices, wake-up from off-mode is slightly
different than in GP devices. This code has been tested on following chip
versions: ES2.1GP, ES3.0EMU, ES3.0HS.

[PATCH 1/6] Support for EMU/HS off-mode for DMA

[Tero Kristo]

- DMA interrupt disable routine added
- Added DMA controller reset to DMA context restore

Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
---
 arch/arm/plat-omap/dma.c              |   14 ++++++++++++++
 arch/arm/plat-omap/include/mach/dma.h |    2 ++
 2 files changed, 16 insertions(+), 0 deletions(-)
 mode change 100644 => 100755 arch/arm/plat-omap/dma.c
 mode change 100644 => 100755 arch/arm/plat-omap/include/mach/dma.h

diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
old mode 100644
new mode 100755
index 38c57ce..4d4016f
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -2309,6 +2309,9 @@ EXPORT_SYMBOL(omap_dma_global_context_save);
 
 void omap_dma_global_context_restore(void)
 {
+	dma_write(0x2, OCP_SYSCONFIG);
+	while (!__raw_readl(omap_dma_base + OMAP_DMA4_SYSSTATUS))
+		;
 	dma_write(omap_dma_global_context.dma_gcr, GCR);
 	dma_write(omap_dma_global_context.dma_ocp_sysconfig,
 		OCP_SYSCONFIG);
@@ -2317,6 +2320,17 @@ void omap_dma_global_context_restore(void)
 }
 EXPORT_SYMBOL(omap_dma_global_context_restore);
 
+void omap_dma_disable_irq(int lch)
+{
+	u32 val;
+	if (cpu_class_is_omap2()) {
+		/* Disable interrupts */
+		val = dma_read(IRQENABLE_L0);
+		val &= ~(1 << lch);
+		dma_write(val, IRQENABLE_L0);
+	}
+}
+
 /*----------------------------------------------------------------------------*/
 
 static int __init omap_init_dma(void)
diff --git a/arch/arm/plat-omap/include/mach/dma.h b/arch/arm/plat-omap/include/mach/dma.h
old mode 100644
new mode 100755
index f1f588a..1cd390d
--- a/arch/arm/plat-omap/include/mach/dma.h
+++ b/arch/arm/plat-omap/include/mach/dma.h
@@ -531,6 +531,8 @@ extern int omap_get_dma_index(int lch, int *ei, int *fi);
 void omap_dma_global_context_save(void);
 void omap_dma_global_context_restore(void);
 
+extern void omap_dma_disable_irq(int lch);
+
 /* Chaining APIs */
 #ifndef CONFIG_ARCH_OMAP1
 extern int omap_request_dma_chain(int dev_id, const char *dev_name,
-- 
1.5.4.3

[PATCH 2/6] HS/EMU OMAP3 SRAM size fix

[Tero Kristo]

Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
---
 arch/arm/plat-omap/sram.c |   12 +++++++++---
 1 files changed, 9 insertions(+), 3 deletions(-)
 mode change 100644 => 100755 arch/arm/plat-omap/sram.c

diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
old mode 100644
new mode 100755
index 9cfb77f..f0ac426
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -125,9 +125,15 @@ void __init omap_detect_sram(void)
 	if (cpu_class_is_omap2()) {
 		if (is_sram_locked()) {
 			if (cpu_is_omap34xx()) {
-				omap_sram_base = OMAP3_SRAM_PUB_VA;
-				omap_sram_start = OMAP3_SRAM_PUB_PA;
-				omap_sram_size = 0x8000; /* 32K */
+				if (omap_type() == OMAP2_DEVICE_TYPE_GP) {
+					omap_sram_base = OMAP3_SRAM_PUB_VA;
+					omap_sram_start = OMAP3_SRAM_PUB_PA;
+					omap_sram_size = 0x8000; /* 32K */
+				} else {
+					omap_sram_base = OMAP3_SRAM_PUB_VA;
+					omap_sram_start = OMAP3_SRAM_PUB_PA;
+					omap_sram_size = 0x7000; /* 28K */
+				}
 			} else {
 				omap_sram_base = OMAP2_SRAM_PUB_VA;
 				omap_sram_start = OMAP2_SRAM_PUB_PA;
-- 
1.5.4.3

[PATCH 3/6] PM: OMAP3 HS/EMU off-mode support

[Tero Kristo]

Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
---
 arch/arm/mach-omap2/pm34xx.c         |   58 +++++++++++++++++++++++++-
 arch/arm/mach-omap2/sleep34xx.S      |   74 ++++++++++++++++++++++++++++++++++
 arch/arm/plat-omap/include/mach/pm.h |    2 +
 3 files changed, 132 insertions(+), 2 deletions(-)
 mode change 100644 => 100755 arch/arm/mach-omap2/pm34xx.c
 mode change 100644 => 100755 arch/arm/mach-omap2/sleep34xx.S
 mode change 100644 => 100755 arch/arm/plat-omap/include/mach/pm.h

diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
old mode 100644
new mode 100755
index 9d97dd6..d5892c5
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -31,6 +31,7 @@
 #include <mach/powerdomain.h>
 #include <mach/common.h>
 #include <mach/sdrc.h>
+#include <mach/dma.h>
 #include <asm/tlbflush.h>
 #include "sdrc.h"
 
@@ -55,6 +56,11 @@ struct power_state {
 	struct list_head node;
 };
 
+struct sram_mem {
+	u32 i[32000];
+};
+struct sram_mem *sdram_mem;
+
 u32 *scratchpad_restore_addr;
 u32 restore_pointer_address;
 
@@ -62,6 +68,8 @@ static LIST_HEAD(pwrst_list);
 
 void (*_omap_sram_idle)(u32 *addr, int save_state);
 
+static int (*_omap_save_secure_sram)(u32 *addr);
+
 static void (*saved_idle)(void);
 
 static struct powerdomain *mpu_pwrdm;
@@ -208,6 +216,32 @@ static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
 	return IRQ_HANDLED;
 }
 
+void omap3_save_secure_ram_context(u32 target_mpu_state)
+{
+	u32 ret;
+
+	if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
+		/* Disable dma irq before calling secure rom code API */
+		omap_dma_disable_irq(0);
+		omap_dma_disable_irq(1);
+		/*
+		 * MPU next state must be set to POWER_ON temporarily,
+		 * otherwise the WFI executed inside the ROM code
+		 * will hang the system.
+		 */
+		pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
+		ret = _omap_save_secure_sram((u32 *)__pa(sdram_mem));
+		pwrdm_set_next_pwrst(mpu_pwrdm, target_mpu_state);
+		/* Following is for error tracking, it should not happen */
+		if (ret) {
+			printk(KERN_ERR "save_secure_sram() returns %08x\n",
+				ret);
+			while (1)
+				;
+		}
+	}
+}
+
 static void restore_control_register(u32 val)
 {
 	__asm__ __volatile__ ("mcr p15, 0, %0, c1, c0, 0" : : "r" (val));
@@ -249,6 +283,7 @@ void omap_sram_idle(void)
 	int mpu_next_state = PWRDM_POWER_ON, core_next_state = PWRDM_POWER_ON,
 		per_next_state = PWRDM_POWER_ON;
 	int mpu_prev_state, core_prev_state, per_prev_state;
+	u32 sdrc_pwr;
 
 	if (!_omap_sram_idle)
 		return;
@@ -304,6 +339,7 @@ void omap_sram_idle(void)
 			omap3_save_core_ctx();
 			omap_save_uart_ctx(0);
 			omap_save_uart_ctx(1);
+			omap3_save_secure_ram_context(mpu_next_state);
 		}
 		omap_serial_enable_clocks(0, 0);
 		omap_serial_enable_clocks(0, 1);
@@ -809,6 +845,9 @@ void omap_push_sram_idle()
 {
 	_omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend,
 					omap34xx_cpu_suspend_sz);
+	if (omap_type() != OMAP2_DEVICE_TYPE_GP)
+		_omap_save_secure_sram = omap_sram_push(save_secure_ram_context,
+				save_secure_ram_context_sz);
 }
 
 int __init omap3_pm_init(void)
@@ -822,7 +861,6 @@ int __init omap3_pm_init(void)
 	/* XXX prcm_setup_regs needs to be before enabling hw
 	 * supervised mode for powerdomains */
 	prcm_setup_regs();
-	save_scratchpad_contents();
 
 	ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
 			  (irq_handler_t)prcm_interrupt_handler,
@@ -867,6 +905,19 @@ int __init omap3_pm_init(void)
 	pwrdm_add_wkdep(neon_pwrdm, mpu_pwrdm);
 	pwrdm_add_wkdep(per_pwrdm, core_pwrdm);
 
+	if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
+		sdram_mem = kmalloc(sizeof(struct sram_mem), GFP_KERNEL);
+		if (!sdram_mem)
+			printk(KERN_ERR "Memory allocation failed when"
+				"allocating for secure sram context\n");
+	}
+	save_scratchpad_contents();
+
+	printk(KERN_INFO "system_rev=%08x\n", system_rev);
+	if (omap_type() == OMAP2_DEVICE_TYPE_GP)
+		printk(KERN_INFO "GP device\n");
+	else
+		printk(KERN_INFO "non-GP device\n");
 err1:
 	return ret;
 err2:
@@ -921,7 +972,10 @@ void save_scratchpad_contents(void)
 	restore_pointer_address = (u32) restore_address;
 	*(scratchpad_address++) = 0x0;
 	/* Secure ram restore pointer */
-	*(scratchpad_address++) = 0x0;
+	if (omap_type() == OMAP2_DEVICE_TYPE_GP)
+		*(scratchpad_address++) = 0x0;
+	else
+		*(scratchpad_address++) = (u32) __pa(sdram_mem);
 	/* SDRC Module semaphore */
 	*(scratchpad_address++) = 0x0;
 	/* PRCM Block Offset */
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
old mode 100644
new mode 100755
index efafa7e..a2bdab2
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -38,6 +38,8 @@
 #define PM_PREPWSTST_MPU_V	OMAP34XX_PRM_REGADDR(MPU_MOD, \
 				OMAP3430_PM_PREPWSTST)
 #define PM_PWSTCTRL_MPU_P	0x483069E0
+#define SRAM_BASE_P		0x40200000
+#define CONTROL_STAT		0x480022F0
 #define SCRATCHPAD_MEM_OFFS	0x310 /* Move this as correct place is
 				       * available */
 #define SCRATCHPAD_BASE_P	0x48002910
@@ -51,6 +53,40 @@ ENTRY(get_restore_pointer)
         ldmfd   sp!, {pc}     @ restore regs and return
 ENTRY(get_restore_pointer_sz)
         .word   . - get_restore_pointer_sz
+
+/* Function to call rom code to save secure ram context */
+ENTRY(save_secure_ram_context)
+	stmfd	sp!, {r1-r12, lr}	@ save registers on stack
+save_secure_ram_debug:
+	/* b save_secure_ram_debug */	@ enable to debug save code
+	adr	r3, api_params		@ r3 points to parameters
+	str	r0, [r3,#0x4]		@ r0 has sdram address
+	ldr	r12, high_mask
+	and	r3, r3, r12
+	ldr	r12, sram_phy_addr_mask
+	orr	r3, r3, r12
+	mov	r0, #25			@ set service ID for PPA
+	mov	r12, r0			@ copy secure Service ID in r12
+	mov	r1, #0			@ set task id for ROM code in r1
+	mov	r2, #7			@ set some flags in r2, r6
+	mov	r6, #0xff
+	mcr	p15, 0, r0, c7, c10, 4	@ data write barrier
+	mcr	p15, 0, r0, c7, c10, 5	@ data memory barrier
+	.word	0xE1600071		@ call SMI monitor (smi #1)
+	nop
+	nop
+	nop
+	nop
+	ldmfd	sp!, {r1-r12, pc}
+sram_phy_addr_mask:
+	.word	SRAM_BASE_P
+high_mask:
+	.word	0xffff
+api_params:
+	.word	0x4, 0x0, 0x0, 0x1, 0x1
+ENTRY(save_secure_ram_context_sz)
+	.word	. - save_secure_ram_context
+
 /*
  * Forces OMAP into idle state
  *
@@ -107,9 +143,45 @@ restore:
         moveq   r9, #0x3        @ MPU OFF => L1 and L2 lost
 	movne	r9, #0x1	@ Only L1 and L2 lost => avoid L2 invalidation
 	bne	logic_l1_restore
+
+	ldr	r0, control_stat
+	ldr	r1, [r0]
+	and	r1, #0x700
+	cmp	r1, #0x300
+	beq	l2_inv_gp
+	mov	r0, #40		@ set service ID for PPA
+	mov	r12, r0		@ copy secure Service ID in r12
+	mov	r1, #0		@ set task id for ROM code in r1
+	mov	r2, #4		@ set some flags in r2, r6
+	mov	r6, #0xff
+	adr	r3, l2_inv_api_params	@ r3 points to dummy parameters
+	mcr	p15, 0, r0, c7, c10, 4	@ data write barrier
+	mcr	p15, 0, r0, c7, c10, 5	@ data memory barrier
+	.word	0xE1600071		@ call SMI monitor (smi #1)
+	/* Write to Aux control register to set some bits */
+	mov	r0, #42		@ set service ID for PPA
+	mov	r12, r0		@ copy secure Service ID in r12
+	mov	r1, #0		@ set task id for ROM code in r1
+	mov	r2, #4		@ set some flags in r2, r6
+	mov	r6, #0xff
+	adr	r3, write_aux_control_params	@ r3 points to parameters
+	mcr	p15, 0, r0, c7, c10, 4	@ data write barrier
+	mcr	p15, 0, r0, c7, c10, 5	@ data memory barrier
+	.word	0xE1600071		@ call SMI monitor (smi #1)
+
+	b	logic_l1_restore
+l2_inv_api_params:
+	.word	0x1, 0x00
+write_aux_control_params:
+	.word	0x1, 0x72
+l2_inv_gp:
 	/* Execute smi to invalidate L2 cache */
 	mov r12, #0x1                         @ set up to invalide L2
 smi:    .word 0xE1600070                @ Call SMI monitor (smieq)
+	/* Write to Aux control register to set some bits */
+	mov	r0, #0x72
+	mov	r12, #0x3
+	.word 0xE1600070		@ Call SMI monitor (smieq)
 logic_l1_restore:
 	mov	r1, #0
 	/* Invalidate all instruction caches to PoU
@@ -540,5 +612,7 @@ table_entry:
 	.word	0x00000C02
 cache_pred_disable_mask:
 	.word	0xFFFFE7FB
+control_stat:
+	.word	CONTROL_STAT
 ENTRY(omap34xx_cpu_suspend_sz)
 	.word	. - omap34xx_cpu_suspend
diff --git a/arch/arm/plat-omap/include/mach/pm.h b/arch/arm/plat-omap/include/mach/pm.h
old mode 100644
new mode 100755
index fd08490..532ffe9
--- a/arch/arm/plat-omap/include/mach/pm.h
+++ b/arch/arm/plat-omap/include/mach/pm.h
@@ -148,6 +148,7 @@ extern void omap1610_cpu_suspend(unsigned short, unsigned short);
 extern void omap24xx_cpu_suspend(u32 dll_ctrl, void __iomem *sdrc_dlla_ctrl,
 					void __iomem *sdrc_power);
 extern void omap34xx_cpu_suspend(u32 *addr, int save_state);
+extern void save_secure_ram_context(u32 *addr);
 extern void omap730_idle_loop_suspend(void);
 extern void omap1510_idle_loop_suspend(void);
 extern void omap1610_idle_loop_suspend(void);
@@ -168,6 +169,7 @@ extern unsigned int omap1510_idle_loop_suspend_sz;
 extern unsigned int omap1610_idle_loop_suspend_sz;
 extern unsigned int omap24xx_idle_loop_suspend_sz;
 extern unsigned int omap34xx_suspend_sz;
+extern unsigned int save_secure_ram_context_sz;
 
 #ifdef CONFIG_OMAP_SERIAL_WAKE
 extern void omap_serial_wake_trigger(int enable);
-- 
1.5.4.3

[PATCH 4/6] Enable SDRAM auto-refresh during sleep

[Tero Kristo]

Fix for ES3.0 bug: SDRC not sending auto-refresh when OMAP wakes-up from OFF
mode (warning for HS devices.)

Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
---
 arch/arm/mach-omap2/pm34xx.c |   27 +++++++++++++++++++++++++++
 1 files changed, 27 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index d5892c5..513c4bf 100755
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -46,6 +46,11 @@
 
 #define OMAP3430_PRM_RSTST      \
 	OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0058)
+#define SDRC_POWER_AUTOCOUNT_SHIFT 8
+#define SDRC_POWER_AUTOCOUNT_MASK (0xffff << SDRC_POWER_AUTOCOUNT_SHIFT)
+#define SDRC_POWER_CLKCTRL_SHIFT 4
+#define SDRC_POWER_CLKCTRL_MASK (0x3 << SDRC_POWER_CLKCTRL_SHIFT)
+#define SDRC_SELF_REFRESH_ON_AUTOCOUNT (0x2 << SDRC_POWER_CLKCTRL_SHIFT)
 
 u32 context_mem[128];
 
@@ -349,12 +354,34 @@ void omap_sram_idle(void)
 		prm_set_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN);
 	}
 
+	/*
+	 * Force SDRAM controller to self-refresh mode after timeout on
+	 * autocount. This is needed on ES3.0 to avoid SDRAM controller
+	 * hang-ups.
+	 */
+	if (system_rev >= OMAP3430_REV_ES3_0 &&
+	    omap_type() != OMAP2_DEVICE_TYPE_GP &&
+	    core_next_state == PWRDM_POWER_OFF) {
+		sdrc_pwr = sdrc_read_reg(SDRC_POWER);
+		sdrc_write_reg((sdrc_pwr &
+			~(SDRC_POWER_AUTOCOUNT_MASK|SDRC_POWER_CLKCTRL_MASK)) |
+			(1 << SDRC_POWER_AUTOCOUNT_SHIFT) |
+			SDRC_SELF_REFRESH_ON_AUTOCOUNT, SDRC_POWER);
+	}
+
 	*(scratchpad_restore_addr) = restore_pointer_address;
 
 	_omap_sram_idle(context_mem, save_state);
 
 	*(scratchpad_restore_addr) = 0x0;
 
+	/* Restore normal SDRAM settings */
+	if (system_rev >= OMAP3430_REV_ES3_0 &&
+	    omap_type() != OMAP2_DEVICE_TYPE_GP &&
+	    core_next_state == PWRDM_POWER_OFF) {
+		sdrc_write_reg(sdrc_pwr, SDRC_POWER);
+       }
+
 	/* Restore table entry modified during MMU restoration */
 	if (pwrdm_read_prev_pwrst(mpu_pwrdm) == 0x0)
 		restore_table_entry();
-- 
1.5.4.3

[PATCH 5/6] Add new register definitions for SDRAM controller

[Tero Kristo]

Added SDRC_EMR2_* and SDRC_MANUAL_*

Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
---
 arch/arm/plat-omap/include/mach/sdrc.h |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/arch/arm/plat-omap/include/mach/sdrc.h b/arch/arm/plat-omap/include/mach/sdrc.h
index c66c838..a5a6cf9 100644
--- a/arch/arm/plat-omap/include/mach/sdrc.h
+++ b/arch/arm/plat-omap/include/mach/sdrc.h
@@ -31,14 +31,18 @@
 #define SDRC_POWER		0x070
 #define SDRC_MCFG_0		0x080
 #define SDRC_MR_0		0x084
+#define SDRC_EMR2_0		0x08c
 #define SDRC_ACTIM_CTRL_A_0	0x09c
 #define SDRC_ACTIM_CTRL_B_0	0x0a0
 #define SDRC_RFR_CTRL_0		0x0a4
+#define SDRC_MANUAL_0		0x0a8
 #define SDRC_MCFG_1		0x0B0
 #define SDRC_MR_1		0x0B4
+#define SDRC_EMR2_1		0x0BC
 #define SDRC_ACTIM_CTRL_A_1	0x0C4
 #define SDRC_ACTIM_CTRL_B_1	0x0C8
 #define SDRC_RFR_CTRL_1		0x0D4
+#define SDRC_MANUAL_1		0x0D8
 
 /*
  * These values represent the number of memory clock cycles between
-- 
1.5.4.3

[PATCH 6/6] Errata: ES3.0 SDRC not sending auto-refresh when OMAP wakes-up from OFF mode

[Tero Kristo]

Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
---
 arch/arm/mach-omap2/pm34xx.c         |    5 ++-
 arch/arm/mach-omap2/sleep34xx.S      |   84 +++++++++++++++++++++++++++++++++-
 arch/arm/plat-omap/include/mach/pm.h |    1 +
 3 files changed, 88 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 513c4bf..5474b12 100755
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -982,7 +982,10 @@ void save_scratchpad_contents(void)
 	/* Get virtual address of SCRATCHPAD */
 	scratchpad_address = (u32 *) OMAP2_IO_ADDRESS(SCRATCHPAD);
 	/* Get Restore pointer to jump to while waking up from OFF */
-	restore_address = get_restore_pointer();
+	if (system_rev >= OMAP3430_REV_ES3_0)
+		restore_address = get_es3_restore_pointer();
+	else
+		restore_address = get_restore_pointer();
 	/* Convert it to physical address */
 	restore_address = (u32 *) io_v2p(restore_address);
 	/* Get address where registers are saved in SDRAM */
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index a2bdab2..f724e65 100755
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -35,6 +35,7 @@
 
 #define PM_PREPWSTST_CORE_V	OMAP34XX_PRM_REGADDR(CORE_MOD, \
 				OMAP3430_PM_PREPWSTST)
+#define PM_PREPWSTST_CORE_P	0x48306AE8
 #define PM_PREPWSTST_MPU_V	OMAP34XX_PRM_REGADDR(MPU_MOD, \
 				OMAP3430_PM_PREPWSTST)
 #define PM_PWSTCTRL_MPU_P	0x483069E0
@@ -44,6 +45,13 @@
 				       * available */
 #define SCRATCHPAD_BASE_P	0x48002910
 #define SDRC_POWER_V		OMAP34XX_SDRC_REGADDR(SDRC_POWER)
+#define SDRC_SYSCONFIG_P	(OMAP343X_SDRC_BASE + SDRC_SYSCONFIG)
+#define SDRC_MR_0_P		(OMAP343X_SDRC_BASE + SDRC_MR_0)
+#define SDRC_EMR2_0_P		(OMAP343X_SDRC_BASE + SDRC_EMR2_0)
+#define SDRC_MANUAL_0_P		(OMAP343X_SDRC_BASE + SDRC_MANUAL_0)
+#define SDRC_MR_1_P		(OMAP343X_SDRC_BASE + SDRC_MR_1)
+#define SDRC_EMR2_1_P		(OMAP343X_SDRC_BASE + SDRC_EMR2_1)
+#define SDRC_MANUAL_1_P		(OMAP343X_SDRC_BASE + SDRC_MANUAL_1)
 
 	.text
 /* Function call to get the restore pointer for resume from OFF */
@@ -52,7 +60,59 @@ ENTRY(get_restore_pointer)
 	adr	r0, restore
         ldmfd   sp!, {pc}     @ restore regs and return
 ENTRY(get_restore_pointer_sz)
-        .word   . - get_restore_pointer_sz
+        .word   . - get_restore_pointer
+
+	.text
+/* Function call to get the restore pointer for for ES3 to resume from OFF */
+ENTRY(get_es3_restore_pointer)
+        stmfd   sp!, {lr}     @ save registers on stack
+	adr	r0, restore_es3
+        ldmfd   sp!, {pc}     @ restore regs and return
+ENTRY(get_es3_restore_pointer_sz)
+        .word   . - get_es3_restore_pointer
+
+ENTRY(es3_sdrc_fix)
+	ldr	r4, sdrc_syscfg		@ get config addr
+	ldr	r5, [r4]		@ get value
+	tst	r5, #0x100		@ is part access blocked
+	it	eq
+	biceq	r5, r5, #0x100		@ clear bit if set
+	str	r5, [r4]		@ write back change
+	ldr	r4, sdrc_mr_0		@ get config addr
+	ldr	r5, [r4]		@ get value
+	str	r5, [r4]		@ write back change
+	ldr	r4, sdrc_emr2_0		@ get config addr
+	ldr	r5, [r4]		@ get value
+	str	r5, [r4]		@ write back change
+	ldr	r4, sdrc_manual_0	@ get config addr
+	mov	r5, #0x2		@ autorefresh command
+	str	r5, [r4]		@ kick off refreshes
+	ldr	r4, sdrc_mr_1		@ get config addr
+	ldr	r5, [r4]		@ get value
+	str	r5, [r4]		@ write back change
+	ldr	r4, sdrc_emr2_1		@ get config addr
+	ldr	r5, [r4]		@ get value
+	str	r5, [r4]		@ write back change
+	ldr	r4, sdrc_manual_1	@ get config addr
+	mov	r5, #0x2		@ autorefresh command
+	str	r5, [r4]		@ kick off refreshes
+	bx	lr
+sdrc_syscfg:
+	.word SDRC_SYSCONFIG_P
+sdrc_mr_0:
+	.word SDRC_MR_0_P
+sdrc_emr2_0:
+	.word SDRC_EMR2_0_P
+sdrc_manual_0:
+	.word SDRC_MANUAL_0_P
+sdrc_mr_1:
+	.word SDRC_MR_1_P
+sdrc_emr2_1:
+	.word SDRC_EMR2_1_P
+sdrc_manual_1:
+	.word SDRC_MANUAL_1_P
+ENTRY(es3_sdrc_fix_sz)
+	.word	. - es3_sdrc_fix
 
 /* Function to call rom code to save secure ram context */
 ENTRY(save_secure_ram_context)
@@ -130,6 +190,24 @@ loop:
 	bl i_dll_wait
 
 	ldmfd	sp!, {r0-r12, pc}		@ restore regs and return
+restore_es3:
+	/*b restore_es3*/ 		@ Enable to debug restore code
+	ldr	r5, pm_prepwstst_core_p
+	ldr	r4, [r5]
+	and	r4, r4, #0x3
+	cmp	r4, #0x0	@ Check if previous power state of CORE is OFF
+	bne	restore
+	adr	r0, es3_sdrc_fix
+	ldr	r1, sram_base
+	ldr	r2, es3_sdrc_fix_sz
+	mov	r2, r2, ror #2
+copy_to_sram:
+	ldmia	r0!, {r3}    @ val = *src
+	stmia	r1!, {r3}    @ *dst = val
+	subs	r2, r2, #0x1 @ num_words--
+	bne	copy_to_sram
+	ldr	r1, sram_base
+	blx	r1
 restore:
 	/* b restore*/  @ Enable to debug restore code
         /* Check what was the reason for mpu reset and store the reason in r9*/
@@ -588,12 +666,16 @@ i_dll_delay:
 	bx	lr
 pm_prepwstst_core:
 	.word	PM_PREPWSTST_CORE_V
+pm_prepwstst_core_p:
+	.word	PM_PREPWSTST_CORE_P
 pm_prepwstst_mpu:
 	.word	PM_PREPWSTST_MPU_V
 pm_pwstctrl_mpu:
 	.word	PM_PWSTCTRL_MPU_P
 scratchpad_base:
 	.word	SCRATCHPAD_BASE_P
+sram_base:
+	.word	SRAM_BASE_P + 0x8000
 sdrc_power:
 	.word SDRC_POWER_V
 context_mem:
diff --git a/arch/arm/plat-omap/include/mach/pm.h b/arch/arm/plat-omap/include/mach/pm.h
index 532ffe9..4a6512f 100755
--- a/arch/arm/plat-omap/include/mach/pm.h
+++ b/arch/arm/plat-omap/include/mach/pm.h
@@ -157,6 +157,7 @@ extern void omap24xx_idle_loop_suspend(void);
 extern void save_scratchpad_contents(void);
 extern void clear_scratchpad_contents(void);
 extern u32 *get_restore_pointer(void);
+extern u32 *get_es3_restore_pointer(void);
 extern void vfp_enable(void);
 
 extern unsigned int omap730_cpu_suspend_sz;
-- 
1.5.4.3

Re: [PATCH 2/6] HS/EMU OMAP3 SRAM size fix

[Felipe Contreras]

On Tue, Oct 14, 2008 at 3:23 PM, Tero Kristo <tero.kristo@nokia.com> wrote:
> Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
> ---
>  arch/arm/plat-omap/sram.c |   12 +++++++++---
>  1 files changed, 9 insertions(+), 3 deletions(-)
>  mode change 100644 => 100755 arch/arm/plat-omap/sram.c
>
> diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
> old mode 100644
> new mode 100755
> index 9cfb77f..f0ac426
> --- a/arch/arm/plat-omap/sram.c
> +++ b/arch/arm/plat-omap/sram.c
> @@ -125,9 +125,15 @@ void __init omap_detect_sram(void)
>        if (cpu_class_is_omap2()) {
>                if (is_sram_locked()) {
>                        if (cpu_is_omap34xx()) {
> -                               omap_sram_base = OMAP3_SRAM_PUB_VA;
> -                               omap_sram_start = OMAP3_SRAM_PUB_PA;
> -                               omap_sram_size = 0x8000; /* 32K */
> +                               if (omap_type() == OMAP2_DEVICE_TYPE_GP) {
> +                                       omap_sram_base = OMAP3_SRAM_PUB_VA;
> +                                       omap_sram_start = OMAP3_SRAM_PUB_PA;
> +                                       omap_sram_size = 0x8000; /* 32K */
> +                               } else {
> +                                       omap_sram_base = OMAP3_SRAM_PUB_VA;
> +                                       omap_sram_start = OMAP3_SRAM_PUB_PA;
> +                                       omap_sram_size = 0x7000; /* 28K */
> +                               }

It seems omap_sram_base and _start are the same, maybe have leave them
outside the if?

>                        } else {
>                                omap_sram_base = OMAP2_SRAM_PUB_VA;
>                                omap_sram_start = OMAP2_SRAM_PUB_PA;
> --
> 1.5.4.3

-- 
Felipe Contreras

Re: PM: OMAP3 HS/EMU off-mode support

[Kevin Hilman]

Tero Kristo <tero.kristo@nokia.com> writes:

> This patchset provides off-mode support for OMAP3 HS/EMU devices. Due to
> secure environment in these devices, wake-up from off-mode is slightly
> different than in GP devices. This code has been tested on following chip
> versions: ES2.1GP, ES3.0EMU, ES3.0HS.

Thanks, I'm pulling this series into the next PM branch.

Kevin