From: jouni.hogander@nokia.com (Högander Jouni)
To: ext Paul Walmsley <paul@pwsan.com>
Cc: "Woodruff, Richard" <r-woodruff2@ti.com>,
Koen Kooi <k.kooi@student.utwente.nl>,
"Gadiyar, Anand" <gadiyar@ti.com>,
"linux-omap@vger.kernel.org" <linux-omap@vger.kernel.org>,
Dirk Behme <dirk.behme@googlemail.com>
Subject: Re: [PATCH v2] OMAP3 clock: fix omap2_clk_wait_ready for OMAP3430ES2 DSS
Date: Tue, 24 Jun 2008 08:54:13 +0300 [thread overview]
Message-ID: <877icfl6nu.fsf@trdhcp146196.ntc.nokia.com> (raw)
In-Reply-To: <alpine.DEB.1.00.0806230849130.4919@utopia.booyaka.com> (ext Paul Walmsley's message of "Mon, 23 Jun 2008 08:52:00 -0600 (MDT)")
"ext Paul Walmsley" <paul@pwsan.com> writes:
> Hi Jouni
>
> On Mon, 23 Jun 2008, Högander Jouni wrote:
>
>> Hello Paul,
>>
>> It should actually wait for SSI also. Read my comments below.
>
> ...
>
>> And add this part
>>
>> + if (cpu_is_omap34xx() &&
>> + prcm_mod == OMAP34XX_CM_REGADDR(CORE_MOD, 0) &&
>> + clk->enable_bit == OMAP3430_EN_SSI_SHIFT) {
>> + bit = OMAP3430ES2_ST_SSI_IDLE;
>
> what should OMAP3430ES2_ST_SSI_IDLE be set to? I don't have any
> documentation here that defines this bit.
Sorry for not to mention this in my first mail:
#define OMAP3430ES2_ST_SSI_IDLE (1 << 8)
#define OMAP3430ES2_ST_SSI_STDBY (1 << 0)
--
Jouni Högander
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next prev parent reply other threads:[~2008-06-24 5:54 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-06-20 14:33 Boot failure on OMAP 3430 SDP Gadiyar, Anand
2008-06-21 6:44 ` Dirk Behme
2008-06-21 8:20 ` Gadiyar, Anand
2008-06-21 12:18 ` Dirk Behme
2008-06-21 17:05 ` [PATCH] OMAP3 clock: fix omap2_clk_wait_ready for OMAP3430ES2 DSS Paul Walmsley
2008-06-22 10:35 ` Koen Kooi
2008-06-22 12:51 ` Woodruff, Richard
2008-06-22 13:21 ` Koen Kooi
2008-06-22 19:09 ` [PATCH v2] " Paul Walmsley
2008-06-23 6:16 ` Högander Jouni
2008-06-23 14:52 ` Paul Walmsley
2008-06-24 5:54 ` Högander Jouni [this message]
2008-06-22 12:01 ` [PATCH] " Dirk Behme
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