[PATCH v2 0/5] Convert I2C driver to use omap_device/runtime PM

[PATCH v2 0/5] Convert I2C driver to use omap_device/runtime PM

[Rajendra Nayak]

This series makes I2C device registration use hwmod
and omap_device api's and converts the I2C driver to use
runtime PM api's.

Patches apply on the pm-core branch from Kevin's tree.

v2 has minor review comment fixes over v1 and is additionally
boot tested on a 2430sdp platform along with being tested on
3430sdp and 4430sdp.

4430sdp tests are done using the below series
http://www.spinics.net/lists/linux-omap/msg36023.html

Paul Walmsley (2):
  OMAP2xxx: hwmod: add I2C hwmods for OMAP2420, 2430
  OMAP: I2C: split device registration and convert OMAP2+ to
    omap_device

Rajendra Nayak (3):
  OMAP3: hwmod: add I2C hwmods for OMAP3430
  OMAP4: hwmod: add I2C hwmods for OMAP4430
  OMAP: I2C: Convert i2c driver to use PM runtime api's

 arch/arm/mach-omap2/omap_hwmod_2420_data.c |  138 ++++++++++++++++-
 arch/arm/mach-omap2/omap_hwmod_2430_data.c |  144 +++++++++++++++++-
 arch/arm/mach-omap2/omap_hwmod_3xxx_data.c |  232 +++++++++++++++++++++++++++
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c |  237 ++++++++++++++++++++++++++++
 arch/arm/mach-omap2/prm-regbits-34xx.h     |    3 +
 arch/arm/plat-omap/i2c.c                   |  124 ++++++---------
 arch/arm/plat-omap/include/plat/i2c.h      |   16 ++
 arch/arm/plat-omap/include/plat/l4_3xxx.h  |   24 +++
 drivers/i2c/busses/i2c-omap.c              |   67 +++------
 include/linux/i2c-omap.h                   |    5 +
 10 files changed, 865 insertions(+), 125 deletions(-)
 create mode 100644 arch/arm/plat-omap/include/plat/l4_3xxx.h

[PATCH v2 1/5] OMAP2xxx: hwmod: add I2C hwmods for OMAP2420, 2430

[Rajendra Nayak]

From: Paul Walmsley <paul@pwsan.com>

Add hwmod structures for I2C controllers on OMAP2420/2430.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
---
 arch/arm/mach-omap2/omap_hwmod_2420_data.c |  138 ++++++++++++++++++++++++++-
 arch/arm/mach-omap2/omap_hwmod_2430_data.c |  144 +++++++++++++++++++++++++++-
 2 files changed, 278 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index 3cc768e..ec730e4 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -15,9 +15,12 @@
 #include <mach/irqs.h>
 #include <plat/cpu.h>
 #include <plat/dma.h>
+#include <plat/i2c.h>
+#include <plat/omap24xx.h>
 
 #include "omap_hwmod_common_data.h"
 
+#include "cm-regbits-24xx.h"
 #include "prm-regbits-24xx.h"
 
 /*
@@ -71,6 +74,8 @@ static struct omap_hwmod omap2420_l3_main_hwmod = {
 };
 
 static struct omap_hwmod omap2420_l4_wkup_hwmod;
+static struct omap_hwmod omap2420_i2c1_hwmod;
+static struct omap_hwmod omap2420_i2c2_hwmod;
 
 /* L4_CORE -> L4_WKUP interface */
 static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = {
@@ -79,6 +84,45 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = {
 	.user	= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* I2C IP block address space length (in bytes) */
+#define OMAP2_I2C_AS_LEN		128
+
+/* L4 CORE -> I2C1 interface */
+static struct omap_hwmod_addr_space omap2420_i2c1_addr_space[] = {
+	{
+		.pa_start	= 0x48070000,
+		.pa_end		= 0x48070000 + OMAP2_I2C_AS_LEN - 1,
+		.flags		= ADDR_TYPE_RT,
+	},
+};
+
+static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
+	.master		= &omap2420_l4_core_hwmod,
+	.slave		= &omap2420_i2c1_hwmod,
+	.clk		= "i2c1_ick",
+	.addr		= omap2420_i2c1_addr_space,
+	.addr_cnt	= ARRAY_SIZE(omap2420_i2c1_addr_space),
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 CORE -> I2C2 interface */
+static struct omap_hwmod_addr_space omap2420_i2c2_addr_space[] = {
+	{
+		.pa_start	= 0x48072000,
+		.pa_end		= 0x48072000 + OMAP2_I2C_AS_LEN - 1,
+		.flags		= ADDR_TYPE_RT,
+	},
+};
+
+static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
+	.master		= &omap2420_l4_core_hwmod,
+	.slave		= &omap2420_i2c2_hwmod,
+	.clk		= "i2c2_ick",
+	.addr		= omap2420_i2c2_addr_space,
+	.addr_cnt	= ARRAY_SIZE(omap2420_i2c2_addr_space),
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 /* Slave interfaces on the L4_CORE interconnect */
 static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = {
 	&omap2420_l3_main__l4_core,
@@ -87,6 +131,8 @@ static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = {
 /* Master interfaces on the L4_CORE interconnect */
 static struct omap_hwmod_ocp_if *omap2420_l4_core_masters[] = {
 	&omap2420_l4_core__l4_wkup,
+	&omap2420_l4_core__i2c1,
+	&omap2420_l4_core__i2c2
 };
 
 /* L4 CORE */
@@ -165,6 +211,96 @@ static struct omap_hwmod omap2420_iva_hwmod = {
 	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 };
 
+/* I2C common */
+static struct omap_hwmod_class_sysconfig i2c_sysc = {
+	.rev_offs	= 0x00,
+	.sysc_offs	= 0x20,
+	.syss_offs	= 0x10,
+	.sysc_flags	= SYSC_HAS_SOFTRESET,
+	.sysc_fields	= &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class i2c_class = {
+	.name		= "i2c",
+	.sysc		= &i2c_sysc,
+};
+
+static struct omap_i2c_dev_attr i2c_dev_attr;
+
+/* I2C1 */
+
+static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
+	{ .irq = INT_24XX_I2C1_IRQ, },
+};
+
+static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
+	{ .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
+	{ .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
+};
+
+static struct omap_hwmod_ocp_if *omap2420_i2c1_slaves[] = {
+	&omap2420_l4_core__i2c1,
+};
+
+static struct omap_hwmod omap2420_i2c1_hwmod = {
+	.name		= "i2c1",
+	.mpu_irqs	= i2c1_mpu_irqs,
+	.mpu_irqs_cnt	= ARRAY_SIZE(i2c1_mpu_irqs),
+	.sdma_reqs	= i2c1_sdma_reqs,
+	.sdma_reqs_cnt	= ARRAY_SIZE(i2c1_sdma_reqs),
+	.main_clk	= "i2c1_fck",
+	.prcm		= {
+		.omap2 = {
+			.prcm_reg_id = 1,
+			.module_bit = OMAP2420_EN_I2C1_SHIFT,
+			.idlest_reg_id = 1,
+			.idlest_idle_bit = OMAP2420_EN_I2C1_SHIFT,
+		},
+	},
+	.slaves		= omap2420_i2c1_slaves,
+	.slaves_cnt	= ARRAY_SIZE(omap2420_i2c1_slaves),
+	.class		= &i2c_class,
+	.dev_attr	= &i2c_dev_attr,
+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+};
+
+/* I2C2 */
+
+static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
+	{ .irq = INT_24XX_I2C2_IRQ, },
+};
+
+static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
+	{ .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
+	{ .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
+};
+
+static struct omap_hwmod_ocp_if *omap2420_i2c2_slaves[] = {
+	&omap2420_l4_core__i2c2,
+};
+
+static struct omap_hwmod omap2420_i2c2_hwmod = {
+	.name		= "i2c2",
+	.mpu_irqs	= i2c2_mpu_irqs,
+	.mpu_irqs_cnt	= ARRAY_SIZE(i2c2_mpu_irqs),
+	.sdma_reqs	= i2c2_sdma_reqs,
+	.sdma_reqs_cnt	= ARRAY_SIZE(i2c2_sdma_reqs),
+	.main_clk	= "i2c2_fck",
+	.prcm		= {
+		.omap2 = {
+			.prcm_reg_id = 1,
+			.module_bit = OMAP2420_EN_I2C2_SHIFT,
+			.idlest_reg_id = 1,
+			.idlest_idle_bit = OMAP2420_EN_I2C2_SHIFT,
+		},
+	},
+	.slaves		= omap2420_i2c2_slaves,
+	.slaves_cnt	= ARRAY_SIZE(omap2420_i2c2_slaves),
+	.class		= &i2c_class,
+	.dev_attr	= &i2c_dev_attr,
+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+};
+
 static __initdata struct omap_hwmod *omap2420_hwmods[] = {
 	&omap2420_l3_main_hwmod,
 	&omap2420_l4_core_hwmod,
@@ -178,5 +314,3 @@ int __init omap2420_hwmod_init(void)
 {
 	return omap_hwmod_init(omap2420_hwmods);
 }
-
-
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 4526628..9884db6 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -15,10 +15,13 @@
 #include <mach/irqs.h>
 #include <plat/cpu.h>
 #include <plat/dma.h>
+#include <plat/i2c.h>
+#include <plat/omap24xx.h>
 
 #include "omap_hwmod_common_data.h"
 
 #include "prm-regbits-24xx.h"
+#include "cm-regbits-24xx.h"
 
 /*
  * OMAP2430 hardware module integration data
@@ -71,6 +74,47 @@ static struct omap_hwmod omap2430_l3_main_hwmod = {
 };
 
 static struct omap_hwmod omap2430_l4_wkup_hwmod;
+static struct omap_hwmod omap2430_i2c1_hwmod;
+static struct omap_hwmod omap2430_i2c2_hwmod;
+
+/* I2C IP block address space length (in bytes) */
+#define OMAP2_I2C_AS_LEN		128
+
+/* L4 CORE -> I2C1 interface */
+static struct omap_hwmod_addr_space omap2430_i2c1_addr_space[] = {
+	{
+		.pa_start	= 0x48070000,
+		.pa_end		= 0x48070000 + OMAP2_I2C_AS_LEN - 1,
+		.flags		= ADDR_TYPE_RT,
+	},
+};
+
+static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = {
+	.master		= &omap2430_l4_core_hwmod,
+	.slave		= &omap2430_i2c1_hwmod,
+	.clk		= "i2c1_ick",
+	.addr		= omap2430_i2c1_addr_space,
+	.addr_cnt	= ARRAY_SIZE(omap2430_i2c1_addr_space),
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 CORE -> I2C2 interface */
+static struct omap_hwmod_addr_space omap2430_i2c2_addr_space[] = {
+	{
+		.pa_start	= 0x48072000,
+		.pa_end		= 0x48072000 + OMAP2_I2C_AS_LEN - 1,
+		.flags		= ADDR_TYPE_RT,
+	},
+};
+
+static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = {
+	.master		= &omap2430_l4_core_hwmod,
+	.slave		= &omap2430_i2c2_hwmod,
+	.clk		= "i2c2_ick",
+	.addr		= omap2430_i2c2_addr_space,
+	.addr_cnt	= ARRAY_SIZE(omap2430_i2c2_addr_space),
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
 
 /* L4_CORE -> L4_WKUP interface */
 static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = {
@@ -165,6 +209,104 @@ static struct omap_hwmod omap2430_iva_hwmod = {
 	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 };
 
+/* I2C common */
+static struct omap_hwmod_class_sysconfig i2c_sysc = {
+	.rev_offs	= 0x00,
+	.sysc_offs	= 0x20,
+	.syss_offs	= 0x10,
+	.sysc_flags	= (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+	.sysc_fields	= &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class i2c_class = {
+	.name		= "i2c",
+	.sysc		= &i2c_sysc,
+};
+
+static struct omap_i2c_dev_attr i2c_dev_attr;
+
+/* I2C1 */
+
+static struct omap_i2c_dev_attr i2c1_dev_attr = {
+	.fifo_depth	= 8, /* bytes */
+};
+
+static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
+	{ .irq = INT_24XX_I2C1_IRQ, },
+};
+
+static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
+	{ .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
+	{ .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
+};
+
+static struct omap_hwmod_ocp_if *omap2430_i2c1_slaves[] = {
+	&omap2430_l4_core__i2c1,
+};
+
+static struct omap_hwmod omap2430_i2c1_hwmod = {
+	.name		= "i2c1",
+	.mpu_irqs	= i2c1_mpu_irqs,
+	.mpu_irqs_cnt	= ARRAY_SIZE(i2c1_mpu_irqs),
+	.sdma_reqs	= i2c1_sdma_reqs,
+	.sdma_reqs_cnt	= ARRAY_SIZE(i2c1_sdma_reqs),
+	.main_clk	= "i2c1_fck",
+	.prcm		= {
+		.omap2 = {
+			.prcm_reg_id = 1,
+			.module_bit = OMAP2430_EN_I2CHS1_SHIFT,
+			.idlest_reg_id = 1,
+			.idlest_idle_bit = OMAP2430_EN_I2CHS1_SHIFT,
+		},
+	},
+	.slaves		= omap2430_i2c1_slaves,
+	.slaves_cnt	= ARRAY_SIZE(omap2430_i2c1_slaves),
+	.class		= &i2c_class,
+	.dev_attr	= &i2c1_dev_attr,
+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
+/* I2C2 */
+
+static struct omap_i2c_dev_attr i2c2_dev_attr = {
+	.fifo_depth	= 8, /* bytes */
+};
+
+static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
+	{ .irq = INT_24XX_I2C2_IRQ, },
+};
+
+static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
+	{ .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
+	{ .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
+};
+
+static struct omap_hwmod_ocp_if *omap2430_i2c2_slaves[] = {
+	&omap2430_l4_core__i2c2,
+};
+
+static struct omap_hwmod omap2430_i2c2_hwmod = {
+	.name		= "i2c2_hwmod",
+	.mpu_irqs	= i2c2_mpu_irqs,
+	.mpu_irqs_cnt	= ARRAY_SIZE(i2c2_mpu_irqs),
+	.sdma_reqs	= i2c2_sdma_reqs,
+	.sdma_reqs_cnt	= ARRAY_SIZE(i2c2_sdma_reqs),
+	.main_clk	= "i2c2_fck",
+	.prcm		= {
+		.omap2 = {
+			.prcm_reg_id = 1,
+			.module_bit = OMAP2430_EN_I2CHS2_SHIFT,
+			.idlest_reg_id = 1,
+			.idlest_idle_bit = OMAP2430_EN_I2CHS2_SHIFT,
+		},
+	},
+	.slaves		= omap2430_i2c2_slaves,
+	.slaves_cnt	= ARRAY_SIZE(omap2430_i2c2_slaves),
+	.class		= &i2c_class,
+	.dev_attr	= &i2c2_dev_attr,
+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
 static __initdata struct omap_hwmod *omap2430_hwmods[] = {
 	&omap2430_l3_main_hwmod,
 	&omap2430_l4_core_hwmod,
@@ -178,5 +320,3 @@ int __init omap2430_hwmod_init(void)
 {
 	return omap_hwmod_init(omap2430_hwmods);
 }
-
-
-- 
1.7.0.4

[PATCH v2 2/5] OMAP3: hwmod: add I2C hwmods for OMAP3430

[Rajendra Nayak]

Add hwmod structures for I2C controllers on OMAP3430.

This patch was developed in collaboration with Paul Walmsley <paul@pwsan.com>.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
---
 arch/arm/mach-omap2/omap_hwmod_3xxx_data.c |  232 ++++++++++++++++++++++++++++
 arch/arm/mach-omap2/prm-regbits-34xx.h     |    3 +
 arch/arm/plat-omap/include/plat/i2c.h      |   16 ++
 arch/arm/plat-omap/include/plat/l4_3xxx.h  |   24 +++
 4 files changed, 275 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/plat-omap/include/plat/l4_3xxx.h

diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 5d8eb58..b12920e 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -17,6 +17,9 @@
 #include <mach/irqs.h>
 #include <plat/cpu.h>
 #include <plat/dma.h>
+#include <plat/l4_3xxx.h>
+#include <plat/i2c.h>
+#include <plat/omap34xx.h>
 
 #include "omap_hwmod_common_data.h"
 
@@ -36,6 +39,9 @@ static struct omap_hwmod omap3xxx_iva_hwmod;
 static struct omap_hwmod omap3xxx_l3_main_hwmod;
 static struct omap_hwmod omap3xxx_l4_core_hwmod;
 static struct omap_hwmod omap3xxx_l4_per_hwmod;
+static struct omap_hwmod omap3xxx_i2c1_hwmod;
+static struct omap_hwmod omap3xxx_i2c2_hwmod;
+static struct omap_hwmod omap3xxx_i2c3_hwmod;
 
 /* L3 -> L4_CORE interface */
 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
@@ -90,6 +96,85 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
 	.user	= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+
+/* I2C IP block address space length (in bytes) */
+#define OMAP2_I2C_AS_LEN		128
+
+/* L4 CORE -> I2C1 interface */
+static struct omap_hwmod_addr_space omap3xxx_i2c1_addr_space[] = {
+	{
+		.pa_start	= 0x48070000,
+		.pa_end		= 0x48070000 + OMAP2_I2C_AS_LEN - 1,
+		.flags		= ADDR_TYPE_RT,
+	},
+};
+
+static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
+	.master		= &omap3xxx_l4_core_hwmod,
+	.slave		= &omap3xxx_i2c1_hwmod,
+	.clk		= "i2c1_ick",
+	.addr		= omap3xxx_i2c1_addr_space,
+	.addr_cnt	= ARRAY_SIZE(omap3xxx_i2c1_addr_space),
+	.fw = {
+		.omap2 = {
+			.l4_fw_region  = OMAP3_L4_CORE_FW_I2C1_REGION,
+			.l4_prot_group = 7,
+			.flags	= OMAP_FIREWALL_L4,
+		}
+	},
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 CORE -> I2C2 interface */
+static struct omap_hwmod_addr_space omap3xxx_i2c2_addr_space[] = {
+	{
+		.pa_start	= 0x48072000,
+		.pa_end		= 0x48072000 + OMAP2_I2C_AS_LEN - 1,
+		.flags		= ADDR_TYPE_RT,
+	},
+};
+
+static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
+	.master		= &omap3xxx_l4_core_hwmod,
+	.slave		= &omap3xxx_i2c2_hwmod,
+	.clk		= "i2c2_ick",
+	.addr		= omap3xxx_i2c2_addr_space,
+	.addr_cnt	= ARRAY_SIZE(omap3xxx_i2c2_addr_space),
+	.fw = {
+		.omap2 = {
+			.l4_fw_region  = OMAP3_L4_CORE_FW_I2C2_REGION,
+			.l4_prot_group = 7,
+			.flags = OMAP_FIREWALL_L4,
+		}
+	},
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 CORE -> I2C3 interface */
+static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
+	{
+		.pa_start	= 0x48060000,
+		.pa_end		= 0x48060000 + OMAP2_I2C_AS_LEN - 1,
+		.flags		= ADDR_TYPE_RT,
+	},
+};
+
+static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
+	.master		= &omap3xxx_l4_core_hwmod,
+	.slave		= &omap3xxx_i2c3_hwmod,
+	.clk		= "i2c3_ick",
+	.addr		= omap3xxx_i2c3_addr_space,
+	.addr_cnt	= ARRAY_SIZE(omap3xxx_i2c3_addr_space),
+	.fw = {
+		.omap2 = {
+			.l4_fw_region  = OMAP3_L4_CORE_FW_I2C3_REGION,
+			.l4_prot_group = 7,
+			.flags = OMAP_FIREWALL_L4,
+		}
+	},
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 /* Slave interfaces on the L4_CORE interconnect */
 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
 	&omap3xxx_l3_main__l4_core,
@@ -98,6 +183,9 @@ static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
 /* Master interfaces on the L4_CORE interconnect */
 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_masters[] = {
 	&omap3xxx_l4_core__l4_wkup,
+	&omap3_l4_core__i2c1,
+	&omap3_l4_core__i2c2,
+	&omap3_l4_core__i2c3,
 };
 
 /* L4 CORE */
@@ -197,6 +285,147 @@ static struct omap_hwmod omap3xxx_iva_hwmod = {
 	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 };
 
+
+/* I2C common */
+static struct omap_hwmod_class_sysconfig i2c_sysc = {
+	.rev_offs	= 0x00,
+	.sysc_offs	= 0x20,
+	.syss_offs	= 0x10,
+	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+			   SYSC_HAS_AUTOIDLE),
+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+	.sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class i2c_class = {
+	.name = "i2c",
+	.sysc = &i2c_sysc,
+};
+
+/* I2C1 */
+
+static struct omap_i2c_dev_attr i2c1_dev_attr = {
+	.fifo_depth	= 8, /* bytes */
+};
+
+static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
+	{ .irq = INT_24XX_I2C1_IRQ, },
+};
+
+static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
+	{ .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
+	{ .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
+};
+
+static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
+	&omap3_l4_core__i2c1,
+};
+
+static struct omap_hwmod omap3xxx_i2c1_hwmod = {
+	.name		= "i2c1",
+	.mpu_irqs	= i2c1_mpu_irqs,
+	.mpu_irqs_cnt	= ARRAY_SIZE(i2c1_mpu_irqs),
+	.sdma_reqs	= i2c1_sdma_reqs,
+	.sdma_reqs_cnt	= ARRAY_SIZE(i2c1_sdma_reqs),
+	.main_clk	= "i2c1_fck",
+	.prcm		= {
+		.omap2 = {
+			.prcm_reg_id = 1,
+			.module_bit = OMAP3430_GRPSEL_I2C1_SHIFT,
+			.idlest_reg_id = 1,
+			.idlest_idle_bit = OMAP3430_GRPSEL_I2C1_SHIFT,
+		},
+	},
+	.slaves		= omap3xxx_i2c1_slaves,
+	.slaves_cnt	= ARRAY_SIZE(omap3xxx_i2c1_slaves),
+	.class		= &i2c_class,
+	.dev_attr	= &i2c1_dev_attr,
+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/* I2C2 */
+
+static struct omap_i2c_dev_attr i2c2_dev_attr = {
+	.fifo_depth	= 8, /* bytes */
+};
+
+static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
+	{ .irq = INT_24XX_I2C2_IRQ, },
+};
+
+static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
+	{ .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
+	{ .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
+};
+
+static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
+	&omap3_l4_core__i2c2,
+};
+
+static struct omap_hwmod omap3xxx_i2c2_hwmod = {
+	.name		= "i2c2",
+	.mpu_irqs	= i2c2_mpu_irqs,
+	.mpu_irqs_cnt	= ARRAY_SIZE(i2c2_mpu_irqs),
+	.sdma_reqs	= i2c2_sdma_reqs,
+	.sdma_reqs_cnt	= ARRAY_SIZE(i2c2_sdma_reqs),
+	.main_clk	= "i2c2_fck",
+	.prcm		= {
+		.omap2 = {
+			.prcm_reg_id = 1,
+			.module_bit = OMAP3430_GRPSEL_I2C2_SHIFT,
+			.idlest_reg_id = 1,
+			.idlest_idle_bit = OMAP3430_GRPSEL_I2C2_SHIFT,
+		},
+	},
+	.slaves		= omap3xxx_i2c2_slaves,
+	.slaves_cnt	= ARRAY_SIZE(omap3xxx_i2c2_slaves),
+	.class		= &i2c_class,
+	.dev_attr	= &i2c2_dev_attr,
+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/* I2C3 */
+
+static struct omap_i2c_dev_attr i2c3_dev_attr = {
+	.fifo_depth	= 64, /* bytes */
+};
+
+static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
+	{ .irq = INT_34XX_I2C3_IRQ, },
+};
+
+static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
+	{ .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
+	{ .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
+};
+
+static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
+	&omap3_l4_core__i2c3,
+};
+
+static struct omap_hwmod omap3xxx_i2c3_hwmod = {
+	.name		= "i2c3",
+	.mpu_irqs	= i2c3_mpu_irqs,
+	.mpu_irqs_cnt	= ARRAY_SIZE(i2c3_mpu_irqs),
+	.sdma_reqs	= i2c3_sdma_reqs,
+	.sdma_reqs_cnt	= ARRAY_SIZE(i2c3_sdma_reqs),
+	.main_clk	= "i2c3_fck",
+	.prcm		= {
+		.omap2 = {
+			.prcm_reg_id = 1,
+			.module_bit = OMAP3430_GRPSEL_I2C3_SHIFT,
+			.idlest_reg_id = 1,
+			.idlest_idle_bit = OMAP3430_GRPSEL_I2C3_SHIFT,
+		},
+	},
+	.slaves		= omap3xxx_i2c3_slaves,
+	.slaves_cnt	= ARRAY_SIZE(omap3xxx_i2c3_slaves),
+	.class		= &i2c_class,
+	.dev_attr	= &i2c3_dev_attr,
+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
 static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
 	&omap3xxx_l3_main_hwmod,
 	&omap3xxx_l4_core_hwmod,
@@ -204,6 +433,9 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
 	&omap3xxx_l4_wkup_hwmod,
 	&omap3xxx_mpu_hwmod,
 	&omap3xxx_iva_hwmod,
+	&omap3xxx_i2c1_hwmod,
+	&omap3xxx_i2c2_hwmod,
+	&omap3xxx_i2c3_hwmod,
 	NULL,
 };
 
diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h
index 7fd6023..51c354e 100644
--- a/arch/arm/mach-omap2/prm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-34xx.h
@@ -101,8 +101,11 @@
 #define OMAP3430_GRPSEL_MCSPI3_MASK			(1 << 20)
 #define OMAP3430_GRPSEL_MCSPI2_MASK			(1 << 19)
 #define OMAP3430_GRPSEL_MCSPI1_MASK			(1 << 18)
+#define OMAP3430_GRPSEL_I2C3_SHIFT			17
 #define OMAP3430_GRPSEL_I2C3_MASK			(1 << 17)
+#define OMAP3430_GRPSEL_I2C2_SHIFT			16
 #define OMAP3430_GRPSEL_I2C2_MASK			(1 << 16)
+#define OMAP3430_GRPSEL_I2C1_SHIFT			15
 #define OMAP3430_GRPSEL_I2C1_MASK			(1 << 15)
 #define OMAP3430_GRPSEL_UART2_MASK			(1 << 14)
 #define OMAP3430_GRPSEL_UART1_MASK			(1 << 13)
diff --git a/arch/arm/plat-omap/include/plat/i2c.h b/arch/arm/plat-omap/include/plat/i2c.h
index 87f6bf2..86d0199 100644
--- a/arch/arm/plat-omap/include/plat/i2c.h
+++ b/arch/arm/plat-omap/include/plat/i2c.h
@@ -18,6 +18,8 @@
  * 02110-1301 USA
  *
  */
+#ifndef __ASM_ARCH_I2C_H
+#define __ASM_ARCH_I2C_H
 
 #include <linux/i2c.h>
 
@@ -34,5 +36,19 @@ static inline int omap_register_i2c_bus(int bus_id, u32 clkrate,
 }
 #endif
 
+/**
+ * i2c_dev_attr - OMAP I2C controller device attributes for omap_hwmod
+ * @fifo_depth: total controller FIFO size (in bytes)
+ * @flags: differences in hardware support capability
+ *
+ * @fifo_depth represents what exists on the hardware, not what is
+ * actually configured at runtime by the device driver.
+ */
+struct omap_i2c_dev_attr {
+	u8	fifo_depth;
+	u8	flags;
+};
+
 void __init omap1_i2c_mux_pins(int bus_id);
 void __init omap2_i2c_mux_pins(int bus_id);
+#endif
diff --git a/arch/arm/plat-omap/include/plat/l4_3xxx.h b/arch/arm/plat-omap/include/plat/l4_3xxx.h
new file mode 100644
index 0000000..5e19493
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/l4_3xxx.h
@@ -0,0 +1,24 @@
+/*
+ * arch/arm/plat-omap/include/mach/l4_3xxx.h - L4 firewall definitions
+ *
+ * Copyright (C) 2009 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_L4_3XXX_H
+#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_L4_3XXX_H
+
+/* L4 CORE */
+#define OMAP3_L4_CORE_FW_I2C1_REGION				21
+#define OMAP3_L4_CORE_FW_I2C1_TA_REGION				22
+#define OMAP3_L4_CORE_FW_I2C2_REGION				23
+#define OMAP3_L4_CORE_FW_I2C2_TA_REGION				24
+#define OMAP3_L4_CORE_FW_I2C3_REGION				73
+#define OMAP3_L4_CORE_FW_I2C3_TA_REGION				74
+
+#endif
-- 
1.7.0.4

[PATCH v2 3/5] OMAP4: hwmod: add I2C hwmods for OMAP4430

[Rajendra Nayak]

Add hwmod structures for I2C controllers on OMAP4430.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
---
This patch is extracted from the below patch
OMAP4: hwmod: Add initial data for OMAP4430 ES1 & ES2
https://patchwork.kernel.org/patch/117347/

 arch/arm/mach-omap2/omap_hwmod_44xx_data.c |  237 ++++++++++++++++++++++++++++
 1 files changed, 237 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index e20b0ee..2cb63fc 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -383,6 +383,238 @@ static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
 };
 
 /*
+ * 'i2c' class
+ * multimaster high-speed i2c controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
+	.sysc_offs	= 0x0010,
+	.syss_offs	= 0x0090,
+	.sysc_flags	= (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
+			   SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SOFTRESET |
+			   SYSC_HAS_AUTOIDLE),
+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+	.sysc_fields	= &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
+	.name = "i2c",
+	.sysc = &omap44xx_i2c_sysc,
+};
+
+/* i2c1 */
+static struct omap_hwmod omap44xx_i2c1_hwmod;
+static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
+	{ .irq = 56 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
+	{ .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
+	{ .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
+	{
+		.pa_start	= 0x48070000,
+		.pa_end		= 0x480700ff,
+		.flags		= ADDR_TYPE_RT
+	},
+};
+
+/* l4_per -> i2c1 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
+	.master		= &omap44xx_l4_per_hwmod,
+	.slave		= &omap44xx_i2c1_hwmod,
+	.clk		= "l4_div_ck",
+	.addr		= omap44xx_i2c1_addrs,
+	.addr_cnt	= ARRAY_SIZE(omap44xx_i2c1_addrs),
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* i2c1 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
+	&omap44xx_l4_per__i2c1,
+};
+
+static struct omap_hwmod omap44xx_i2c1_hwmod = {
+	.name		= "i2c1",
+	.class		= &omap44xx_i2c_hwmod_class,
+	.flags		= HWMOD_INIT_NO_RESET,
+	.mpu_irqs	= omap44xx_i2c1_irqs,
+	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_i2c1_irqs),
+	.sdma_reqs	= omap44xx_i2c1_sdma_reqs,
+	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_i2c1_sdma_reqs),
+	.main_clk	= "i2c1_fck",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
+		},
+	},
+	.slaves		= omap44xx_i2c1_slaves,
+	.slaves_cnt	= ARRAY_SIZE(omap44xx_i2c1_slaves),
+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* i2c2 */
+static struct omap_hwmod omap44xx_i2c2_hwmod;
+static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
+	{ .irq = 57 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
+	{ .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
+	{ .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
+	{
+		.pa_start	= 0x48072000,
+		.pa_end		= 0x480720ff,
+		.flags		= ADDR_TYPE_RT
+	},
+};
+
+/* l4_per -> i2c2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
+	.master		= &omap44xx_l4_per_hwmod,
+	.slave		= &omap44xx_i2c2_hwmod,
+	.clk		= "l4_div_ck",
+	.addr		= omap44xx_i2c2_addrs,
+	.addr_cnt	= ARRAY_SIZE(omap44xx_i2c2_addrs),
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* i2c2 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
+	&omap44xx_l4_per__i2c2,
+};
+
+static struct omap_hwmod omap44xx_i2c2_hwmod = {
+	.name		= "i2c2",
+	.class		= &omap44xx_i2c_hwmod_class,
+	.flags		= HWMOD_INIT_NO_RESET,
+	.mpu_irqs	= omap44xx_i2c2_irqs,
+	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_i2c2_irqs),
+	.sdma_reqs	= omap44xx_i2c2_sdma_reqs,
+	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_i2c2_sdma_reqs),
+	.main_clk	= "i2c2_fck",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
+		},
+	},
+	.slaves		= omap44xx_i2c2_slaves,
+	.slaves_cnt	= ARRAY_SIZE(omap44xx_i2c2_slaves),
+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* i2c3 */
+static struct omap_hwmod omap44xx_i2c3_hwmod;
+static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
+	{ .irq = 61 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
+	{ .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
+	{ .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
+	{
+		.pa_start	= 0x48060000,
+		.pa_end		= 0x480600ff,
+		.flags		= ADDR_TYPE_RT
+	},
+};
+
+/* l4_per -> i2c3 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
+	.master		= &omap44xx_l4_per_hwmod,
+	.slave		= &omap44xx_i2c3_hwmod,
+	.clk		= "l4_div_ck",
+	.addr		= omap44xx_i2c3_addrs,
+	.addr_cnt	= ARRAY_SIZE(omap44xx_i2c3_addrs),
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* i2c3 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
+	&omap44xx_l4_per__i2c3,
+};
+
+static struct omap_hwmod omap44xx_i2c3_hwmod = {
+	.name		= "i2c3",
+	.class		= &omap44xx_i2c_hwmod_class,
+	.flags		= HWMOD_INIT_NO_RESET,
+	.mpu_irqs	= omap44xx_i2c3_irqs,
+	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_i2c3_irqs),
+	.sdma_reqs	= omap44xx_i2c3_sdma_reqs,
+	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_i2c3_sdma_reqs),
+	.main_clk	= "i2c3_fck",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
+		},
+	},
+	.slaves		= omap44xx_i2c3_slaves,
+	.slaves_cnt	= ARRAY_SIZE(omap44xx_i2c3_slaves),
+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* i2c4 */
+static struct omap_hwmod omap44xx_i2c4_hwmod;
+static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
+	{ .irq = 62 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
+	{ .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
+	{ .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
+	{
+		.pa_start	= 0x48350000,
+		.pa_end		= 0x483500ff,
+		.flags		= ADDR_TYPE_RT
+	},
+};
+
+/* l4_per -> i2c4 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
+	.master		= &omap44xx_l4_per_hwmod,
+	.slave		= &omap44xx_i2c4_hwmod,
+	.clk		= "l4_div_ck",
+	.addr		= omap44xx_i2c4_addrs,
+	.addr_cnt	= ARRAY_SIZE(omap44xx_i2c4_addrs),
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* i2c4 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
+	&omap44xx_l4_per__i2c4,
+};
+
+static struct omap_hwmod omap44xx_i2c4_hwmod = {
+	.name		= "i2c4",
+	.class		= &omap44xx_i2c_hwmod_class,
+	.flags		= HWMOD_INIT_NO_RESET,
+	.mpu_irqs	= omap44xx_i2c4_irqs,
+	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_i2c4_irqs),
+	.sdma_reqs	= omap44xx_i2c4_sdma_reqs,
+	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_i2c4_sdma_reqs),
+	.main_clk	= "i2c4_fck",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
+		},
+	},
+	.slaves		= omap44xx_i2c4_slaves,
+	.slaves_cnt	= ARRAY_SIZE(omap44xx_i2c4_slaves),
+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
  * 'mpu_bus' class
  * instance(s): mpu_private
  */
@@ -467,6 +699,11 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
 	&omap44xx_l4_cfg_hwmod,
 	&omap44xx_l4_per_hwmod,
 	&omap44xx_l4_wkup_hwmod,
+	/* i2c class */
+	&omap44xx_i2c1_hwmod,
+	&omap44xx_i2c2_hwmod,
+	&omap44xx_i2c3_hwmod,
+	&omap44xx_i2c4_hwmod,
 	/* mpu_bus class */
 	&omap44xx_mpu_private_hwmod,
 
-- 
1.7.0.4

[PATCH v2 4/5] OMAP: I2C: split device registration and convert OMAP2+ to omap_device

[Rajendra Nayak]

From: Paul Walmsley <paul@pwsan.com>

Split the OMAP1 and OMAP2+ platform_device build and register code.
Convert the OMAP2+ variant to use omap_device.

This patch was developed in collaboration with Rajendra Nayak
<rnayak@ti.com>.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
---
 arch/arm/plat-omap/i2c.c |  124 ++++++++++++++++++----------------------------
 include/linux/i2c-omap.h |    5 ++
 2 files changed, 54 insertions(+), 75 deletions(-)

diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c
index a5ce4f0..a5bff9c 100644
--- a/arch/arm/plat-omap/i2c.c
+++ b/arch/arm/plat-omap/i2c.c
@@ -27,18 +27,18 @@
 #include <linux/platform_device.h>
 #include <linux/i2c.h>
 #include <linux/i2c-omap.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include <linux/clk.h>
 
 #include <mach/irqs.h>
 #include <plat/mux.h>
 #include <plat/i2c.h>
 #include <plat/omap-pm.h>
+#include <plat/omap_device.h>
 
 #define OMAP_I2C_SIZE		0x3f
 #define OMAP1_I2C_BASE		0xfffb3800
-#define OMAP2_I2C_BASE1		0x48070000
-#define OMAP2_I2C_BASE2		0x48072000
-#define OMAP2_I2C_BASE3		0x48060000
-#define OMAP4_I2C_BASE4		0x48350000
 
 static const char name[] = "i2c_omap";
 
@@ -55,15 +55,6 @@ static const char name[] = "i2c_omap";
 
 static struct resource i2c_resources[][2] = {
 	{ I2C_RESOURCE_BUILDER(0, 0) },
-#if	defined(CONFIG_ARCH_OMAP2PLUS)
-	{ I2C_RESOURCE_BUILDER(OMAP2_I2C_BASE2, 0) },
-#endif
-#if	defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
-	{ I2C_RESOURCE_BUILDER(OMAP2_I2C_BASE3, 0) },
-#endif
-#if	defined(CONFIG_ARCH_OMAP4)
-	{ I2C_RESOURCE_BUILDER(OMAP4_I2C_BASE4, 0) },
-#endif
 };
 
 #define I2C_DEV_BUILDER(bus_id, res, data)		\
@@ -77,18 +68,11 @@ static struct resource i2c_resources[][2] = {
 		},					\
 	}
 
-static struct omap_i2c_bus_platform_data i2c_pdata[ARRAY_SIZE(i2c_resources)];
+#define MAX_OMAP_I2C_HWMOD_NAME_LEN	16
+#define OMAP_I2C_MAX_CONTROLLERS 4
+static struct omap_i2c_bus_platform_data i2c_pdata[OMAP_I2C_MAX_CONTROLLERS];
 static struct platform_device omap_i2c_devices[] = {
 	I2C_DEV_BUILDER(1, i2c_resources[0], &i2c_pdata[0]),
-#if	defined(CONFIG_ARCH_OMAP2PLUS)
-	I2C_DEV_BUILDER(2, i2c_resources[1], &i2c_pdata[1]),
-#endif
-#if	defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
-	I2C_DEV_BUILDER(3, i2c_resources[2], &i2c_pdata[2]),
-#endif
-#if	defined(CONFIG_ARCH_OMAP4)
-	I2C_DEV_BUILDER(4, i2c_resources[3], &i2c_pdata[3]),
-#endif
 };
 
 #define OMAP_I2C_CMDLINE_SETUP	(BIT(31))
@@ -109,35 +93,20 @@ static int __init omap_i2c_nr_ports(void)
 	return ports;
 }
 
-/* Shared between omap2 and 3 */
-static resource_size_t omap2_i2c_irq[3] __initdata = {
-	INT_24XX_I2C1_IRQ,
-	INT_24XX_I2C2_IRQ,
-	INT_34XX_I2C3_IRQ,
-};
-
-static resource_size_t omap4_i2c_irq[4] __initdata = {
-	OMAP44XX_IRQ_I2C1,
-	OMAP44XX_IRQ_I2C2,
-	OMAP44XX_IRQ_I2C3,
-	OMAP44XX_IRQ_I2C4,
-};
-
-static inline int omap1_i2c_add_bus(struct platform_device *pdev, int bus_id)
+static inline int omap1_i2c_add_bus(int bus_id)
 {
-	struct omap_i2c_bus_platform_data *pd;
-	struct resource *res;
-
-	pd = pdev->dev.platform_data;
-	res = pdev->resource;
-	res[0].start = OMAP1_I2C_BASE;
-	res[0].end = res[0].start + OMAP_I2C_SIZE;
-	res[1].start = INT_I2C;
+	struct platform_device *pdev;
+	struct omap_i2c_bus_platform_data *pdata;
+
 	omap1_i2c_mux_pins(bus_id);
 
+	pdev = &omap_i2c_devices[bus_id - 1];
+	pdata = &i2c_pdata[bus_id - 1];
+
 	return platform_device_register(pdev);
 }
 
+
 /*
  * XXX This function is a temporary compatibility wrapper - only
  * needed until the I2C driver can be converted to call
@@ -148,52 +117,57 @@ static void omap_pm_set_max_mpu_wakeup_lat_compat(struct device *dev, long t)
 	omap_pm_set_max_mpu_wakeup_lat(dev, t);
 }
 
-static inline int omap2_i2c_add_bus(struct platform_device *pdev, int bus_id)
-{
-	struct resource *res;
-	resource_size_t *irq;
+static struct omap_device_pm_latency omap_i2c_latency[] = {
+	[0] = {
+		.deactivate_func	= omap_device_idle_hwmods,
+		.activate_func		= omap_device_enable_hwmods,
+		.flags			= OMAP_DEVICE_LATENCY_AUTO_ADJUST,
+	},
+};
 
-	res = pdev->resource;
+static inline int omap2_i2c_add_bus(int bus_id)
+{
+	int l;
+	struct omap_hwmod *oh;
+	struct omap_device *od;
+	char oh_name[MAX_OMAP_I2C_HWMOD_NAME_LEN];
+	struct omap_i2c_bus_platform_data *pdata;
 
-	if (!cpu_is_omap44xx())
-		irq = omap2_i2c_irq;
-	else
-		irq = omap4_i2c_irq;
+	omap2_i2c_mux_pins(bus_id);
 
-	if (bus_id == 1) {
-		res[0].start = OMAP2_I2C_BASE1;
-		res[0].end = res[0].start + OMAP_I2C_SIZE;
+	l = snprintf(oh_name, MAX_OMAP_I2C_HWMOD_NAME_LEN, "i2c%d", bus_id);
+	WARN(l >= MAX_OMAP_I2C_HWMOD_NAME_LEN,
+		"String buffer overflow in I2C%d device setup\n", bus_id);
+	oh = omap_hwmod_lookup(oh_name);
+	if (!oh) {
+			pr_err("Could not look up %s\n", oh_name);
+			return -EEXIST;
 	}
 
-	res[1].start = irq[bus_id - 1];
-	omap2_i2c_mux_pins(bus_id);
-
+	pdata = &i2c_pdata[bus_id - 1];
 	/*
 	 * When waiting for completion of a i2c transfer, we need to
 	 * set a wake up latency constraint for the MPU. This is to
 	 * ensure quick enough wakeup from idle, when transfer
 	 * completes.
+	 * Only omap3 has support for constraints
 	 */
-	if (cpu_is_omap34xx()) {
-		struct omap_i2c_bus_platform_data *pd;
-
-		pd = pdev->dev.platform_data;
-		pd->set_mpu_wkup_lat = omap_pm_set_max_mpu_wakeup_lat_compat;
-	}
-
-	return platform_device_register(pdev);
+	if (cpu_is_omap34xx())
+		pdata->set_mpu_wkup_lat = omap_pm_set_max_mpu_wakeup_lat_compat;
+	od = omap_device_build(name, bus_id, oh, pdata,
+			sizeof(struct omap_i2c_bus_platform_data),
+			omap_i2c_latency, ARRAY_SIZE(omap_i2c_latency), 0);
+	WARN(IS_ERR(od), "Could not build omap_device for %s\n", name);
+
+	return PTR_ERR(od);
 }
 
 static int __init omap_i2c_add_bus(int bus_id)
 {
-	struct platform_device *pdev;
-
-	pdev = &omap_i2c_devices[bus_id - 1];
-
 	if (cpu_class_is_omap1())
-		return omap1_i2c_add_bus(pdev, bus_id);
+		return omap1_i2c_add_bus(bus_id);
 	else
-		return omap2_i2c_add_bus(pdev, bus_id);
+		return omap2_i2c_add_bus(bus_id);
 }
 
 /**
diff --git a/include/linux/i2c-omap.h b/include/linux/i2c-omap.h
index 78ebf50..7472449 100644
--- a/include/linux/i2c-omap.h
+++ b/include/linux/i2c-omap.h
@@ -1,9 +1,14 @@
 #ifndef __I2C_OMAP_H__
 #define __I2C_OMAP_H__
 
+#include <linux/platform_device.h>
+
 struct omap_i2c_bus_platform_data {
 	u32		clkrate;
 	void		(*set_mpu_wkup_lat)(struct device *dev, long set);
+	int		(*device_enable) (struct platform_device *pdev);
+	int		(*device_shutdown) (struct platform_device *pdev);
+	int		(*device_idle) (struct platform_device *pdev);
 };
 
 #endif
-- 
1.7.0.4

[PATCH v2 5/5] OMAP: I2C: Convert i2c driver to use PM runtime api's

[Rajendra Nayak]

This patch converts the i2c driver to use PM runtime apis

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Paul Walmsley <paul@pwsan.com>
---
 drivers/i2c/busses/i2c-omap.c |   67 +++++++++++++----------------------------
 1 files changed, 21 insertions(+), 46 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 7674efb..126bde9 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -39,6 +39,7 @@
 #include <linux/io.h>
 #include <linux/slab.h>
 #include <linux/i2c-omap.h>
+#include <linux/pm_runtime.h>
 
 /* I2C controller revisions */
 #define OMAP_I2C_REV_2			0x20
@@ -175,8 +176,6 @@ struct omap_i2c_dev {
 	void __iomem		*base;		/* virtual */
 	int			irq;
 	int			reg_shift;      /* bit shift for I2C register addresses */
-	struct clk		*iclk;		/* Interface clock */
-	struct clk		*fclk;		/* Functional clock */
 	struct completion	cmd_complete;
 	struct resource		*ioarea;
 	u32			latency;	/* maximum mpu wkup latency */
@@ -265,45 +264,18 @@ static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
 				(i2c_dev->regs[reg] << i2c_dev->reg_shift));
 }
 
-static int __init omap_i2c_get_clocks(struct omap_i2c_dev *dev)
+static void omap_i2c_unidle(struct omap_i2c_dev *dev)
 {
-	int ret;
+	struct platform_device *pdev;
+	struct omap_i2c_bus_platform_data *pdata;
 
-	dev->iclk = clk_get(dev->dev, "ick");
-	if (IS_ERR(dev->iclk)) {
-		ret = PTR_ERR(dev->iclk);
-		dev->iclk = NULL;
-		return ret;
-	}
+	WARN_ON(!dev->idle);
 
-	dev->fclk = clk_get(dev->dev, "fck");
-	if (IS_ERR(dev->fclk)) {
-		ret = PTR_ERR(dev->fclk);
-		if (dev->iclk != NULL) {
-			clk_put(dev->iclk);
-			dev->iclk = NULL;
-		}
-		dev->fclk = NULL;
-		return ret;
-	}
+	pdev = to_platform_device(dev->dev);
+	pdata = pdev->dev.platform_data;
 
-	return 0;
-}
+	pm_runtime_get_sync(&pdev->dev);
 
-static void omap_i2c_put_clocks(struct omap_i2c_dev *dev)
-{
-	clk_put(dev->fclk);
-	dev->fclk = NULL;
-	clk_put(dev->iclk);
-	dev->iclk = NULL;
-}
-
-static void omap_i2c_unidle(struct omap_i2c_dev *dev)
-{
-	WARN_ON(!dev->idle);
-
-	clk_enable(dev->iclk);
-	clk_enable(dev->fclk);
 	if (cpu_is_omap34xx()) {
 		omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
 		omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, dev->pscstate);
@@ -326,10 +298,15 @@ static void omap_i2c_unidle(struct omap_i2c_dev *dev)
 
 static void omap_i2c_idle(struct omap_i2c_dev *dev)
 {
+	struct platform_device *pdev;
+	struct omap_i2c_bus_platform_data *pdata;
 	u16 iv;
 
 	WARN_ON(dev->idle);
 
+	pdev = to_platform_device(dev->dev);
+	pdata = pdev->dev.platform_data;
+
 	dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
 	if (dev->rev >= OMAP_I2C_REV_ON_4430)
 		omap_i2c_write_reg(dev, OMAP_I2C_IRQENABLE_CLR, 1);
@@ -345,8 +322,8 @@ static void omap_i2c_idle(struct omap_i2c_dev *dev)
 		omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
 	}
 	dev->idle = 1;
-	clk_disable(dev->fclk);
-	clk_disable(dev->iclk);
+
+	pm_runtime_put_sync(&pdev->dev);
 }
 
 static int omap_i2c_init(struct omap_i2c_dev *dev)
@@ -356,6 +333,7 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
 	unsigned long fclk_rate = 12000000;
 	unsigned long timeout;
 	unsigned long internal_clk = 0;
+	struct clk *fclk;
 
 	if (dev->rev >= OMAP_I2C_REV_2) {
 		/* Disable I2C controller before soft reset */
@@ -414,7 +392,8 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
 		 * always returns 12MHz for the functional clock, we can
 		 * do this bit unconditionally.
 		 */
-		fclk_rate = clk_get_rate(dev->fclk);
+		fclk = clk_get(dev->dev, "fck");
+		fclk_rate = clk_get_rate(fclk);
 
 		/* TRM for 5912 says the I2C clock must be prescaled to be
 		 * between 7 - 12 MHz. The XOR input clock is typically
@@ -443,7 +422,8 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
 			internal_clk = 9600;
 		else
 			internal_clk = 4000;
-		fclk_rate = clk_get_rate(dev->fclk) / 1000;
+		fclk = clk_get(dev->dev, "fck");
+		fclk_rate = clk_get_rate(fclk) / 1000;
 
 		/* Compute prescaler divisor */
 		psc = fclk_rate / internal_clk;
@@ -1046,14 +1026,12 @@ omap_i2c_probe(struct platform_device *pdev)
 	else
 		dev->reg_shift = 2;
 
-	if ((r = omap_i2c_get_clocks(dev)) != 0)
-		goto err_iounmap;
-
 	if (cpu_is_omap44xx())
 		dev->regs = (u8 *) omap4_reg_map;
 	else
 		dev->regs = (u8 *) reg_map;
 
+	pm_runtime_enable(&pdev->dev);
 	omap_i2c_unidle(dev);
 
 	dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;
@@ -1125,8 +1103,6 @@ err_free_irq:
 err_unuse_clocks:
 	omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
 	omap_i2c_idle(dev);
-	omap_i2c_put_clocks(dev);
-err_iounmap:
 	iounmap(dev->base);
 err_free_mem:
 	platform_set_drvdata(pdev, NULL);
@@ -1148,7 +1124,6 @@ omap_i2c_remove(struct platform_device *pdev)
 	free_irq(dev->irq, dev);
 	i2c_del_adapter(&dev->adapter);
 	omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
-	omap_i2c_put_clocks(dev);
 	iounmap(dev->base);
 	kfree(dev);
 	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-- 
1.7.0.4

Re: [PATCH v2 3/5] OMAP4: hwmod: add I2C hwmods for OMAP4430

[Kevin Hilman]

Rajendra Nayak <rnayak@ti.com> writes:

> Add hwmod structures for I2C controllers on OMAP4430.
>
> Signed-off-by: Rajendra Nayak <rnayak@ti.com>
> Signed-off-by: Benoit Cousson <b-cousson@ti.com>
> ---
> This patch is extracted from the below patch
> OMAP4: hwmod: Add initial data for OMAP4430 ES1 & ES2
> https://patchwork.kernel.org/patch/117347/

minor note: I will change the authorship to Benoit for this patch.

Thanks,

Kevin

>  arch/arm/mach-omap2/omap_hwmod_44xx_data.c |  237 ++++++++++++++++++++++++++++
>  1 files changed, 237 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
> index e20b0ee..2cb63fc 100644
> --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
> +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
> @@ -383,6 +383,238 @@ static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
>  };
>  
>  /*
> + * 'i2c' class
> + * multimaster high-speed i2c controller
> + */
> +
> +static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
> +	.sysc_offs	= 0x0010,
> +	.syss_offs	= 0x0090,
> +	.sysc_flags	= (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
> +			   SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SOFTRESET |
> +			   SYSC_HAS_AUTOIDLE),
> +	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
> +	.sysc_fields	= &omap_hwmod_sysc_type1,
> +};
> +
> +static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
> +	.name = "i2c",
> +	.sysc = &omap44xx_i2c_sysc,
> +};
> +
> +/* i2c1 */
> +static struct omap_hwmod omap44xx_i2c1_hwmod;
> +static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
> +	{ .irq = 56 + OMAP44XX_IRQ_GIC_START },
> +};
> +
> +static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
> +	{ .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
> +	{ .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
> +};
> +
> +static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
> +	{
> +		.pa_start	= 0x48070000,
> +		.pa_end		= 0x480700ff,
> +		.flags		= ADDR_TYPE_RT
> +	},
> +};
> +
> +/* l4_per -> i2c1 */
> +static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
> +	.master		= &omap44xx_l4_per_hwmod,
> +	.slave		= &omap44xx_i2c1_hwmod,
> +	.clk		= "l4_div_ck",
> +	.addr		= omap44xx_i2c1_addrs,
> +	.addr_cnt	= ARRAY_SIZE(omap44xx_i2c1_addrs),
> +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* i2c1 slave ports */
> +static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
> +	&omap44xx_l4_per__i2c1,
> +};
> +
> +static struct omap_hwmod omap44xx_i2c1_hwmod = {
> +	.name		= "i2c1",
> +	.class		= &omap44xx_i2c_hwmod_class,
> +	.flags		= HWMOD_INIT_NO_RESET,
> +	.mpu_irqs	= omap44xx_i2c1_irqs,
> +	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_i2c1_irqs),
> +	.sdma_reqs	= omap44xx_i2c1_sdma_reqs,
> +	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_i2c1_sdma_reqs),
> +	.main_clk	= "i2c1_fck",
> +	.prcm = {
> +		.omap4 = {
> +			.clkctrl_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
> +		},
> +	},
> +	.slaves		= omap44xx_i2c1_slaves,
> +	.slaves_cnt	= ARRAY_SIZE(omap44xx_i2c1_slaves),
> +	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
> +};
> +
> +/* i2c2 */
> +static struct omap_hwmod omap44xx_i2c2_hwmod;
> +static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
> +	{ .irq = 57 + OMAP44XX_IRQ_GIC_START },
> +};
> +
> +static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
> +	{ .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
> +	{ .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
> +};
> +
> +static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
> +	{
> +		.pa_start	= 0x48072000,
> +		.pa_end		= 0x480720ff,
> +		.flags		= ADDR_TYPE_RT
> +	},
> +};
> +
> +/* l4_per -> i2c2 */
> +static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
> +	.master		= &omap44xx_l4_per_hwmod,
> +	.slave		= &omap44xx_i2c2_hwmod,
> +	.clk		= "l4_div_ck",
> +	.addr		= omap44xx_i2c2_addrs,
> +	.addr_cnt	= ARRAY_SIZE(omap44xx_i2c2_addrs),
> +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* i2c2 slave ports */
> +static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
> +	&omap44xx_l4_per__i2c2,
> +};
> +
> +static struct omap_hwmod omap44xx_i2c2_hwmod = {
> +	.name		= "i2c2",
> +	.class		= &omap44xx_i2c_hwmod_class,
> +	.flags		= HWMOD_INIT_NO_RESET,
> +	.mpu_irqs	= omap44xx_i2c2_irqs,
> +	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_i2c2_irqs),
> +	.sdma_reqs	= omap44xx_i2c2_sdma_reqs,
> +	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_i2c2_sdma_reqs),
> +	.main_clk	= "i2c2_fck",
> +	.prcm = {
> +		.omap4 = {
> +			.clkctrl_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
> +		},
> +	},
> +	.slaves		= omap44xx_i2c2_slaves,
> +	.slaves_cnt	= ARRAY_SIZE(omap44xx_i2c2_slaves),
> +	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
> +};
> +
> +/* i2c3 */
> +static struct omap_hwmod omap44xx_i2c3_hwmod;
> +static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
> +	{ .irq = 61 + OMAP44XX_IRQ_GIC_START },
> +};
> +
> +static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
> +	{ .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
> +	{ .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
> +};
> +
> +static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
> +	{
> +		.pa_start	= 0x48060000,
> +		.pa_end		= 0x480600ff,
> +		.flags		= ADDR_TYPE_RT
> +	},
> +};
> +
> +/* l4_per -> i2c3 */
> +static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
> +	.master		= &omap44xx_l4_per_hwmod,
> +	.slave		= &omap44xx_i2c3_hwmod,
> +	.clk		= "l4_div_ck",
> +	.addr		= omap44xx_i2c3_addrs,
> +	.addr_cnt	= ARRAY_SIZE(omap44xx_i2c3_addrs),
> +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* i2c3 slave ports */
> +static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
> +	&omap44xx_l4_per__i2c3,
> +};
> +
> +static struct omap_hwmod omap44xx_i2c3_hwmod = {
> +	.name		= "i2c3",
> +	.class		= &omap44xx_i2c_hwmod_class,
> +	.flags		= HWMOD_INIT_NO_RESET,
> +	.mpu_irqs	= omap44xx_i2c3_irqs,
> +	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_i2c3_irqs),
> +	.sdma_reqs	= omap44xx_i2c3_sdma_reqs,
> +	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_i2c3_sdma_reqs),
> +	.main_clk	= "i2c3_fck",
> +	.prcm = {
> +		.omap4 = {
> +			.clkctrl_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
> +		},
> +	},
> +	.slaves		= omap44xx_i2c3_slaves,
> +	.slaves_cnt	= ARRAY_SIZE(omap44xx_i2c3_slaves),
> +	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
> +};
> +
> +/* i2c4 */
> +static struct omap_hwmod omap44xx_i2c4_hwmod;
> +static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
> +	{ .irq = 62 + OMAP44XX_IRQ_GIC_START },
> +};
> +
> +static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
> +	{ .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
> +	{ .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
> +};
> +
> +static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
> +	{
> +		.pa_start	= 0x48350000,
> +		.pa_end		= 0x483500ff,
> +		.flags		= ADDR_TYPE_RT
> +	},
> +};
> +
> +/* l4_per -> i2c4 */
> +static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
> +	.master		= &omap44xx_l4_per_hwmod,
> +	.slave		= &omap44xx_i2c4_hwmod,
> +	.clk		= "l4_div_ck",
> +	.addr		= omap44xx_i2c4_addrs,
> +	.addr_cnt	= ARRAY_SIZE(omap44xx_i2c4_addrs),
> +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* i2c4 slave ports */
> +static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
> +	&omap44xx_l4_per__i2c4,
> +};
> +
> +static struct omap_hwmod omap44xx_i2c4_hwmod = {
> +	.name		= "i2c4",
> +	.class		= &omap44xx_i2c_hwmod_class,
> +	.flags		= HWMOD_INIT_NO_RESET,
> +	.mpu_irqs	= omap44xx_i2c4_irqs,
> +	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_i2c4_irqs),
> +	.sdma_reqs	= omap44xx_i2c4_sdma_reqs,
> +	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_i2c4_sdma_reqs),
> +	.main_clk	= "i2c4_fck",
> +	.prcm = {
> +		.omap4 = {
> +			.clkctrl_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
> +		},
> +	},
> +	.slaves		= omap44xx_i2c4_slaves,
> +	.slaves_cnt	= ARRAY_SIZE(omap44xx_i2c4_slaves),
> +	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
> +};
> +
> +/*
>   * 'mpu_bus' class
>   * instance(s): mpu_private
>   */
> @@ -467,6 +699,11 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
>  	&omap44xx_l4_cfg_hwmod,
>  	&omap44xx_l4_per_hwmod,
>  	&omap44xx_l4_wkup_hwmod,
> +	/* i2c class */
> +	&omap44xx_i2c1_hwmod,
> +	&omap44xx_i2c2_hwmod,
> +	&omap44xx_i2c3_hwmod,
> +	&omap44xx_i2c4_hwmod,
>  	/* mpu_bus class */
>  	&omap44xx_mpu_private_hwmod,

RE: [PATCH v2 3/5] OMAP4: hwmod: add I2C hwmods for OMAP4430

[Nayak, Rajendra]

> -----Original Message-----
> From: Kevin Hilman [mailto:khilman@deeprootsystems.com]
> Sent: Tuesday, September 28, 2010 10:43 PM
> To: Nayak, Rajendra
> Cc: linux-omap@vger.kernel.org; Cousson, Benoit
> Subject: Re: [PATCH v2 3/5] OMAP4: hwmod: add I2C hwmods for OMAP4430
> 
> Rajendra Nayak <rnayak@ti.com> writes:
> 
> > Add hwmod structures for I2C controllers on OMAP4430.
> >
> > Signed-off-by: Rajendra Nayak <rnayak@ti.com>
> > Signed-off-by: Benoit Cousson <b-cousson@ti.com>
> > ---
> > This patch is extracted from the below patch
> > OMAP4: hwmod: Add initial data for OMAP4430 ES1 & ES2
> > https://patchwork.kernel.org/patch/117347/
> 
> minor note: I will change the authorship to Benoit for this patch.

Sure, should be fine.
Thanks,
Rajendra

> 
> Thanks,
> 
> Kevin
> 
> >  arch/arm/mach-omap2/omap_hwmod_44xx_data.c |  237 ++++++++++++++++++++++++++++
> >  1 files changed, 237 insertions(+), 0 deletions(-)
> >
> > diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
> > index e20b0ee..2cb63fc 100644
> > --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
> > +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
> > @@ -383,6 +383,238 @@ static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
> >  };
> >
> >  /*
> > + * 'i2c' class
> > + * multimaster high-speed i2c controller
> > + */
> > +
> > +static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
> > +	.sysc_offs	= 0x0010,
> > +	.syss_offs	= 0x0090,
> > +	.sysc_flags	= (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
> > +			   SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SOFTRESET |
> > +			   SYSC_HAS_AUTOIDLE),
> > +	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
> > +	.sysc_fields	= &omap_hwmod_sysc_type1,
> > +};
> > +
> > +static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
> > +	.name = "i2c",
> > +	.sysc = &omap44xx_i2c_sysc,
> > +};
> > +
> > +/* i2c1 */
> > +static struct omap_hwmod omap44xx_i2c1_hwmod;
> > +static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
> > +	{ .irq = 56 + OMAP44XX_IRQ_GIC_START },
> > +};
> > +
> > +static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
> > +	{ .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
> > +	{ .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
> > +};
> > +
> > +static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
> > +	{
> > +		.pa_start	= 0x48070000,
> > +		.pa_end		= 0x480700ff,
> > +		.flags		= ADDR_TYPE_RT
> > +	},
> > +};
> > +
> > +/* l4_per -> i2c1 */
> > +static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
> > +	.master		= &omap44xx_l4_per_hwmod,
> > +	.slave		= &omap44xx_i2c1_hwmod,
> > +	.clk		= "l4_div_ck",
> > +	.addr		= omap44xx_i2c1_addrs,
> > +	.addr_cnt	= ARRAY_SIZE(omap44xx_i2c1_addrs),
> > +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
> > +};
> > +
> > +/* i2c1 slave ports */
> > +static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
> > +	&omap44xx_l4_per__i2c1,
> > +};
> > +
> > +static struct omap_hwmod omap44xx_i2c1_hwmod = {
> > +	.name		= "i2c1",
> > +	.class		= &omap44xx_i2c_hwmod_class,
> > +	.flags		= HWMOD_INIT_NO_RESET,
> > +	.mpu_irqs	= omap44xx_i2c1_irqs,
> > +	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_i2c1_irqs),
> > +	.sdma_reqs	= omap44xx_i2c1_sdma_reqs,
> > +	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_i2c1_sdma_reqs),
> > +	.main_clk	= "i2c1_fck",
> > +	.prcm = {
> > +		.omap4 = {
> > +			.clkctrl_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
> > +		},
> > +	},
> > +	.slaves		= omap44xx_i2c1_slaves,
> > +	.slaves_cnt	= ARRAY_SIZE(omap44xx_i2c1_slaves),
> > +	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
> > +};
> > +
> > +/* i2c2 */
> > +static struct omap_hwmod omap44xx_i2c2_hwmod;
> > +static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
> > +	{ .irq = 57 + OMAP44XX_IRQ_GIC_START },
> > +};
> > +
> > +static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
> > +	{ .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
> > +	{ .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
> > +};
> > +
> > +static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
> > +	{
> > +		.pa_start	= 0x48072000,
> > +		.pa_end		= 0x480720ff,
> > +		.flags		= ADDR_TYPE_RT
> > +	},
> > +};
> > +
> > +/* l4_per -> i2c2 */
> > +static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
> > +	.master		= &omap44xx_l4_per_hwmod,
> > +	.slave		= &omap44xx_i2c2_hwmod,
> > +	.clk		= "l4_div_ck",
> > +	.addr		= omap44xx_i2c2_addrs,
> > +	.addr_cnt	= ARRAY_SIZE(omap44xx_i2c2_addrs),
> > +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
> > +};
> > +
> > +/* i2c2 slave ports */
> > +static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
> > +	&omap44xx_l4_per__i2c2,
> > +};
> > +
> > +static struct omap_hwmod omap44xx_i2c2_hwmod = {
> > +	.name		= "i2c2",
> > +	.class		= &omap44xx_i2c_hwmod_class,
> > +	.flags		= HWMOD_INIT_NO_RESET,
> > +	.mpu_irqs	= omap44xx_i2c2_irqs,
> > +	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_i2c2_irqs),
> > +	.sdma_reqs	= omap44xx_i2c2_sdma_reqs,
> > +	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_i2c2_sdma_reqs),
> > +	.main_clk	= "i2c2_fck",
> > +	.prcm = {
> > +		.omap4 = {
> > +			.clkctrl_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
> > +		},
> > +	},
> > +	.slaves		= omap44xx_i2c2_slaves,
> > +	.slaves_cnt	= ARRAY_SIZE(omap44xx_i2c2_slaves),
> > +	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
> > +};
> > +
> > +/* i2c3 */
> > +static struct omap_hwmod omap44xx_i2c3_hwmod;
> > +static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
> > +	{ .irq = 61 + OMAP44XX_IRQ_GIC_START },
> > +};
> > +
> > +static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
> > +	{ .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
> > +	{ .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
> > +};
> > +
> > +static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
> > +	{
> > +		.pa_start	= 0x48060000,
> > +		.pa_end		= 0x480600ff,
> > +		.flags		= ADDR_TYPE_RT
> > +	},
> > +};
> > +
> > +/* l4_per -> i2c3 */
> > +static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
> > +	.master		= &omap44xx_l4_per_hwmod,
> > +	.slave		= &omap44xx_i2c3_hwmod,
> > +	.clk		= "l4_div_ck",
> > +	.addr		= omap44xx_i2c3_addrs,
> > +	.addr_cnt	= ARRAY_SIZE(omap44xx_i2c3_addrs),
> > +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
> > +};
> > +
> > +/* i2c3 slave ports */
> > +static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
> > +	&omap44xx_l4_per__i2c3,
> > +};
> > +
> > +static struct omap_hwmod omap44xx_i2c3_hwmod = {
> > +	.name		= "i2c3",
> > +	.class		= &omap44xx_i2c_hwmod_class,
> > +	.flags		= HWMOD_INIT_NO_RESET,
> > +	.mpu_irqs	= omap44xx_i2c3_irqs,
> > +	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_i2c3_irqs),
> > +	.sdma_reqs	= omap44xx_i2c3_sdma_reqs,
> > +	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_i2c3_sdma_reqs),
> > +	.main_clk	= "i2c3_fck",
> > +	.prcm = {
> > +		.omap4 = {
> > +			.clkctrl_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
> > +		},
> > +	},
> > +	.slaves		= omap44xx_i2c3_slaves,
> > +	.slaves_cnt	= ARRAY_SIZE(omap44xx_i2c3_slaves),
> > +	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
> > +};
> > +
> > +/* i2c4 */
> > +static struct omap_hwmod omap44xx_i2c4_hwmod;
> > +static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
> > +	{ .irq = 62 + OMAP44XX_IRQ_GIC_START },
> > +};
> > +
> > +static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
> > +	{ .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
> > +	{ .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
> > +};
> > +
> > +static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
> > +	{
> > +		.pa_start	= 0x48350000,
> > +		.pa_end		= 0x483500ff,
> > +		.flags		= ADDR_TYPE_RT
> > +	},
> > +};
> > +
> > +/* l4_per -> i2c4 */
> > +static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
> > +	.master		= &omap44xx_l4_per_hwmod,
> > +	.slave		= &omap44xx_i2c4_hwmod,
> > +	.clk		= "l4_div_ck",
> > +	.addr		= omap44xx_i2c4_addrs,
> > +	.addr_cnt	= ARRAY_SIZE(omap44xx_i2c4_addrs),
> > +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
> > +};
> > +
> > +/* i2c4 slave ports */
> > +static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
> > +	&omap44xx_l4_per__i2c4,
> > +};
> > +
> > +static struct omap_hwmod omap44xx_i2c4_hwmod = {
> > +	.name		= "i2c4",
> > +	.class		= &omap44xx_i2c_hwmod_class,
> > +	.flags		= HWMOD_INIT_NO_RESET,
> > +	.mpu_irqs	= omap44xx_i2c4_irqs,
> > +	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_i2c4_irqs),
> > +	.sdma_reqs	= omap44xx_i2c4_sdma_reqs,
> > +	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_i2c4_sdma_reqs),
> > +	.main_clk	= "i2c4_fck",
> > +	.prcm = {
> > +		.omap4 = {
> > +			.clkctrl_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
> > +		},
> > +	},
> > +	.slaves		= omap44xx_i2c4_slaves,
> > +	.slaves_cnt	= ARRAY_SIZE(omap44xx_i2c4_slaves),
> > +	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
> > +};
> > +
> > +/*
> >   * 'mpu_bus' class
> >   * instance(s): mpu_private
> >   */
> > @@ -467,6 +699,11 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
> >  	&omap44xx_l4_cfg_hwmod,
> >  	&omap44xx_l4_per_hwmod,
> >  	&omap44xx_l4_wkup_hwmod,
> > +	/* i2c class */
> > +	&omap44xx_i2c1_hwmod,
> > +	&omap44xx_i2c2_hwmod,
> > +	&omap44xx_i2c3_hwmod,
> > +	&omap44xx_i2c4_hwmod,
> >  	/* mpu_bus class */
> >  	&omap44xx_mpu_private_hwmod,

Re: [PATCH v2 2/5] OMAP3: hwmod: add I2C hwmods for OMAP3430

[Paul Walmsley]

On Fri, 17 Sep 2010, Rajendra Nayak wrote:

> Add hwmod structures for I2C controllers on OMAP3430.

Also in this patch:

> +static struct omap_hwmod omap3xxx_i2c1_hwmod = {
> +	.name		= "i2c1",
> +	.mpu_irqs	= i2c1_mpu_irqs,
> +	.mpu_irqs_cnt	= ARRAY_SIZE(i2c1_mpu_irqs),
> +	.sdma_reqs	= i2c1_sdma_reqs,
> +	.sdma_reqs_cnt	= ARRAY_SIZE(i2c1_sdma_reqs),
> +	.main_clk	= "i2c1_fck",
> +	.prcm		= {
> +		.omap2 = {
> +			.prcm_reg_id = 1,
> +			.module_bit = OMAP3430_GRPSEL_I2C1_SHIFT,
> +			.idlest_reg_id = 1,
> +			.idlest_idle_bit = OMAP3430_GRPSEL_I2C1_SHIFT,

This should be OMAP3430_ST_I2C1_SHIFT; likewise for the rest of the I2C 
hwmods.

> +		},
> +	},
> +	.slaves		= omap3xxx_i2c1_slaves,
> +	.slaves_cnt	= ARRAY_SIZE(omap3xxx_i2c1_slaves),
> +	.class		= &i2c_class,
> +	.dev_attr	= &i2c1_dev_attr,
> +	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
> +};


- Paul

RE: [PATCH v2 2/5] OMAP3: hwmod: add I2C hwmods for OMAP3430

[Nayak, Rajendra]

> -----Original Message-----
> From: Paul Walmsley [mailto:paul@pwsan.com]
> Sent: Tuesday, September 21, 2010 12:47 PM
> To: Nayak, Rajendra
> Cc: linux-omap@vger.kernel.org; Kevin Hilman
> Subject: Re: [PATCH v2 2/5] OMAP3: hwmod: add I2C hwmods for OMAP3430
> 
> On Fri, 17 Sep 2010, Rajendra Nayak wrote:
> 
> > Add hwmod structures for I2C controllers on OMAP3430.
> 
> Also in this patch:
> 
> > +static struct omap_hwmod omap3xxx_i2c1_hwmod = {
> > +	.name		= "i2c1",
> > +	.mpu_irqs	= i2c1_mpu_irqs,
> > +	.mpu_irqs_cnt	= ARRAY_SIZE(i2c1_mpu_irqs),
> > +	.sdma_reqs	= i2c1_sdma_reqs,
> > +	.sdma_reqs_cnt	= ARRAY_SIZE(i2c1_sdma_reqs),
> > +	.main_clk	= "i2c1_fck",
> > +	.prcm		= {
> > +		.omap2 = {
> > +			.prcm_reg_id = 1,
> > +			.module_bit = OMAP3430_GRPSEL_I2C1_SHIFT,
> > +			.idlest_reg_id = 1,
> > +			.idlest_idle_bit = OMAP3430_GRPSEL_I2C1_SHIFT,
> 
> This should be OMAP3430_ST_I2C1_SHIFT; likewise for the rest of the I2C
> hwmods.

Thanks. Will fix this too.

> 
> > +		},
> > +	},
> > +	.slaves		= omap3xxx_i2c1_slaves,
> > +	.slaves_cnt	= ARRAY_SIZE(omap3xxx_i2c1_slaves),
> > +	.class		= &i2c_class,
> > +	.dev_attr	= &i2c1_dev_attr,
> > +	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
> > +};
> 
> 
> - Paul

Re: [PATCH v2 1/5] OMAP2xxx: hwmod: add I2C hwmods for OMAP2420, 2430

[Paul Walmsley]

Hi Rajendra,

On Fri, 17 Sep 2010, Rajendra Nayak wrote:

> From: Paul Walmsley <paul@pwsan.com>
> 
> Add hwmod structures for I2C controllers on OMAP2420/2430.

Looking at this series, patch 3 seems to be missing.  Could you please 
investigate why?

regards

- Paul

Re: [PATCH v2 1/5] OMAP2xxx: hwmod: add I2C hwmods for OMAP2420, 2430

[Paul Walmsley]

On Tue, 21 Sep 2010, Paul Walmsley wrote:

> Hi Rajendra,
> 
> On Fri, 17 Sep 2010, Rajendra Nayak wrote:
> 
> > From: Paul Walmsley <paul@pwsan.com>
> > 
> > Add hwmod structures for I2C controllers on OMAP2420/2430.
> 
> Looking at this series, patch 3 seems to be missing.  Could you please 
> investigate why?

Oops, never mind - I see it now.


- Paul

Re: [PATCH v2 1/5] OMAP2xxx: hwmod: add I2C hwmods for OMAP2420, 2430

[Paul Walmsley]

On Fri, 17 Sep 2010, Rajendra Nayak wrote:

> From: Paul Walmsley <paul@pwsan.com>
> 
> Add hwmod structures for I2C controllers on OMAP2420/2430.
> 
> Signed-off-by: Paul Walmsley <paul@pwsan.com>
> Signed-off-by: Rajendra Nayak <rnayak@ti.com>

Some items that stick out in this patch that should be fixed:

> +static struct omap_hwmod omap2420_i2c1_hwmod = {
> +	.name		= "i2c1",
> +	.mpu_irqs	= i2c1_mpu_irqs,
> +	.mpu_irqs_cnt	= ARRAY_SIZE(i2c1_mpu_irqs),
> +	.sdma_reqs	= i2c1_sdma_reqs,
> +	.sdma_reqs_cnt	= ARRAY_SIZE(i2c1_sdma_reqs),
> +	.main_clk	= "i2c1_fck",
> +	.prcm		= {
> +		.omap2 = {
> +			.prcm_reg_id = 1,
> +			.module_bit = OMAP2420_EN_I2C1_SHIFT,
> +			.idlest_reg_id = 1,
> +			.idlest_idle_bit = OMAP2420_EN_I2C1_SHIFT,

This should be OMAP2420_ST_I2C1_SHIFT, not OMAP2420_EN_I2C1_SHIFT.  
Likewise for the other entries.

> +static struct omap_hwmod omap2430_i2c1_hwmod = {
> +	.name		= "i2c1",
> +	.mpu_irqs	= i2c1_mpu_irqs,
> +	.mpu_irqs_cnt	= ARRAY_SIZE(i2c1_mpu_irqs),
> +	.sdma_reqs	= i2c1_sdma_reqs,
> +	.sdma_reqs_cnt	= ARRAY_SIZE(i2c1_sdma_reqs),
> +	.main_clk	= "i2c1_fck",
> +	.prcm		= {
> +		.omap2 = {
> +			.prcm_reg_id = 1,
> +			.module_bit = OMAP2430_EN_I2CHS1_SHIFT,
> +			.idlest_reg_id = 1,

This is wrong - the idlest_reg_id for the 2430 I2CHS blocks is different.  
Were these patches tested on 2430?

> +			.idlest_idle_bit = OMAP2430_EN_I2CHS1_SHIFT,
> +		},
> +	},
> +	.slaves		= omap2430_i2c1_slaves,
> +	.slaves_cnt	= ARRAY_SIZE(omap2430_i2c1_slaves),
> +	.class		= &i2c_class,
> +	.dev_attr	= &i2c1_dev_attr,
> +	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
> +};


- Paul

RE: [PATCH v2 1/5] OMAP2xxx: hwmod: add I2C hwmods for OMAP2420, 2430

[Nayak, Rajendra]

> -----Original Message-----
> From: Paul Walmsley [mailto:paul@pwsan.com]
> Sent: Tuesday, September 21, 2010 12:39 PM
> To: Nayak, Rajendra
> Cc: linux-omap@vger.kernel.org; Kevin Hilman
> Subject: Re: [PATCH v2 1/5] OMAP2xxx: hwmod: add I2C hwmods for OMAP2420,
> 2430
> 
> On Fri, 17 Sep 2010, Rajendra Nayak wrote:
> 
> > From: Paul Walmsley <paul@pwsan.com>
> >
> > Add hwmod structures for I2C controllers on OMAP2420/2430.
> >
> > Signed-off-by: Paul Walmsley <paul@pwsan.com>
> > Signed-off-by: Rajendra Nayak <rnayak@ti.com>
> 
> Some items that stick out in this patch that should be fixed:
> 
> > +static struct omap_hwmod omap2420_i2c1_hwmod = {
> > +	.name		= "i2c1",
> > +	.mpu_irqs	= i2c1_mpu_irqs,
> > +	.mpu_irqs_cnt	= ARRAY_SIZE(i2c1_mpu_irqs),
> > +	.sdma_reqs	= i2c1_sdma_reqs,
> > +	.sdma_reqs_cnt	= ARRAY_SIZE(i2c1_sdma_reqs),
> > +	.main_clk	= "i2c1_fck",
> > +	.prcm		= {
> > +		.omap2 = {
> > +			.prcm_reg_id = 1,
> > +			.module_bit = OMAP2420_EN_I2C1_SHIFT,
> > +			.idlest_reg_id = 1,
> > +			.idlest_idle_bit = OMAP2420_EN_I2C1_SHIFT,
> 
> This should be OMAP2420_ST_I2C1_SHIFT, not OMAP2420_EN_I2C1_SHIFT.
> Likewise for the other entries.

Thanks for catching this Paul, will fix it before I repost.

> 
> > +static struct omap_hwmod omap2430_i2c1_hwmod = {
> > +	.name		= "i2c1",
> > +	.mpu_irqs	= i2c1_mpu_irqs,
> > +	.mpu_irqs_cnt	= ARRAY_SIZE(i2c1_mpu_irqs),
> > +	.sdma_reqs	= i2c1_sdma_reqs,
> > +	.sdma_reqs_cnt	= ARRAY_SIZE(i2c1_sdma_reqs),
> > +	.main_clk	= "i2c1_fck",
> > +	.prcm		= {
> > +		.omap2 = {
> > +			.prcm_reg_id = 1,
> > +			.module_bit = OMAP2430_EN_I2CHS1_SHIFT,
> > +			.idlest_reg_id = 1,
> 
> This is wrong - the idlest_reg_id for the 2430 I2CHS blocks is different.
> Were these patches tested on 2430?

I did boot test on a 2430SDP after hacking around a lot with configs and commenting
out a bunch of stuff.

And I looked for this in the boot log and assumed I2C was fine
"i2c_omap i2c_omap.1: bus 1 rev3.7 at 100 kHz
 i2c_omap i2c_omap.2: bus 2 rev3.7 at 2600 kHz"

I will certainly have a relook again.

---- 2430 SDP boot log ---
Uncompressing Linux... done, booting the kernel.
Linux version 2.6.36-rc3-00044-g27f5f22-dirty (x0016154@omaplbp) (gcc version 4.4.1 (Sourcery G++ Lite 2010q1-202) ) #14 PREEMPT Wed Sep 15 15:02:45 IST 2010
CPU: ARMv6-compatible processor [4107b366] revision 6 (ARMv6TEJ), cr=00c5387f
CPU: VIPT aliasing data cache, VIPT aliasing instruction cache
Machine: OMAP2430 sdp2430 board
Memory policy: ECC disabled, Data cache writeback OMAP2430

SRAM: Mapped pa 0x40200000 to va 0xfe400000 size: 0x100000 Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 32512 Kernel command line: root=/dev/ram0 rw console=ttyS0,115200n8 initrd=0x81600000,20M ramdisk_size=20480 PID hash table entries: 512 (order: -1, 2048 bytes) Dentry cache hash table entries: 16384 (order: 4, 65536 bytes) Inode-cache hash table entries: 8192 (order: 3, 32768 bytes)
Memory: 128MB = 128MB total
Memory: 105540k/105540k available, 25532k reserved, 0K highmem Virtual kernel memory layout:
    vector  : 0xffff0000 - 0xffff1000   (   4 kB)
    fixmap  : 0xfff00000 - 0xfffe0000   ( 896 kB)
    DMA     : 0xffc00000 - 0xffe00000   (   2 MB)
    vmalloc : 0xc8800000 - 0xf8000000   ( 760 MB)
    lowmem  : 0xc0000000 - 0xc8000000   ( 128 MB)
    modules : 0xbf000000 - 0xc0000000   (  16 MB)
      .init : 0xc0008000 - 0xc002c000   ( 144 kB)
      .text : 0xc002c000 - 0xc0367000   (3308 kB)
      .data : 0xc0380000 - 0xc03b0160   ( 193 kB)
Hierarchical RCU implementation.
        Verbose stalled-CPUs detection is disabled.
NR_IRQS:388
Clocking rate (Crystal/DPLL/MPU): 13.0/660/330 MHz GPMC revision 3.0
IRQ: Found an INTC at 0xfa0fe000 (revision 3.0) with 96 interrupts Total of 96 interrupts on 1 active controller OMAP GPIO hardware version 2.4 OMAP clockevent source: GPTIMER1 at 32000 Hz
Console: colour dummy device 80x30
Calibrating delay loop... 320.37 BogoMIPS (lpj=1253376)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 512
CPU: Testing write buffer coherency: ok
regulator: core version 0.5
NET: Registered protocol family 16
USB: hmc 0, usb0 3 wires, Mini-AB on usb0 OMAP DMA hardware revision 4.0
bio: create slab <bio-0> at 0
i2c_omap i2c_omap.1: bus 1 rev3.7 at 100 kHz i2c_omap i2c_omap.2: bus 2 rev3.7 at 2600 kHz
twl4030: PIH (irq 7) chaining IRQs 368..375
twl4030: power (irq 373) chaining IRQs 376..383 Switching to clocksource 32k_counter
NET: Registered protocol family 2
IP route cache hash table entries: 1024 (order: 0, 4096 bytes) TCP established hash table entries: 4096 (order: 3, 32768 bytes) TCP bind hash table entries: 4096 (order: 2, 16384 bytes)
TCP: Hash tables configured (established 4096 bind 4096) TCP reno registered UDP hash table entries: 256 (order: 0, 4096 bytes) UDP-Lite hash table entries: 256 (order: 0, 4096 bytes)
NET: Registered protocol family 1
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
Trying to unpack rootfs image as initramfs...
rootfs image is not initramfs (junk in compressed archive); looks like an initrd Freeing initrd memory: 20480K
PMU: registered new PMU device of type 0 NetWinder Floating Point Emulator V0.97 (double precision)
VFS: Disk quotas dquot_6.5.2
Dquot-cache hash table entries: 1024 (order 0, 4096 bytes)
JFFS2 version 2.2. (NAND) (c) 2001-2006 Red Hat, Inc.
msgmni has been set to 246
alg: No test for stdrng (krng)
io scheduler noop registered
io scheduler deadline registered
io scheduler cfq registered (default)
omapfb: configured for panel sdp2430
omapfb: DISPC version 3.0 initialized
Console: switching to colour frame buffer device 30x40
omapfb: Framebuffer initialized. Total vram 155648 planes 1
omapfb: Pixclock 5156 kHz hfreq 18.2 kHz vfreq 54.8 Hz omap_rng omap_rng: OMAP Random Number Generator ver. 50
Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
serial8250.0: ttyS0 at MMIO 0x4806a000 (irq = 72) is a ST16654 console [ttyS0] enabled
serial8250.1: ttyS1 at MMIO 0x4806c000 (irq = 73) is a ST16654
serial8250.2: ttyS2 at MMIO 0x4806e000 (irq = 74) is a ST16654
brd: module loaded
loop: module loaded
OneNAND driver initializing
smc91x.c: v1.1, sep 22 2004 by Nicolas Pitre <nico@fluxnic.net>
eth0: SMC91C94 (rev 9) at c8858300 IRQ 309 [nowait]
eth0: Ethernet addr: 00:08:ff:03:47:43
i2c /dev entries driver
OMAP Watchdog Timer Rev 0x22: initial timeout 60 sec TCP cubic registered
NET: Registered protocol family 17
NET: Registered protocol family 15
Power Management for OMAP2 initializing
PRCM revision 1.0
VFP support v0.3: implementor 41 architecture 1 part 20 variant b rev 2
RAMDISK: ext2 filesystem found at block 0
RAMDISK: Loading 20480KiB [1 disk] into ram disk... done.
EXT2-fs (ram0): warning: mounting unchecked fs, running e2fsck is recommended
VFS: Mounted root (ext2 filesystem) on device 1:0.
Freeing init memory: 144K

> 
> > +			.idlest_idle_bit = OMAP2430_EN_I2CHS1_SHIFT,
> > +		},
> > +	},
> > +	.slaves		= omap2430_i2c1_slaves,
> > +	.slaves_cnt	= ARRAY_SIZE(omap2430_i2c1_slaves),
> > +	.class		= &i2c_class,
> > +	.dev_attr	= &i2c1_dev_attr,
> > +	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
> > +};
> 
> 
> - Paul

RE: [PATCH v2 1/5] OMAP2xxx: hwmod: add I2C hwmods for OMAP2420, 2430

[Paul Walmsley]

Hi Rajendra,

On Tue, 21 Sep 2010, Nayak, Rajendra wrote:

> > -----Original Message-----
> > From: Paul Walmsley [mailto:paul@pwsan.com]
> > Sent: Tuesday, September 21, 2010 12:39 PM
> > To: Nayak, Rajendra
> > Cc: linux-omap@vger.kernel.org; Kevin Hilman
> > Subject: Re: [PATCH v2 1/5] OMAP2xxx: hwmod: add I2C hwmods for OMAP2420,
> > 2430
> > 
> > On Fri, 17 Sep 2010, Rajendra Nayak wrote:
> > 
> > > From: Paul Walmsley <paul@pwsan.com>
> > >
> > > Add hwmod structures for I2C controllers on OMAP2420/2430.
> > >
> > > Signed-off-by: Paul Walmsley <paul@pwsan.com>
> > > Signed-off-by: Rajendra Nayak <rnayak@ti.com>
> > 
> > 
> > > +static struct omap_hwmod omap2430_i2c1_hwmod = {
> > > +	.name		= "i2c1",
> > > +	.mpu_irqs	= i2c1_mpu_irqs,
> > > +	.mpu_irqs_cnt	= ARRAY_SIZE(i2c1_mpu_irqs),
> > > +	.sdma_reqs	= i2c1_sdma_reqs,
> > > +	.sdma_reqs_cnt	= ARRAY_SIZE(i2c1_sdma_reqs),
> > > +	.main_clk	= "i2c1_fck",
> > > +	.prcm		= {
> > > +		.omap2 = {
> > > +			.prcm_reg_id = 1,
> > > +			.module_bit = OMAP2430_EN_I2CHS1_SHIFT,
> > > +			.idlest_reg_id = 1,
> > 
> > This is wrong - the idlest_reg_id for the 2430 I2CHS blocks is different.
> > Were these patches tested on 2430?
> 
> I did boot test on a 2430SDP after hacking around a lot with configs and commenting
> out a bunch of stuff.
> 
> And I looked for this in the boot log and assumed I2C was fine
> "i2c_omap i2c_omap.1: bus 1 rev3.7 at 100 kHz
>  i2c_omap i2c_omap.2: bus 2 rev3.7 at 2600 kHz"
> 
> I will certainly have a relook again.

My original comment was somewhat inaccurate.  Looking again at the 2430 
TRM, it looks like the idlest_reg_id is correct, but that the prcm_reg_id 
is not quite correct, at least for the FCLKEN register - not currently 
used by hwmod.  We may have to add a workaround flag for the 2430 I2CHS 
case.

I can see why this didn't cause a problem in your testing.  The clock 
framework writes to the correct FCLKEN bit, and the hwmod code currently 
doesn't touch the FCLKEN bit.  And then the hwmod code checks the 
correct IDLEST bit.

It may be that the clock framework is also buggy for the 2430 I2CHS case - 
that code will probably write to CM_ICLKEN2_CORE for 2430 I2CHS, but it 
should write to CM_ICLKEN1_CORE.  sigh...


- Paul

RE: [PATCH v2 1/5] OMAP2xxx: hwmod: add I2C hwmods for OMAP2420, 2430

[Paul Walmsley]

On Tue, 21 Sep 2010, Paul Walmsley wrote:

> My original comment was somewhat inaccurate.  Looking again at the 2430 
> TRM, it looks like the idlest_reg_id is correct, but that the prcm_reg_id 
> is not quite correct, at least for the FCLKEN register - not currently 
> used by hwmod.  We may have to add a workaround flag for the 2430 I2CHS 
> case.
> 
> I can see why this didn't cause a problem in your testing.  The clock 
> framework writes to the correct FCLKEN bit, and the hwmod code currently 
> doesn't touch the FCLKEN bit.  And then the hwmod code checks the 
> correct IDLEST bit.
> 
> It may be that the clock framework is also buggy for the 2430 I2CHS case - 
> that code will probably write to CM_ICLKEN2_CORE for 2430 I2CHS, but it 
> should write to CM_ICLKEN1_CORE.  sigh...

Just double-checked the clock code and data - it looks like the clock code 
is doing the right thing for 2430 I2CHS: it uses CM_ICLKEN1_CORE, 
CM_FCLKEN2_CORE, and CM_IDLEST1_CORE, despite the commit log comments on 
3dc2197579089c5b74c7fba666c8ccf1a449afb4, which are wrong.

So, that issue that I raised was a false alarm.  But it would be good if 
you could drop a comment at the top of the two 2430 I2CHS hwmod 
structures, and simply note that the CM_FCLKEN* registers for those IP 
blocks don't follow the usual pattern.  That way, that knowledge won't be 
lost completely once the IDLEST handling is removed from the clock 
framework, which we'll do as soon as the I2C hwmod code is merged.

Sorry about the confusion,

- Paul

RE: [PATCH v2 1/5] OMAP2xxx: hwmod: add I2C hwmods for OMAP2420, 2430

[Nayak, Rajendra]

> -----Original Message-----
> From: Paul Walmsley [mailto:paul@pwsan.com]
> Sent: Tuesday, September 21, 2010 1:36 PM
> To: Nayak, Rajendra
> Cc: linux-omap@vger.kernel.org; Kevin Hilman
> Subject: RE: [PATCH v2 1/5] OMAP2xxx: hwmod: add I2C hwmods for OMAP2420,
> 2430
> 
> On Tue, 21 Sep 2010, Paul Walmsley wrote:
> 
> > My original comment was somewhat inaccurate.  Looking again at the 2430
> > TRM, it looks like the idlest_reg_id is correct, but that the prcm_reg_id
> > is not quite correct, at least for the FCLKEN register - not currently
> > used by hwmod.  We may have to add a workaround flag for the 2430 I2CHS
> > case.
> >
> > I can see why this didn't cause a problem in your testing.  The clock
> > framework writes to the correct FCLKEN bit, and the hwmod code currently
> > doesn't touch the FCLKEN bit.  And then the hwmod code checks the
> > correct IDLEST bit.
> >
> > It may be that the clock framework is also buggy for the 2430 I2CHS case -
> > that code will probably write to CM_ICLKEN2_CORE for 2430 I2CHS, but it
> > should write to CM_ICLKEN1_CORE.  sigh...
> 
> Just double-checked the clock code and data - it looks like the clock code
> is doing the right thing for 2430 I2CHS: it uses CM_ICLKEN1_CORE,
> CM_FCLKEN2_CORE, and CM_IDLEST1_CORE, despite the commit log comments on
> 3dc2197579089c5b74c7fba666c8ccf1a449afb4, which are wrong.
> 
> So, that issue that I raised was a false alarm.  But it would be good if
> you could drop a comment at the top of the two 2430 I2CHS hwmod
> structures, and simply note that the CM_FCLKEN* registers for those IP
> blocks don't follow the usual pattern.  That way, that knowledge won't be
> lost completely once the IDLEST handling is removed from the clock
> framework, which we'll do as soon as the I2C hwmod code is merged.

Sure, will add a note on this.

> 
> Sorry about the confusion,
> 
> - Paul

Re: [PATCH v2 0/5] Convert I2C driver to use omap_device/runtime PM

[Kevin Hilman]

Rajendra Nayak <rnayak@ti.com> writes:

> This series makes I2C device registration use hwmod
> and omap_device api's and converts the I2C driver to use
> runtime PM api's.
>
> Patches apply on the pm-core branch from Kevin's tree.
>
> v2 has minor review comment fixes over v1 and is additionally
> boot tested on a 2430sdp platform along with being tested on
> 3430sdp and 4430sdp.
>
> 4430sdp tests are done using the below series
> http://www.spinics.net/lists/linux-omap/msg36023.html

Hi Rajendra,

This series looks good to queue for 2.6.37.

Can you re-post one more time with linux-arm-kernel in CC as well as the
I2C list and Ben Dooks (MAINAINERS excerpt below for addresses.)

I will gladly merge patches 1-4, but I'll need an ack/signoff from Ben
to merge patch 5.

Thanks,

Kevin


I2C SUBSYSTEM
M:	"Jean Delvare (PC drivers, core)" <khali@linux-fr.org>
M:	"Ben Dooks (embedded platforms)" <ben-linux@fluff.org>
L:	linux-i2c@vger.kernel.org

RE: [PATCH v2 0/5] Convert I2C driver to use omap_device/runtime PM

[Nayak, Rajendra]

> -----Original Message-----
> From: Kevin Hilman [mailto:khilman@deeprootsystems.com]
> Sent: Monday, September 20, 2010 11:46 PM
> To: Nayak, Rajendra
> Cc: linux-omap@vger.kernel.org
> Subject: Re: [PATCH v2 0/5] Convert I2C driver to use omap_device/runtime PM
> 
> Rajendra Nayak <rnayak@ti.com> writes:
> 
> > This series makes I2C device registration use hwmod
> > and omap_device api's and converts the I2C driver to use
> > runtime PM api's.
> >
> > Patches apply on the pm-core branch from Kevin's tree.
> >
> > v2 has minor review comment fixes over v1 and is additionally
> > boot tested on a 2430sdp platform along with being tested on
> > 3430sdp and 4430sdp.
> >
> > 4430sdp tests are done using the below series
> > http://www.spinics.net/lists/linux-omap/msg36023.html
> 
> Hi Rajendra,
> 
> This series looks good to queue for 2.6.37.
> 
> Can you re-post one more time with linux-arm-kernel in CC as well as the
> I2C list and Ben Dooks (MAINAINERS excerpt below for addresses.)

Ok, thanks. Will do.

> 
> I will gladly merge patches 1-4, but I'll need an ack/signoff from Ben
> to merge patch 5.
> 
> Thanks,
> 
> Kevin
> 
> 
> I2C SUBSYSTEM
> M:	"Jean Delvare (PC drivers, core)" <khali@linux-fr.org>
> M:	"Ben Dooks (embedded platforms)" <ben-linux@fluff.org>
> L:	linux-i2c@vger.kernel.org
>