[PATCHv2 0/11] Misc fixes [for PM branch]

[PATCHv2 0/11] Misc fixes [for PM branch]

[Tero Kristo]

From: Tero Kristo <tero.kristo@nokia.com>

This set is now missing following patches compared to the previous set:

- IVA2 suspend fix
- Dynamic check for core target state
- Block core off when DSS active
- Next state check for IVA2, USB and PER
- USBHOST powerdomain force to sleep after warm reset

Also removed one of the patches Kevin already applied.

I am still trying to figure out what to do with the remaining patches, but
I decided I would send this partial set which I have modified according to
comments already.

-Tero

[PATCH 01/11] OMAP3: PM: Fixed padconf save done check

[Tero Kristo]

From: Carlos Chinea <carlos.chinea@nokia.com>

Previously the operator precedence dictated that the delay loop was exited
immediately, potentially causing off-mode to be entered too soon.

Signed-off-by: Carlos Chinea <carlos.chinea@nokia.com>
Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com>
---
 arch/arm/mach-omap2/pm34xx.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 01260ec..8353764 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -146,8 +146,8 @@ static void omap3_core_save_context(void)
 	control_padconf_off |= START_PADCONF_SAVE;
 	omap_ctrl_writel(control_padconf_off, OMAP343X_CONTROL_PADCONF_OFF);
 	/* wait for the save to complete */
-	while (!omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS)
-			& PADCONF_SAVE_DONE)
+	while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS)
+			& PADCONF_SAVE_DONE))
 		;
 	/* Save the Interrupt controller context */
 	omap3_intc_save_context();
-- 
1.5.4.3

[PATCH 02/11] OMAP3: Disable Smartreflex before pwrdm enters RET

[Tero Kristo]

From: Tero Kristo <tero.kristo@nokia.com>

Smartreflex for the corresponding powerdomain (MPU/CORE) must be disabled
before the domain enters retention, otherwise the device may hang. This is
caused by overlapping smartreflex / auto retention command on the voltage
channel resulting in incorrect voltage.

This fix has been confirmed from TI.

Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
---
 arch/arm/mach-omap2/pm34xx.c |   22 +++++++++++++++++-----
 1 files changed, 17 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 8353764..6782792 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -403,11 +403,17 @@ void omap_sram_idle(void)
 	if (pwrdm_read_pwrst(cam_pwrdm) == PWRDM_POWER_ON)
 		omap2_clkdm_deny_idle(mpu_pwrdm->pwrdm_clkdms[0]);
 
-	/* CORE */
-	if (core_next_state < PWRDM_POWER_ON) {
-		/* Disable smartreflex before entering WFI */
+	/*
+	 * Disable smartreflex before entering WFI.
+	 * Only needed if we are going to enter retention or off.
+	 */
+	if (mpu_next_state <= PWRDM_POWER_RET)
 		disable_smartreflex(SR1);
+	if (core_next_state <= PWRDM_POWER_RET)
 		disable_smartreflex(SR2);
+
+	/* CORE */
+	if (core_next_state < PWRDM_POWER_ON) {
 		omap_uart_prepare_idle(0);
 		omap_uart_prepare_idle(1);
 		if (core_next_state == PWRDM_POWER_OFF) {
@@ -480,10 +486,16 @@ void omap_sram_idle(void)
 			prm_clear_mod_reg_bits(OMAP3430_AUTO_RET,
 						OMAP3430_GR_MOD,
 						OMAP3_PRM_VOLTCTRL_OFFSET);
-		/* Enable smartreflex after WFI */
+	}
+
+	/*
+	 * Enable smartreflex after WFI. Only needed if we entered
+	 * retention or off
+	 */
+	if (mpu_next_state <= PWRDM_POWER_RET)
 		enable_smartreflex(SR1);
+	if (core_next_state <= PWRDM_POWER_RET)
 		enable_smartreflex(SR2);
-	}
 
 	/* PER */
 	if (per_next_state < PWRDM_POWER_ON) {
-- 
1.5.4.3

[PATCH 03/11] OMAP2/3: DMTIMER: Clear pending interrupts when stopping a timer

[Tero Kristo]

From: Tero Kristo <tero.kristo@nokia.com>

OMAP GP timers keep running for a few cycles after they are stopped,
which can cause the timer to expire and generate an interrupt. The pending
interrupt will prevent e.g. OMAP from entering suspend, thus we ack it
manually.

Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
---
 arch/arm/plat-omap/dmtimer.c |   10 ++++++++++
 1 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 830b072..09a623d 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -551,6 +551,16 @@ void omap_dm_timer_stop(struct omap_dm_timer *timer)
 	if (l & OMAP_TIMER_CTRL_ST) {
 		l &= ~0x1;
 		omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
+		/* Readback to make sure write has completed */
+		omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
+		 /*
+		  * Wait for functional clock period x 3.5 to make sure that
+		  * timer is stopped
+		  */
+		udelay(3500000 / clk_get_rate(timer->fclk) + 1);
+		/* Ack possibly pending interrupt */
+		omap_dm_timer_write_reg(timer, OMAP_TIMER_STAT_REG,
+				OMAP_TIMER_INT_OVERFLOW);
 	}
 }
 EXPORT_SYMBOL_GPL(omap_dm_timer_stop);
-- 
1.5.4.3

[PATCH 04/11] OMAP3: PM: Ack pending interrupts before entering suspend

[Tero Kristo]

From: Tero Kristo <tero.kristo@nokia.com>

Suspending drivers may still generate interrupts just before their suspend is
completed. Any pending interrupts here will prevent sleep.

Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
---
 arch/arm/mach-omap2/irq.c              |    6 ++++++
 arch/arm/mach-omap2/pm34xx.c           |    2 +-
 arch/arm/plat-omap/include/mach/irqs.h |    1 +
 3 files changed, 8 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index aceedd8..ee8c68a 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -266,4 +266,10 @@ void omap3_intc_restore_context(void)
 	}
 	/* MIRs are saved and restore with other PRCM registers */
 }
+
+void omap3_intc_suspend(void)
+{
+	/* A pending interrupt would prevent OMAP from entering suspend */
+	omap_ack_irq(0);
+}
 #endif /* CONFIG_ARCH_OMAP3 */
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 6782792..53544d3 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -640,7 +640,7 @@ static int omap3_pm_suspend(void)
 	}
 
 	omap_uart_prepare_suspend();
-
+	omap3_intc_suspend();
 	regset_save_on_suspend = 1;
 	omap_sram_idle();
 	regset_save_on_suspend = 0;
diff --git a/arch/arm/plat-omap/include/mach/irqs.h b/arch/arm/plat-omap/include/mach/irqs.h
index 2473910..ff1faa8 100644
--- a/arch/arm/plat-omap/include/mach/irqs.h
+++ b/arch/arm/plat-omap/include/mach/irqs.h
@@ -485,6 +485,7 @@ extern void omap_init_irq(void);
 extern int omap_irq_pending(void);
 void omap3_intc_save_context(void);
 void omap3_intc_restore_context(void);
+void omap3_intc_suspend(void);
 #endif
 
 #include <mach/hardware.h>
-- 
1.5.4.3

[PATCH 05/11] OMAP3: PM: Enable system control module autoidle

[Tero Kristo]

From: Tero Kristo <tero.kristo@nokia.com>

This saves some power.

Signed-off-by: Mika Westerberg <ext-mika.1.westerberg@nokia.com>
---
 arch/arm/mach-omap2/pm34xx.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 53544d3..492458e 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -900,6 +900,8 @@ static void __init prcm_setup_regs(void)
 			CM_AUTOIDLE);
 	}
 
+	omap_ctrl_writel(OMAP3430_AUTOIDLE, OMAP2_CONTROL_SYSCONFIG);
+
 	/*
 	 * Set all plls to autoidle. This is needed until autoidle is
 	 * enabled by clockfw
-- 
1.5.4.3

[PATCH 06/11] OMAP3: PM: Disable interrupt controller AUTOIDLE before WFI

[Tero Kristo]

From: Tero Kristo <tero.kristo@nokia.com>

OMAP interrupt controller goes to unknown state when there is right
combination of l3,l4 sleep/wake-up transitions, l4 autoidle in
interrupt controller and some interrupt. When this happens, interrupts
are not delivered to ARM anymore and ARM will remain in WFI (wait for
interrupt) until interrupt controller is forced to wake-up
(i.e. lauterbach).

Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
---
 arch/arm/mach-omap2/irq.c              |   12 ++++++++++++
 arch/arm/mach-omap2/pm34xx.c           |    2 ++
 arch/arm/plat-omap/include/mach/irqs.h |    2 ++
 3 files changed, 16 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index ee8c68a..9241b87 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -272,4 +272,16 @@ void omap3_intc_suspend(void)
 	/* A pending interrupt would prevent OMAP from entering suspend */
 	omap_ack_irq(0);
 }
+
+void omap3_intc_prepare_idle(void)
+{
+	/* Disable autoidle as it can stall interrupt controller */
+	intc_bank_write_reg(0, &irq_banks[0], INTC_SYSCONFIG);
+}
+
+void omap3_intc_resume_idle(void)
+{
+	/* Re-enable autoidle */
+	intc_bank_write_reg(1, &irq_banks[0], INTC_SYSCONFIG);
+}
 #endif /* CONFIG_ARCH_OMAP3 */
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 492458e..fec9c38 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -431,6 +431,7 @@ void omap_sram_idle(void)
 		prm_set_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN);
 		omap3_enable_io_chain();
 	}
+	omap3_intc_prepare_idle();
 
 	/*
 	* On EMU/HS devices ROM code restores a SRDC value
@@ -487,6 +488,7 @@ void omap_sram_idle(void)
 						OMAP3430_GR_MOD,
 						OMAP3_PRM_VOLTCTRL_OFFSET);
 	}
+	omap3_intc_resume_idle();
 
 	/*
 	 * Enable smartreflex after WFI. Only needed if we entered
diff --git a/arch/arm/plat-omap/include/mach/irqs.h b/arch/arm/plat-omap/include/mach/irqs.h
index ff1faa8..b736c5d 100644
--- a/arch/arm/plat-omap/include/mach/irqs.h
+++ b/arch/arm/plat-omap/include/mach/irqs.h
@@ -486,6 +486,8 @@ extern int omap_irq_pending(void);
 void omap3_intc_save_context(void);
 void omap3_intc_restore_context(void);
 void omap3_intc_suspend(void);
+void omap3_intc_prepare_idle(void);
+void omap3_intc_resume_idle(void);
 #endif
 
 #include <mach/hardware.h>
-- 
1.5.4.3

[PATCH 07/11] OMAP3: Fixed ARM aux ctrl register save/restore

[Tero Kristo]

From: Tero Kristo <tero.kristo@nokia.com>

Current value is stored on SDRAM and it is written back during wakeup.
Previously a static value of 0x72 was written there.

Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com>
---
 arch/arm/mach-omap2/control.c   |    1 +
 arch/arm/mach-omap2/sleep34xx.S |   23 ++++++++++++++++++++---
 2 files changed, 21 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index 296f2c2..730fc53 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -94,6 +94,7 @@ void *omap3_secure_ram_storage;
  * during the restore path.
  */
 u32 omap3_arm_context[128];
+u32 omap3_aux_ctrl[2] = { 0x1, 0x0 };
 
 struct omap3_control_regs {
 	u32 sysconfig;
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index f4f5ebe..0b03bf9 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -26,6 +26,7 @@
  */
 #include <linux/linkage.h>
 #include <asm/assembler.h>
+#include <asm/memory.h>
 #include <mach/io.h>
 #include <mach/control.h>
 
@@ -278,7 +279,11 @@ restore:
 	mov	r1, #0		@ set task id for ROM code in r1
 	mov	r2, #4		@ set some flags in r2, r6
 	mov	r6, #0xff
-	adr	r3, write_aux_control_params	@ r3 points to parameters
+	ldr	r3, write_aux_control_params	@ r3 points to parameters
+	ldr	r4, phys_offset
+	adds	r3, r3, r4
+	ldr	r4, page_offset
+	subs	r3, r3, r4
 	mcr	p15, 0, r0, c7, c10, 4	@ data write barrier
 	mcr	p15, 0, r0, c7, c10, 5	@ data memory barrier
 	.word	0xE1600071		@ call SMI monitor (smi #1)
@@ -287,13 +292,18 @@ restore:
 l2_inv_api_params:
 	.word   0x1, 0x00
 write_aux_control_params:
-	.word   0x1, 0x72
+	.word	omap3_aux_ctrl
 l2_inv_gp:
 	/* Execute smi to invalidate L2 cache */
 	mov r12, #0x1                         @ set up to invalide L2
 smi:    .word 0xE1600070		@ Call SMI monitor (smieq)
 	/* Write to Aux control register to set some bits */
-	mov	r0, #0x72
+	ldr	r1, write_aux_control_params
+	ldr	r0, phys_offset
+	adds	r1, r1, r0
+	ldr	r0, page_offset
+	subs	r1, r1, r0
+	ldr	r0, [r1, #4]
 	mov	r12, #0x3
 	.word 0xE1600070	@ Call SMI monitor (smieq)
 logic_l1_restore:
@@ -420,6 +430,9 @@ usettbr0:
 save_context_wfi:
 	/*b	save_context_wfi*/	@ enable to debug save code
 	mov	r8, r0 /* Store SDRAM address in r8 */
+	mrc	p15, 0, r4, c1, c0, 1	@ Read Auxiliary Control Register
+	ldr	r5, write_aux_control_params
+	str	r4, [r5, #4]
         /* Check what that target sleep state is:stored in r1*/
         /* 1 - Only L1 and logic lost */
         /* 2 - Only L2 lost */
@@ -605,6 +618,10 @@ wait_dll_lock:
         bne     wait_dll_lock
         bx      lr
 
+phys_offset:
+	.word	PHYS_OFFSET
+page_offset:
+	.word	PAGE_OFFSET
 cm_idlest1_core:
 	.word	CM_IDLEST1_CORE_V
 sdrc_dlla_status:
-- 
1.5.4.3

[PATCH 08/11] OMAP3: PM: Disabled I2C4 repeated start operation mode

[Tero Kristo]

From: Tero Kristo <tero.kristo@nokia.com>

Repeated start forces I2C4 pads low during idle, which increases power
consumption through external pull-ups. On the other hand, this change
increases I2C4 command latencies a bit.

Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
---
 arch/arm/mach-omap2/pm34xx.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index fec9c38..154cd31 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -1219,7 +1219,7 @@ static void __init configure_vc(void)
 	prm_write_mod_reg(OMAP3430_CMD1 | OMAP3430_RAV1, OMAP3430_GR_MOD,
 			  OMAP3_PRM_VC_CH_CONF_OFFSET);
 
-	prm_write_mod_reg(OMAP3430_MCODE_SHIFT | OMAP3430_HSEN | OMAP3430_SREN,
+	prm_write_mod_reg(OMAP3430_MCODE_SHIFT | OMAP3430_HSEN,
 			  OMAP3430_GR_MOD,
 			  OMAP3_PRM_VC_I2C_CFG_OFFSET);
 
-- 
1.5.4.3

[PATCH 09/11] OMAP3: PM: Added support for L2 aux ctrl register save and restore

[Tero Kristo]

From: Tero Kristo <tero.kristo@nokia.com>

This patch adds a save and restore mechanism for ARM L2 auxiliary control
register. This feature is enabled via Kconfig option
OMAP3_L2_AUX_SECURE_SAVE_RESTORE and the service ID for PPA can be provided
via option OMAP3_L2_AUX_SECURE_SERVICE_SET_ID. If bootloader does not modify
L2 aux register, using this save and restore logic for it is not needed.

Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
---
 arch/arm/mach-omap2/control.c   |    1 +
 arch/arm/mach-omap2/sleep34xx.S |   31 +++++++++++++++++++++++++++++++
 arch/arm/plat-omap/Kconfig      |   17 +++++++++++++++++
 3 files changed, 49 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index 730fc53..82d8f1a 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -95,6 +95,7 @@ void *omap3_secure_ram_storage;
  */
 u32 omap3_arm_context[128];
 u32 omap3_aux_ctrl[2] = { 0x1, 0x0 };
+u32 omap3_l2_aux_ctrl[2] = { 0x1, 0x0 };
 
 struct omap3_control_regs {
 	u32 sysconfig;
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index 0b03bf9..e291d6d 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -288,11 +288,30 @@ restore:
 	mcr	p15, 0, r0, c7, c10, 5	@ data memory barrier
 	.word	0xE1600071		@ call SMI monitor (smi #1)
 
+#ifdef CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE
+	/* Restore L2 aux control register */
+	@ set service ID for PPA
+	mov	r0, #CONFIG_OMAP3_L2_AUX_SECURE_SERVICE_SET_ID
+	mov	r12, r0		@ copy service ID in r12
+	mov	r1, #0		@ set task ID for ROM code in r1
+	mov	r2, #4		@ set some flags in r2, r6
+	mov	r6, #0xff
+	ldr	r3, write_l2_aux_control_params	@ r3 points to parameters
+	ldr	r4, phys_offset
+	adds	r3, r3, r4
+	ldr	r4, page_offset
+	subs	r3, r3, r4
+	mcr	p15, 0, r0, c7, c10, 4	@ data write barrier
+	mcr	p15, 0, r0, c7, c10, 5	@ data memory barrier
+	.word	0xE1600071		@ call SMI monitor (smi #1)
+#endif
 	b	logic_l1_restore
 l2_inv_api_params:
 	.word   0x1, 0x00
 write_aux_control_params:
 	.word	omap3_aux_ctrl
+write_l2_aux_control_params:
+	.word	omap3_l2_aux_ctrl
 l2_inv_gp:
 	/* Execute smi to invalidate L2 cache */
 	mov r12, #0x1                         @ set up to invalide L2
@@ -306,6 +325,15 @@ smi:    .word 0xE1600070		@ Call SMI monitor (smieq)
 	ldr	r0, [r1, #4]
 	mov	r12, #0x3
 	.word 0xE1600070	@ Call SMI monitor (smieq)
+	/* Restore L2 AUX control register */
+	ldr	r1, write_l2_aux_control_params
+	ldr	r0, phys_offset
+	adds	r1, r1, r0
+	ldr	r0, page_offset
+	subs	r1, r1, r0
+	ldr	r0, [r1, #4]
+	mov	r12, #0x2
+	.word 0xE1600070	@ Call SMI monitor (smieq)
 logic_l1_restore:
 	mov	r1, #0
 	/* Invalidate all instruction caches to PoU
@@ -433,6 +461,9 @@ save_context_wfi:
 	mrc	p15, 0, r4, c1, c0, 1	@ Read Auxiliary Control Register
 	ldr	r5, write_aux_control_params
 	str	r4, [r5, #4]
+	mrc	p15, 1, r4, c9, c0, 2	@ Read L2 AUX ctrl register
+	ldr	r5, write_l2_aux_control_params
+	str	r4, [r5, #4]
         /* Check what that target sleep state is:stored in r1*/
         /* 1 - Only L1 and logic lost */
         /* 2 - Only L2 lost */
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index 2143db5..3ff1a5f 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -185,6 +185,23 @@ config OMAP3_DEBOBS
 	help
 	  Use ETK pads for debug observability
 
+config OMAP3_L2_AUX_SECURE_SAVE_RESTORE
+	bool "OMAP3 HS/EMU save and restore for L2 AUX control register"
+	depends on ARCH_OMAP3 && PM
+	default n
+	help
+	  Without this option, L2 Auxiliary control register contents are
+	  lost during off-mode entry on HS/EMU devices. This feature
+	  requires support from PPA / boot-loader in HS/EMU devices, which
+	  currently does not exist by default.
+
+config OMAP3_L2_AUX_SECURE_SERVICE_SET_ID
+	int "Service ID for the support routine to set L2 AUX control"
+	depends on OMAP3_L2_AUX_SECURE_SAVE_RESTORE
+	default 43
+	help
+	  PPA routine service ID for setting L2 auxiliary control register.
+
 config OMAP_32K_TIMER_HZ
        int "Kernel internal timer frequency for 32KHz timer"
        range 32 1024
-- 
1.5.4.3

[PATCH 10/11] OMAP3: PM: Write voltage and clock setup times dynamically in idle loop

[Tero Kristo]

From: Tero Kristo <tero.kristo@nokia.com>

It is suggested by TI (SWPA152 February 2009) to write clksetup,
voltsetup_time1, voltsetup_time2, voltsetup2 dynamically in idle loop.

This allows us to optimize the voltage + clock setup times according to the
used power save mode.

Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
---
 arch/arm/mach-omap2/pm.h     |   10 ++++-
 arch/arm/mach-omap2/pm34xx.c |   86 ++++++++++++++++++++++++------------------
 2 files changed, 57 insertions(+), 39 deletions(-)

diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index f8d11a2..b384eb1 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -24,12 +24,18 @@ extern int omap3_can_sleep(void);
 extern int set_pwrdm_state(struct powerdomain *pwrdm, u32 state);
 extern int omap3_idle_init(void);
 
-struct prm_setup_vc {
+struct prm_setup_times_vc {
 	u16 clksetup;
 	u16 voltsetup_time1;
 	u16 voltsetup_time2;
-	u16 voltoffset;
 	u16 voltsetup2;
+	u16 voltsetup1;
+};
+
+struct prm_setup_vc {
+	struct prm_setup_times_vc *setup_times;
+	struct prm_setup_times_vc *setup_times_off;
+	u16 voltoffset;
 /* PRM_VC_CMD_VAL_0 specific bits */
 	u16 vdd0_on;
 	u16 vdd0_onlp;
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 154cd31..5eb7321 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -82,12 +82,17 @@ static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
 static struct powerdomain *core_pwrdm, *per_pwrdm;
 static struct powerdomain *cam_pwrdm;
 
-static struct prm_setup_vc prm_setup = {
+static struct prm_setup_times_vc prm_setup_times_default = {
 	.clksetup = 0xff,
 	.voltsetup_time1 = 0xfff,
 	.voltsetup_time2 = 0xfff,
-	.voltoffset = 0xff,
 	.voltsetup2 = 0xff,
+};
+
+static struct prm_setup_vc prm_setup_default = {
+	.setup_times = &prm_setup_times_default,
+	.setup_times_off = NULL,
+	.voltoffset = 0xff,
 	.vdd0_on = 0x30,	/* 1.2v */
 	.vdd0_onlp = 0x20,	/* 1.0v */
 	.vdd0_ret = 0x1e,	/* 0.975v */
@@ -98,6 +103,8 @@ static struct prm_setup_vc prm_setup = {
 	.vdd1_off = 0x00,	/* 0.6v */
 };
 
+static struct prm_setup_vc *prm_setup = &prm_setup_default;
+
 static inline void omap3_per_save_context(void)
 {
 	omap3_gpio_save_context();
@@ -338,6 +345,16 @@ static void restore_table_entry(void)
 	restore_control_register(control_reg_value);
 }
 
+static void prm_program_setup_times(struct prm_setup_times_vc *times)
+{
+	prm_write_mod_reg(times->voltsetup1, OMAP3430_GR_MOD,
+			OMAP3_PRM_VOLTSETUP1_OFFSET);
+	prm_write_mod_reg(times->voltsetup2, OMAP3430_GR_MOD,
+			OMAP3_PRM_VOLTSETUP2_OFFSET);
+	prm_write_mod_reg(times->clksetup, OMAP3430_GR_MOD,
+			OMAP3_PRM_CLKSETUP_OFFSET);
+}
+
 void omap_sram_idle(void)
 {
 	/* Variable to tell what needs to be saved and restored
@@ -422,6 +439,9 @@ void omap_sram_idle(void)
 					     OMAP3_PRM_VOLTCTRL_OFFSET);
 			omap3_core_save_context();
 			omap3_prcm_save_context();
+			if (prm_setup->setup_times_off != NULL)
+				prm_program_setup_times(prm_setup->
+					setup_times_off);
 		} else if (core_next_state == PWRDM_POWER_RET) {
 			prm_set_mod_reg_bits(OMAP3430_AUTO_RET,
 						OMAP3430_GR_MOD,
@@ -479,11 +499,13 @@ void omap_sram_idle(void)
 		}
 		omap_uart_resume_idle(0);
 		omap_uart_resume_idle(1);
-		if (core_next_state == PWRDM_POWER_OFF)
+		if (core_next_state == PWRDM_POWER_OFF) {
 			prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF,
 					       OMAP3430_GR_MOD,
 					       OMAP3_PRM_VOLTCTRL_OFFSET);
-		else if (core_next_state == PWRDM_POWER_RET)
+			if (prm_setup->setup_times_off != NULL)
+				prm_program_setup_times(prm_setup->setup_times);
+		} else if (core_next_state == PWRDM_POWER_RET)
 			prm_clear_mod_reg_bits(OMAP3430_AUTO_RET,
 						OMAP3430_GR_MOD,
 						OMAP3_PRM_VOLTCTRL_OFFSET);
@@ -1043,21 +1065,19 @@ int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
 	return -EINVAL;
 }
 
+static void omap3_init_prm_setup_times(struct prm_setup_times_vc *conf)
+{
+	if (conf == NULL)
+		return;
+
+	conf->voltsetup1 =
+		(conf->voltsetup_time2 << OMAP3430_SETUP_TIME2_SHIFT) |
+		(conf->voltsetup_time1 << OMAP3430_SETUP_TIME1_SHIFT);
+}
+
 void omap3_set_prm_setup_vc(struct prm_setup_vc *setup_vc)
 {
-	prm_setup.clksetup = setup_vc->clksetup;
-	prm_setup.voltsetup_time1 = setup_vc->voltsetup_time1;
-	prm_setup.voltsetup_time2 = setup_vc->voltsetup_time2;
-	prm_setup.voltoffset = setup_vc->voltoffset;
-	prm_setup.voltsetup2 = setup_vc->voltsetup2;
-	prm_setup.vdd0_on = setup_vc->vdd0_on;
-	prm_setup.vdd0_onlp = setup_vc->vdd0_onlp;
-	prm_setup.vdd0_ret = setup_vc->vdd0_ret;
-	prm_setup.vdd0_off = setup_vc->vdd0_off;
-	prm_setup.vdd1_on = setup_vc->vdd1_on;
-	prm_setup.vdd1_onlp = setup_vc->vdd1_onlp;
-	prm_setup.vdd1_ret = setup_vc->vdd1_ret;
-	prm_setup.vdd1_off = setup_vc->vdd1_off;
+	prm_setup = setup_vc;
 }
 
 static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
@@ -1204,16 +1224,16 @@ static void __init configure_vc(void)
 			  (R_VDD1_SR_CONTROL << OMAP3430_VOLRA0_SHIFT),
 			  OMAP3430_GR_MOD, OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET);
 
-	prm_write_mod_reg((prm_setup.vdd0_on << OMAP3430_VC_CMD_ON_SHIFT) |
-		(prm_setup.vdd0_onlp << OMAP3430_VC_CMD_ONLP_SHIFT) |
-		(prm_setup.vdd0_ret << OMAP3430_VC_CMD_RET_SHIFT) |
-		(prm_setup.vdd0_off << OMAP3430_VC_CMD_OFF_SHIFT),
+	prm_write_mod_reg((prm_setup->vdd0_on << OMAP3430_VC_CMD_ON_SHIFT) |
+		(prm_setup->vdd0_onlp << OMAP3430_VC_CMD_ONLP_SHIFT) |
+		(prm_setup->vdd0_ret << OMAP3430_VC_CMD_RET_SHIFT) |
+		(prm_setup->vdd0_off << OMAP3430_VC_CMD_OFF_SHIFT),
 		OMAP3430_GR_MOD, OMAP3_PRM_VC_CMD_VAL_0_OFFSET);
 
-	prm_write_mod_reg((prm_setup.vdd1_on << OMAP3430_VC_CMD_ON_SHIFT) |
-		(prm_setup.vdd1_onlp << OMAP3430_VC_CMD_ONLP_SHIFT) |
-		(prm_setup.vdd1_ret << OMAP3430_VC_CMD_RET_SHIFT) |
-		(prm_setup.vdd1_off << OMAP3430_VC_CMD_OFF_SHIFT),
+	prm_write_mod_reg((prm_setup->vdd1_on << OMAP3430_VC_CMD_ON_SHIFT) |
+		(prm_setup->vdd1_onlp << OMAP3430_VC_CMD_ONLP_SHIFT) |
+		(prm_setup->vdd1_ret << OMAP3430_VC_CMD_RET_SHIFT) |
+		(prm_setup->vdd1_off << OMAP3430_VC_CMD_OFF_SHIFT),
 		OMAP3430_GR_MOD, OMAP3_PRM_VC_CMD_VAL_1_OFFSET);
 
 	prm_write_mod_reg(OMAP3430_CMD1 | OMAP3430_RAV1, OMAP3430_GR_MOD,
@@ -1224,19 +1244,11 @@ static void __init configure_vc(void)
 			  OMAP3_PRM_VC_I2C_CFG_OFFSET);
 
 	/* Write setup times */
-	prm_write_mod_reg(prm_setup.clksetup, OMAP3430_GR_MOD,
-			OMAP3_PRM_CLKSETUP_OFFSET);
-	prm_write_mod_reg((prm_setup.voltsetup_time2 <<
-			OMAP3430_SETUP_TIME2_SHIFT) |
-			(prm_setup.voltsetup_time1 <<
-			OMAP3430_SETUP_TIME1_SHIFT),
-			OMAP3430_GR_MOD, OMAP3_PRM_VOLTSETUP1_OFFSET);
-
-	prm_write_mod_reg(prm_setup.voltoffset, OMAP3430_GR_MOD,
+	omap3_init_prm_setup_times(prm_setup->setup_times);
+	omap3_init_prm_setup_times(prm_setup->setup_times_off);
+	prm_program_setup_times(prm_setup->setup_times);
+	prm_write_mod_reg(prm_setup->voltoffset, OMAP3430_GR_MOD,
 			OMAP3_PRM_VOLTOFFSET_OFFSET);
-	prm_write_mod_reg(prm_setup.voltsetup2, OMAP3430_GR_MOD,
-			OMAP3_PRM_VOLTSETUP2_OFFSET);
-
 	pm_dbg_regset_init(1);
 	pm_dbg_regset_init(2);
 }
-- 
1.5.4.3

[PATCH 11/11] OMAP3: PM: Disable OTG autoidle when waking up from off-mode

[Tero Kristo]

From: Tero Kristo <tero.kristo@nokia.com>

OMAP3 sleep can be prevented in some cases where OTG autoidle is enabled.
This patch force disables autoidle during wakeup from off-mode. See omap
errata 1.164.

Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
---
 arch/arm/mach-omap2/pm34xx.c          |    6 ++++++
 arch/arm/mach-omap2/usb-musb.c        |   14 ++++++++------
 arch/arm/plat-omap/include/mach/usb.h |    3 +++
 3 files changed, 17 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 5eb7321..070a0a2 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -39,6 +39,7 @@
 #include <mach/gpmc.h>
 #include <mach/dma.h>
 #include <mach/dmtimer.h>
+#include <mach/usb.h>
 
 #include <asm/tlbflush.h>
 
@@ -496,6 +497,11 @@ void omap_sram_idle(void)
 			omap3_prcm_restore_context();
 			omap3_sram_restore_context();
 			omap2_sms_restore_context();
+			/*
+			 * Errata 1.164 fix : OTG autoidle can prevent
+			 * sleep
+			 */
+			usb_musb_disable_autoidle();
 		}
 		omap_uart_resume_idle(0);
 		omap_uart_resume_idle(1);
diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c
index 8dde0b7..f4b86c0 100644
--- a/arch/arm/mach-omap2/usb-musb.c
+++ b/arch/arm/mach-omap2/usb-musb.c
@@ -44,10 +44,11 @@ static struct platform_device dummy_pdev = {
 	},
 };
 
+static void __iomem *otg_base;
+static struct clk *otg_clk;
+
 static void __init usb_musb_pm_init(void)
 {
-	void __iomem *otg_base;
-	struct clk *otg_clk;
 	struct device *dev = &dummy_pdev.dev;
 
 	if (!cpu_is_omap34xx())
@@ -74,12 +75,13 @@ static void __init usb_musb_pm_init(void)
 			cpu_relax();
 	}
 
-	if (otg_clk) {
+	if (otg_clk)
 		clk_disable(otg_clk);
-		clk_put(otg_clk);
-	}
+}
 
-	iounmap(otg_base);
+void usb_musb_disable_autoidle(void)
+{
+	__raw_writel(0, otg_base + OTG_SYSCONFIG);
 }
 
 #ifdef CONFIG_USB_MUSB_SOC
diff --git a/arch/arm/plat-omap/include/mach/usb.h b/arch/arm/plat-omap/include/mach/usb.h
index a4068a4..310ee17 100644
--- a/arch/arm/plat-omap/include/mach/usb.h
+++ b/arch/arm/plat-omap/include/mach/usb.h
@@ -46,6 +46,9 @@ extern void usb_musb_init(void);
 
 extern void usb_ehci_init(struct ehci_hcd_omap_platform_data *pdata);
 
+/* This is needed for OMAP3 errata 1.164: enabled autoidle can prevent sleep */
+extern void usb_musb_disable_autoidle(void);
+
 #endif
 
 void omap_usb_init(struct omap_usb_config *pdata);
-- 
1.5.4.3

Re: [PATCH 11/11] OMAP3: PM: Disable OTG autoidle when waking up from off-mode

[Kevin Hilman]

Tero Kristo <tero.kristo@nokia.com> writes:

> From: Tero Kristo <tero.kristo@nokia.com>
>
> OMAP3 sleep can be prevented in some cases where OTG autoidle is enabled.
> This patch force disables autoidle during wakeup from off-mode. See omap
> errata 1.164.
>
> Signed-off-by: Tero Kristo <tero.kristo@nokia.com>

This one needs a refresh against current PM branch.

> ---
>  arch/arm/mach-omap2/pm34xx.c          |    6 ++++++
>  arch/arm/mach-omap2/usb-musb.c        |   14 ++++++++------
>  arch/arm/plat-omap/include/mach/usb.h |    3 +++

mach/usb.h moved to plat/usb.h

>  3 files changed, 17 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
> index 5eb7321..070a0a2 100644
> --- a/arch/arm/mach-omap2/pm34xx.c
> +++ b/arch/arm/mach-omap2/pm34xx.c
> @@ -39,6 +39,7 @@
>  #include <mach/gpmc.h>
>  #include <mach/dma.h>
>  #include <mach/dmtimer.h>
> +#include <mach/usb.h>
>  
>  #include <asm/tlbflush.h>
>  
> @@ -496,6 +497,11 @@ void omap_sram_idle(void)
>  			omap3_prcm_restore_context();
>  			omap3_sram_restore_context();
>  			omap2_sms_restore_context();
> +			/*
> +			 * Errata 1.164 fix : OTG autoidle can prevent
> +			 * sleep
> +			 */
> +			usb_musb_disable_autoidle();

NAK.  This belongs in the MUSB driver, not in the idle path.

Kevin

>  		}
>  		omap_uart_resume_idle(0);
>  		omap_uart_resume_idle(1);
> diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c
> index 8dde0b7..f4b86c0 100644
> --- a/arch/arm/mach-omap2/usb-musb.c
> +++ b/arch/arm/mach-omap2/usb-musb.c
> @@ -44,10 +44,11 @@ static struct platform_device dummy_pdev = {
>  	},
>  };
>  
> +static void __iomem *otg_base;
> +static struct clk *otg_clk;
> +
>  static void __init usb_musb_pm_init(void)
>  {
> -	void __iomem *otg_base;
> -	struct clk *otg_clk;
>  	struct device *dev = &dummy_pdev.dev;
>  
>  	if (!cpu_is_omap34xx())
> @@ -74,12 +75,13 @@ static void __init usb_musb_pm_init(void)
>  			cpu_relax();
>  	}
>  
> -	if (otg_clk) {
> +	if (otg_clk)
>  		clk_disable(otg_clk);
> -		clk_put(otg_clk);
> -	}
> +}
>
>  
> -	iounmap(otg_base);
> +void usb_musb_disable_autoidle(void)
> +{
> +	__raw_writel(0, otg_base + OTG_SYSCONFIG);
>  }
>  
>  #ifdef CONFIG_USB_MUSB_SOC
> diff --git a/arch/arm/plat-omap/include/mach/usb.h b/arch/arm/plat-omap/include/mach/usb.h
> index a4068a4..310ee17 100644
> --- a/arch/arm/plat-omap/include/mach/usb.h
> +++ b/arch/arm/plat-omap/include/mach/usb.h
> @@ -46,6 +46,9 @@ extern void usb_musb_init(void);
>  
>  extern void usb_ehci_init(struct ehci_hcd_omap_platform_data *pdata);
>  
> +/* This is needed for OMAP3 errata 1.164: enabled autoidle can prevent sleep */
> +extern void usb_musb_disable_autoidle(void);
> +
>  #endif
>  
>  void omap_usb_init(struct omap_usb_config *pdata);
> -- 
> 1.5.4.3
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

RE: [PATCH 11/11] OMAP3: PM: Disable OTG autoidle when waking up from off-mode

[Gadiyar, Anand]

Kevin Hilman wrote:
> Tero Kristo <tero.kristo@nokia.com> writes:
> 
> > From: Tero Kristo <tero.kristo@nokia.com>
> >
> > OMAP3 sleep can be prevented in some cases where OTG autoidle is enabled.
> > This patch force disables autoidle during wakeup from off-mode. See omap
> > errata 1.164.
> >
> > Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
> 
> This one needs a refresh against current PM branch.
> 
> > ---
> >  arch/arm/mach-omap2/pm34xx.c          |    6 ++++++
> >  arch/arm/mach-omap2/usb-musb.c        |   14 ++++++++------
> >  arch/arm/plat-omap/include/mach/usb.h |    3 +++
> 
> mach/usb.h moved to plat/usb.h
> 
> >  3 files changed, 17 insertions(+), 6 deletions(-)
> >
> > diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
> > index 5eb7321..070a0a2 100644
> > --- a/arch/arm/mach-omap2/pm34xx.c
> > +++ b/arch/arm/mach-omap2/pm34xx.c
> > @@ -39,6 +39,7 @@
> >  #include <mach/gpmc.h>
> >  #include <mach/dma.h>
> >  #include <mach/dmtimer.h>
> > +#include <mach/usb.h>
> >  
> >  #include <asm/tlbflush.h>
> >  
> > @@ -496,6 +497,11 @@ void omap_sram_idle(void)
> >  			omap3_prcm_restore_context();
> >  			omap3_sram_restore_context();
> >  			omap2_sms_restore_context();
> > +			/*
> > +			 * Errata 1.164 fix : OTG autoidle can prevent
> > +			 * sleep
> > +			 */
> > +			usb_musb_disable_autoidle();
> 
> NAK.  This belongs in the MUSB driver, not in the idle path.
> 

Kevin,

When we exit off-mode, the autoidle will get enabled, and needs
an explicit disable. If the MUSB driver is not loaded, there will
be no one to do this.

- Anand

> Kevin
> 
> >  		}
> >  		omap_uart_resume_idle(0);
> >  		omap_uart_resume_idle(1);
> > diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c
> > index 8dde0b7..f4b86c0 100644
> > --- a/arch/arm/mach-omap2/usb-musb.c
> > +++ b/arch/arm/mach-omap2/usb-musb.c
> > @@ -44,10 +44,11 @@ static struct platform_device dummy_pdev = {
> >  	},
> >  };
> >  
> > +static void __iomem *otg_base;
> > +static struct clk *otg_clk;
> > +
> >  static void __init usb_musb_pm_init(void)
> >  {
> > -	void __iomem *otg_base;
> > -	struct clk *otg_clk;
> >  	struct device *dev = &dummy_pdev.dev;
> >  
> >  	if (!cpu_is_omap34xx())
> > @@ -74,12 +75,13 @@ static void __init usb_musb_pm_init(void)
> >  			cpu_relax();
> >  	}
> >  
> > -	if (otg_clk) {
> > +	if (otg_clk)
> >  		clk_disable(otg_clk);
> > -		clk_put(otg_clk);
> > -	}
> > +}
> >
> >  
> > -	iounmap(otg_base);
> > +void usb_musb_disable_autoidle(void)
> > +{
> > +	__raw_writel(0, otg_base + OTG_SYSCONFIG);
> >  }
> >  
> >  #ifdef CONFIG_USB_MUSB_SOC
> > diff --git a/arch/arm/plat-omap/include/mach/usb.h b/arch/arm/plat-omap/include/mach/usb.h
> > index a4068a4..310ee17 100644
> > --- a/arch/arm/plat-omap/include/mach/usb.h
> > +++ b/arch/arm/plat-omap/include/mach/usb.h
> > @@ -46,6 +46,9 @@ extern void usb_musb_init(void);
> >  
> >  extern void usb_ehci_init(struct ehci_hcd_omap_platform_data *pdata);
> >  
> > +/* This is needed for OMAP3 errata 1.164: enabled autoidle can prevent sleep */
> > +extern void usb_musb_disable_autoidle(void);
> > +
> >  #endif
> >  
> >  void omap_usb_init(struct omap_usb_config *pdata);

RE: [PATCH 11/11] OMAP3: PM: Disable OTG autoidle when waking up from off-mode

[Gadiyar, Anand]

<snip>

> > > @@ -496,6 +497,11 @@ void omap_sram_idle(void)
> > >  			omap3_prcm_restore_context();
> > >  			omap3_sram_restore_context();
> > >  			omap2_sms_restore_context();
> > > +			/*
> > > +			 * Errata 1.164 fix : OTG autoidle can prevent
> > > +			 * sleep
> > > +			 */
> > > +			usb_musb_disable_autoidle();
> > 
> > NAK.  This belongs in the MUSB driver, not in the idle path.
> > 
> 
> Kevin,
> 
> When we exit off-mode, the autoidle will get enabled, and needs
> an explicit disable. If the MUSB driver is not loaded, there will
> be no one to do this.
> 
> - Anand
> 
> > Kevin
> > 
> > >  		}
> > >  		omap_uart_resume_idle(0);
> > >  		omap_uart_resume_idle(1);
> > > diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c
> > > index 8dde0b7..f4b86c0 100644
> > > --- a/arch/arm/mach-omap2/usb-musb.c
> > > +++ b/arch/arm/mach-omap2/usb-musb.c
> > > @@ -44,10 +44,11 @@ static struct platform_device dummy_pdev = {
> > >  	},
> > >  };
> > >  
> > > +static void __iomem *otg_base;
> > > +static struct clk *otg_clk;
> > > +
> > >  static void __init usb_musb_pm_init(void)
> > >  {
> > > -	void __iomem *otg_base;
> > > -	struct clk *otg_clk;
> > >  	struct device *dev = &dummy_pdev.dev;
> > >  
> > >  	if (!cpu_is_omap34xx())

Just realized, this probably should read cpu_is_omap3430().

cpu_is_omap34xx is true for 3630 as well, and this chip doesn't need
this workaround.

(Won't hurt much to have this like this for now - until we switch to
the CHIP_HAS_ERRATA way)

- Anand

RE: [PATCH 11/11] OMAP3: PM: Disable OTG autoidle when waking up from off-mode

[Tero.Kristo]

 

>-----Original Message-----
>From: ext Gadiyar, Anand [mailto:gadiyar@ti.com] 
>Sent: 12 November, 2009 08:25
>To: Kevin Hilman; Kristo Tero (Nokia-D/Tampere)
>Cc: linux-omap@vger.kernel.org
>Subject: RE: [PATCH 11/11] OMAP3: PM: Disable OTG autoidle 
>when waking up from off-mode
>
>Kevin Hilman wrote:
>> Tero Kristo <tero.kristo@nokia.com> writes:
>> 
>> > From: Tero Kristo <tero.kristo@nokia.com>
>> >
>> > OMAP3 sleep can be prevented in some cases where OTG 
>autoidle is enabled.
>> > This patch force disables autoidle during wakeup from 
>off-mode. See omap
>> > errata 1.164.
>> >
>> > Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
>> 
>> This one needs a refresh against current PM branch.
>> 
>> > ---
>> >  arch/arm/mach-omap2/pm34xx.c          |    6 ++++++
>> >  arch/arm/mach-omap2/usb-musb.c        |   14 ++++++++------
>> >  arch/arm/plat-omap/include/mach/usb.h |    3 +++
>> 
>> mach/usb.h moved to plat/usb.h
>> 
>> >  3 files changed, 17 insertions(+), 6 deletions(-)
>> >
>> > diff --git a/arch/arm/mach-omap2/pm34xx.c 
>b/arch/arm/mach-omap2/pm34xx.c
>> > index 5eb7321..070a0a2 100644
>> > --- a/arch/arm/mach-omap2/pm34xx.c
>> > +++ b/arch/arm/mach-omap2/pm34xx.c
>> > @@ -39,6 +39,7 @@
>> >  #include <mach/gpmc.h>
>> >  #include <mach/dma.h>
>> >  #include <mach/dmtimer.h>
>> > +#include <mach/usb.h>
>> >  
>> >  #include <asm/tlbflush.h>
>> >  
>> > @@ -496,6 +497,11 @@ void omap_sram_idle(void)
>> >  			omap3_prcm_restore_context();
>> >  			omap3_sram_restore_context();
>> >  			omap2_sms_restore_context();
>> > +			/*
>> > +			 * Errata 1.164 fix : OTG autoidle can prevent
>> > +			 * sleep
>> > +			 */
>> > +			usb_musb_disable_autoidle();
>> 
>> NAK.  This belongs in the MUSB driver, not in the idle path.
>> 
>
>Kevin,
>
>When we exit off-mode, the autoidle will get enabled, and needs
>an explicit disable. If the MUSB driver is not loaded, there will
>be no one to do this.

Also, even if the driver is loaded, it doesn't disable this bit each sleep cycle.

>
>- Anand
>
>> Kevin
>> 
>> >  		}
>> >  		omap_uart_resume_idle(0);
>> >  		omap_uart_resume_idle(1);
>> > diff --git a/arch/arm/mach-omap2/usb-musb.c 
>b/arch/arm/mach-omap2/usb-musb.c
>> > index 8dde0b7..f4b86c0 100644
>> > --- a/arch/arm/mach-omap2/usb-musb.c
>> > +++ b/arch/arm/mach-omap2/usb-musb.c
>> > @@ -44,10 +44,11 @@ static struct platform_device dummy_pdev = {
>> >  	},
>> >  };
>> >  
>> > +static void __iomem *otg_base;
>> > +static struct clk *otg_clk;
>> > +
>> >  static void __init usb_musb_pm_init(void)
>> >  {
>> > -	void __iomem *otg_base;
>> > -	struct clk *otg_clk;
>> >  	struct device *dev = &dummy_pdev.dev;
>> >  
>> >  	if (!cpu_is_omap34xx())
>> > @@ -74,12 +75,13 @@ static void __init usb_musb_pm_init(void)
>> >  			cpu_relax();
>> >  	}
>> >  
>> > -	if (otg_clk) {
>> > +	if (otg_clk)
>> >  		clk_disable(otg_clk);
>> > -		clk_put(otg_clk);
>> > -	}
>> > +}
>> >
>> >  
>> > -	iounmap(otg_base);
>> > +void usb_musb_disable_autoidle(void)
>> > +{
>> > +	__raw_writel(0, otg_base + OTG_SYSCONFIG);
>> >  }
>> >  
>> >  #ifdef CONFIG_USB_MUSB_SOC
>> > diff --git a/arch/arm/plat-omap/include/mach/usb.h 
>b/arch/arm/plat-omap/include/mach/usb.h
>> > index a4068a4..310ee17 100644
>> > --- a/arch/arm/plat-omap/include/mach/usb.h
>> > +++ b/arch/arm/plat-omap/include/mach/usb.h
>> > @@ -46,6 +46,9 @@ extern void usb_musb_init(void);
>> >  
>> >  extern void usb_ehci_init(struct 
>ehci_hcd_omap_platform_data *pdata);
>> >  
>> > +/* This is needed for OMAP3 errata 1.164: enabled 
>autoidle can prevent sleep */
>> > +extern void usb_musb_disable_autoidle(void);
>> > +
>> >  #endif
>> >  
>> >  void omap_usb_init(struct omap_usb_config *pdata);
>

Re: [PATCH 11/11] OMAP3: PM: Disable OTG autoidle when waking up from off-mode

[Kevin Hilman]

"Gadiyar, Anand" <gadiyar@ti.com> writes:

> Kevin Hilman wrote:
>> Tero Kristo <tero.kristo@nokia.com> writes:
>> 
>> > From: Tero Kristo <tero.kristo@nokia.com>
>> >
>> > OMAP3 sleep can be prevented in some cases where OTG autoidle is enabled.
>> > This patch force disables autoidle during wakeup from off-mode. See omap
>> > errata 1.164.
>> >
>> > Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
>> 
>> This one needs a refresh against current PM branch.
>> 
>> > ---
>> >  arch/arm/mach-omap2/pm34xx.c          |    6 ++++++
>> >  arch/arm/mach-omap2/usb-musb.c        |   14 ++++++++------
>> >  arch/arm/plat-omap/include/mach/usb.h |    3 +++
>> 
>> mach/usb.h moved to plat/usb.h
>> 
>> >  3 files changed, 17 insertions(+), 6 deletions(-)
>> >
>> > diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
>> > index 5eb7321..070a0a2 100644
>> > --- a/arch/arm/mach-omap2/pm34xx.c
>> > +++ b/arch/arm/mach-omap2/pm34xx.c
>> > @@ -39,6 +39,7 @@
>> >  #include <mach/gpmc.h>
>> >  #include <mach/dma.h>
>> >  #include <mach/dmtimer.h>
>> > +#include <mach/usb.h>
>> >  
>> >  #include <asm/tlbflush.h>
>> >  
>> > @@ -496,6 +497,11 @@ void omap_sram_idle(void)
>> >  			omap3_prcm_restore_context();
>> >  			omap3_sram_restore_context();
>> >  			omap2_sms_restore_context();
>> > +			/*
>> > +			 * Errata 1.164 fix : OTG autoidle can prevent
>> > +			 * sleep
>> > +			 */
>> > +			usb_musb_disable_autoidle();
>> 
>> NAK.  This belongs in the MUSB driver, not in the idle path.
>> 
>
> Kevin,
>
> When we exit off-mode, the autoidle will get enabled, and needs
> an explicit disable. If the MUSB driver is not loaded, there will
> be no one to do this.
>

OK, thanks for the clarification.  The changelog should be updated to
describe this problem in more detail.

Kevin

>
>> Kevin
>> 
>> >  		}
>> >  		omap_uart_resume_idle(0);
>> >  		omap_uart_resume_idle(1);
>> > diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c
>> > index 8dde0b7..f4b86c0 100644
>> > --- a/arch/arm/mach-omap2/usb-musb.c
>> > +++ b/arch/arm/mach-omap2/usb-musb.c
>> > @@ -44,10 +44,11 @@ static struct platform_device dummy_pdev = {
>> >  	},
>> >  };
>> >  
>> > +static void __iomem *otg_base;
>> > +static struct clk *otg_clk;
>> > +
>> >  static void __init usb_musb_pm_init(void)
>> >  {
>> > -	void __iomem *otg_base;
>> > -	struct clk *otg_clk;
>> >  	struct device *dev = &dummy_pdev.dev;
>> >  
>> >  	if (!cpu_is_omap34xx())
>> > @@ -74,12 +75,13 @@ static void __init usb_musb_pm_init(void)
>> >  			cpu_relax();
>> >  	}
>> >  
>> > -	if (otg_clk) {
>> > +	if (otg_clk)
>> >  		clk_disable(otg_clk);
>> > -		clk_put(otg_clk);
>> > -	}
>> > +}
>> >
>> >  
>> > -	iounmap(otg_base);
>> > +void usb_musb_disable_autoidle(void)
>> > +{
>> > +	__raw_writel(0, otg_base + OTG_SYSCONFIG);
>> >  }
>> >  
>> >  #ifdef CONFIG_USB_MUSB_SOC
>> > diff --git a/arch/arm/plat-omap/include/mach/usb.h b/arch/arm/plat-omap/include/mach/usb.h
>> > index a4068a4..310ee17 100644
>> > --- a/arch/arm/plat-omap/include/mach/usb.h
>> > +++ b/arch/arm/plat-omap/include/mach/usb.h
>> > @@ -46,6 +46,9 @@ extern void usb_musb_init(void);
>> >  
>> >  extern void usb_ehci_init(struct ehci_hcd_omap_platform_data *pdata);
>> >  
>> > +/* This is needed for OMAP3 errata 1.164: enabled autoidle can prevent sleep */
>> > +extern void usb_musb_disable_autoidle(void);
>> > +
>> >  #endif
>> >  
>> >  void omap_usb_init(struct omap_usb_config *pdata);

Re: [PATCH 10/11] OMAP3: PM: Write voltage and clock setup times dynamically in idle loop

[Kevin Hilman]

Tero Kristo <tero.kristo@nokia.com> writes:

> From: Tero Kristo <tero.kristo@nokia.com>
>
> It is suggested by TI (SWPA152 February 2009) to write clksetup,
> voltsetup_time1, voltsetup_time2, voltsetup2 dynamically in idle loop.
>
> This allows us to optimize the voltage + clock setup times according to the
> used power save mode.
>
> Signed-off-by: Tero Kristo <tero.kristo@nokia.com>

This one needs a refresh against current PM branch, in particular, Rajendra's
changes to the PRM setup code were merged and conflict with this.

Kevin



> ---
>  arch/arm/mach-omap2/pm.h     |   10 ++++-
>  arch/arm/mach-omap2/pm34xx.c |   86 ++++++++++++++++++++++++------------------
>  2 files changed, 57 insertions(+), 39 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
> index f8d11a2..b384eb1 100644
> --- a/arch/arm/mach-omap2/pm.h
> +++ b/arch/arm/mach-omap2/pm.h
> @@ -24,12 +24,18 @@ extern int omap3_can_sleep(void);
>  extern int set_pwrdm_state(struct powerdomain *pwrdm, u32 state);
>  extern int omap3_idle_init(void);
>  
> -struct prm_setup_vc {
> +struct prm_setup_times_vc {
>  	u16 clksetup;
>  	u16 voltsetup_time1;
>  	u16 voltsetup_time2;
> -	u16 voltoffset;
>  	u16 voltsetup2;
> +	u16 voltsetup1;
> +};
> +
> +struct prm_setup_vc {
> +	struct prm_setup_times_vc *setup_times;
> +	struct prm_setup_times_vc *setup_times_off;
> +	u16 voltoffset;
>  /* PRM_VC_CMD_VAL_0 specific bits */
>  	u16 vdd0_on;
>  	u16 vdd0_onlp;
> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
> index 154cd31..5eb7321 100644
> --- a/arch/arm/mach-omap2/pm34xx.c
> +++ b/arch/arm/mach-omap2/pm34xx.c
> @@ -82,12 +82,17 @@ static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
>  static struct powerdomain *core_pwrdm, *per_pwrdm;
>  static struct powerdomain *cam_pwrdm;
>  
> -static struct prm_setup_vc prm_setup = {
> +static struct prm_setup_times_vc prm_setup_times_default = {
>  	.clksetup = 0xff,
>  	.voltsetup_time1 = 0xfff,
>  	.voltsetup_time2 = 0xfff,
> -	.voltoffset = 0xff,
>  	.voltsetup2 = 0xff,
> +};
> +
> +static struct prm_setup_vc prm_setup_default = {
> +	.setup_times = &prm_setup_times_default,
> +	.setup_times_off = NULL,
> +	.voltoffset = 0xff,
>  	.vdd0_on = 0x30,	/* 1.2v */
>  	.vdd0_onlp = 0x20,	/* 1.0v */
>  	.vdd0_ret = 0x1e,	/* 0.975v */
> @@ -98,6 +103,8 @@ static struct prm_setup_vc prm_setup = {
>  	.vdd1_off = 0x00,	/* 0.6v */
>  };
>  
> +static struct prm_setup_vc *prm_setup = &prm_setup_default;
> +
>  static inline void omap3_per_save_context(void)
>  {
>  	omap3_gpio_save_context();
> @@ -338,6 +345,16 @@ static void restore_table_entry(void)
>  	restore_control_register(control_reg_value);
>  }
>  
> +static void prm_program_setup_times(struct prm_setup_times_vc *times)
> +{
> +	prm_write_mod_reg(times->voltsetup1, OMAP3430_GR_MOD,
> +			OMAP3_PRM_VOLTSETUP1_OFFSET);
> +	prm_write_mod_reg(times->voltsetup2, OMAP3430_GR_MOD,
> +			OMAP3_PRM_VOLTSETUP2_OFFSET);
> +	prm_write_mod_reg(times->clksetup, OMAP3430_GR_MOD,
> +			OMAP3_PRM_CLKSETUP_OFFSET);
> +}
> +
>  void omap_sram_idle(void)
>  {
>  	/* Variable to tell what needs to be saved and restored
> @@ -422,6 +439,9 @@ void omap_sram_idle(void)
>  					     OMAP3_PRM_VOLTCTRL_OFFSET);
>  			omap3_core_save_context();
>  			omap3_prcm_save_context();
> +			if (prm_setup->setup_times_off != NULL)
> +				prm_program_setup_times(prm_setup->
> +					setup_times_off);
>  		} else if (core_next_state == PWRDM_POWER_RET) {
>  			prm_set_mod_reg_bits(OMAP3430_AUTO_RET,
>  						OMAP3430_GR_MOD,
> @@ -479,11 +499,13 @@ void omap_sram_idle(void)
>  		}
>  		omap_uart_resume_idle(0);
>  		omap_uart_resume_idle(1);
> -		if (core_next_state == PWRDM_POWER_OFF)
> +		if (core_next_state == PWRDM_POWER_OFF) {
>  			prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF,
>  					       OMAP3430_GR_MOD,
>  					       OMAP3_PRM_VOLTCTRL_OFFSET);
> -		else if (core_next_state == PWRDM_POWER_RET)
> +			if (prm_setup->setup_times_off != NULL)
> +				prm_program_setup_times(prm_setup->setup_times);
> +		} else if (core_next_state == PWRDM_POWER_RET)
>  			prm_clear_mod_reg_bits(OMAP3430_AUTO_RET,
>  						OMAP3430_GR_MOD,
>  						OMAP3_PRM_VOLTCTRL_OFFSET);
> @@ -1043,21 +1065,19 @@ int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
>  	return -EINVAL;
>  }
>  
> +static void omap3_init_prm_setup_times(struct prm_setup_times_vc *conf)
> +{
> +	if (conf == NULL)
> +		return;
> +
> +	conf->voltsetup1 =
> +		(conf->voltsetup_time2 << OMAP3430_SETUP_TIME2_SHIFT) |
> +		(conf->voltsetup_time1 << OMAP3430_SETUP_TIME1_SHIFT);
> +}
> +
>  void omap3_set_prm_setup_vc(struct prm_setup_vc *setup_vc)
>  {
> -	prm_setup.clksetup = setup_vc->clksetup;
> -	prm_setup.voltsetup_time1 = setup_vc->voltsetup_time1;
> -	prm_setup.voltsetup_time2 = setup_vc->voltsetup_time2;
> -	prm_setup.voltoffset = setup_vc->voltoffset;
> -	prm_setup.voltsetup2 = setup_vc->voltsetup2;
> -	prm_setup.vdd0_on = setup_vc->vdd0_on;
> -	prm_setup.vdd0_onlp = setup_vc->vdd0_onlp;
> -	prm_setup.vdd0_ret = setup_vc->vdd0_ret;
> -	prm_setup.vdd0_off = setup_vc->vdd0_off;
> -	prm_setup.vdd1_on = setup_vc->vdd1_on;
> -	prm_setup.vdd1_onlp = setup_vc->vdd1_onlp;
> -	prm_setup.vdd1_ret = setup_vc->vdd1_ret;
> -	prm_setup.vdd1_off = setup_vc->vdd1_off;
> +	prm_setup = setup_vc;
>  }
>  
>  static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
> @@ -1204,16 +1224,16 @@ static void __init configure_vc(void)
>  			  (R_VDD1_SR_CONTROL << OMAP3430_VOLRA0_SHIFT),
>  			  OMAP3430_GR_MOD, OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET);
>  
> -	prm_write_mod_reg((prm_setup.vdd0_on << OMAP3430_VC_CMD_ON_SHIFT) |
> -		(prm_setup.vdd0_onlp << OMAP3430_VC_CMD_ONLP_SHIFT) |
> -		(prm_setup.vdd0_ret << OMAP3430_VC_CMD_RET_SHIFT) |
> -		(prm_setup.vdd0_off << OMAP3430_VC_CMD_OFF_SHIFT),
> +	prm_write_mod_reg((prm_setup->vdd0_on << OMAP3430_VC_CMD_ON_SHIFT) |
> +		(prm_setup->vdd0_onlp << OMAP3430_VC_CMD_ONLP_SHIFT) |
> +		(prm_setup->vdd0_ret << OMAP3430_VC_CMD_RET_SHIFT) |
> +		(prm_setup->vdd0_off << OMAP3430_VC_CMD_OFF_SHIFT),
>  		OMAP3430_GR_MOD, OMAP3_PRM_VC_CMD_VAL_0_OFFSET);
>  
> -	prm_write_mod_reg((prm_setup.vdd1_on << OMAP3430_VC_CMD_ON_SHIFT) |
> -		(prm_setup.vdd1_onlp << OMAP3430_VC_CMD_ONLP_SHIFT) |
> -		(prm_setup.vdd1_ret << OMAP3430_VC_CMD_RET_SHIFT) |
> -		(prm_setup.vdd1_off << OMAP3430_VC_CMD_OFF_SHIFT),
> +	prm_write_mod_reg((prm_setup->vdd1_on << OMAP3430_VC_CMD_ON_SHIFT) |
> +		(prm_setup->vdd1_onlp << OMAP3430_VC_CMD_ONLP_SHIFT) |
> +		(prm_setup->vdd1_ret << OMAP3430_VC_CMD_RET_SHIFT) |
> +		(prm_setup->vdd1_off << OMAP3430_VC_CMD_OFF_SHIFT),
>  		OMAP3430_GR_MOD, OMAP3_PRM_VC_CMD_VAL_1_OFFSET);
>  
>  	prm_write_mod_reg(OMAP3430_CMD1 | OMAP3430_RAV1, OMAP3430_GR_MOD,
> @@ -1224,19 +1244,11 @@ static void __init configure_vc(void)
>  			  OMAP3_PRM_VC_I2C_CFG_OFFSET);
>  
>  	/* Write setup times */
> -	prm_write_mod_reg(prm_setup.clksetup, OMAP3430_GR_MOD,
> -			OMAP3_PRM_CLKSETUP_OFFSET);
> -	prm_write_mod_reg((prm_setup.voltsetup_time2 <<
> -			OMAP3430_SETUP_TIME2_SHIFT) |
> -			(prm_setup.voltsetup_time1 <<
> -			OMAP3430_SETUP_TIME1_SHIFT),
> -			OMAP3430_GR_MOD, OMAP3_PRM_VOLTSETUP1_OFFSET);
> -
> -	prm_write_mod_reg(prm_setup.voltoffset, OMAP3430_GR_MOD,
> +	omap3_init_prm_setup_times(prm_setup->setup_times);
> +	omap3_init_prm_setup_times(prm_setup->setup_times_off);
> +	prm_program_setup_times(prm_setup->setup_times);
> +	prm_write_mod_reg(prm_setup->voltoffset, OMAP3430_GR_MOD,
>  			OMAP3_PRM_VOLTOFFSET_OFFSET);
> -	prm_write_mod_reg(prm_setup.voltsetup2, OMAP3430_GR_MOD,
> -			OMAP3_PRM_VOLTSETUP2_OFFSET);
> -
>  	pm_dbg_regset_init(1);
>  	pm_dbg_regset_init(2);
>  }
> -- 
> 1.5.4.3
>
> --
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Re: [PATCH 09/11] OMAP3: PM: Added support for L2 aux ctrl register save and restore

[Kevin Hilman]

Tero Kristo <tero.kristo@nokia.com> writes:

> From: Tero Kristo <tero.kristo@nokia.com>
>
> This patch adds a save and restore mechanism for ARM L2 auxiliary control
> register. This feature is enabled via Kconfig option
> OMAP3_L2_AUX_SECURE_SAVE_RESTORE and the service ID for PPA can be provided
> via option OMAP3_L2_AUX_SECURE_SERVICE_SET_ID. If bootloader does not modify
> L2 aux register, using this save and restore logic for it is not needed.
>
> Signed-off-by: Tero Kristo <tero.kristo@nokia.com>

Thanks, pulling into PM branch.

Kevin

> ---
>  arch/arm/mach-omap2/control.c   |    1 +
>  arch/arm/mach-omap2/sleep34xx.S |   31 +++++++++++++++++++++++++++++++
>  arch/arm/plat-omap/Kconfig      |   17 +++++++++++++++++
>  3 files changed, 49 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
> index 730fc53..82d8f1a 100644
> --- a/arch/arm/mach-omap2/control.c
> +++ b/arch/arm/mach-omap2/control.c
> @@ -95,6 +95,7 @@ void *omap3_secure_ram_storage;
>   */
>  u32 omap3_arm_context[128];
>  u32 omap3_aux_ctrl[2] = { 0x1, 0x0 };
> +u32 omap3_l2_aux_ctrl[2] = { 0x1, 0x0 };
>  
>  struct omap3_control_regs {
>  	u32 sysconfig;
> diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
> index 0b03bf9..e291d6d 100644
> --- a/arch/arm/mach-omap2/sleep34xx.S
> +++ b/arch/arm/mach-omap2/sleep34xx.S
> @@ -288,11 +288,30 @@ restore:
>  	mcr	p15, 0, r0, c7, c10, 5	@ data memory barrier
>  	.word	0xE1600071		@ call SMI monitor (smi #1)
>  
> +#ifdef CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE
> +	/* Restore L2 aux control register */
> +	@ set service ID for PPA
> +	mov	r0, #CONFIG_OMAP3_L2_AUX_SECURE_SERVICE_SET_ID
> +	mov	r12, r0		@ copy service ID in r12
> +	mov	r1, #0		@ set task ID for ROM code in r1
> +	mov	r2, #4		@ set some flags in r2, r6
> +	mov	r6, #0xff
> +	ldr	r3, write_l2_aux_control_params	@ r3 points to parameters
> +	ldr	r4, phys_offset
> +	adds	r3, r3, r4
> +	ldr	r4, page_offset
> +	subs	r3, r3, r4
> +	mcr	p15, 0, r0, c7, c10, 4	@ data write barrier
> +	mcr	p15, 0, r0, c7, c10, 5	@ data memory barrier
> +	.word	0xE1600071		@ call SMI monitor (smi #1)
> +#endif
>  	b	logic_l1_restore
>  l2_inv_api_params:
>  	.word   0x1, 0x00
>  write_aux_control_params:
>  	.word	omap3_aux_ctrl
> +write_l2_aux_control_params:
> +	.word	omap3_l2_aux_ctrl
>  l2_inv_gp:
>  	/* Execute smi to invalidate L2 cache */
>  	mov r12, #0x1                         @ set up to invalide L2
> @@ -306,6 +325,15 @@ smi:    .word 0xE1600070		@ Call SMI monitor (smieq)
>  	ldr	r0, [r1, #4]
>  	mov	r12, #0x3
>  	.word 0xE1600070	@ Call SMI monitor (smieq)
> +	/* Restore L2 AUX control register */
> +	ldr	r1, write_l2_aux_control_params
> +	ldr	r0, phys_offset
> +	adds	r1, r1, r0
> +	ldr	r0, page_offset
> +	subs	r1, r1, r0
> +	ldr	r0, [r1, #4]
> +	mov	r12, #0x2
> +	.word 0xE1600070	@ Call SMI monitor (smieq)
>  logic_l1_restore:
>  	mov	r1, #0
>  	/* Invalidate all instruction caches to PoU
> @@ -433,6 +461,9 @@ save_context_wfi:
>  	mrc	p15, 0, r4, c1, c0, 1	@ Read Auxiliary Control Register
>  	ldr	r5, write_aux_control_params
>  	str	r4, [r5, #4]
> +	mrc	p15, 1, r4, c9, c0, 2	@ Read L2 AUX ctrl register
> +	ldr	r5, write_l2_aux_control_params
> +	str	r4, [r5, #4]
>          /* Check what that target sleep state is:stored in r1*/
>          /* 1 - Only L1 and logic lost */
>          /* 2 - Only L2 lost */
> diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
> index 2143db5..3ff1a5f 100644
> --- a/arch/arm/plat-omap/Kconfig
> +++ b/arch/arm/plat-omap/Kconfig
> @@ -185,6 +185,23 @@ config OMAP3_DEBOBS
>  	help
>  	  Use ETK pads for debug observability
>  
> +config OMAP3_L2_AUX_SECURE_SAVE_RESTORE
> +	bool "OMAP3 HS/EMU save and restore for L2 AUX control register"
> +	depends on ARCH_OMAP3 && PM
> +	default n
> +	help
> +	  Without this option, L2 Auxiliary control register contents are
> +	  lost during off-mode entry on HS/EMU devices. This feature
> +	  requires support from PPA / boot-loader in HS/EMU devices, which
> +	  currently does not exist by default.
> +
> +config OMAP3_L2_AUX_SECURE_SERVICE_SET_ID
> +	int "Service ID for the support routine to set L2 AUX control"
> +	depends on OMAP3_L2_AUX_SECURE_SAVE_RESTORE
> +	default 43
> +	help
> +	  PPA routine service ID for setting L2 auxiliary control register.
> +
>  config OMAP_32K_TIMER_HZ
>         int "Kernel internal timer frequency for 32KHz timer"
>         range 32 1024
> -- 
> 1.5.4.3
>
> --
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RE: [PATCH 09/11] OMAP3: PM: Added support for L2 aux ctrl register save and restore

[Tero.Kristo]

 

>-----Original Message-----
>From: ext Kevin Hilman [mailto:khilman@deeprootsystems.com] 
>Sent: 12 November, 2009 01:45
>To: Kristo Tero (Nokia-D/Tampere)
>Cc: linux-omap@vger.kernel.org
>Subject: Re: [PATCH 09/11] OMAP3: PM: Added support for L2 aux 
>ctrl register save and restore
>
>Tero Kristo <tero.kristo@nokia.com> writes:
>
>> From: Tero Kristo <tero.kristo@nokia.com>
>>
>> This patch adds a save and restore mechanism for ARM L2 
>auxiliary control
>> register. This feature is enabled via Kconfig option
>> OMAP3_L2_AUX_SECURE_SAVE_RESTORE and the service ID for PPA 
>can be provided
>> via option OMAP3_L2_AUX_SECURE_SERVICE_SET_ID. If bootloader 
>does not modify
>> L2 aux register, using this save and restore logic for it is 
>not needed.
>>
>> Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
>
>Thanks, pulling into PM branch.

Same thing for this one, I have a version that uses arm_context as storage area. I'll send it out also in a bit.

>
>Kevin
>
>> ---
>>  arch/arm/mach-omap2/control.c   |    1 +
>>  arch/arm/mach-omap2/sleep34xx.S |   31 
>+++++++++++++++++++++++++++++++
>>  arch/arm/plat-omap/Kconfig      |   17 +++++++++++++++++
>>  3 files changed, 49 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/mach-omap2/control.c 
>b/arch/arm/mach-omap2/control.c
>> index 730fc53..82d8f1a 100644
>> --- a/arch/arm/mach-omap2/control.c
>> +++ b/arch/arm/mach-omap2/control.c
>> @@ -95,6 +95,7 @@ void *omap3_secure_ram_storage;
>>   */
>>  u32 omap3_arm_context[128];
>>  u32 omap3_aux_ctrl[2] = { 0x1, 0x0 };
>> +u32 omap3_l2_aux_ctrl[2] = { 0x1, 0x0 };
>>  
>>  struct omap3_control_regs {
>>  	u32 sysconfig;
>> diff --git a/arch/arm/mach-omap2/sleep34xx.S 
>b/arch/arm/mach-omap2/sleep34xx.S
>> index 0b03bf9..e291d6d 100644
>> --- a/arch/arm/mach-omap2/sleep34xx.S
>> +++ b/arch/arm/mach-omap2/sleep34xx.S
>> @@ -288,11 +288,30 @@ restore:
>>  	mcr	p15, 0, r0, c7, c10, 5	@ data memory barrier
>>  	.word	0xE1600071		@ call SMI monitor (smi #1)
>>  
>> +#ifdef CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE
>> +	/* Restore L2 aux control register */
>> +	@ set service ID for PPA
>> +	mov	r0, #CONFIG_OMAP3_L2_AUX_SECURE_SERVICE_SET_ID
>> +	mov	r12, r0		@ copy service ID in r12
>> +	mov	r1, #0		@ set task ID for ROM code in r1
>> +	mov	r2, #4		@ set some flags in r2, r6
>> +	mov	r6, #0xff
>> +	ldr	r3, write_l2_aux_control_params	@ r3 points to 
>parameters
>> +	ldr	r4, phys_offset
>> +	adds	r3, r3, r4
>> +	ldr	r4, page_offset
>> +	subs	r3, r3, r4
>> +	mcr	p15, 0, r0, c7, c10, 4	@ data write barrier
>> +	mcr	p15, 0, r0, c7, c10, 5	@ data memory barrier
>> +	.word	0xE1600071		@ call SMI monitor (smi #1)
>> +#endif
>>  	b	logic_l1_restore
>>  l2_inv_api_params:
>>  	.word   0x1, 0x00
>>  write_aux_control_params:
>>  	.word	omap3_aux_ctrl
>> +write_l2_aux_control_params:
>> +	.word	omap3_l2_aux_ctrl
>>  l2_inv_gp:
>>  	/* Execute smi to invalidate L2 cache */
>>  	mov r12, #0x1                         @ set up to invalide L2
>> @@ -306,6 +325,15 @@ smi:    .word 0xE1600070		
>@ Call SMI monitor (smieq)
>>  	ldr	r0, [r1, #4]
>>  	mov	r12, #0x3
>>  	.word 0xE1600070	@ Call SMI monitor (smieq)
>> +	/* Restore L2 AUX control register */
>> +	ldr	r1, write_l2_aux_control_params
>> +	ldr	r0, phys_offset
>> +	adds	r1, r1, r0
>> +	ldr	r0, page_offset
>> +	subs	r1, r1, r0
>> +	ldr	r0, [r1, #4]
>> +	mov	r12, #0x2
>> +	.word 0xE1600070	@ Call SMI monitor (smieq)
>>  logic_l1_restore:
>>  	mov	r1, #0
>>  	/* Invalidate all instruction caches to PoU
>> @@ -433,6 +461,9 @@ save_context_wfi:
>>  	mrc	p15, 0, r4, c1, c0, 1	@ Read Auxiliary 
>Control Register
>>  	ldr	r5, write_aux_control_params
>>  	str	r4, [r5, #4]
>> +	mrc	p15, 1, r4, c9, c0, 2	@ Read L2 AUX ctrl register
>> +	ldr	r5, write_l2_aux_control_params
>> +	str	r4, [r5, #4]
>>          /* Check what that target sleep state is:stored in r1*/
>>          /* 1 - Only L1 and logic lost */
>>          /* 2 - Only L2 lost */
>> diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
>> index 2143db5..3ff1a5f 100644
>> --- a/arch/arm/plat-omap/Kconfig
>> +++ b/arch/arm/plat-omap/Kconfig
>> @@ -185,6 +185,23 @@ config OMAP3_DEBOBS
>>  	help
>>  	  Use ETK pads for debug observability
>>  
>> +config OMAP3_L2_AUX_SECURE_SAVE_RESTORE
>> +	bool "OMAP3 HS/EMU save and restore for L2 AUX control register"
>> +	depends on ARCH_OMAP3 && PM
>> +	default n
>> +	help
>> +	  Without this option, L2 Auxiliary control register 
>contents are
>> +	  lost during off-mode entry on HS/EMU devices. This feature
>> +	  requires support from PPA / boot-loader in HS/EMU 
>devices, which
>> +	  currently does not exist by default.
>> +
>> +config OMAP3_L2_AUX_SECURE_SERVICE_SET_ID
>> +	int "Service ID for the support routine to set L2 AUX control"
>> +	depends on OMAP3_L2_AUX_SECURE_SAVE_RESTORE
>> +	default 43
>> +	help
>> +	  PPA routine service ID for setting L2 auxiliary 
>control register.
>> +
>>  config OMAP_32K_TIMER_HZ
>>         int "Kernel internal timer frequency for 32KHz timer"
>>         range 32 1024
>> -- 
>> 1.5.4.3
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe 
>linux-omap" in
>> the body of a message to majordomo@vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>

Re: [PATCH 08/11] OMAP3: PM: Disabled I2C4 repeated start operation mode

[Kevin Hilman]

Tero Kristo <tero.kristo@nokia.com> writes:

> From: Tero Kristo <tero.kristo@nokia.com>
>
> Repeated start forces I2C4 pads low during idle, which increases power
> consumption through external pull-ups. On the other hand, this change
> increases I2C4 command latencies a bit.

Could you give an idea about how much the latencies increased?

I'll apply this one but would like to update the changelog with some
more details if available.

Kevin

> Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
> ---
>  arch/arm/mach-omap2/pm34xx.c |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
> index fec9c38..154cd31 100644
> --- a/arch/arm/mach-omap2/pm34xx.c
> +++ b/arch/arm/mach-omap2/pm34xx.c
> @@ -1219,7 +1219,7 @@ static void __init configure_vc(void)
>  	prm_write_mod_reg(OMAP3430_CMD1 | OMAP3430_RAV1, OMAP3430_GR_MOD,
>  			  OMAP3_PRM_VC_CH_CONF_OFFSET);
>  
> -	prm_write_mod_reg(OMAP3430_MCODE_SHIFT | OMAP3430_HSEN | OMAP3430_SREN,
> +	prm_write_mod_reg(OMAP3430_MCODE_SHIFT | OMAP3430_HSEN,
>  			  OMAP3430_GR_MOD,
>  			  OMAP3_PRM_VC_I2C_CFG_OFFSET);
>  
> -- 
> 1.5.4.3
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

RE: [PATCH 08/11] OMAP3: PM: Disabled I2C4 repeated start operation mode

[Tero.Kristo]

 

>-----Original Message-----
>From: ext Kevin Hilman [mailto:khilman@deeprootsystems.com] 
>Sent: 12 November, 2009 01:30
>To: Kristo Tero (Nokia-D/Tampere)
>Cc: linux-omap@vger.kernel.org
>Subject: Re: [PATCH 08/11] OMAP3: PM: Disabled I2C4 repeated 
>start operation mode
>
>Tero Kristo <tero.kristo@nokia.com> writes:
>
>> From: Tero Kristo <tero.kristo@nokia.com>
>>
>> Repeated start forces I2C4 pads low during idle, which 
>increases power
>> consumption through external pull-ups. On the other hand, this change
>> increases I2C4 command latencies a bit.
>
>Could you give an idea about how much the latencies increased?

There is an additional master code (= 10 bits with start + ack) transmitted in the beginning of each I2C4 transmission. It is transmitted in fast/standard mode instead of high-speed, thus the duration of each I2C command is approximately doubled, from 25us to 50us. I'll update the patch description a bit and re-send.

>
>I'll apply this one but would like to update the changelog with some
>more details if available.
>
>Kevin
>
>> Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
>> ---
>>  arch/arm/mach-omap2/pm34xx.c |    2 +-
>>  1 files changed, 1 insertions(+), 1 deletions(-)
>>
>> diff --git a/arch/arm/mach-omap2/pm34xx.c 
>b/arch/arm/mach-omap2/pm34xx.c
>> index fec9c38..154cd31 100644
>> --- a/arch/arm/mach-omap2/pm34xx.c
>> +++ b/arch/arm/mach-omap2/pm34xx.c
>> @@ -1219,7 +1219,7 @@ static void __init configure_vc(void)
>>  	prm_write_mod_reg(OMAP3430_CMD1 | OMAP3430_RAV1, 
>OMAP3430_GR_MOD,
>>  			  OMAP3_PRM_VC_CH_CONF_OFFSET);
>>  
>> -	prm_write_mod_reg(OMAP3430_MCODE_SHIFT | OMAP3430_HSEN 
>| OMAP3430_SREN,
>> +	prm_write_mod_reg(OMAP3430_MCODE_SHIFT | OMAP3430_HSEN,
>>  			  OMAP3430_GR_MOD,
>>  			  OMAP3_PRM_VC_I2C_CFG_OFFSET);
>>  
>> -- 
>> 1.5.4.3
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe 
>linux-omap" in
>> the body of a message to majordomo@vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>

RE: [PATCH 07/11] OMAP3: Fixed ARM aux ctrl register save/restore

[Gopinath, Thara]

>>-----Original Message-----
>>From: linux-omap-owner@vger.kernel.org [mailto:linux-omap-owner@vger.kernel.org] On Behalf Of Tero
>>Kristo
>>Sent: Friday, October 23, 2009 9:34 PM
>>To: linux-omap@vger.kernel.org
>>Subject: [PATCH 07/11] OMAP3: Fixed ARM aux ctrl register save/restore
>>
>>From: Tero Kristo <tero.kristo@nokia.com>
>>
>>Current value is stored on SDRAM and it is written back during wakeup.
>>Previously a static value of 0x72 was written there.
>>
>>Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
>>Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com>
>>---
>> arch/arm/mach-omap2/control.c   |    1 +
>> arch/arm/mach-omap2/sleep34xx.S |   23 ++++++++++++++++++++---
>> 2 files changed, 21 insertions(+), 3 deletions(-)
>>
>>diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
>>index 296f2c2..730fc53 100644
>>--- a/arch/arm/mach-omap2/control.c
>>+++ b/arch/arm/mach-omap2/control.c
>>@@ -94,6 +94,7 @@ void *omap3_secure_ram_storage;
>>  * during the restore path.
>>  */
>> u32 omap3_arm_context[128];
>>+u32 omap3_aux_ctrl[2] = { 0x1, 0x0 };
>>
>> struct omap3_control_regs {
>> 	u32 sysconfig;
>>diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
>>index f4f5ebe..0b03bf9 100644
>>--- a/arch/arm/mach-omap2/sleep34xx.S
>>+++ b/arch/arm/mach-omap2/sleep34xx.S
>>@@ -26,6 +26,7 @@
>>  */
>> #include <linux/linkage.h>
>> #include <asm/assembler.h>
>>+#include <asm/memory.h>
>> #include <mach/io.h>
>> #include <mach/control.h>
>>
>>@@ -278,7 +279,11 @@ restore:
>> 	mov	r1, #0		@ set task id for ROM code in r1
>> 	mov	r2, #4		@ set some flags in r2, r6
>> 	mov	r6, #0xff
>>-	adr	r3, write_aux_control_params	@ r3 points to parameters
>>+	ldr	r3, write_aux_control_params	@ r3 points to parameters
>>+	ldr	r4, phys_offset
>>+	adds	r3, r3, r4
>>+	ldr	r4, page_offset
>>+	subs	r3, r3, r4
>> 	mcr	p15, 0, r0, c7, c10, 4	@ data write barrier
>> 	mcr	p15, 0, r0, c7, c10, 5	@ data memory barrier
>> 	.word	0xE1600071		@ call SMI monitor (smi #1)
>>@@ -287,13 +292,18 @@ restore:
>> l2_inv_api_params:
>> 	.word   0x1, 0x00
>> write_aux_control_params:
>>-	.word   0x1, 0x72
>>+	.word	omap3_aux_ctrl
>> l2_inv_gp:
>> 	/* Execute smi to invalidate L2 cache */
>> 	mov r12, #0x1                         @ set up to invalide L2
>> smi:    .word 0xE1600070		@ Call SMI monitor (smieq)
>> 	/* Write to Aux control register to set some bits */
>>-	mov	r0, #0x72
>>+	ldr	r1, write_aux_control_params
>>+	ldr	r0, phys_offset
>>+	adds	r1, r1, r0
>>+	ldr	r0, page_offset
>>+	subs	r1, r1, r0
>>+	ldr	r0, [r1, #4]
>> 	mov	r12, #0x3
>> 	.word 0xE1600070	@ Call SMI monitor (smieq)
>> logic_l1_restore:
>>@@ -420,6 +430,9 @@ usettbr0:
>> save_context_wfi:
>> 	/*b	save_context_wfi*/	@ enable to debug save code
>> 	mov	r8, r0 /* Store SDRAM address in r8 */
>>+	mrc	p15, 0, r4, c1, c0, 1	@ Read Auxiliary Control Register
>>+	ldr	r5, write_aux_control_params
>>+	str	r4, [r5, #4]

There is a simpler way of doing this. Store the aux control value at the top of the sdram array where other parameters are stored. It would be something like following
		mrc	p15, 0, r4, c1, c0, 1
	      str	r4, [r8]
		add r8, r8, #4
In the restore, you can read it from this location and pass it as parameter for smi for gp device or pass this location as a parameter for emu device. In this way no need to define page_offset and phys_offset. I have a patch done for this for an internal code base. I can share it with you if interested. Else I can post it after rebasing. Do let me know.

>>         /* Check what that target sleep state is:stored in r1*/
>>         /* 1 - Only L1 and logic lost */
>>         /* 2 - Only L2 lost */
>>@@ -605,6 +618,10 @@ wait_dll_lock:
>>         bne     wait_dll_lock
>>         bx      lr
>>
>>+phys_offset:
>>+	.word	PHYS_OFFSET
>>+page_offset:
>>+	.word	PAGE_OFFSET
>> cm_idlest1_core:
>> 	.word	CM_IDLEST1_CORE_V
>> sdrc_dlla_status:
>>--
>>1.5.4.3
>>
>>--
>>To unsubscribe from this list: send the line "unsubscribe linux-omap" in
>>the body of a message to majordomo@vger.kernel.org
>>More majordomo info at  http://vger.kernel.org/majordomo-info.html

RE: [PATCH 07/11] OMAP3: Fixed ARM aux ctrl register save/restore

[Tero.Kristo]

 

>-----Original Message-----
>From: ext Gopinath, Thara [mailto:thara@ti.com] 
>Sent: 28 October, 2009 11:32
>To: Kristo Tero (Nokia-D/Tampere); linux-omap@vger.kernel.org
>Subject: RE: [PATCH 07/11] OMAP3: Fixed ARM aux ctrl register 
>save/restore
>
>
>
>>>-----Original Message-----
>>>From: linux-omap-owner@vger.kernel.org 
>[mailto:linux-omap-owner@vger.kernel.org] On Behalf Of Tero
>>>Kristo
>>>Sent: Friday, October 23, 2009 9:34 PM
>>>To: linux-omap@vger.kernel.org
>>>Subject: [PATCH 07/11] OMAP3: Fixed ARM aux ctrl register 
>save/restore
>>>
>>>From: Tero Kristo <tero.kristo@nokia.com>
>>>
>>>Current value is stored on SDRAM and it is written back 
>during wakeup.
>>>Previously a static value of 0x72 was written there.
>>>
>>>Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
>>>Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com>
>>>---
>>> arch/arm/mach-omap2/control.c   |    1 +
>>> arch/arm/mach-omap2/sleep34xx.S |   23 ++++++++++++++++++++---
>>> 2 files changed, 21 insertions(+), 3 deletions(-)
>>>
>>>diff --git a/arch/arm/mach-omap2/control.c 
>b/arch/arm/mach-omap2/control.c
>>>index 296f2c2..730fc53 100644
>>>--- a/arch/arm/mach-omap2/control.c
>>>+++ b/arch/arm/mach-omap2/control.c
>>>@@ -94,6 +94,7 @@ void *omap3_secure_ram_storage;
>>>  * during the restore path.
>>>  */
>>> u32 omap3_arm_context[128];
>>>+u32 omap3_aux_ctrl[2] = { 0x1, 0x0 };
>>>
>>> struct omap3_control_regs {
>>> 	u32 sysconfig;
>>>diff --git a/arch/arm/mach-omap2/sleep34xx.S 
>b/arch/arm/mach-omap2/sleep34xx.S
>>>index f4f5ebe..0b03bf9 100644
>>>--- a/arch/arm/mach-omap2/sleep34xx.S
>>>+++ b/arch/arm/mach-omap2/sleep34xx.S
>>>@@ -26,6 +26,7 @@
>>>  */
>>> #include <linux/linkage.h>
>>> #include <asm/assembler.h>
>>>+#include <asm/memory.h>
>>> #include <mach/io.h>
>>> #include <mach/control.h>
>>>
>>>@@ -278,7 +279,11 @@ restore:
>>> 	mov	r1, #0		@ set task id for ROM code in r1
>>> 	mov	r2, #4		@ set some flags in r2, r6
>>> 	mov	r6, #0xff
>>>-	adr	r3, write_aux_control_params	@ r3 points to 
>parameters
>>>+	ldr	r3, write_aux_control_params	@ r3 points to 
>parameters
>>>+	ldr	r4, phys_offset
>>>+	adds	r3, r3, r4
>>>+	ldr	r4, page_offset
>>>+	subs	r3, r3, r4
>>> 	mcr	p15, 0, r0, c7, c10, 4	@ data write barrier
>>> 	mcr	p15, 0, r0, c7, c10, 5	@ data memory barrier
>>> 	.word	0xE1600071		@ call SMI monitor (smi #1)
>>>@@ -287,13 +292,18 @@ restore:
>>> l2_inv_api_params:
>>> 	.word   0x1, 0x00
>>> write_aux_control_params:
>>>-	.word   0x1, 0x72
>>>+	.word	omap3_aux_ctrl
>>> l2_inv_gp:
>>> 	/* Execute smi to invalidate L2 cache */
>>> 	mov r12, #0x1                         @ set up to invalide L2
>>> smi:    .word 0xE1600070		@ Call SMI monitor (smieq)
>>> 	/* Write to Aux control register to set some bits */
>>>-	mov	r0, #0x72
>>>+	ldr	r1, write_aux_control_params
>>>+	ldr	r0, phys_offset
>>>+	adds	r1, r1, r0
>>>+	ldr	r0, page_offset
>>>+	subs	r1, r1, r0
>>>+	ldr	r0, [r1, #4]
>>> 	mov	r12, #0x3
>>> 	.word 0xE1600070	@ Call SMI monitor (smieq)
>>> logic_l1_restore:
>>>@@ -420,6 +430,9 @@ usettbr0:
>>> save_context_wfi:
>>> 	/*b	save_context_wfi*/	@ enable to debug save code
>>> 	mov	r8, r0 /* Store SDRAM address in r8 */
>>>+	mrc	p15, 0, r4, c1, c0, 1	@ Read Auxiliary 
>Control Register
>>>+	ldr	r5, write_aux_control_params
>>>+	str	r4, [r5, #4]
>
>There is a simpler way of doing this. Store the aux control 
>value at the top of the sdram array where other parameters are 
>stored. It would be something like following
>		mrc	p15, 0, r4, c1, c0, 1
>	      str	r4, [r8]
>		add r8, r8, #4
>In the restore, you can read it from this location and pass it 
>as parameter for smi for gp device or pass this location as a 
>parameter for emu device. In this way no need to define 
>page_offset and phys_offset. I have a patch done for this for 
>an internal code base. I can share it with you if interested. 
>Else I can post it after rebasing. Do let me know.

I can modify my patch according to this. However, do you know how much of the sdram array is currently used? The size is 128 32bit words but I would not like to calculate manually how much of that is used and whether I need to increase its size or not.


>
>>>         /* Check what that target sleep state is:stored in r1*/
>>>         /* 1 - Only L1 and logic lost */
>>>         /* 2 - Only L2 lost */
>>>@@ -605,6 +618,10 @@ wait_dll_lock:
>>>         bne     wait_dll_lock
>>>         bx      lr
>>>
>>>+phys_offset:
>>>+	.word	PHYS_OFFSET
>>>+page_offset:
>>>+	.word	PAGE_OFFSET
>>> cm_idlest1_core:
>>> 	.word	CM_IDLEST1_CORE_V
>>> sdrc_dlla_status:
>>>--
>>>1.5.4.3
>>>
>>>--
>>>To unsubscribe from this list: send the line "unsubscribe 
>linux-omap" in
>>>the body of a message to majordomo@vger.kernel.org
>>>More majordomo info at  http://vger.kernel.org/majordomo-info.html
>
>

RE: [PATCH 07/11] OMAP3: Fixed ARM aux ctrl register save/restore

[Gopinath, Thara]

>>-----Original Message-----
>>From: Tero.Kristo@nokia.com [mailto:Tero.Kristo@nokia.com]
>>Sent: Wednesday, October 28, 2009 4:24 PM
>>To: Gopinath, Thara; linux-omap@vger.kernel.org
>>Subject: RE: [PATCH 07/11] OMAP3: Fixed ARM aux ctrl register save/restore
>>
>>
>>
>>>-----Original Message-----
>>>From: ext Gopinath, Thara [mailto:thara@ti.com]
>>>Sent: 28 October, 2009 11:32
>>>To: Kristo Tero (Nokia-D/Tampere); linux-omap@vger.kernel.org
>>>Subject: RE: [PATCH 07/11] OMAP3: Fixed ARM aux ctrl register
>>>save/restore
>>>
>>>
>>>
>>>>>-----Original Message-----
>>>>>From: linux-omap-owner@vger.kernel.org
>>>[mailto:linux-omap-owner@vger.kernel.org] On Behalf Of Tero
>>>>>Kristo
>>>>>Sent: Friday, October 23, 2009 9:34 PM
>>>>>To: linux-omap@vger.kernel.org
>>>>>Subject: [PATCH 07/11] OMAP3: Fixed ARM aux ctrl register
>>>save/restore
>>>>>
>>>>>From: Tero Kristo <tero.kristo@nokia.com>
>>>>>
>>>>>Current value is stored on SDRAM and it is written back
>>>during wakeup.
>>>>>Previously a static value of 0x72 was written there.
>>>>>
>>>>>Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
>>>>>Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com>
>>>>>---
>>>>> arch/arm/mach-omap2/control.c   |    1 +
>>>>> arch/arm/mach-omap2/sleep34xx.S |   23 ++++++++++++++++++++---
>>>>> 2 files changed, 21 insertions(+), 3 deletions(-)
>>>>>
>>>>>diff --git a/arch/arm/mach-omap2/control.c
>>>b/arch/arm/mach-omap2/control.c
>>>>>index 296f2c2..730fc53 100644
>>>>>--- a/arch/arm/mach-omap2/control.c
>>>>>+++ b/arch/arm/mach-omap2/control.c
>>>>>@@ -94,6 +94,7 @@ void *omap3_secure_ram_storage;
>>>>>  * during the restore path.
>>>>>  */
>>>>> u32 omap3_arm_context[128];
>>>>>+u32 omap3_aux_ctrl[2] = { 0x1, 0x0 };
>>>>>
>>>>> struct omap3_control_regs {
>>>>> 	u32 sysconfig;
>>>>>diff --git a/arch/arm/mach-omap2/sleep34xx.S
>>>b/arch/arm/mach-omap2/sleep34xx.S
>>>>>index f4f5ebe..0b03bf9 100644
>>>>>--- a/arch/arm/mach-omap2/sleep34xx.S
>>>>>+++ b/arch/arm/mach-omap2/sleep34xx.S
>>>>>@@ -26,6 +26,7 @@
>>>>>  */
>>>>> #include <linux/linkage.h>
>>>>> #include <asm/assembler.h>
>>>>>+#include <asm/memory.h>
>>>>> #include <mach/io.h>
>>>>> #include <mach/control.h>
>>>>>
>>>>>@@ -278,7 +279,11 @@ restore:
>>>>> 	mov	r1, #0		@ set task id for ROM code in r1
>>>>> 	mov	r2, #4		@ set some flags in r2, r6
>>>>> 	mov	r6, #0xff
>>>>>-	adr	r3, write_aux_control_params	@ r3 points to
>>>parameters
>>>>>+	ldr	r3, write_aux_control_params	@ r3 points to
>>>parameters
>>>>>+	ldr	r4, phys_offset
>>>>>+	adds	r3, r3, r4
>>>>>+	ldr	r4, page_offset
>>>>>+	subs	r3, r3, r4
>>>>> 	mcr	p15, 0, r0, c7, c10, 4	@ data write barrier
>>>>> 	mcr	p15, 0, r0, c7, c10, 5	@ data memory barrier
>>>>> 	.word	0xE1600071		@ call SMI monitor (smi #1)
>>>>>@@ -287,13 +292,18 @@ restore:
>>>>> l2_inv_api_params:
>>>>> 	.word   0x1, 0x00
>>>>> write_aux_control_params:
>>>>>-	.word   0x1, 0x72
>>>>>+	.word	omap3_aux_ctrl
>>>>> l2_inv_gp:
>>>>> 	/* Execute smi to invalidate L2 cache */
>>>>> 	mov r12, #0x1                         @ set up to invalide L2
>>>>> smi:    .word 0xE1600070		@ Call SMI monitor (smieq)
>>>>> 	/* Write to Aux control register to set some bits */
>>>>>-	mov	r0, #0x72
>>>>>+	ldr	r1, write_aux_control_params
>>>>>+	ldr	r0, phys_offset
>>>>>+	adds	r1, r1, r0
>>>>>+	ldr	r0, page_offset
>>>>>+	subs	r1, r1, r0
>>>>>+	ldr	r0, [r1, #4]
>>>>> 	mov	r12, #0x3
>>>>> 	.word 0xE1600070	@ Call SMI monitor (smieq)
>>>>> logic_l1_restore:
>>>>>@@ -420,6 +430,9 @@ usettbr0:
>>>>> save_context_wfi:
>>>>> 	/*b	save_context_wfi*/	@ enable to debug save code
>>>>> 	mov	r8, r0 /* Store SDRAM address in r8 */
>>>>>+	mrc	p15, 0, r4, c1, c0, 1	@ Read Auxiliary
>>>Control Register
>>>>>+	ldr	r5, write_aux_control_params
>>>>>+	str	r4, [r5, #4]
>>>
>>>There is a simpler way of doing this. Store the aux control
>>>value at the top of the sdram array where other parameters are
>>>stored. It would be something like following
>>>		mrc	p15, 0, r4, c1, c0, 1
>>>	      str	r4, [r8]
>>>		add r8, r8, #4
>>>In the restore, you can read it from this location and pass it
>>>as parameter for smi for gp device or pass this location as a
>>>parameter for emu device. In this way no need to define
>>>page_offset and phys_offset. I have a patch done for this for
>>>an internal code base. I can share it with you if interested.
>>>Else I can post it after rebasing. Do let me know.
>>
>>I can modify my patch according to this. However, do you know how much of the sdram array is
>>currently used? The size is 128 32bit words but I would not like to calculate manually how much of
>>that is used and whether I need to increase its size or not.

Top of my head, I do not remember. But I remember it was safe to add one more register to the save sequence. I had done this calculation once. Let me see if I can pull out the data.
>>
>>
>>>
>>>>>         /* Check what that target sleep state is:stored in r1*/
>>>>>         /* 1 - Only L1 and logic lost */
>>>>>         /* 2 - Only L2 lost */
>>>>>@@ -605,6 +618,10 @@ wait_dll_lock:
>>>>>         bne     wait_dll_lock
>>>>>         bx      lr
>>>>>
>>>>>+phys_offset:
>>>>>+	.word	PHYS_OFFSET
>>>>>+page_offset:
>>>>>+	.word	PAGE_OFFSET
>>>>> cm_idlest1_core:
>>>>> 	.word	CM_IDLEST1_CORE_V
>>>>> sdrc_dlla_status:
>>>>>--
>>>>>1.5.4.3
>>>>>
>>>>>--
>>>>>To unsubscribe from this list: send the line "unsubscribe
>>>linux-omap" in
>>>>>the body of a message to majordomo@vger.kernel.org
>>>>>More majordomo info at  http://vger.kernel.org/majordomo-info.html
>>>
>>>

Re: [PATCH 07/11] OMAP3: Fixed ARM aux ctrl register save/restore

[Kevin Hilman]

Tero Kristo <tero.kristo@nokia.com> writes:

> From: Tero Kristo <tero.kristo@nokia.com>
>
> Current value is stored on SDRAM and it is written back during wakeup.
> Previously a static value of 0x72 was written there.
>
> Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
> Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com>

Thanks, applying to PM branch, queuing for pm-fixes.

Kevin

> ---
>  arch/arm/mach-omap2/control.c   |    1 +
>  arch/arm/mach-omap2/sleep34xx.S |   23 ++++++++++++++++++++---
>  2 files changed, 21 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
> index 296f2c2..730fc53 100644
> --- a/arch/arm/mach-omap2/control.c
> +++ b/arch/arm/mach-omap2/control.c
> @@ -94,6 +94,7 @@ void *omap3_secure_ram_storage;
>   * during the restore path.
>   */
>  u32 omap3_arm_context[128];
> +u32 omap3_aux_ctrl[2] = { 0x1, 0x0 };
>  
>  struct omap3_control_regs {
>  	u32 sysconfig;
> diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
> index f4f5ebe..0b03bf9 100644
> --- a/arch/arm/mach-omap2/sleep34xx.S
> +++ b/arch/arm/mach-omap2/sleep34xx.S
> @@ -26,6 +26,7 @@
>   */
>  #include <linux/linkage.h>
>  #include <asm/assembler.h>
> +#include <asm/memory.h>
>  #include <mach/io.h>
>  #include <mach/control.h>
>  
> @@ -278,7 +279,11 @@ restore:
>  	mov	r1, #0		@ set task id for ROM code in r1
>  	mov	r2, #4		@ set some flags in r2, r6
>  	mov	r6, #0xff
> -	adr	r3, write_aux_control_params	@ r3 points to parameters
> +	ldr	r3, write_aux_control_params	@ r3 points to parameters
> +	ldr	r4, phys_offset
> +	adds	r3, r3, r4
> +	ldr	r4, page_offset
> +	subs	r3, r3, r4
>  	mcr	p15, 0, r0, c7, c10, 4	@ data write barrier
>  	mcr	p15, 0, r0, c7, c10, 5	@ data memory barrier
>  	.word	0xE1600071		@ call SMI monitor (smi #1)
> @@ -287,13 +292,18 @@ restore:
>  l2_inv_api_params:
>  	.word   0x1, 0x00
>  write_aux_control_params:
> -	.word   0x1, 0x72
> +	.word	omap3_aux_ctrl
>  l2_inv_gp:
>  	/* Execute smi to invalidate L2 cache */
>  	mov r12, #0x1                         @ set up to invalide L2
>  smi:    .word 0xE1600070		@ Call SMI monitor (smieq)
>  	/* Write to Aux control register to set some bits */
> -	mov	r0, #0x72
> +	ldr	r1, write_aux_control_params
> +	ldr	r0, phys_offset
> +	adds	r1, r1, r0
> +	ldr	r0, page_offset
> +	subs	r1, r1, r0
> +	ldr	r0, [r1, #4]
>  	mov	r12, #0x3
>  	.word 0xE1600070	@ Call SMI monitor (smieq)
>  logic_l1_restore:
> @@ -420,6 +430,9 @@ usettbr0:
>  save_context_wfi:
>  	/*b	save_context_wfi*/	@ enable to debug save code
>  	mov	r8, r0 /* Store SDRAM address in r8 */
> +	mrc	p15, 0, r4, c1, c0, 1	@ Read Auxiliary Control Register
> +	ldr	r5, write_aux_control_params
> +	str	r4, [r5, #4]
>          /* Check what that target sleep state is:stored in r1*/
>          /* 1 - Only L1 and logic lost */
>          /* 2 - Only L2 lost */
> @@ -605,6 +618,10 @@ wait_dll_lock:
>          bne     wait_dll_lock
>          bx      lr
>  
> +phys_offset:
> +	.word	PHYS_OFFSET
> +page_offset:
> +	.word	PAGE_OFFSET
>  cm_idlest1_core:
>  	.word	CM_IDLEST1_CORE_V
>  sdrc_dlla_status:
> -- 
> 1.5.4.3
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

RE: [PATCH 07/11] OMAP3: Fixed ARM aux ctrl register save/restore

[Tero.Kristo]

 

>-----Original Message-----
>From: linux-omap-owner@vger.kernel.org 
>[mailto:linux-omap-owner@vger.kernel.org] On Behalf Of ext Kevin Hilman
>Sent: 12 November, 2009 01:27
>To: Kristo Tero (Nokia-D/Tampere)
>Cc: linux-omap@vger.kernel.org
>Subject: Re: [PATCH 07/11] OMAP3: Fixed ARM aux ctrl register 
>save/restore
>
>Tero Kristo <tero.kristo@nokia.com> writes:
>
>> From: Tero Kristo <tero.kristo@nokia.com>
>>
>> Current value is stored on SDRAM and it is written back 
>during wakeup.
>> Previously a static value of 0x72 was written there.
>>
>> Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
>> Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com>
>
>Thanks, applying to PM branch, queuing for pm-fixes.

I have a slightly modified version available of this now, which stores the data inside arm_context. It is probably a bit nicer than this one. I'll send out the refreshed version of this patch and you can see which one you want to use.

>
>Kevin
>
>> ---
>>  arch/arm/mach-omap2/control.c   |    1 +
>>  arch/arm/mach-omap2/sleep34xx.S |   23 ++++++++++++++++++++---
>>  2 files changed, 21 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/arm/mach-omap2/control.c 
>b/arch/arm/mach-omap2/control.c
>> index 296f2c2..730fc53 100644
>> --- a/arch/arm/mach-omap2/control.c
>> +++ b/arch/arm/mach-omap2/control.c
>> @@ -94,6 +94,7 @@ void *omap3_secure_ram_storage;
>>   * during the restore path.
>>   */
>>  u32 omap3_arm_context[128];
>> +u32 omap3_aux_ctrl[2] = { 0x1, 0x0 };
>>  
>>  struct omap3_control_regs {
>>  	u32 sysconfig;
>> diff --git a/arch/arm/mach-omap2/sleep34xx.S 
>b/arch/arm/mach-omap2/sleep34xx.S
>> index f4f5ebe..0b03bf9 100644
>> --- a/arch/arm/mach-omap2/sleep34xx.S
>> +++ b/arch/arm/mach-omap2/sleep34xx.S
>> @@ -26,6 +26,7 @@
>>   */
>>  #include <linux/linkage.h>
>>  #include <asm/assembler.h>
>> +#include <asm/memory.h>
>>  #include <mach/io.h>
>>  #include <mach/control.h>
>>  
>> @@ -278,7 +279,11 @@ restore:
>>  	mov	r1, #0		@ set task id for ROM code in r1
>>  	mov	r2, #4		@ set some flags in r2, r6
>>  	mov	r6, #0xff
>> -	adr	r3, write_aux_control_params	@ r3 points to 
>parameters
>> +	ldr	r3, write_aux_control_params	@ r3 points to 
>parameters
>> +	ldr	r4, phys_offset
>> +	adds	r3, r3, r4
>> +	ldr	r4, page_offset
>> +	subs	r3, r3, r4
>>  	mcr	p15, 0, r0, c7, c10, 4	@ data write barrier
>>  	mcr	p15, 0, r0, c7, c10, 5	@ data memory barrier
>>  	.word	0xE1600071		@ call SMI monitor (smi #1)
>> @@ -287,13 +292,18 @@ restore:
>>  l2_inv_api_params:
>>  	.word   0x1, 0x00
>>  write_aux_control_params:
>> -	.word   0x1, 0x72
>> +	.word	omap3_aux_ctrl
>>  l2_inv_gp:
>>  	/* Execute smi to invalidate L2 cache */
>>  	mov r12, #0x1                         @ set up to invalide L2
>>  smi:    .word 0xE1600070		@ Call SMI monitor (smieq)
>>  	/* Write to Aux control register to set some bits */
>> -	mov	r0, #0x72
>> +	ldr	r1, write_aux_control_params
>> +	ldr	r0, phys_offset
>> +	adds	r1, r1, r0
>> +	ldr	r0, page_offset
>> +	subs	r1, r1, r0
>> +	ldr	r0, [r1, #4]
>>  	mov	r12, #0x3
>>  	.word 0xE1600070	@ Call SMI monitor (smieq)
>>  logic_l1_restore:
>> @@ -420,6 +430,9 @@ usettbr0:
>>  save_context_wfi:
>>  	/*b	save_context_wfi*/	@ enable to debug save code
>>  	mov	r8, r0 /* Store SDRAM address in r8 */
>> +	mrc	p15, 0, r4, c1, c0, 1	@ Read Auxiliary 
>Control Register
>> +	ldr	r5, write_aux_control_params
>> +	str	r4, [r5, #4]
>>          /* Check what that target sleep state is:stored in r1*/
>>          /* 1 - Only L1 and logic lost */
>>          /* 2 - Only L2 lost */
>> @@ -605,6 +618,10 @@ wait_dll_lock:
>>          bne     wait_dll_lock
>>          bx      lr
>>  
>> +phys_offset:
>> +	.word	PHYS_OFFSET
>> +page_offset:
>> +	.word	PAGE_OFFSET
>>  cm_idlest1_core:
>>  	.word	CM_IDLEST1_CORE_V
>>  sdrc_dlla_status:
>> -- 
>> 1.5.4.3
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe 
>linux-omap" in
>> the body of a message to majordomo@vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>--
>To unsubscribe from this list: send the line "unsubscribe 
>linux-omap" in
>the body of a message to majordomo@vger.kernel.org
>More majordomo info at  http://vger.kernel.org/majordomo-info.html
>

RE: [PATCH 07/11] OMAP3: Fixed ARM aux ctrl register save/restore

[Gopinath, Thara]

>>-----Original Message-----
>>From: linux-omap-owner@vger.kernel.org [mailto:linux-omap-owner@vger.kernel.org] On Behalf Of Kevin
>>Hilman
>>Sent: Thursday, November 12, 2009 4:57 AM
>>To: Tero Kristo
>>Cc: linux-omap@vger.kernel.org
>>Subject: Re: [PATCH 07/11] OMAP3: Fixed ARM aux ctrl register save/restore
>>
>>Tero Kristo <tero.kristo@nokia.com> writes:
>>
>>> From: Tero Kristo <tero.kristo@nokia.com>
>>>
>>> Current value is stored on SDRAM and it is written back during wakeup.
>>> Previously a static value of 0x72 was written there.
>>>
>>> Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
>>> Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com>
>>
>>Thanks, applying to PM branch, queuing for pm-fixes.

There were review comments for this patch to be redone in a different manner. Are they not going to be addressed ?
>>
>>Kevin
>>
>>> ---
>>>  arch/arm/mach-omap2/control.c   |    1 +
>>>  arch/arm/mach-omap2/sleep34xx.S |   23 ++++++++++++++++++++---
>>>  2 files changed, 21 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
>>> index 296f2c2..730fc53 100644
>>> --- a/arch/arm/mach-omap2/control.c
>>> +++ b/arch/arm/mach-omap2/control.c
>>> @@ -94,6 +94,7 @@ void *omap3_secure_ram_storage;
>>>   * during the restore path.
>>>   */
>>>  u32 omap3_arm_context[128];
>>> +u32 omap3_aux_ctrl[2] = { 0x1, 0x0 };
>>>
>>>  struct omap3_control_regs {
>>>  	u32 sysconfig;
>>> diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
>>> index f4f5ebe..0b03bf9 100644
>>> --- a/arch/arm/mach-omap2/sleep34xx.S
>>> +++ b/arch/arm/mach-omap2/sleep34xx.S
>>> @@ -26,6 +26,7 @@
>>>   */
>>>  #include <linux/linkage.h>
>>>  #include <asm/assembler.h>
>>> +#include <asm/memory.h>
>>>  #include <mach/io.h>
>>>  #include <mach/control.h>
>>>
>>> @@ -278,7 +279,11 @@ restore:
>>>  	mov	r1, #0		@ set task id for ROM code in r1
>>>  	mov	r2, #4		@ set some flags in r2, r6
>>>  	mov	r6, #0xff
>>> -	adr	r3, write_aux_control_params	@ r3 points to parameters
>>> +	ldr	r3, write_aux_control_params	@ r3 points to parameters
>>> +	ldr	r4, phys_offset
>>> +	adds	r3, r3, r4
>>> +	ldr	r4, page_offset
>>> +	subs	r3, r3, r4
>>>  	mcr	p15, 0, r0, c7, c10, 4	@ data write barrier
>>>  	mcr	p15, 0, r0, c7, c10, 5	@ data memory barrier
>>>  	.word	0xE1600071		@ call SMI monitor (smi #1)
>>> @@ -287,13 +292,18 @@ restore:
>>>  l2_inv_api_params:
>>>  	.word   0x1, 0x00
>>>  write_aux_control_params:
>>> -	.word   0x1, 0x72
>>> +	.word	omap3_aux_ctrl
>>>  l2_inv_gp:
>>>  	/* Execute smi to invalidate L2 cache */
>>>  	mov r12, #0x1                         @ set up to invalide L2
>>>  smi:    .word 0xE1600070		@ Call SMI monitor (smieq)
>>>  	/* Write to Aux control register to set some bits */
>>> -	mov	r0, #0x72
>>> +	ldr	r1, write_aux_control_params
>>> +	ldr	r0, phys_offset
>>> +	adds	r1, r1, r0
>>> +	ldr	r0, page_offset
>>> +	subs	r1, r1, r0
>>> +	ldr	r0, [r1, #4]
>>>  	mov	r12, #0x3
>>>  	.word 0xE1600070	@ Call SMI monitor (smieq)
>>>  logic_l1_restore:
>>> @@ -420,6 +430,9 @@ usettbr0:
>>>  save_context_wfi:
>>>  	/*b	save_context_wfi*/	@ enable to debug save code
>>>  	mov	r8, r0 /* Store SDRAM address in r8 */
>>> +	mrc	p15, 0, r4, c1, c0, 1	@ Read Auxiliary Control Register
>>> +	ldr	r5, write_aux_control_params
>>> +	str	r4, [r5, #4]
>>>          /* Check what that target sleep state is:stored in r1*/
>>>          /* 1 - Only L1 and logic lost */
>>>          /* 2 - Only L2 lost */
>>> @@ -605,6 +618,10 @@ wait_dll_lock:
>>>          bne     wait_dll_lock
>>>          bx      lr
>>>
>>> +phys_offset:
>>> +	.word	PHYS_OFFSET
>>> +page_offset:
>>> +	.word	PAGE_OFFSET
>>>  cm_idlest1_core:
>>>  	.word	CM_IDLEST1_CORE_V
>>>  sdrc_dlla_status:
>>> --
>>> 1.5.4.3
>>>
>>> --
>>> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
>>> the body of a message to majordomo@vger.kernel.org
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Re: [PATCH 07/11] OMAP3: Fixed ARM aux ctrl register save/restore

[Kevin Hilman]

"Gopinath, Thara" <thara@ti.com> writes:

[...]

>>>
>>>Thanks, applying to PM branch, queuing for pm-fixes.
>
> There were review comments for this patch to be redone in a
> different manner. Are they not going to be addressed ?

Thara, my apologies.  Somehow I missed your comments.

Tero has posted a new version of this patch.  Please add your comments
or Ack to that one.

Thanks,

Kevin

Re: [PATCH 06/11] OMAP3: PM: Disable interrupt controller AUTOIDLE before WFI

[Kevin Hilman]

Tero Kristo <tero.kristo@nokia.com> writes:

> From: Tero Kristo <tero.kristo@nokia.com>
>
> OMAP interrupt controller goes to unknown state when there is right
> combination of l3,l4 sleep/wake-up transitions, l4 autoidle in
> interrupt controller and some interrupt. When this happens, interrupts
> are not delivered to ARM anymore and ARM will remain in WFI (wait for
> interrupt) until interrupt controller is forced to wake-up
> (i.e. lauterbach).
>
> Signed-off-by: Tero Kristo <tero.kristo@nokia.com>

Thanks, applying to PM branch, queuing for pm-fixes.

Kevin

> ---
>  arch/arm/mach-omap2/irq.c              |   12 ++++++++++++
>  arch/arm/mach-omap2/pm34xx.c           |    2 ++
>  arch/arm/plat-omap/include/mach/irqs.h |    2 ++
>  3 files changed, 16 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
> index ee8c68a..9241b87 100644
> --- a/arch/arm/mach-omap2/irq.c
> +++ b/arch/arm/mach-omap2/irq.c
> @@ -272,4 +272,16 @@ void omap3_intc_suspend(void)
>  	/* A pending interrupt would prevent OMAP from entering suspend */
>  	omap_ack_irq(0);
>  }
> +
> +void omap3_intc_prepare_idle(void)
> +{
> +	/* Disable autoidle as it can stall interrupt controller */
> +	intc_bank_write_reg(0, &irq_banks[0], INTC_SYSCONFIG);
> +}
> +
> +void omap3_intc_resume_idle(void)
> +{
> +	/* Re-enable autoidle */
> +	intc_bank_write_reg(1, &irq_banks[0], INTC_SYSCONFIG);
> +}
>  #endif /* CONFIG_ARCH_OMAP3 */
> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
> index 492458e..fec9c38 100644
> --- a/arch/arm/mach-omap2/pm34xx.c
> +++ b/arch/arm/mach-omap2/pm34xx.c
> @@ -431,6 +431,7 @@ void omap_sram_idle(void)
>  		prm_set_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN);
>  		omap3_enable_io_chain();
>  	}
> +	omap3_intc_prepare_idle();
>  
>  	/*
>  	* On EMU/HS devices ROM code restores a SRDC value
> @@ -487,6 +488,7 @@ void omap_sram_idle(void)
>  						OMAP3430_GR_MOD,
>  						OMAP3_PRM_VOLTCTRL_OFFSET);
>  	}
> +	omap3_intc_resume_idle();
>  
>  	/*
>  	 * Enable smartreflex after WFI. Only needed if we entered
> diff --git a/arch/arm/plat-omap/include/mach/irqs.h b/arch/arm/plat-omap/include/mach/irqs.h
> index ff1faa8..b736c5d 100644
> --- a/arch/arm/plat-omap/include/mach/irqs.h
> +++ b/arch/arm/plat-omap/include/mach/irqs.h
> @@ -486,6 +486,8 @@ extern int omap_irq_pending(void);
>  void omap3_intc_save_context(void);
>  void omap3_intc_restore_context(void);
>  void omap3_intc_suspend(void);
> +void omap3_intc_prepare_idle(void);
> +void omap3_intc_resume_idle(void);
>  #endif
>  
>  #include <mach/hardware.h>
> -- 
> 1.5.4.3
>
> --
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Re: [PATCH 04/11] OMAP3: PM: Ack pending interrupts before entering suspend

[Kevin Hilman]

Tero Kristo <tero.kristo@nokia.com> writes:

> From: Tero Kristo <tero.kristo@nokia.com>
>
> Suspending drivers may still generate interrupts just before their suspend is
> completed. Any pending interrupts here will prevent sleep.
>
> Signed-off-by: Tero Kristo <tero.kristo@nokia.com>

Thanks, applying to PM branch, queuing for pm-fixes.

Kevin

> ---
>  arch/arm/mach-omap2/irq.c              |    6 ++++++
>  arch/arm/mach-omap2/pm34xx.c           |    2 +-
>  arch/arm/plat-omap/include/mach/irqs.h |    1 +
>  3 files changed, 8 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
> index aceedd8..ee8c68a 100644
> --- a/arch/arm/mach-omap2/irq.c
> +++ b/arch/arm/mach-omap2/irq.c
> @@ -266,4 +266,10 @@ void omap3_intc_restore_context(void)
>  	}
>  	/* MIRs are saved and restore with other PRCM registers */
>  }
> +
> +void omap3_intc_suspend(void)
> +{
> +	/* A pending interrupt would prevent OMAP from entering suspend */
> +	omap_ack_irq(0);
> +}
>  #endif /* CONFIG_ARCH_OMAP3 */
> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
> index 6782792..53544d3 100644
> --- a/arch/arm/mach-omap2/pm34xx.c
> +++ b/arch/arm/mach-omap2/pm34xx.c
> @@ -640,7 +640,7 @@ static int omap3_pm_suspend(void)
>  	}
>  
>  	omap_uart_prepare_suspend();
> -
> +	omap3_intc_suspend();
>  	regset_save_on_suspend = 1;
>  	omap_sram_idle();
>  	regset_save_on_suspend = 0;
> diff --git a/arch/arm/plat-omap/include/mach/irqs.h b/arch/arm/plat-omap/include/mach/irqs.h
> index 2473910..ff1faa8 100644
> --- a/arch/arm/plat-omap/include/mach/irqs.h
> +++ b/arch/arm/plat-omap/include/mach/irqs.h
> @@ -485,6 +485,7 @@ extern void omap_init_irq(void);
>  extern int omap_irq_pending(void);
>  void omap3_intc_save_context(void);
>  void omap3_intc_restore_context(void);
> +void omap3_intc_suspend(void);
>  #endif
>  
>  #include <mach/hardware.h>
> -- 
> 1.5.4.3
>
> --
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Re: [PATCH 03/11] OMAP2/3: DMTIMER: Clear pending interrupts when stopping a timer

[Kevin Hilman]

Tero Kristo <tero.kristo@nokia.com> writes:

> From: Tero Kristo <tero.kristo@nokia.com>
>
> OMAP GP timers keep running for a few cycles after they are stopped,
> which can cause the timer to expire and generate an interrupt. The pending
> interrupt will prevent e.g. OMAP from entering suspend, thus we ack it
> manually.
>
> Signed-off-by: Tero Kristo <tero.kristo@nokia.com>

Thanks, applying to PM branch, queueing in pm-fixes.

Kevin

> ---
>  arch/arm/plat-omap/dmtimer.c |   10 ++++++++++
>  1 files changed, 10 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
> index 830b072..09a623d 100644
> --- a/arch/arm/plat-omap/dmtimer.c
> +++ b/arch/arm/plat-omap/dmtimer.c
> @@ -551,6 +551,16 @@ void omap_dm_timer_stop(struct omap_dm_timer *timer)
>  	if (l & OMAP_TIMER_CTRL_ST) {
>  		l &= ~0x1;
>  		omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
> +		/* Readback to make sure write has completed */
> +		omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
> +		 /*
> +		  * Wait for functional clock period x 3.5 to make sure that
> +		  * timer is stopped
> +		  */
> +		udelay(3500000 / clk_get_rate(timer->fclk) + 1);
> +		/* Ack possibly pending interrupt */
> +		omap_dm_timer_write_reg(timer, OMAP_TIMER_STAT_REG,
> +				OMAP_TIMER_INT_OVERFLOW);
>  	}
>  }
>  EXPORT_SYMBOL_GPL(omap_dm_timer_stop);
> -- 
> 1.5.4.3
>
> --
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Re: [PATCH 02/11] OMAP3: Disable Smartreflex before pwrdm enters RET

[Kevin Hilman]

Tero Kristo <tero.kristo@nokia.com> writes:

> From: Tero Kristo <tero.kristo@nokia.com>
>
> Smartreflex for the corresponding powerdomain (MPU/CORE) must be disabled
> before the domain enters retention, otherwise the device may hang. This is
> caused by overlapping smartreflex / auto retention command on the voltage
> channel resulting in incorrect voltage.
>
> This fix has been confirmed from TI.
>
> Signed-off-by: Tero Kristo <tero.kristo@nokia.com>

Thanks, applying to PM branch, queuing in pm-fixes.

Kevin

> ---
>  arch/arm/mach-omap2/pm34xx.c |   22 +++++++++++++++++-----
>  1 files changed, 17 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
> index 8353764..6782792 100644
> --- a/arch/arm/mach-omap2/pm34xx.c
> +++ b/arch/arm/mach-omap2/pm34xx.c
> @@ -403,11 +403,17 @@ void omap_sram_idle(void)
>  	if (pwrdm_read_pwrst(cam_pwrdm) == PWRDM_POWER_ON)
>  		omap2_clkdm_deny_idle(mpu_pwrdm->pwrdm_clkdms[0]);
>  
> -	/* CORE */
> -	if (core_next_state < PWRDM_POWER_ON) {
> -		/* Disable smartreflex before entering WFI */
> +	/*
> +	 * Disable smartreflex before entering WFI.
> +	 * Only needed if we are going to enter retention or off.
> +	 */
> +	if (mpu_next_state <= PWRDM_POWER_RET)
>  		disable_smartreflex(SR1);
> +	if (core_next_state <= PWRDM_POWER_RET)
>  		disable_smartreflex(SR2);
> +
> +	/* CORE */
> +	if (core_next_state < PWRDM_POWER_ON) {
>  		omap_uart_prepare_idle(0);
>  		omap_uart_prepare_idle(1);
>  		if (core_next_state == PWRDM_POWER_OFF) {
> @@ -480,10 +486,16 @@ void omap_sram_idle(void)
>  			prm_clear_mod_reg_bits(OMAP3430_AUTO_RET,
>  						OMAP3430_GR_MOD,
>  						OMAP3_PRM_VOLTCTRL_OFFSET);
> -		/* Enable smartreflex after WFI */
> +	}
> +
> +	/*
> +	 * Enable smartreflex after WFI. Only needed if we entered
> +	 * retention or off
> +	 */
> +	if (mpu_next_state <= PWRDM_POWER_RET)
>  		enable_smartreflex(SR1);
> +	if (core_next_state <= PWRDM_POWER_RET)
>  		enable_smartreflex(SR2);
> -	}
>  
>  	/* PER */
>  	if (per_next_state < PWRDM_POWER_ON) {
> -- 
> 1.5.4.3
>
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Re: [PATCH 01/11] OMAP3: PM: Fixed padconf save done check

[Kevin Hilman]

Tero Kristo <tero.kristo@nokia.com> writes:

> From: Carlos Chinea <carlos.chinea@nokia.com>
>
> Previously the operator precedence dictated that the delay loop was exited
> immediately, potentially causing off-mode to be entered too soon.
>
> Signed-off-by: Carlos Chinea <carlos.chinea@nokia.com>
> Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com>

Looks good.  Applying to PM branch and will queue in my pm-fixes branch
for after 2.6.32 is released.

Kevin

> ---
>  arch/arm/mach-omap2/pm34xx.c |    4 ++--
>  1 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
> index 01260ec..8353764 100644
> --- a/arch/arm/mach-omap2/pm34xx.c
> +++ b/arch/arm/mach-omap2/pm34xx.c
> @@ -146,8 +146,8 @@ static void omap3_core_save_context(void)
>  	control_padconf_off |= START_PADCONF_SAVE;
>  	omap_ctrl_writel(control_padconf_off, OMAP343X_CONTROL_PADCONF_OFF);
>  	/* wait for the save to complete */
> -	while (!omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS)
> -			& PADCONF_SAVE_DONE)
> +	while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS)
> +			& PADCONF_SAVE_DONE))
>  		;
>  	/* Save the Interrupt controller context */
>  	omap3_intc_save_context();
> -- 
> 1.5.4.3
>
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