From: Kevin Hilman <khilman@ti.com>
To: Jean Pihet <jean.pihet@newoldbits.com>
Cc: Rajendra Nayak <rnayak@ti.com>,
Grazvydas Ignotas <notasas@gmail.com>,
linux-omap@vger.kernel.org, Jean Pihet <j-pihet@ti.com>
Subject: Re: [PATCH 3/3] ARM: OMAP3: PM: cpuidle: optimize the clkdm idle latency in C1 state
Date: Thu, 28 Jun 2012 13:03:44 -0500 [thread overview]
Message-ID: <87a9znpb3z.fsf@ti.com> (raw)
In-Reply-To: <CAORVsuXdszF5+m24tzQg=OXydsVpqFCHH0TxxKobfSvihpBhtQ@mail.gmail.com> (Jean Pihet's message of "Wed, 20 Jun 2012 13:34:06 +0200")
Jean Pihet <jean.pihet@newoldbits.com> writes:
> Hi Rajendra,
>
> On Wed, Jun 20, 2012 at 10:57 AM, Rajendra Nayak <rnayak@ti.com> wrote:
>> Jean,
>>
>>
>> On Wednesday 20 June 2012 02:22 PM, Rajendra Nayak wrote:
>>>
>>> Hi Jean,
>>>
>>> On Wednesday 20 June 2012 02:16 PM, Rajendra Nayak wrote:
>>>>
>>>> On Wednesday 20 June 2012 02:01 PM, Jean Pihet wrote:
>>>>>
>>>>> Hi Rajendra,
>>>>>
>>>>> On Wed, Jun 20, 2012 at 10:19 AM, Rajendra Nayak<rnayak@ti.com> wrote:
>>>>>>
>>>>>> Hi Jean,
>>>>>>
>>>>>>
>>>>>> On Friday 01 June 2012 08:41 PM, Jean Pihet wrote:
>>>>>>>
>>>>>>>
>>>>>>> For a power domain to idle all the clock domains in it must idle.
>>>>>>> This patch implements an optimization of the cpuidle code by
>>>>>>> denying and later allowing only the first registered clock domain
>>>>>>> of a power domain, and so optimizes the latency of the low power code.
>>>>>>
>>>>>>
>>>>>>
>>>>>> How much do we really save doing this? I understand what you are doing
>>>>>> by looking at the patch but the changelog seems very confusing.
>>>>>
>>>>> The gain is on the registers accesses and the internal PRCM state
>>>>> machine.
>>>>> If needed the changelog can be updated.
>>>>
>>>>
>>>> Can you explain a bit more on which register accesses are you talking
>>>> about? and some more on the PRCM state machine.
>>>
>>>
>>> never mind, I looked at the patch again and then the cpuidle code and
>>> figured what you are doing. Makes sense to me now :-)
> Ok!
>
>>
>>
>> How do you like this updated changelog, I just added one more line.
>>
>>
>> "
>> For a power domain to idle all the clock domains in it must idle.
>> Denying just *one* clkdm in a pwrdm from idling should have the
>> same effect as denying *all*.
>>
>> This patch implements an optimization of the cpuidle code by
>> denying and later allowing only the first registered clock domain
>> of a power domain, and so optimizes the latency of the low power code.
>> "
> That looks great!
>
> Kevin,
> Can you take this change still in your for_3.6/pm/performance branch?
>
Sorry, too late.
Kevin
next prev parent reply other threads:[~2012-06-28 18:03 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-06-01 15:11 [PATCH 0/3] ARM: OMAP3: PM: optimize cpuidle C1 state latency Jean Pihet
2012-06-01 15:11 ` [PATCH 1/3] ARM: OMAP3: PM: cpuidle: default to C1 in next_valid_state Jean Pihet
2012-06-01 15:11 ` [PATCH 2/3] ARM: OMAP3: PM: cpuidle: optimize the PER latency in C1 state Jean Pihet
2012-06-01 15:11 ` [PATCH 3/3] ARM: OMAP3: PM: cpuidle: optimize the clkdm idle " Jean Pihet
2012-06-20 8:19 ` Rajendra Nayak
2012-06-20 8:31 ` Jean Pihet
2012-06-20 8:46 ` Rajendra Nayak
2012-06-20 8:52 ` Rajendra Nayak
2012-06-20 8:57 ` Rajendra Nayak
2012-06-20 11:34 ` Jean Pihet
2012-06-28 18:03 ` Kevin Hilman [this message]
2012-06-01 16:26 ` [PATCH 0/3] ARM: OMAP3: PM: optimize cpuidle C1 state latency Kevin Hilman
2012-06-01 16:29 ` Jean Pihet
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