From mboxrd@z Thu Jan 1 00:00:00 1970 From: Kevin Hilman Subject: Re: [PATCH 1/2] OMAP3 PM: move omap3 sleep to ddr Date: Mon, 22 Nov 2010 08:03:59 -0800 Message-ID: <87bp5hz6og.fsf@deeprootsystems.com> References: <1290091906-32539-2-git-send-email-j-pihet@ti.com> <87tyjey6h3.fsf@deeprootsystems.com> <4CE55A88.6010300@ti.com> <20101118175215.GE9264@atomide.com> <20101118182752.GI9264@atomide.com> <92CDD168D1E81F4F9D3839DC45903FC6A5E5A085@dlee03.ent.ti.com> <20101122100716.GC26003@nokia.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Received: from mail-gy0-f174.google.com ([209.85.160.174]:35662 "EHLO mail-gy0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751992Ab0KVQEF (ORCPT ); Mon, 22 Nov 2010 11:04:05 -0500 Received: by gyb11 with SMTP id 11so1371976gyb.19 for ; Mon, 22 Nov 2010 08:04:05 -0800 (PST) In-Reply-To: <20101122100716.GC26003@nokia.com> (Peter De Schrijver's message of "Mon, 22 Nov 2010 12:07:16 +0200") Sender: linux-omap-owner@vger.kernel.org List-Id: linux-omap@vger.kernel.org To: Peter 'p2' De Schrijver Cc: "ext Derrick, David" , Jean Pihet , Tony Lindgren , "Menon, Nishanth" , "linux-omap@vger.kernel.org" , "Sripathy, Vishwanath" , "Pihet-XID, Jean" "Peter 'p2' De Schrijver" writes: > On Fri, Nov 19, 2010 at 05:14:15PM +0100, ext Derrick, David wrote: >> >-----Original Message----- >> >From: Jean Pihet [mailto:jean.pihet@newoldbits.com] >> >Sent: Friday, November 19, 2010 9:37 AM >> >> >On Thu, Nov 18, 2010 at 7:34 PM, Jean Pihet >wrote: >> >> On Thu, Nov 18, 2010 at 7:27 PM, Tony Lindgren wrote: >> >>> * Jean Pihet [101118 10:06]: >> >>>> On Thu, Nov 18, 2010 at 6:52 PM, Tony Lindgren wrote: >> >>>> >> >>>> About the DPLL lock: >> >>>> 1) wait_sdrc_ok is only called when back from the non-OFF modes, >> >>>> 2) I checked that when running wait_sdrc_ok the CORE is already out of >> >>>> idle and the DPLL is already locked. Note: l-o code has no support for >> >>>> the voltages OFF and the external clocks OFF. >> >>>> >> >>>> What to conclude from 1) and 2)? In my test setup ot looks like >> >>>> wait_sdrc_ok is of no use, but I agree this a premature conclusion. >> >>> >> >>> Yeah we should figure out in which cases wait_sdrc_ok is needed. >> >>> >> >>> BTW, are you sure you're hitting core idle in your tests? >> >> Yes it is OK from the console messages and the counters values in >> >> /debug/pm_debug/count. >> >> >> >> Let me confirm asap with the PRCM registers dump. >> >> >Here is what I experimented: >> >1) added a cache flush (v7_flush_kern_cache_all) just before WFI, in all >cases, >> >2) checked the real state entered in low power mode from the console >> >messages, the output of /debug/pm_debug/count and PRCM registers dump >> >> >2) is OK, which means that the RET and OFF modes are correctly hit. >> >> >Can I conclude from 1) that the wake-up code is not running from the >> >cache in RETention? >> >> [Derrick, David] >> >> To add some context to the wait_sdrc_ok function and why it was added: >> >> wait_sdrc_ok was added because the DLL takes 500 L3 clock cycles >> to lock. So you do not want to go back to DDR before DLL is locked. Also, we >> found some times DLL never locked so we introduced the DLL kick procedure to >> force it to lock. >> > > The root cause for the DLL not locking has been found though and a > workaround implemented. So it should work now :) Is the workaround for this reflected in Nishanth's series? Kevin > That still leaves the > 500 L3 cycle delay though. > > Cheers, > > Peter.