Re: [PATCH] OMAP3: Re-program also chipselect 1 when changing SDRAM timing

[Kevin Hilman <khilman@deeprootsystems.com>]

Tero Kristo <tero.kristo@nokia.com> writes:

> From: Tero Kristo <tero.kristo@nokia.com>
>
> Previously only chipselect 0 was controlled, which would result in the
> chipselect 1 running on too low rate during low core OPPs.
>
> Applies on top of PM branch.
>
> Signed-off-by: Tero Kristo <tero.kristo@nokia.com>

Hi Tero,

This does part of what Jean Pihet does in his recent patch[1] to add
support for 2 CSs.  Your version assumes the same parameters for both
SDRAM parts, and Jean has expanded that so board code can configure
different paramaters for the different CSes.

I have yet to fully review Jean's patch, but will probably take his
version so that two different SDRAM parts could be used.

Kevin


[1] See hist post from 26 May: [RFC][PATCH] OMAP3: add support for 2 SDRAM chip selects (was: Re: Beagleboard rev C memory timings & suspend/resume)

> ---
>  arch/arm/mach-omap2/sram34xx.S |   29 +++++++++++++++++++++++------
>  1 files changed, 23 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
> index f41f8d9..bcfe9eb 100644
> --- a/arch/arm/mach-omap2/sram34xx.S
> +++ b/arch/arm/mach-omap2/sram34xx.S
> @@ -187,15 +187,24 @@ wait_dll_unlock:
>  	bne	wait_dll_unlock
>  	bx	lr
>  configure_sdrc:
> -	ldr	r11, omap3_sdrc_rfr_ctrl
> +	ldr	r11, omap3_sdrc_rfr_ctrl_0
>  	str	r0, [r11]
> -	ldr	r11, omap3_sdrc_actim_ctrla
> +	ldr	r11, omap3_sdrc_rfr_ctrl_1
> +	str	r0, [r11]
> +	ldr	r11, omap3_sdrc_actim_ctrla_0
> +	str	r1, [r11]
> +	ldr	r11, omap3_sdrc_actim_ctrla_1
>  	str	r1, [r11]
> -	ldr	r11, omap3_sdrc_actim_ctrlb
> +	ldr	r11, omap3_sdrc_actim_ctrlb_0
> +	str	r2, [r11]
> +	ldr	r11, omap3_sdrc_actim_ctrlb_1
>  	str	r2, [r11]
>  	ldr	r11, omap3_sdrc_mr_0
>  	str	r6, [r11]
>  	ldr	r6, [r11]		@ posted-write barrier for SDRC
> +	ldr	r11, omap3_sdrc_mr_1
> +	str	r6, [r11]
> +	ldr	r6, [r11]		@ posted-write barrier for SDRC
>  	bx	lr
>  
>  omap3_sdrc_power:
> @@ -206,14 +215,22 @@ omap3_cm_idlest1_core:
>  	.word OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST)
>  omap3_cm_iclken1_core:
>  	.word OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1)
> -omap3_sdrc_rfr_ctrl:
> +omap3_sdrc_rfr_ctrl_0:
>  	.word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_0)
> -omap3_sdrc_actim_ctrla:
> +omap3_sdrc_rfr_ctrl_1:
> +	.word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_1)
> +omap3_sdrc_actim_ctrla_0:
>  	.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0)
> -omap3_sdrc_actim_ctrlb:
> +omap3_sdrc_actim_ctrla_1:
> +	.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_1)
> +omap3_sdrc_actim_ctrlb_0:
>  	.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0)
> +omap3_sdrc_actim_ctrlb_1:
> +	.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_1)
>  omap3_sdrc_mr_0:
>  	.word OMAP34XX_SDRC_REGADDR(SDRC_MR_0)
> +omap3_sdrc_mr_1:
> +	.word OMAP34XX_SDRC_REGADDR(SDRC_MR_1)
>  omap3_sdrc_dlla_status:
>  	.word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
>  omap3_sdrc_dlla_ctrl:
> -- 
> 1.5.4.3
>
> --
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