Re: [PATCH v1 1/3] PM / AVS: SmartReflex: disable errgen before vpbound disable

[Kevin Hilman <khilman@linaro.org>]

Andrii Tseglytskyi <andrii.tseglytskyi@ti.com> writes:

> On 05/29/2013 12:58 PM, Andrii Tseglytskyi wrote:
>> Hi Kevin,
>>
>> Thanks a lot for your comments.
>>
>> On 05/28/2013 09:45 PM, Kevin Hilman wrote:
>>> Andrii Tseglytskyi <andrii.tseglytskyi@ti.com> writes:
>>>
>>>> From: Nishanth Menon <nm@ti.com>
>>>>
>>>> vpboundsintr_en is available inside the IP block as an re-sycned
>>>> version and one which is not. Due to this, there is an 1 sysclk
>>>> cycle window where interruptz could be asserted low for 1 cycle.
>>>                               ^^^
>>>
>>> Is that the way the cool kidz are spelling interrupts these days?  ;)
>>
>> Oh! Shame on me. Thank you for catching this :)
>
> Shame on me again (((. Name "interruptz" is more less OK. This is the
> name of signal between Voltage Processor and SmartReflex.
> In documentation it is referenced as "SR_SInterruptz". Anyway commit
> message should be updated to make this more clear.

Ah, OK.  Makes sense now.  

Yes, the changlog should be more clear that this is referring to a
signal name, e.g. 

       ...there is an 1 sysclk cycle window where the SR_SInterruptz
       signal could be asserted low.

(also note that I think the  "for once cycle" that ends that phrase in
the original changelog is redundant, since it already says a "1 sysclk
cycle window".

Kevin