Re: [PATCHV2 REPOST 5/7] ARM: OMAP3PLUS PM: Add IO Daisychain support via hwmod mux

[Kevin Hilman <khilman@ti.com>]

Vishwanath BS <vishwanath.bs@ti.com> writes:

> IO Daisychain feature has to be triggered whenever there is a change in
> device's mux configuration (See section 3.9.4 in OMAP4 Public TRM vP).
>
> Now devices can idle independent of the powerdomain, there can be a window where device
> is idled and corresponding powerdomain can be ON/INACTIVE state. In such situations,
> since both module wake up is enabled at padlevel as well as io daisychain sequence is
> triggered, there will be 2 PRCM interrupts (Module async wake up via swakeup and IO Pad
> interrupt). But as PRCM Interrupt handler clears the Module Padlevel WKST bit in the
> first interrupt, module specific interrupt handler will not triggered for the second time
>
> Also look at detailed explanation given by Rajendra at
> http://www.spinics.net/lists/linux-serial/msg04480.html
>
> Signed-off-by: Vishwanath BS <vishwanath.bs@ti.com>
> Tested-by: Govindraj.R <govindraj.raja@ti.com>
> ---
>  arch/arm/mach-omap2/omap_hwmod.c |    9 +++++++--
>  arch/arm/mach-omap2/pm.c         |   11 +++++++++++
>  arch/arm/mach-omap2/pm.h         |    1 +
>  3 files changed, 19 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
> index f7f22da..1a72463 100644
> --- a/arch/arm/mach-omap2/omap_hwmod.c
> +++ b/arch/arm/mach-omap2/omap_hwmod.c
> @@ -151,6 +151,7 @@
>  #include "prm44xx.h"
>  #include "prminst44xx.h"
>  #include "mux.h"
> +#include "pm.h"
>  
>  /* Maximum microseconds to wait for OMAP module to softreset */
>  #define MAX_MODULE_SOFTRESET_WAIT	10000
> @@ -1462,8 +1463,10 @@ static int _enable(struct omap_hwmod *oh)
>  	/* Mux pins for device runtime if populated */
>  	if (oh->mux && (!oh->mux->enabled ||
>  			((oh->_state == _HWMOD_STATE_IDLE) &&
> -			 oh->mux->pads_dynamic)))
> +			 oh->mux->pads_dynamic))) {
>  		omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED);
> +		omap_trigger_wuclk_ctrl();
> +	}

Why is the IO chain enabled during hwmod _enable()?

>  	_add_initiator_dep(oh, mpu_oh);
>  
> @@ -1553,8 +1556,10 @@ static int _idle(struct omap_hwmod *oh)
>  		clkdm_hwmod_disable(oh->clkdm, oh);
>  
>  	/* Mux pins for device idle if populated */
> -	if (oh->mux && oh->mux->pads_dynamic)
> +	if (oh->mux && oh->mux->pads_dynamic) {
>  		omap_hwmod_mux(oh->mux, _HWMOD_STATE_IDLE);
> +		omap_trigger_wuclk_ctrl();
> +	}

Since this is now happening in idle for every hwmod with dynamic pads,
the underlying function should probably cache the current value so it
doesn't have to do a multiple PRCM register accesses it's only
going to set a bit that's already set.

Kevin

>  	oh->_state = _HWMOD_STATE_IDLE;
>  
> diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
> index 1881fe9..4d8ca28 100644
> --- a/arch/arm/mach-omap2/pm.c
> +++ b/arch/arm/mach-omap2/pm.c
> @@ -25,6 +25,8 @@
>  #include "clockdomain.h"
>  #include "pm.h"
>  #include "twl-common.h"
> +#include "prm2xxx_3xxx.h"
> +#include "prm44xx.h"
>  
>  static struct omap_device_pm_latency *pm_lats;
>  
> @@ -64,6 +66,15 @@ static void omap2_init_processor_devices(void)
>  	}
>  }
>  
> +void omap_trigger_wuclk_ctrl(void)
> +{
> +	if (cpu_is_omap34xx())
> +		omap3_trigger_wuclk_ctrl();
> +
> +	if (cpu_is_omap44xx())
> +		omap4_trigger_wuclk_ctrl();
> +}
> +
>  /* Types of sleep_switch used in omap_set_pwrdm_state */
>  #define FORCEWAKEUP_SWITCH	0
>  #define LOWPOWERSTATE_SWITCH	1
> diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
> index 4e166ad..05c2da2 100644
> --- a/arch/arm/mach-omap2/pm.h
> +++ b/arch/arm/mach-omap2/pm.h
> @@ -21,6 +21,7 @@ extern void omap_sram_idle(void);
>  extern int omap3_can_sleep(void);
>  extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state);
>  extern int omap3_idle_init(void);
> +void omap_trigger_wuclk_ctrl(void);
>  
>  #if defined(CONFIG_PM_OPP)
>  extern int omap3_opp_init(void);