[PATCH 0/2] OMAP3: Cpuidle fixes

[PATCH 0/2] OMAP3: Cpuidle fixes

[Tero Kristo]

From: Tero Kristo <tero.kristo@nokia.com>

Following patches apply on top of PM branch. They implement a couple of
small fixes for cpuidle. Timer resolution patch probably does not change
anything until kernel cpuidle is fixed to support longer timers (there are
some pending patches for this.)

-Tero

[PATCH 1/2] OMAP3: PM: Check BM for C2 state

[Tero Kristo]

From: De-Schrijver Peter <Peter.De-Schrijver@nokia.com>

C2 can't be entered while we have bus activity.

Signed-off-by: Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com>
---
 arch/arm/mach-omap2/cpuidle34xx.c |    7 ++++---
 1 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
index c44a942..a0d9f56 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -38,7 +38,7 @@
 
 #define OMAP3_MAX_STATES 7
 #define OMAP3_STATE_C1 0 /* C1 - MPU WFI + Core active */
-#define OMAP3_STATE_C2 1 /* C2 - MPU WFI + Core inactive */
+#define OMAP3_STATE_C2 1 /* C2 - MPU inactive + Core inactive */
 #define OMAP3_STATE_C3 2 /* C3 - MPU CSWR + Core inactive */
 #define OMAP3_STATE_C4 3 /* C4 - MPU OFF + Core iactive */
 #define OMAP3_STATE_C5 4 /* C5 - MPU RET + Core RET */
@@ -169,7 +169,7 @@ DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
  *
  * Below is the desciption of each C state.
  * 	C1 . MPU WFI + Core active
- *	C2 . MPU WFI + Core inactive
+ *	C2 . MPU inactive + Core inactive
  *	C3 . MPU CSWR + Core inactive
  *	C4 . MPU OFF + Core inactive
  *	C5 . MPU CSWR + Core CSWR
@@ -196,7 +196,8 @@ void omap_init_power_states(void)
 	omap3_power_states[OMAP3_STATE_C2].threshold = 30;
 	omap3_power_states[OMAP3_STATE_C2].mpu_state = PWRDM_POWER_ON;
 	omap3_power_states[OMAP3_STATE_C2].core_state = PWRDM_POWER_ON;
-	omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID;
+	omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID |
+				CPUIDLE_FLAG_CHECK_BM;
 
 	/* C3 . MPU CSWR + Core inactive */
 	omap3_power_states[OMAP3_STATE_C3].valid = 1;
-- 
1.5.4.3

[PATCH 2/2] OMAP3: CPUidle: Fixed timer resolution

[Tero Kristo]

From: Tero Kristo <tero.kristo@nokia.com>

Previously used u32 as temporary data storage that wraps around at 4.294s.

Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
---
 arch/arm/mach-omap2/cpuidle34xx.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
index a0d9f56..0ac3b63 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -137,7 +137,7 @@ return_sleep_time:
 	local_irq_enable();
 	local_fiq_enable();
 
-	return (u32)timespec_to_ns(&ts_idle)/1000;
+	return ts_idle.tv_nsec / NSEC_PER_USEC + ts_idle.tv_sec * USEC_PER_SEC;
 }
 
 /**
-- 
1.5.4.3

Re: [PATCH 2/2] OMAP3: CPUidle: Fixed timer resolution

[Kevin Hilman]

Tero Kristo <tero.kristo@nokia.com> writes:

> From: Tero Kristo <tero.kristo@nokia.com>
>
> Previously used u32 as temporary data storage that wraps around at 4.294s.
>
> Signed-off-by: Tero Kristo <tero.kristo@nokia.com>

Thanks, applying to PM branch, queing for pm-fixes.

Kevin

> ---
>  arch/arm/mach-omap2/cpuidle34xx.c |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
> index a0d9f56..0ac3b63 100644
> --- a/arch/arm/mach-omap2/cpuidle34xx.c
> +++ b/arch/arm/mach-omap2/cpuidle34xx.c
> @@ -137,7 +137,7 @@ return_sleep_time:
>  	local_irq_enable();
>  	local_fiq_enable();
>  
> -	return (u32)timespec_to_ns(&ts_idle)/1000;
> +	return ts_idle.tv_nsec / NSEC_PER_USEC + ts_idle.tv_sec * USEC_PER_SEC;
>  }
>  
>  /**
> -- 
> 1.5.4.3
>
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Re: [PATCH 1/2] OMAP3: PM: Check BM for C2 state

[Kevin Hilman]

Tero Kristo <tero.kristo@nokia.com> writes:

> From: De-Schrijver Peter <Peter.De-Schrijver@nokia.com>
>
> C2 can't be entered while we have bus activity.

Why?

For the benefit of git history, can you add a more verbose changelog
please describing why?

Otherwise, patch looks fine.

Thanks,

Kevin

> Signed-off-by: Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com>
> ---
>  arch/arm/mach-omap2/cpuidle34xx.c |    7 ++++---
>  1 files changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
> index c44a942..a0d9f56 100644
> --- a/arch/arm/mach-omap2/cpuidle34xx.c
> +++ b/arch/arm/mach-omap2/cpuidle34xx.c
> @@ -38,7 +38,7 @@
>  
>  #define OMAP3_MAX_STATES 7
>  #define OMAP3_STATE_C1 0 /* C1 - MPU WFI + Core active */
> -#define OMAP3_STATE_C2 1 /* C2 - MPU WFI + Core inactive */
> +#define OMAP3_STATE_C2 1 /* C2 - MPU inactive + Core inactive */
>  #define OMAP3_STATE_C3 2 /* C3 - MPU CSWR + Core inactive */
>  #define OMAP3_STATE_C4 3 /* C4 - MPU OFF + Core iactive */
>  #define OMAP3_STATE_C5 4 /* C5 - MPU RET + Core RET */
> @@ -169,7 +169,7 @@ DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
>   *
>   * Below is the desciption of each C state.
>   * 	C1 . MPU WFI + Core active
> - *	C2 . MPU WFI + Core inactive
> + *	C2 . MPU inactive + Core inactive
>   *	C3 . MPU CSWR + Core inactive
>   *	C4 . MPU OFF + Core inactive
>   *	C5 . MPU CSWR + Core CSWR
> @@ -196,7 +196,8 @@ void omap_init_power_states(void)
>  	omap3_power_states[OMAP3_STATE_C2].threshold = 30;
>  	omap3_power_states[OMAP3_STATE_C2].mpu_state = PWRDM_POWER_ON;
>  	omap3_power_states[OMAP3_STATE_C2].core_state = PWRDM_POWER_ON;
> -	omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID;
> +	omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID |
> +				CPUIDLE_FLAG_CHECK_BM;
>  
>  	/* C3 . MPU CSWR + Core inactive */
>  	omap3_power_states[OMAP3_STATE_C3].valid = 1;
> -- 
> 1.5.4.3
>
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