From mboxrd@z Thu Jan 1 00:00:00 1970 From: Kevin Hilman Subject: Re: [PATCH V2 4/4] ARM: OMAP3+: PM: VP: ensure VP is idle before disable Date: Fri, 01 Jun 2012 14:03:54 -0700 Message-ID: <87sjeesq11.fsf@ti.com> References: <1338514899-3560-1-git-send-email-nm@ti.com> <1338514899-3560-5-git-send-email-nm@ti.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Received: from na3sys009aog129.obsmtp.com ([74.125.149.142]:42589 "EHLO na3sys009aog129.obsmtp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1759439Ab2FAVEG (ORCPT ); Fri, 1 Jun 2012 17:04:06 -0400 Received: by pbbro12 with SMTP id ro12so3938823pbb.18 for ; Fri, 01 Jun 2012 14:03:53 -0700 (PDT) In-Reply-To: <1338514899-3560-5-git-send-email-nm@ti.com> (Nishanth Menon's message of "Thu, 31 May 2012 20:41:39 -0500") Sender: linux-omap-owner@vger.kernel.org List-Id: linux-omap@vger.kernel.org To: Nishanth Menon Cc: linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Wenbiao Wang , Tony Lindgren Nishanth Menon writes: > From: Wenbiao Wang > > Voltage Processor state machine transition to disable need to > occur from IDLE state. When we transition OPP in a functioning > system, the call sequence for an OPP transition is as follows: > omap_sr_disable > -> sr class 3 disable > -> vp disable > -> sr disable > forceupdate to voltage/frequency scale depending on which OPP > we are transitioning to. > > If we hit a critical timing window where SR had commanded VP > for a voltage transition and VP is in the middle of operating > on that command, it needs to go through a few states before > going to update state(where it actually sends the command to > VC). Initial view of h/w owners is that the state disable of VP > is expected to be sampled for the next transition. > > Instead, to be on a safer side, we ensure that the valid states > of the VP state machine is diligently followed by software. This > can be done by waiting for VP to be in idle prior to disabling > VP. Existing prints have been updated to ensure context is > available on error messages. > > As part of this change, increase timeout for VP idle check to > improbable 500uSec to be certain that system is indeed unable > to continue before crashing out with error(worst case expectancy > remains the same 3-100uSec depending on when we caught VP). > > Cc: Tony Lindgren > Cc: Kevin Hilman > > [nm@ti.com: port from android] and you also convert to use new _vp_wait_for_idle() > Signed-off-by: Nishanth Menon > Signed-off-by: Wenbiao Wang > --- > arch/arm/mach-omap2/vp.c | 4 ++++ > arch/arm/mach-omap2/vp.h | 5 +++-- > 2 files changed, 7 insertions(+), 2 deletions(-) > > diff --git a/arch/arm/mach-omap2/vp.c b/arch/arm/mach-omap2/vp.c > index 2a8a085..9a72deb 100644 > --- a/arch/arm/mach-omap2/vp.c > +++ b/arch/arm/mach-omap2/vp.c > @@ -308,6 +308,10 @@ void omap_vp_disable(struct voltagedomain *voltdm) > return; > } > > + if (_vp_wait_for_idle(voltdm, vp)) { > + pr_warn_ratelimited("%s: vdd_%s timedout!Ignore and try\n", s/timedout/timed out/ no space after '!', also I don't get the "Ignore and try" part Kevin > + __func__, voltdm->name); > + } > /* Disable VP */ > vpconfig = voltdm->read(vp->vpconfig); > vpconfig &= ~vp->common->vpconfig_vpenable; > diff --git a/arch/arm/mach-omap2/vp.h b/arch/arm/mach-omap2/vp.h > index 4655b39..4b4eeb6 100644 > --- a/arch/arm/mach-omap2/vp.h > +++ b/arch/arm/mach-omap2/vp.h > @@ -33,9 +33,10 @@ struct voltagedomain; > /* > * Time out for Voltage processor in micro seconds. Typical latency is < 2uS, > * but worst case latencies could be around 3-200uS depending on where we > - * interrupted VP's operation. > + * interrupted VP's operation. Use an improbable timeout value to be > + * sure that timeout events are beyond doubt. > */ > -#define VP_IDLE_TIMEOUT 200 > +#define VP_IDLE_TIMEOUT 500 > #define VP_TRANXDONE_TIMEOUT 300 > > /**