[PATCH] Load triton2 scripts.

[PATCH] Load triton2 scripts.

[Kalle Jokiniemi]

From: ext Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com>

This patch loads the triton2 (twl4030) with scripts that will cut off VDD1
and VDD2 voltages when SYS_OFF_MODE signal is set.

Signed-off-by: Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com>
Signed-off-by: Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com>
---
 drivers/i2c/chips/Makefile        |    2 +-
 drivers/i2c/chips/twl4030-power.c |  337 +++++++++++++++++++++++++++++++++++++
 2 files changed, 338 insertions(+), 1 deletions(-)
 create mode 100644 drivers/i2c/chips/twl4030-power.c

diff --git a/drivers/i2c/chips/Makefile b/drivers/i2c/chips/Makefile
index 9e245b1..ad5f5db 100644
--- a/drivers/i2c/chips/Makefile
+++ b/drivers/i2c/chips/Makefile
@@ -24,7 +24,7 @@ obj-$(CONFIG_GPIOEXPANDER_OMAP)	+= gpio_expander_omap.o
 obj-$(CONFIG_MENELAUS)		+= menelaus.o
 obj-$(CONFIG_SENSORS_TSL2550)	+= tsl2550.o
 obj-$(CONFIG_SENSORS_TSL2563)	+= tsl2563.o
-obj-$(CONFIG_TWL4030_CORE)	+= twl4030-core.o twl4030-pwrirq.o
+obj-$(CONFIG_TWL4030_CORE)	+= twl4030-core.o twl4030-pwrirq.o twl4030-power.o
 obj-$(CONFIG_TWL4030_GPIO)	+= twl4030-gpio.o
 obj-$(CONFIG_TWL4030_USB)	+= twl4030-usb.o
 obj-$(CONFIG_TWL4030_POWEROFF)	+= twl4030-poweroff.o
diff --git a/drivers/i2c/chips/twl4030-power.c b/drivers/i2c/chips/twl4030-power.c
new file mode 100644
index 0000000..195c3c4
--- /dev/null
+++ b/drivers/i2c/chips/twl4030-power.c
@@ -0,0 +1,337 @@
+/*
+ * linux/drivers/i2c/chips/twl4030-power.c
+ *
+ * Handle TWL4030 Power initialization
+ *
+ * Copyright (C) 2008 Nokia Corporation
+ * Copyright (C) 2006 Texas Instruments, Inc
+ *
+ * Written by 	Kalle Jokiniemi
+ *		Peter De Schrijver <peter.de-schrijver@nokia.com>
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License. See the file "COPYING" in the main directory of this
+ * archive for more details.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/module.h>
+#include <linux/pm.h>
+#include <linux/i2c/twl4030.h>
+
+#define PWR_P1_SW_EVENTS	0x10
+#define PWR_DEVOFF	(1<<0)
+
+#define PHY_TO_OFF_PM_MASTER(p)		(p - 0x36)
+#define PHY_TO_OFF_PM_RECIEVER(p)	(p - 0x5b)
+
+/* resource - hfclk */
+#define R_HFCLKOUT_DEV_GRP 	PHY_TO_OFF_PM_RECIEVER(0xe6)
+
+/* PM events */
+#define R_P1_SW_EVENTS		PHY_TO_OFF_PM_MASTER(0x46)
+#define R_P2_SW_EVENTS		PHY_TO_OFF_PM_MASTER(0x47)
+#define R_P3_SW_EVENTS		PHY_TO_OFF_PM_MASTER(0x48)
+#define R_CFG_P1_TRANSITION	PHY_TO_OFF_PM_MASTER(0x36)
+#define R_CFG_P2_TRANSITION	PHY_TO_OFF_PM_MASTER(0x37)
+#define R_CFG_P3_TRANSITION	PHY_TO_OFF_PM_MASTER(0x38)
+
+#define LVL_WAKEUP	0x08
+
+#define ENABLE_WARMRESET (1<<4)
+
+/* sequence script */
+
+#define END_OF_SCRIPT		0x3f
+
+#define R_SEQ_ADD_A2S		PHY_TO_OFF_PM_MASTER(0x55)
+#define R_SEQ_ADD_SA12		PHY_TO_OFF_PM_MASTER(0x56)
+#define	R_SEQ_ADD_S2A3		PHY_TO_OFF_PM_MASTER(0x57)
+#define	R_SEQ_ADD_WARM		PHY_TO_OFF_PM_MASTER(0x58)
+#define R_MEMORY_ADDRESS	PHY_TO_OFF_PM_MASTER(0x59)
+#define R_MEMORY_DATA		PHY_TO_OFF_PM_MASTER(0x5a)
+
+/* Power bus message definitions */
+
+#define DEV_GRP_NULL		0x0
+#define DEV_GRP_P1		0x1
+#define DEV_GRP_P2		0x2
+#define DEV_GRP_P3		0x4
+
+#define RES_GRP_RES		0x0
+#define RES_GRP_PP		0x1
+#define RES_GRP_RC		0x2
+#define RES_GRP_PP_RC		0x3
+#define RES_GRP_PR		0x4
+#define RES_GRP_PP_PR		0x5
+#define RES_GRP_RC_PR		0x6
+#define RES_GRP_ALL		0x7
+
+#define RES_TYPE2_R0		0x0
+
+#define RES_TYPE_ALL		0x7
+
+#define RES_STATE_WRST		0xF
+#define RES_STATE_ACTIVE	0xE
+#define RES_STATE_SLEEP		0x8
+#define RES_STATE_OFF		0x0
+
+/*
+*	Power Bus Message Format
+*
+*	Broadcast Message (16 Bits)
+*	DEV_GRP[15:13] MT[12]  RES_GRP[11:9]  RES_TYPE2[8:7] RES_TYPE[6:4]
+*	RES_STATE[3:0]
+*
+*	Singular Message (16 Bits)
+*	DEV_GRP[15:13] MT[12]  RES_ID[11:4]  RES_STATE[3:0]
+*
+*/
+
+#define MSG_BROADCAST(devgrp, grp, type, type2, state) \
+	(devgrp << 13 | 1 << 12 | grp << 9 | type2 << 7 | type << 4 | state)
+
+#define MSG_SINGULAR(devgrp, id, state) \
+	(devgrp << 13 | 0 << 12 | id << 4 | state)
+
+#define R_PROTECT_KEY		0x0E
+#define KEY_1			0xC0
+#define KEY_2			0x0C
+
+struct triton_ins {
+	u16 pmb_message;
+	u8 delay;
+};
+
+
+#define CONFIG_DISABLE_HFCLK	1
+
+#if defined(CONFIG_MACH_OMAP_3430SDP) || defined(CONFIG_MACH_OMAP_3430LABRADOR)
+
+struct triton_ins sleep_on_seq[] __initdata = {
+	{MSG_SINGULAR(DEV_GRP_P1, 0xf, RES_STATE_OFF), 4},
+	{MSG_SINGULAR(DEV_GRP_P1, 0x10, RES_STATE_OFF), 2},
+#ifdef CONFIG_DISABLE_HFCLK
+	{MSG_SINGULAR(DEV_GRP_P1, 0x7, RES_STATE_OFF), 3},
+	{MSG_SINGULAR(DEV_GRP_P1, 0x19, RES_STATE_OFF), 3},
+#endif /* #ifdef CONFIG_DISABLE_HFCLK */
+};
+
+struct triton_ins sleep_off_seq[] __initdata = {
+#ifndef CONFIG_DISABLE_HFCLK
+	{MSG_SINGULAR(DEV_GRP_P1, 0xf, RES_STATE_ACTIVE), 4},
+	{MSG_SINGULAR(DEV_GRP_P1, 0x10, RES_STATE_ACTIVE), 2},
+#else
+	{MSG_SINGULAR(DEV_GRP_P1, 0x7, RES_STATE_ACTIVE), 0x30},
+	{MSG_SINGULAR(DEV_GRP_P1, 0xf, RES_STATE_ACTIVE), 0x30},
+	{MSG_SINGULAR(DEV_GRP_P1, 0x10, RES_STATE_ACTIVE), 0x37},
+	{MSG_SINGULAR(DEV_GRP_P1, 0x19, RES_STATE_ACTIVE), 3},
+#endif /* #ifndef CONFIG_DISABLE_HFCLK */
+};
+
+struct triton_ins t2_wrst_seq[] __initdata = {
+	{MSG_SINGULAR(DEV_GRP_NULL, 0x1b, RES_STATE_OFF), 2},
+	{MSG_SINGULAR(DEV_GRP_P1, 0xf, RES_STATE_WRST), 15},
+	{MSG_SINGULAR(DEV_GRP_P1, 0x10, RES_STATE_WRST), 15},
+	{MSG_SINGULAR(DEV_GRP_P1, 0x7, RES_STATE_WRST), 0x60},
+	{MSG_SINGULAR(DEV_GRP_P1, 0x19, RES_STATE_ACTIVE), 2},
+	{MSG_SINGULAR(DEV_GRP_NULL, 0x1b, RES_STATE_ACTIVE), 2},
+};
+#else
+struct triton_ins sleep_on_seq[] __initdata = {
+	{MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_RC, RES_TYPE_ALL, RES_TYPE2_R0,
+			RES_STATE_SLEEP), 4},
+	{MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, RES_TYPE_ALL, RES_TYPE_R7,
+			RES_STATE_SLEEP), 4},
+};
+
+struct triton_ins sleep_off_seq[] __initdata = {
+	{MSG_SINGULAR(DEV_GRP_NULL, 0x17, RES_STATE_ACTIVE), 0x30},
+	{MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_PP_PR, RES_TYPE_ALL, RES_TYPE2_R0,
+			RES_STATE_ACTIVE), 0x37},
+	{MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, RES_TYPE_ALL, RES_TYPE2_R0,
+			RES_STATE_ACTIVE), 0x2},
+};
+#endif
+
+static int __init twl4030_write_script_byte(u8 address, u8 byte)
+{
+	int err;
+
+	err = twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, address,
+					R_MEMORY_ADDRESS);
+	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, byte,
+					R_MEMORY_DATA);
+
+	return err;
+}
+
+static int __init twl4030_write_script_ins(u8 address, u16 pmb_message,
+						u8 delay, u8 next)
+{
+	int err = 0;
+
+	address *= 4;
+	err |= twl4030_write_script_byte(address++, pmb_message >> 8);
+	err |= twl4030_write_script_byte(address++, pmb_message & 0xff);
+	err |= twl4030_write_script_byte(address++, delay);
+	err |= twl4030_write_script_byte(address++, next);
+
+	return err;
+}
+
+static int __init twl4030_write_script(u8 address, struct triton_ins *script,
+					int len)
+{
+	int err = 0;
+
+	for (; len; len--, address++, script++) {
+		if (len == 1)
+			err |= twl4030_write_script_ins(address,
+							script->pmb_message,
+							script->delay,
+							END_OF_SCRIPT);
+		else
+			err |= twl4030_write_script_ins(address,
+							script->pmb_message,
+							script->delay,
+							address + 1);
+	}
+
+	return err;
+}
+
+static int __init config_sleep_wake_sequence(void)
+{
+	int err = 0;
+	u8 data;
+
+	/*
+	 * CLKREQ is pulled high on the 2430SDP, therefore, we need to take
+	 * it out of the HFCLKOUT DEV_GRP for P1 else HFCLKOUT can't be stopped.
+	 */
+
+	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
+				  0x20, R_HFCLKOUT_DEV_GRP);
+
+	/* Set ACTIVE to SLEEP SEQ address in T2 memory*/
+	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0x2B,
+				  R_SEQ_ADD_A2S);
+
+	/* Set SLEEP to ACTIVE SEQ address for P1 and P2 */
+	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0x2F,
+				  R_SEQ_ADD_SA12);
+
+	/* Set SLEEP to ACTIVE SEQ address for P3 */
+	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0x2F,
+				  R_SEQ_ADD_S2A3);
+
+	/* Install Active->Sleep (A2S) sequence */
+	err |= twl4030_write_script(0x2B, sleep_on_seq,
+					ARRAY_SIZE(sleep_on_seq));
+
+	/* Install Sleep->Active (S2A) sequence */
+	err |= twl4030_write_script(0x2F, sleep_off_seq,
+					ARRAY_SIZE(sleep_off_seq));
+
+#if defined(CONFIG_MACH_OMAP_3430SDP) || defined(CONFIG_MACH_OMAP_3430LABRADOR)
+	/* Disabling AC charger effect on sleep-active transitions */
+	err |= twl4030_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &data,
+					R_CFG_P1_TRANSITION);
+	data &= 0x0;
+	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, data ,
+					R_CFG_P1_TRANSITION);
+#endif
+	/* P1/P2/P3 LVL_WAKEUP should be on LEVEL */
+	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, LVL_WAKEUP,
+					R_P1_SW_EVENTS);
+	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, LVL_WAKEUP,
+					R_P2_SW_EVENTS);
+	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, LVL_WAKEUP,
+				R_P3_SW_EVENTS);
+
+	if (err)
+		printk(KERN_ERR "TWL4030 sleep-wake sequence config error\n");
+
+	return err;
+}
+
+
+/* Programming the WARMRESET Sequence on TRITON */
+static int __init config_warmreset_sequence(void)
+{
+
+	int e = 0;
+	u8 rd_data;
+
+	if (!ARRAY_SIZE(t2_wrst_seq))
+		return 0;
+
+	/* Set WARM RESET SEQ address for P1 */
+	e |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0x38,
+				R_SEQ_ADD_WARM);
+
+	/* Install Warm Reset sequence */
+	e |= twl4030_write_script(0x38, t2_wrst_seq,
+					ARRAY_SIZE(t2_wrst_seq));
+
+	/* P1/P2/P3 enable WARMRESET */
+	e |= twl4030_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &rd_data,
+				R_P1_SW_EVENTS);
+	rd_data |= ENABLE_WARMRESET;
+	e |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, rd_data,
+				R_P1_SW_EVENTS);
+
+	e |= twl4030_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &rd_data,
+				R_P2_SW_EVENTS);
+	rd_data |= ENABLE_WARMRESET;
+	e |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, rd_data,
+				R_P2_SW_EVENTS);
+
+	e |= twl4030_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &rd_data,
+				R_P3_SW_EVENTS);
+	rd_data |= ENABLE_WARMRESET;
+	e |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, rd_data,
+				R_P3_SW_EVENTS);
+
+	if (e)
+		printk(KERN_ERR
+			"TWL4030 Power Companion Warmreset seq config error\n");
+	return e;
+}
+
+static int __init twl4030_power_init(void)
+{
+	int err = 0;
+
+	err = twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, KEY_1,
+				R_PROTECT_KEY);
+	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, KEY_2,
+				R_PROTECT_KEY);
+
+	if (err)
+		return err;
+
+	err = config_sleep_wake_sequence();
+	if (err)
+		return err;
+
+	err = config_warmreset_sequence();
+	if (err)
+		return err;
+
+	err = twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0, R_PROTECT_KEY);
+
+	return err;
+
+}
+
+module_init(twl4030_power_init);
-- 
1.5.4.3

Re: [PATCH] Load triton2 scripts.

[Tony Lindgren]

* Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com> [080825 03:28]:
> From: ext Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com>
> 
> This patch loads the triton2 (twl4030) with scripts that will cut off VDD1
> and VDD2 voltages when SYS_OFF_MODE signal is set.

Pushing today. I guess we should remove the CONFIG_DISABLE_HFCLK at
some point?

Tony

> Signed-off-by: Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com>
> Signed-off-by: Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com>
> ---
>  drivers/i2c/chips/Makefile        |    2 +-
>  drivers/i2c/chips/twl4030-power.c |  337 +++++++++++++++++++++++++++++++++++++
>  2 files changed, 338 insertions(+), 1 deletions(-)
>  create mode 100644 drivers/i2c/chips/twl4030-power.c
> 
> diff --git a/drivers/i2c/chips/Makefile b/drivers/i2c/chips/Makefile
> index 9e245b1..ad5f5db 100644
> --- a/drivers/i2c/chips/Makefile
> +++ b/drivers/i2c/chips/Makefile
> @@ -24,7 +24,7 @@ obj-$(CONFIG_GPIOEXPANDER_OMAP)	+= gpio_expander_omap.o
>  obj-$(CONFIG_MENELAUS)		+= menelaus.o
>  obj-$(CONFIG_SENSORS_TSL2550)	+= tsl2550.o
>  obj-$(CONFIG_SENSORS_TSL2563)	+= tsl2563.o
> -obj-$(CONFIG_TWL4030_CORE)	+= twl4030-core.o twl4030-pwrirq.o
> +obj-$(CONFIG_TWL4030_CORE)	+= twl4030-core.o twl4030-pwrirq.o twl4030-power.o
>  obj-$(CONFIG_TWL4030_GPIO)	+= twl4030-gpio.o
>  obj-$(CONFIG_TWL4030_USB)	+= twl4030-usb.o
>  obj-$(CONFIG_TWL4030_POWEROFF)	+= twl4030-poweroff.o
> diff --git a/drivers/i2c/chips/twl4030-power.c b/drivers/i2c/chips/twl4030-power.c
> new file mode 100644
> index 0000000..195c3c4
> --- /dev/null
> +++ b/drivers/i2c/chips/twl4030-power.c
> @@ -0,0 +1,337 @@
> +/*
> + * linux/drivers/i2c/chips/twl4030-power.c
> + *
> + * Handle TWL4030 Power initialization
> + *
> + * Copyright (C) 2008 Nokia Corporation
> + * Copyright (C) 2006 Texas Instruments, Inc
> + *
> + * Written by 	Kalle Jokiniemi
> + *		Peter De Schrijver <peter.de-schrijver@nokia.com>
> + *
> + * This file is subject to the terms and conditions of the GNU General
> + * Public License. See the file "COPYING" in the main directory of this
> + * archive for more details.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
> + */
> +
> +#include <linux/module.h>
> +#include <linux/pm.h>
> +#include <linux/i2c/twl4030.h>
> +
> +#define PWR_P1_SW_EVENTS	0x10
> +#define PWR_DEVOFF	(1<<0)
> +
> +#define PHY_TO_OFF_PM_MASTER(p)		(p - 0x36)
> +#define PHY_TO_OFF_PM_RECIEVER(p)	(p - 0x5b)
> +
> +/* resource - hfclk */
> +#define R_HFCLKOUT_DEV_GRP 	PHY_TO_OFF_PM_RECIEVER(0xe6)
> +
> +/* PM events */
> +#define R_P1_SW_EVENTS		PHY_TO_OFF_PM_MASTER(0x46)
> +#define R_P2_SW_EVENTS		PHY_TO_OFF_PM_MASTER(0x47)
> +#define R_P3_SW_EVENTS		PHY_TO_OFF_PM_MASTER(0x48)
> +#define R_CFG_P1_TRANSITION	PHY_TO_OFF_PM_MASTER(0x36)
> +#define R_CFG_P2_TRANSITION	PHY_TO_OFF_PM_MASTER(0x37)
> +#define R_CFG_P3_TRANSITION	PHY_TO_OFF_PM_MASTER(0x38)
> +
> +#define LVL_WAKEUP	0x08
> +
> +#define ENABLE_WARMRESET (1<<4)
> +
> +/* sequence script */
> +
> +#define END_OF_SCRIPT		0x3f
> +
> +#define R_SEQ_ADD_A2S		PHY_TO_OFF_PM_MASTER(0x55)
> +#define R_SEQ_ADD_SA12		PHY_TO_OFF_PM_MASTER(0x56)
> +#define	R_SEQ_ADD_S2A3		PHY_TO_OFF_PM_MASTER(0x57)
> +#define	R_SEQ_ADD_WARM		PHY_TO_OFF_PM_MASTER(0x58)
> +#define R_MEMORY_ADDRESS	PHY_TO_OFF_PM_MASTER(0x59)
> +#define R_MEMORY_DATA		PHY_TO_OFF_PM_MASTER(0x5a)
> +
> +/* Power bus message definitions */
> +
> +#define DEV_GRP_NULL		0x0
> +#define DEV_GRP_P1		0x1
> +#define DEV_GRP_P2		0x2
> +#define DEV_GRP_P3		0x4
> +
> +#define RES_GRP_RES		0x0
> +#define RES_GRP_PP		0x1
> +#define RES_GRP_RC		0x2
> +#define RES_GRP_PP_RC		0x3
> +#define RES_GRP_PR		0x4
> +#define RES_GRP_PP_PR		0x5
> +#define RES_GRP_RC_PR		0x6
> +#define RES_GRP_ALL		0x7
> +
> +#define RES_TYPE2_R0		0x0
> +
> +#define RES_TYPE_ALL		0x7
> +
> +#define RES_STATE_WRST		0xF
> +#define RES_STATE_ACTIVE	0xE
> +#define RES_STATE_SLEEP		0x8
> +#define RES_STATE_OFF		0x0
> +
> +/*
> +*	Power Bus Message Format
> +*
> +*	Broadcast Message (16 Bits)
> +*	DEV_GRP[15:13] MT[12]  RES_GRP[11:9]  RES_TYPE2[8:7] RES_TYPE[6:4]
> +*	RES_STATE[3:0]
> +*
> +*	Singular Message (16 Bits)
> +*	DEV_GRP[15:13] MT[12]  RES_ID[11:4]  RES_STATE[3:0]
> +*
> +*/
> +
> +#define MSG_BROADCAST(devgrp, grp, type, type2, state) \
> +	(devgrp << 13 | 1 << 12 | grp << 9 | type2 << 7 | type << 4 | state)
> +
> +#define MSG_SINGULAR(devgrp, id, state) \
> +	(devgrp << 13 | 0 << 12 | id << 4 | state)
> +
> +#define R_PROTECT_KEY		0x0E
> +#define KEY_1			0xC0
> +#define KEY_2			0x0C
> +
> +struct triton_ins {
> +	u16 pmb_message;
> +	u8 delay;
> +};
> +
> +
> +#define CONFIG_DISABLE_HFCLK	1
> +
> +#if defined(CONFIG_MACH_OMAP_3430SDP) || defined(CONFIG_MACH_OMAP_3430LABRADOR)
> +
> +struct triton_ins sleep_on_seq[] __initdata = {
> +	{MSG_SINGULAR(DEV_GRP_P1, 0xf, RES_STATE_OFF), 4},
> +	{MSG_SINGULAR(DEV_GRP_P1, 0x10, RES_STATE_OFF), 2},
> +#ifdef CONFIG_DISABLE_HFCLK
> +	{MSG_SINGULAR(DEV_GRP_P1, 0x7, RES_STATE_OFF), 3},
> +	{MSG_SINGULAR(DEV_GRP_P1, 0x19, RES_STATE_OFF), 3},
> +#endif /* #ifdef CONFIG_DISABLE_HFCLK */
> +};
> +
> +struct triton_ins sleep_off_seq[] __initdata = {
> +#ifndef CONFIG_DISABLE_HFCLK
> +	{MSG_SINGULAR(DEV_GRP_P1, 0xf, RES_STATE_ACTIVE), 4},
> +	{MSG_SINGULAR(DEV_GRP_P1, 0x10, RES_STATE_ACTIVE), 2},
> +#else
> +	{MSG_SINGULAR(DEV_GRP_P1, 0x7, RES_STATE_ACTIVE), 0x30},
> +	{MSG_SINGULAR(DEV_GRP_P1, 0xf, RES_STATE_ACTIVE), 0x30},
> +	{MSG_SINGULAR(DEV_GRP_P1, 0x10, RES_STATE_ACTIVE), 0x37},
> +	{MSG_SINGULAR(DEV_GRP_P1, 0x19, RES_STATE_ACTIVE), 3},
> +#endif /* #ifndef CONFIG_DISABLE_HFCLK */
> +};
> +
> +struct triton_ins t2_wrst_seq[] __initdata = {
> +	{MSG_SINGULAR(DEV_GRP_NULL, 0x1b, RES_STATE_OFF), 2},
> +	{MSG_SINGULAR(DEV_GRP_P1, 0xf, RES_STATE_WRST), 15},
> +	{MSG_SINGULAR(DEV_GRP_P1, 0x10, RES_STATE_WRST), 15},
> +	{MSG_SINGULAR(DEV_GRP_P1, 0x7, RES_STATE_WRST), 0x60},
> +	{MSG_SINGULAR(DEV_GRP_P1, 0x19, RES_STATE_ACTIVE), 2},
> +	{MSG_SINGULAR(DEV_GRP_NULL, 0x1b, RES_STATE_ACTIVE), 2},
> +};
> +#else
> +struct triton_ins sleep_on_seq[] __initdata = {
> +	{MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_RC, RES_TYPE_ALL, RES_TYPE2_R0,
> +			RES_STATE_SLEEP), 4},
> +	{MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, RES_TYPE_ALL, RES_TYPE_R7,
> +			RES_STATE_SLEEP), 4},
> +};
> +
> +struct triton_ins sleep_off_seq[] __initdata = {
> +	{MSG_SINGULAR(DEV_GRP_NULL, 0x17, RES_STATE_ACTIVE), 0x30},
> +	{MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_PP_PR, RES_TYPE_ALL, RES_TYPE2_R0,
> +			RES_STATE_ACTIVE), 0x37},
> +	{MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, RES_TYPE_ALL, RES_TYPE2_R0,
> +			RES_STATE_ACTIVE), 0x2},
> +};
> +#endif
> +
> +static int __init twl4030_write_script_byte(u8 address, u8 byte)
> +{
> +	int err;
> +
> +	err = twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, address,
> +					R_MEMORY_ADDRESS);
> +	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, byte,
> +					R_MEMORY_DATA);
> +
> +	return err;
> +}
> +
> +static int __init twl4030_write_script_ins(u8 address, u16 pmb_message,
> +						u8 delay, u8 next)
> +{
> +	int err = 0;
> +
> +	address *= 4;
> +	err |= twl4030_write_script_byte(address++, pmb_message >> 8);
> +	err |= twl4030_write_script_byte(address++, pmb_message & 0xff);
> +	err |= twl4030_write_script_byte(address++, delay);
> +	err |= twl4030_write_script_byte(address++, next);
> +
> +	return err;
> +}
> +
> +static int __init twl4030_write_script(u8 address, struct triton_ins *script,
> +					int len)
> +{
> +	int err = 0;
> +
> +	for (; len; len--, address++, script++) {
> +		if (len == 1)
> +			err |= twl4030_write_script_ins(address,
> +							script->pmb_message,
> +							script->delay,
> +							END_OF_SCRIPT);
> +		else
> +			err |= twl4030_write_script_ins(address,
> +							script->pmb_message,
> +							script->delay,
> +							address + 1);
> +	}
> +
> +	return err;
> +}
> +
> +static int __init config_sleep_wake_sequence(void)
> +{
> +	int err = 0;
> +	u8 data;
> +
> +	/*
> +	 * CLKREQ is pulled high on the 2430SDP, therefore, we need to take
> +	 * it out of the HFCLKOUT DEV_GRP for P1 else HFCLKOUT can't be stopped.
> +	 */
> +
> +	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
> +				  0x20, R_HFCLKOUT_DEV_GRP);
> +
> +	/* Set ACTIVE to SLEEP SEQ address in T2 memory*/
> +	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0x2B,
> +				  R_SEQ_ADD_A2S);
> +
> +	/* Set SLEEP to ACTIVE SEQ address for P1 and P2 */
> +	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0x2F,
> +				  R_SEQ_ADD_SA12);
> +
> +	/* Set SLEEP to ACTIVE SEQ address for P3 */
> +	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0x2F,
> +				  R_SEQ_ADD_S2A3);
> +
> +	/* Install Active->Sleep (A2S) sequence */
> +	err |= twl4030_write_script(0x2B, sleep_on_seq,
> +					ARRAY_SIZE(sleep_on_seq));
> +
> +	/* Install Sleep->Active (S2A) sequence */
> +	err |= twl4030_write_script(0x2F, sleep_off_seq,
> +					ARRAY_SIZE(sleep_off_seq));
> +
> +#if defined(CONFIG_MACH_OMAP_3430SDP) || defined(CONFIG_MACH_OMAP_3430LABRADOR)
> +	/* Disabling AC charger effect on sleep-active transitions */
> +	err |= twl4030_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &data,
> +					R_CFG_P1_TRANSITION);
> +	data &= 0x0;
> +	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, data ,
> +					R_CFG_P1_TRANSITION);
> +#endif
> +	/* P1/P2/P3 LVL_WAKEUP should be on LEVEL */
> +	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, LVL_WAKEUP,
> +					R_P1_SW_EVENTS);
> +	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, LVL_WAKEUP,
> +					R_P2_SW_EVENTS);
> +	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, LVL_WAKEUP,
> +				R_P3_SW_EVENTS);
> +
> +	if (err)
> +		printk(KERN_ERR "TWL4030 sleep-wake sequence config error\n");
> +
> +	return err;
> +}
> +
> +
> +/* Programming the WARMRESET Sequence on TRITON */
> +static int __init config_warmreset_sequence(void)
> +{
> +
> +	int e = 0;
> +	u8 rd_data;
> +
> +	if (!ARRAY_SIZE(t2_wrst_seq))
> +		return 0;
> +
> +	/* Set WARM RESET SEQ address for P1 */
> +	e |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0x38,
> +				R_SEQ_ADD_WARM);
> +
> +	/* Install Warm Reset sequence */
> +	e |= twl4030_write_script(0x38, t2_wrst_seq,
> +					ARRAY_SIZE(t2_wrst_seq));
> +
> +	/* P1/P2/P3 enable WARMRESET */
> +	e |= twl4030_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &rd_data,
> +				R_P1_SW_EVENTS);
> +	rd_data |= ENABLE_WARMRESET;
> +	e |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, rd_data,
> +				R_P1_SW_EVENTS);
> +
> +	e |= twl4030_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &rd_data,
> +				R_P2_SW_EVENTS);
> +	rd_data |= ENABLE_WARMRESET;
> +	e |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, rd_data,
> +				R_P2_SW_EVENTS);
> +
> +	e |= twl4030_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &rd_data,
> +				R_P3_SW_EVENTS);
> +	rd_data |= ENABLE_WARMRESET;
> +	e |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, rd_data,
> +				R_P3_SW_EVENTS);
> +
> +	if (e)
> +		printk(KERN_ERR
> +			"TWL4030 Power Companion Warmreset seq config error\n");
> +	return e;
> +}
> +
> +static int __init twl4030_power_init(void)
> +{
> +	int err = 0;
> +
> +	err = twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, KEY_1,
> +				R_PROTECT_KEY);
> +	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, KEY_2,
> +				R_PROTECT_KEY);
> +
> +	if (err)
> +		return err;
> +
> +	err = config_sleep_wake_sequence();
> +	if (err)
> +		return err;
> +
> +	err = config_warmreset_sequence();
> +	if (err)
> +		return err;
> +
> +	err = twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0, R_PROTECT_KEY);
> +
> +	return err;
> +
> +}
> +
> +module_init(twl4030_power_init);
> -- 
> 1.5.4.3
> 

Re: [PATCH] Load triton2 scripts.

[Steve Sakoman]

On Wed, Sep 10, 2008 at 5:08 PM, Tony Lindgren <tony@atomide.com> wrote:
> * Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com> [080825 03:28]:
>> From: ext Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com>
>>
>> This patch loads the triton2 (twl4030) with scripts that will cut off VDD1
>> and VDD2 voltages when SYS_OFF_MODE signal is set.
>
> Pushing today. I guess we should remove the CONFIG_DISABLE_HFCLK at
> some point?

This patch causes a build error due to a missing define:

|   CC      drivers/i2c/chips/twl4030-power.o
| drivers/i2c/chips/twl4030-power.c:152: error: 'RES_TYPE_R7'
undeclared here (not in a function)


Steve

Re: [PATCH] Load triton2 scripts.

[Koen Kooi]

[-- Attachment #1: Type: text/plain, Size: 2166 bytes --]


Op 11 sep 2008, om 05:20 heeft Steve Sakoman het volgende geschreven:

> On Wed, Sep 10, 2008 at 5:08 PM, Tony Lindgren <tony@atomide.com>  
> wrote:
>> * Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com> [080825 03:28]:
>>> From: ext Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com>
>>>
>>> This patch loads the triton2 (twl4030) with scripts that will cut  
>>> off VDD1
>>> and VDD2 voltages when SYS_OFF_MODE signal is set.
>>
>> Pushing today. I guess we should remove the CONFIG_DISABLE_HFCLK at
>> some point?
>
> This patch causes a build error due to a missing define:
>
> |   CC      drivers/i2c/chips/twl4030-power.o
> | drivers/i2c/chips/twl4030-power.c:152: error: 'RES_TYPE_R7'
> undeclared here (not in a function)

Same here:

make[3]: Entering directory `/OE/angstrom-dev/work/beagleboard- 
angstrom-linux-gnueabi/linux-omap-2.6.26+2.6.27- 
rc6+r1+gite9e9988a4ded6acee1d5387debb39f006f4c11a3-r1/git'
   CC      drivers/i2c/chips/twl4030-power.o
drivers/i2c/chips/twl4030-power.c:152: error: 'RES_TYPE_R7' undeclared  
here (not in a function)
drivers/i2c/chips/twl4030-power.c: In function  
'config_sleep_wake_sequence':
drivers/i2c/chips/twl4030-power.c:215: warning: unused variable 'data'
drivers/i2c/chips/twl4030-power.c: In function  
'config_warmreset_sequence':
drivers/i2c/chips/twl4030-power.c:275: error: 't2_wrst_seq' undeclared  
(first use in this function)
drivers/i2c/chips/twl4030-power.c:275: error: (Each undeclared  
identifier is reported only once
drivers/i2c/chips/twl4030-power.c:275: error: for each function it  
appears in.)
drivers/i2c/chips/twl4030-power.c:275: error: invalid operands to  
binary /
drivers/i2c/chips/twl4030-power.c:284: error: invalid operands to  
binary /
drivers/i2c/chips/twl4030-power.c:284: warning: passing argument 3 of  
'twl4030_write_script' makes integer from pointer without a cast
make[3]: *** [drivers/i2c/chips/twl4030-power.o] Error 1

regards,

Koen




>
>
>
> Steve
> --
> To unsubscribe from this list: send the line "unsubscribe linux- 
> omap" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>


[-- Attachment #2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 186 bytes --]

Re: [PATCH] Load triton2 scripts.

[Kevin Hilman]

Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com> writes:

> From: ext Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com>
>
> This patch loads the triton2 (twl4030) with scripts that will cut off VDD1
> and VDD2 voltages when SYS_OFF_MODE signal is set.
>
> Signed-off-by: Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com>
> Signed-off-by: Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com>
> ---
>  drivers/i2c/chips/Makefile        |    2 +-
>  drivers/i2c/chips/twl4030-power.c |  337 +++++++++++++++++++++++++++++++++++++
>  2 files changed, 338 insertions(+), 1 deletions(-)
>  create mode 100644 drivers/i2c/chips/twl4030-power.c
>
> diff --git a/drivers/i2c/chips/Makefile b/drivers/i2c/chips/Makefile
> index 9e245b1..ad5f5db 100644
> --- a/drivers/i2c/chips/Makefile
> +++ b/drivers/i2c/chips/Makefile
> @@ -24,7 +24,7 @@ obj-$(CONFIG_GPIOEXPANDER_OMAP)	+= gpio_expander_omap.o
>  obj-$(CONFIG_MENELAUS)		+= menelaus.o
>  obj-$(CONFIG_SENSORS_TSL2550)	+= tsl2550.o
>  obj-$(CONFIG_SENSORS_TSL2563)	+= tsl2563.o
> -obj-$(CONFIG_TWL4030_CORE)	+= twl4030-core.o twl4030-pwrirq.o
> +obj-$(CONFIG_TWL4030_CORE)	+= twl4030-core.o twl4030-pwrirq.o twl4030-power.o
>  obj-$(CONFIG_TWL4030_GPIO)	+= twl4030-gpio.o
>  obj-$(CONFIG_TWL4030_USB)	+= twl4030-usb.o
>  obj-$(CONFIG_TWL4030_POWEROFF)	+= twl4030-poweroff.o
> diff --git a/drivers/i2c/chips/twl4030-power.c b/drivers/i2c/chips/twl4030-power.c
> new file mode 100644
> index 0000000..195c3c4
> --- /dev/null
> +++ b/drivers/i2c/chips/twl4030-power.c
> @@ -0,0 +1,337 @@
> +/*
> + * linux/drivers/i2c/chips/twl4030-power.c
> + *
> + * Handle TWL4030 Power initialization
> + *
> + * Copyright (C) 2008 Nokia Corporation
> + * Copyright (C) 2006 Texas Instruments, Inc
> + *
> + * Written by 	Kalle Jokiniemi
> + *		Peter De Schrijver <peter.de-schrijver@nokia.com>
> + *
> + * This file is subject to the terms and conditions of the GNU General
> + * Public License. See the file "COPYING" in the main directory of this
> + * archive for more details.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
> + */
> +
> +#include <linux/module.h>
> +#include <linux/pm.h>
> +#include <linux/i2c/twl4030.h>
> +
> +#define PWR_P1_SW_EVENTS	0x10
> +#define PWR_DEVOFF	(1<<0)
> +
> +#define PHY_TO_OFF_PM_MASTER(p)		(p - 0x36)
> +#define PHY_TO_OFF_PM_RECIEVER(p)	(p - 0x5b)
> +
> +/* resource - hfclk */
> +#define R_HFCLKOUT_DEV_GRP 	PHY_TO_OFF_PM_RECIEVER(0xe6)
> +
> +/* PM events */
> +#define R_P1_SW_EVENTS		PHY_TO_OFF_PM_MASTER(0x46)
> +#define R_P2_SW_EVENTS		PHY_TO_OFF_PM_MASTER(0x47)
> +#define R_P3_SW_EVENTS		PHY_TO_OFF_PM_MASTER(0x48)
> +#define R_CFG_P1_TRANSITION	PHY_TO_OFF_PM_MASTER(0x36)
> +#define R_CFG_P2_TRANSITION	PHY_TO_OFF_PM_MASTER(0x37)
> +#define R_CFG_P3_TRANSITION	PHY_TO_OFF_PM_MASTER(0x38)
> +
> +#define LVL_WAKEUP	0x08
> +
> +#define ENABLE_WARMRESET (1<<4)
> +
> +/* sequence script */
> +
> +#define END_OF_SCRIPT		0x3f
> +
> +#define R_SEQ_ADD_A2S		PHY_TO_OFF_PM_MASTER(0x55)
> +#define R_SEQ_ADD_SA12		PHY_TO_OFF_PM_MASTER(0x56)
> +#define	R_SEQ_ADD_S2A3		PHY_TO_OFF_PM_MASTER(0x57)
> +#define	R_SEQ_ADD_WARM		PHY_TO_OFF_PM_MASTER(0x58)
> +#define R_MEMORY_ADDRESS	PHY_TO_OFF_PM_MASTER(0x59)
> +#define R_MEMORY_DATA		PHY_TO_OFF_PM_MASTER(0x5a)
> +
> +/* Power bus message definitions */
> +
> +#define DEV_GRP_NULL		0x0
> +#define DEV_GRP_P1		0x1
> +#define DEV_GRP_P2		0x2
> +#define DEV_GRP_P3		0x4
> +
> +#define RES_GRP_RES		0x0
> +#define RES_GRP_PP		0x1
> +#define RES_GRP_RC		0x2
> +#define RES_GRP_PP_RC		0x3
> +#define RES_GRP_PR		0x4
> +#define RES_GRP_PP_PR		0x5
> +#define RES_GRP_RC_PR		0x6
> +#define RES_GRP_ALL		0x7
> +
> +#define RES_TYPE2_R0		0x0
> +
> +#define RES_TYPE_ALL		0x7
> +
> +#define RES_STATE_WRST		0xF
> +#define RES_STATE_ACTIVE	0xE
> +#define RES_STATE_SLEEP		0x8
> +#define RES_STATE_OFF		0x0
> +
> +/*
> +*	Power Bus Message Format
> +*
> +*	Broadcast Message (16 Bits)
> +*	DEV_GRP[15:13] MT[12]  RES_GRP[11:9]  RES_TYPE2[8:7] RES_TYPE[6:4]
> +*	RES_STATE[3:0]
> +*
> +*	Singular Message (16 Bits)
> +*	DEV_GRP[15:13] MT[12]  RES_ID[11:4]  RES_STATE[3:0]
> +*
> +*/
> +
> +#define MSG_BROADCAST(devgrp, grp, type, type2, state) \
> +	(devgrp << 13 | 1 << 12 | grp << 9 | type2 << 7 | type << 4 | state)
> +
> +#define MSG_SINGULAR(devgrp, id, state) \
> +	(devgrp << 13 | 0 << 12 | id << 4 | state)
> +
> +#define R_PROTECT_KEY		0x0E
> +#define KEY_1			0xC0
> +#define KEY_2			0x0C
> +
> +struct triton_ins {
> +	u16 pmb_message;
> +	u8 delay;
> +};
> +
> +
> +#define CONFIG_DISABLE_HFCLK	1
> +
> +#if defined(CONFIG_MACH_OMAP_3430SDP) || defined(CONFIG_MACH_OMAP_3430LABRADOR)

Labrador mach-type is not an option.  I'd guess this should be
CONFIG_MACH_OMAP_LDP?

Kevin

> +struct triton_ins sleep_on_seq[] __initdata = {
> +	{MSG_SINGULAR(DEV_GRP_P1, 0xf, RES_STATE_OFF), 4},
> +	{MSG_SINGULAR(DEV_GRP_P1, 0x10, RES_STATE_OFF), 2},
> +#ifdef CONFIG_DISABLE_HFCLK
> +	{MSG_SINGULAR(DEV_GRP_P1, 0x7, RES_STATE_OFF), 3},
> +	{MSG_SINGULAR(DEV_GRP_P1, 0x19, RES_STATE_OFF), 3},
> +#endif /* #ifdef CONFIG_DISABLE_HFCLK */
> +};
> +
> +struct triton_ins sleep_off_seq[] __initdata = {
> +#ifndef CONFIG_DISABLE_HFCLK
> +	{MSG_SINGULAR(DEV_GRP_P1, 0xf, RES_STATE_ACTIVE), 4},
> +	{MSG_SINGULAR(DEV_GRP_P1, 0x10, RES_STATE_ACTIVE), 2},
> +#else
> +	{MSG_SINGULAR(DEV_GRP_P1, 0x7, RES_STATE_ACTIVE), 0x30},
> +	{MSG_SINGULAR(DEV_GRP_P1, 0xf, RES_STATE_ACTIVE), 0x30},
> +	{MSG_SINGULAR(DEV_GRP_P1, 0x10, RES_STATE_ACTIVE), 0x37},
> +	{MSG_SINGULAR(DEV_GRP_P1, 0x19, RES_STATE_ACTIVE), 3},
> +#endif /* #ifndef CONFIG_DISABLE_HFCLK */
> +};
> +
> +struct triton_ins t2_wrst_seq[] __initdata = {
> +	{MSG_SINGULAR(DEV_GRP_NULL, 0x1b, RES_STATE_OFF), 2},
> +	{MSG_SINGULAR(DEV_GRP_P1, 0xf, RES_STATE_WRST), 15},
> +	{MSG_SINGULAR(DEV_GRP_P1, 0x10, RES_STATE_WRST), 15},
> +	{MSG_SINGULAR(DEV_GRP_P1, 0x7, RES_STATE_WRST), 0x60},
> +	{MSG_SINGULAR(DEV_GRP_P1, 0x19, RES_STATE_ACTIVE), 2},
> +	{MSG_SINGULAR(DEV_GRP_NULL, 0x1b, RES_STATE_ACTIVE), 2},
> +};
> +#else
> +struct triton_ins sleep_on_seq[] __initdata = {
> +	{MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_RC, RES_TYPE_ALL, RES_TYPE2_R0,
> +			RES_STATE_SLEEP), 4},
> +	{MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, RES_TYPE_ALL, RES_TYPE_R7,
> +			RES_STATE_SLEEP), 4},
> +};
> +
> +struct triton_ins sleep_off_seq[] __initdata = {
> +	{MSG_SINGULAR(DEV_GRP_NULL, 0x17, RES_STATE_ACTIVE), 0x30},
> +	{MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_PP_PR, RES_TYPE_ALL, RES_TYPE2_R0,
> +			RES_STATE_ACTIVE), 0x37},
> +	{MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, RES_TYPE_ALL, RES_TYPE2_R0,
> +			RES_STATE_ACTIVE), 0x2},
> +};
> +#endif
> +
> +static int __init twl4030_write_script_byte(u8 address, u8 byte)
> +{
> +	int err;
> +
> +	err = twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, address,
> +					R_MEMORY_ADDRESS);
> +	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, byte,
> +					R_MEMORY_DATA);
> +
> +	return err;
> +}
> +
> +static int __init twl4030_write_script_ins(u8 address, u16 pmb_message,
> +						u8 delay, u8 next)
> +{
> +	int err = 0;
> +
> +	address *= 4;
> +	err |= twl4030_write_script_byte(address++, pmb_message >> 8);
> +	err |= twl4030_write_script_byte(address++, pmb_message & 0xff);
> +	err |= twl4030_write_script_byte(address++, delay);
> +	err |= twl4030_write_script_byte(address++, next);
> +
> +	return err;
> +}
> +
> +static int __init twl4030_write_script(u8 address, struct triton_ins *script,
> +					int len)
> +{
> +	int err = 0;
> +
> +	for (; len; len--, address++, script++) {
> +		if (len == 1)
> +			err |= twl4030_write_script_ins(address,
> +							script->pmb_message,
> +							script->delay,
> +							END_OF_SCRIPT);
> +		else
> +			err |= twl4030_write_script_ins(address,
> +							script->pmb_message,
> +							script->delay,
> +							address + 1);
> +	}
> +
> +	return err;
> +}
> +
> +static int __init config_sleep_wake_sequence(void)
> +{
> +	int err = 0;
> +	u8 data;
> +
> +	/*
> +	 * CLKREQ is pulled high on the 2430SDP, therefore, we need to take
> +	 * it out of the HFCLKOUT DEV_GRP for P1 else HFCLKOUT can't be stopped.
> +	 */
> +
> +	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
> +				  0x20, R_HFCLKOUT_DEV_GRP);
> +
> +	/* Set ACTIVE to SLEEP SEQ address in T2 memory*/
> +	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0x2B,
> +				  R_SEQ_ADD_A2S);
> +
> +	/* Set SLEEP to ACTIVE SEQ address for P1 and P2 */
> +	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0x2F,
> +				  R_SEQ_ADD_SA12);
> +
> +	/* Set SLEEP to ACTIVE SEQ address for P3 */
> +	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0x2F,
> +				  R_SEQ_ADD_S2A3);
> +
> +	/* Install Active->Sleep (A2S) sequence */
> +	err |= twl4030_write_script(0x2B, sleep_on_seq,
> +					ARRAY_SIZE(sleep_on_seq));
> +
> +	/* Install Sleep->Active (S2A) sequence */
> +	err |= twl4030_write_script(0x2F, sleep_off_seq,
> +					ARRAY_SIZE(sleep_off_seq));
> +
> +#if defined(CONFIG_MACH_OMAP_3430SDP) || defined(CONFIG_MACH_OMAP_3430LABRADOR)
> +	/* Disabling AC charger effect on sleep-active transitions */
> +	err |= twl4030_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &data,
> +					R_CFG_P1_TRANSITION);
> +	data &= 0x0;
> +	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, data ,
> +					R_CFG_P1_TRANSITION);
> +#endif
> +	/* P1/P2/P3 LVL_WAKEUP should be on LEVEL */
> +	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, LVL_WAKEUP,
> +					R_P1_SW_EVENTS);
> +	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, LVL_WAKEUP,
> +					R_P2_SW_EVENTS);
> +	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, LVL_WAKEUP,
> +				R_P3_SW_EVENTS);
> +
> +	if (err)
> +		printk(KERN_ERR "TWL4030 sleep-wake sequence config error\n");
> +
> +	return err;
> +}
> +
> +
> +/* Programming the WARMRESET Sequence on TRITON */
> +static int __init config_warmreset_sequence(void)
> +{
> +
> +	int e = 0;
> +	u8 rd_data;
> +
> +	if (!ARRAY_SIZE(t2_wrst_seq))
> +		return 0;
> +
> +	/* Set WARM RESET SEQ address for P1 */
> +	e |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0x38,
> +				R_SEQ_ADD_WARM);
> +
> +	/* Install Warm Reset sequence */
> +	e |= twl4030_write_script(0x38, t2_wrst_seq,
> +					ARRAY_SIZE(t2_wrst_seq));
> +
> +	/* P1/P2/P3 enable WARMRESET */
> +	e |= twl4030_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &rd_data,
> +				R_P1_SW_EVENTS);
> +	rd_data |= ENABLE_WARMRESET;
> +	e |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, rd_data,
> +				R_P1_SW_EVENTS);
> +
> +	e |= twl4030_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &rd_data,
> +				R_P2_SW_EVENTS);
> +	rd_data |= ENABLE_WARMRESET;
> +	e |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, rd_data,
> +				R_P2_SW_EVENTS);
> +
> +	e |= twl4030_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &rd_data,
> +				R_P3_SW_EVENTS);
> +	rd_data |= ENABLE_WARMRESET;
> +	e |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, rd_data,
> +				R_P3_SW_EVENTS);
> +
> +	if (e)
> +		printk(KERN_ERR
> +			"TWL4030 Power Companion Warmreset seq config error\n");
> +	return e;
> +}
> +
> +static int __init twl4030_power_init(void)
> +{
> +	int err = 0;
> +
> +	err = twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, KEY_1,
> +				R_PROTECT_KEY);
> +	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, KEY_2,
> +				R_PROTECT_KEY);
> +
> +	if (err)
> +		return err;
> +
> +	err = config_sleep_wake_sequence();
> +	if (err)
> +		return err;
> +
> +	err = config_warmreset_sequence();
> +	if (err)
> +		return err;
> +
> +	err = twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0, R_PROTECT_KEY);
> +
> +	return err;
> +
> +}
> +
> +module_init(twl4030_power_init);
> -- 
> 1.5.4.3
>
> --
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> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

RFC: OMAP3 SYS_OFF_MODE support

[Peter 'p2' De Schrijver]

The following patch set introduces support for the OMAP3 SYS_OFF_MODE
signal. This will cause a properly programmed triton2 to shutdown the
VDD1 and VDD2 regulators when both core and MPU powerdomain are in off
state. The patches includes programming triton2 with the appropriate
scripts for the SDP3430 board.
By default the OMAP3 polarity of the SYS_OFF_MODE signal is inverted
compared to what triton2 expects. This means the polarity needs to be
changed before the triton2 scripts are activated, otherwise the system
will crash. At the moment this is done in omap2_clk_init as this
function is called before triton2 is initialized. Better suggestions are
welcome.
Thanks to Kalle Jokiniemi for doing the initial patch and test work.

[PATCH] Set correct off mode polarity

[Peter 'p2' De Schrijver]

Signed-off-by: Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com>
---
 arch/arm/mach-omap2/clock34xx.c |    6 +++++-
 1 files changed, 5 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 6bb25cf..b0bc1b9 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -46,6 +46,8 @@
 
 #define MAX_DPLL_WAIT_TRIES		1000000
 
+#define OFFMODE_POL 			(1<<3)
+
 struct vdd_prcm_config *curr_vdd1_prcm_set;
 struct vdd_prcm_config *curr_vdd2_prcm_set;
 static struct clk *dpll1_clk, *dpll2_clk, *dpll3_clk;
@@ -684,6 +686,9 @@ int __init omap2_clk_init(void)
 	}
 #endif
 
+	prm_clear_mod_reg_bits(OFFMODE_POL, OMAP3430_GR_MOD,
+				OMAP3_PRM_POLCTRL_OFFSET);
+
 	printk(KERN_INFO "Clocking rate (Crystal/DPLL/ARM core): "
 	       "%ld.%01ld/%ld/%ld MHz\n",
 	       (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
@@ -797,7 +802,6 @@ static int omap3_select_table_rate(struct clk *clk, unsigned long rate)
 		return -EINVAL;
 	}
 
-
 	if (clk == &virt_vdd1_prcm_set) {
 		curr_mpu_speed = curr_vdd1_prcm_set->speed;
 		clk_set_rate(dpll1_clk, prcm_vdd->speed);
-- 
1.5.3.4

[PATCH] Enable SYSOFFMODE use

[Peter 'p2' De Schrijver]

Signed-off-by: Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com>
---
 arch/arm/mach-omap2/smartreflex.c |   10 +++++-----
 1 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
index 0f3a659..b41fe96 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -396,17 +396,17 @@ static void sr_configure_vc(void)
 
 	/* Setup voltctrl and other setup times */
 	/* XXX CONFIG_SYSOFFMODE has not been implemented yet */
-#ifdef CONFIG_SYSOFFMODE
-	prm_write_mod_reg(OMAP3430_AUTO_OFF | OMAP3430_AUTO_RET,
-			OMAP3430_GR_MOD,
+#ifdef CONFIG_OMAP_SYSOFFMODE
+	prm_write_mod_reg(OMAP3430_AUTO_OFF | OMAP3430_AUTO_RET |
+			OMAP3430_SEL_OFF, OMAP3430_GR_MOD,
 			OMAP3_PRM_VOLTCTRL_OFFSET);
 
 	prm_write_mod_reg(OMAP3430_CLKSETUP_DURATION, OMAP3430_GR_MOD,
 			OMAP3_PRM_CLKSETUP_OFFSET);
 	prm_write_mod_reg((OMAP3430_VOLTSETUP_TIME2 <<
-			OMAP3430_VOLTSETUP_TIME2_OFFSET) |
+			OMAP3430_SETUP_TIME2_SHIFT) |
 			(OMAP3430_VOLTSETUP_TIME1 <<
-			OMAP3430_VOLTSETUP_TIME1_OFFSET),
+			OMAP3430_SETUP_TIME1_SHIFT),
 			OMAP3430_GR_MOD, OMAP3_PRM_VOLTSETUP1_OFFSET);
 
 	prm_write_mod_reg(OMAP3430_VOLTOFFSET_DURATION, OMAP3430_GR_MOD,
-- 
1.5.3.4

[PATCH] Add SYSOFFMODE option.

[Peter 'p2' De Schrijver]

Signed-off-by: Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com>
---
 arch/arm/plat-omap/Kconfig |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index d7b34ff..6f891b7 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -73,6 +73,12 @@ config OMAP_SMARTREFLEX
 	  compensation for VDD1 and VDD2, user must write 1 to
 	  /sys/power/sr_vddX_autocomp, where X is 1 or 2.
 
+config OMAP_SYSOFFMODE
+        bool "OFF mode support"
+	depends on ARCH_OMAP34XX
+	help
+	  Say Y if you want to allow OMAP to enter OFF mode.
+
 config OMAP_SMARTREFLEX_TESTING
 	bool "Smartreflex testing support"
 	depends on OMAP_SMARTREFLEX
-- 
1.5.3.4

[PATCH] Load triton2 scripts.

[Peter 'p2' De Schrijver]

Signed-off-by: Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com>
---
 drivers/i2c/chips/Makefile        |    2 +-
 drivers/i2c/chips/twl4030-power.c |  337 +++++++++++++++++++++++++++++++++++++
 2 files changed, 338 insertions(+), 1 deletions(-)
 create mode 100644 drivers/i2c/chips/twl4030-power.c

diff --git a/drivers/i2c/chips/Makefile b/drivers/i2c/chips/Makefile
index 1f81ebd..a44e617 100644
--- a/drivers/i2c/chips/Makefile
+++ b/drivers/i2c/chips/Makefile
@@ -23,7 +23,7 @@ obj-$(CONFIG_GPIOEXPANDER_OMAP)	+= gpio_expander_omap.o
 obj-$(CONFIG_MENELAUS)		+= menelaus.o
 obj-$(CONFIG_SENSORS_TSL2550)	+= tsl2550.o
 obj-$(CONFIG_SENSORS_TSL2563)	+= tsl2563.o
-obj-$(CONFIG_TWL4030_CORE)	+= twl4030-core.o twl4030-pwrirq.o
+obj-$(CONFIG_TWL4030_CORE)	+= twl4030-core.o twl4030-pwrirq.o twl4030-power.o
 obj-$(CONFIG_TWL4030_GPIO)	+= twl4030-gpio.o
 obj-$(CONFIG_TWL4030_USB)	+= twl4030-usb.o
 obj-$(CONFIG_TWL4030_POWEROFF)	+= twl4030-poweroff.o
diff --git a/drivers/i2c/chips/twl4030-power.c b/drivers/i2c/chips/twl4030-power.c
new file mode 100644
index 0000000..195c3c4
--- /dev/null
+++ b/drivers/i2c/chips/twl4030-power.c
@@ -0,0 +1,337 @@
+/*
+ * linux/drivers/i2c/chips/twl4030-power.c
+ *
+ * Handle TWL4030 Power initialization
+ *
+ * Copyright (C) 2008 Nokia Corporation
+ * Copyright (C) 2006 Texas Instruments, Inc
+ *
+ * Written by 	Kalle Jokiniemi
+ *		Peter De Schrijver <peter.de-schrijver@nokia.com>
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License. See the file "COPYING" in the main directory of this
+ * archive for more details.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/module.h>
+#include <linux/pm.h>
+#include <linux/i2c/twl4030.h>
+
+#define PWR_P1_SW_EVENTS	0x10
+#define PWR_DEVOFF	(1<<0)
+
+#define PHY_TO_OFF_PM_MASTER(p)		(p - 0x36)
+#define PHY_TO_OFF_PM_RECIEVER(p)	(p - 0x5b)
+
+/* resource - hfclk */
+#define R_HFCLKOUT_DEV_GRP 	PHY_TO_OFF_PM_RECIEVER(0xe6)
+
+/* PM events */
+#define R_P1_SW_EVENTS		PHY_TO_OFF_PM_MASTER(0x46)
+#define R_P2_SW_EVENTS		PHY_TO_OFF_PM_MASTER(0x47)
+#define R_P3_SW_EVENTS		PHY_TO_OFF_PM_MASTER(0x48)
+#define R_CFG_P1_TRANSITION	PHY_TO_OFF_PM_MASTER(0x36)
+#define R_CFG_P2_TRANSITION	PHY_TO_OFF_PM_MASTER(0x37)
+#define R_CFG_P3_TRANSITION	PHY_TO_OFF_PM_MASTER(0x38)
+
+#define LVL_WAKEUP	0x08
+
+#define ENABLE_WARMRESET (1<<4)
+
+/* sequence script */
+
+#define END_OF_SCRIPT		0x3f
+
+#define R_SEQ_ADD_A2S		PHY_TO_OFF_PM_MASTER(0x55)
+#define R_SEQ_ADD_SA12		PHY_TO_OFF_PM_MASTER(0x56)
+#define	R_SEQ_ADD_S2A3		PHY_TO_OFF_PM_MASTER(0x57)
+#define	R_SEQ_ADD_WARM		PHY_TO_OFF_PM_MASTER(0x58)
+#define R_MEMORY_ADDRESS	PHY_TO_OFF_PM_MASTER(0x59)
+#define R_MEMORY_DATA		PHY_TO_OFF_PM_MASTER(0x5a)
+
+/* Power bus message definitions */
+
+#define DEV_GRP_NULL		0x0
+#define DEV_GRP_P1		0x1
+#define DEV_GRP_P2		0x2
+#define DEV_GRP_P3		0x4
+
+#define RES_GRP_RES		0x0
+#define RES_GRP_PP		0x1
+#define RES_GRP_RC		0x2
+#define RES_GRP_PP_RC		0x3
+#define RES_GRP_PR		0x4
+#define RES_GRP_PP_PR		0x5
+#define RES_GRP_RC_PR		0x6
+#define RES_GRP_ALL		0x7
+
+#define RES_TYPE2_R0		0x0
+
+#define RES_TYPE_ALL		0x7
+
+#define RES_STATE_WRST		0xF
+#define RES_STATE_ACTIVE	0xE
+#define RES_STATE_SLEEP		0x8
+#define RES_STATE_OFF		0x0
+
+/*
+*	Power Bus Message Format
+*
+*	Broadcast Message (16 Bits)
+*	DEV_GRP[15:13] MT[12]  RES_GRP[11:9]  RES_TYPE2[8:7] RES_TYPE[6:4]
+*	RES_STATE[3:0]
+*
+*	Singular Message (16 Bits)
+*	DEV_GRP[15:13] MT[12]  RES_ID[11:4]  RES_STATE[3:0]
+*
+*/
+
+#define MSG_BROADCAST(devgrp, grp, type, type2, state) \
+	(devgrp << 13 | 1 << 12 | grp << 9 | type2 << 7 | type << 4 | state)
+
+#define MSG_SINGULAR(devgrp, id, state) \
+	(devgrp << 13 | 0 << 12 | id << 4 | state)
+
+#define R_PROTECT_KEY		0x0E
+#define KEY_1			0xC0
+#define KEY_2			0x0C
+
+struct triton_ins {
+	u16 pmb_message;
+	u8 delay;
+};
+
+
+#define CONFIG_DISABLE_HFCLK	1
+
+#if defined(CONFIG_MACH_OMAP_3430SDP) || defined(CONFIG_MACH_OMAP_3430LABRADOR)
+
+struct triton_ins sleep_on_seq[] __initdata = {
+	{MSG_SINGULAR(DEV_GRP_P1, 0xf, RES_STATE_OFF), 4},
+	{MSG_SINGULAR(DEV_GRP_P1, 0x10, RES_STATE_OFF), 2},
+#ifdef CONFIG_DISABLE_HFCLK
+	{MSG_SINGULAR(DEV_GRP_P1, 0x7, RES_STATE_OFF), 3},
+	{MSG_SINGULAR(DEV_GRP_P1, 0x19, RES_STATE_OFF), 3},
+#endif /* #ifdef CONFIG_DISABLE_HFCLK */
+};
+
+struct triton_ins sleep_off_seq[] __initdata = {
+#ifndef CONFIG_DISABLE_HFCLK
+	{MSG_SINGULAR(DEV_GRP_P1, 0xf, RES_STATE_ACTIVE), 4},
+	{MSG_SINGULAR(DEV_GRP_P1, 0x10, RES_STATE_ACTIVE), 2},
+#else
+	{MSG_SINGULAR(DEV_GRP_P1, 0x7, RES_STATE_ACTIVE), 0x30},
+	{MSG_SINGULAR(DEV_GRP_P1, 0xf, RES_STATE_ACTIVE), 0x30},
+	{MSG_SINGULAR(DEV_GRP_P1, 0x10, RES_STATE_ACTIVE), 0x37},
+	{MSG_SINGULAR(DEV_GRP_P1, 0x19, RES_STATE_ACTIVE), 3},
+#endif /* #ifndef CONFIG_DISABLE_HFCLK */
+};
+
+struct triton_ins t2_wrst_seq[] __initdata = {
+	{MSG_SINGULAR(DEV_GRP_NULL, 0x1b, RES_STATE_OFF), 2},
+	{MSG_SINGULAR(DEV_GRP_P1, 0xf, RES_STATE_WRST), 15},
+	{MSG_SINGULAR(DEV_GRP_P1, 0x10, RES_STATE_WRST), 15},
+	{MSG_SINGULAR(DEV_GRP_P1, 0x7, RES_STATE_WRST), 0x60},
+	{MSG_SINGULAR(DEV_GRP_P1, 0x19, RES_STATE_ACTIVE), 2},
+	{MSG_SINGULAR(DEV_GRP_NULL, 0x1b, RES_STATE_ACTIVE), 2},
+};
+#else
+struct triton_ins sleep_on_seq[] __initdata = {
+	{MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_RC, RES_TYPE_ALL, RES_TYPE2_R0,
+			RES_STATE_SLEEP), 4},
+	{MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, RES_TYPE_ALL, RES_TYPE_R7,
+			RES_STATE_SLEEP), 4},
+};
+
+struct triton_ins sleep_off_seq[] __initdata = {
+	{MSG_SINGULAR(DEV_GRP_NULL, 0x17, RES_STATE_ACTIVE), 0x30},
+	{MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_PP_PR, RES_TYPE_ALL, RES_TYPE2_R0,
+			RES_STATE_ACTIVE), 0x37},
+	{MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, RES_TYPE_ALL, RES_TYPE2_R0,
+			RES_STATE_ACTIVE), 0x2},
+};
+#endif
+
+static int __init twl4030_write_script_byte(u8 address, u8 byte)
+{
+	int err;
+
+	err = twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, address,
+					R_MEMORY_ADDRESS);
+	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, byte,
+					R_MEMORY_DATA);
+
+	return err;
+}
+
+static int __init twl4030_write_script_ins(u8 address, u16 pmb_message,
+						u8 delay, u8 next)
+{
+	int err = 0;
+
+	address *= 4;
+	err |= twl4030_write_script_byte(address++, pmb_message >> 8);
+	err |= twl4030_write_script_byte(address++, pmb_message & 0xff);
+	err |= twl4030_write_script_byte(address++, delay);
+	err |= twl4030_write_script_byte(address++, next);
+
+	return err;
+}
+
+static int __init twl4030_write_script(u8 address, struct triton_ins *script,
+					int len)
+{
+	int err = 0;
+
+	for (; len; len--, address++, script++) {
+		if (len == 1)
+			err |= twl4030_write_script_ins(address,
+							script->pmb_message,
+							script->delay,
+							END_OF_SCRIPT);
+		else
+			err |= twl4030_write_script_ins(address,
+							script->pmb_message,
+							script->delay,
+							address + 1);
+	}
+
+	return err;
+}
+
+static int __init config_sleep_wake_sequence(void)
+{
+	int err = 0;
+	u8 data;
+
+	/*
+	 * CLKREQ is pulled high on the 2430SDP, therefore, we need to take
+	 * it out of the HFCLKOUT DEV_GRP for P1 else HFCLKOUT can't be stopped.
+	 */
+
+	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
+				  0x20, R_HFCLKOUT_DEV_GRP);
+
+	/* Set ACTIVE to SLEEP SEQ address in T2 memory*/
+	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0x2B,
+				  R_SEQ_ADD_A2S);
+
+	/* Set SLEEP to ACTIVE SEQ address for P1 and P2 */
+	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0x2F,
+				  R_SEQ_ADD_SA12);
+
+	/* Set SLEEP to ACTIVE SEQ address for P3 */
+	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0x2F,
+				  R_SEQ_ADD_S2A3);
+
+	/* Install Active->Sleep (A2S) sequence */
+	err |= twl4030_write_script(0x2B, sleep_on_seq,
+					ARRAY_SIZE(sleep_on_seq));
+
+	/* Install Sleep->Active (S2A) sequence */
+	err |= twl4030_write_script(0x2F, sleep_off_seq,
+					ARRAY_SIZE(sleep_off_seq));
+
+#if defined(CONFIG_MACH_OMAP_3430SDP) || defined(CONFIG_MACH_OMAP_3430LABRADOR)
+	/* Disabling AC charger effect on sleep-active transitions */
+	err |= twl4030_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &data,
+					R_CFG_P1_TRANSITION);
+	data &= 0x0;
+	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, data ,
+					R_CFG_P1_TRANSITION);
+#endif
+	/* P1/P2/P3 LVL_WAKEUP should be on LEVEL */
+	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, LVL_WAKEUP,
+					R_P1_SW_EVENTS);
+	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, LVL_WAKEUP,
+					R_P2_SW_EVENTS);
+	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, LVL_WAKEUP,
+				R_P3_SW_EVENTS);
+
+	if (err)
+		printk(KERN_ERR "TWL4030 sleep-wake sequence config error\n");
+
+	return err;
+}
+
+
+/* Programming the WARMRESET Sequence on TRITON */
+static int __init config_warmreset_sequence(void)
+{
+
+	int e = 0;
+	u8 rd_data;
+
+	if (!ARRAY_SIZE(t2_wrst_seq))
+		return 0;
+
+	/* Set WARM RESET SEQ address for P1 */
+	e |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0x38,
+				R_SEQ_ADD_WARM);
+
+	/* Install Warm Reset sequence */
+	e |= twl4030_write_script(0x38, t2_wrst_seq,
+					ARRAY_SIZE(t2_wrst_seq));
+
+	/* P1/P2/P3 enable WARMRESET */
+	e |= twl4030_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &rd_data,
+				R_P1_SW_EVENTS);
+	rd_data |= ENABLE_WARMRESET;
+	e |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, rd_data,
+				R_P1_SW_EVENTS);
+
+	e |= twl4030_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &rd_data,
+				R_P2_SW_EVENTS);
+	rd_data |= ENABLE_WARMRESET;
+	e |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, rd_data,
+				R_P2_SW_EVENTS);
+
+	e |= twl4030_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &rd_data,
+				R_P3_SW_EVENTS);
+	rd_data |= ENABLE_WARMRESET;
+	e |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, rd_data,
+				R_P3_SW_EVENTS);
+
+	if (e)
+		printk(KERN_ERR
+			"TWL4030 Power Companion Warmreset seq config error\n");
+	return e;
+}
+
+static int __init twl4030_power_init(void)
+{
+	int err = 0;
+
+	err = twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, KEY_1,
+				R_PROTECT_KEY);
+	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, KEY_2,
+				R_PROTECT_KEY);
+
+	if (err)
+		return err;
+
+	err = config_sleep_wake_sequence();
+	if (err)
+		return err;
+
+	err = config_warmreset_sequence();
+	if (err)
+		return err;
+
+	err = twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0, R_PROTECT_KEY);
+
+	return err;
+
+}
+
+module_init(twl4030_power_init);
-- 
1.5.3.4

Re: [PATCH] Load triton2 scripts.

[Kalle Jokiniemi]

Hi Tony,

This patch should be safe to apply now as the sys off mode pin polarity
was fixed in the patch "Add early init for voltage controller
configuration and off mode polarity" (index a6cfc46..fc72c11 100644).

I compile & boot tested it on SDP board, on both plain master branch and
with Jouni's workarounds. Works for me.

regards,
Kalle

On ma, 2008-07-21 at 19:17 +0300, ext Peter 'p2' De Schrijver wrote: 
> Signed-off-by: Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com>
> ---
>  drivers/i2c/chips/Makefile        |    2 +-
>  drivers/i2c/chips/twl4030-power.c |  337 +++++++++++++++++++++++++++++++++++++
>  2 files changed, 338 insertions(+), 1 deletions(-)
>  create mode 100644 drivers/i2c/chips/twl4030-power.c
> 
> diff --git a/drivers/i2c/chips/Makefile b/drivers/i2c/chips/Makefile
> index 1f81ebd..a44e617 100644
> --- a/drivers/i2c/chips/Makefile
> +++ b/drivers/i2c/chips/Makefile
> @@ -23,7 +23,7 @@ obj-$(CONFIG_GPIOEXPANDER_OMAP)	+= gpio_expander_omap.o
>  obj-$(CONFIG_MENELAUS)		+= menelaus.o
>  obj-$(CONFIG_SENSORS_TSL2550)	+= tsl2550.o
>  obj-$(CONFIG_SENSORS_TSL2563)	+= tsl2563.o
> -obj-$(CONFIG_TWL4030_CORE)	+= twl4030-core.o twl4030-pwrirq.o
> +obj-$(CONFIG_TWL4030_CORE)	+= twl4030-core.o twl4030-pwrirq.o twl4030-power.o
>  obj-$(CONFIG_TWL4030_GPIO)	+= twl4030-gpio.o
>  obj-$(CONFIG_TWL4030_USB)	+= twl4030-usb.o
>  obj-$(CONFIG_TWL4030_POWEROFF)	+= twl4030-poweroff.o
> diff --git a/drivers/i2c/chips/twl4030-power.c b/drivers/i2c/chips/twl4030-power.c
> new file mode 100644
> index 0000000..195c3c4
> --- /dev/null
> +++ b/drivers/i2c/chips/twl4030-power.c
> @@ -0,0 +1,337 @@
> +/*
> + * linux/drivers/i2c/chips/twl4030-power.c
> + *
> + * Handle TWL4030 Power initialization
> + *
> + * Copyright (C) 2008 Nokia Corporation
> + * Copyright (C) 2006 Texas Instruments, Inc
> + *
> + * Written by 	Kalle Jokiniemi
> + *		Peter De Schrijver <peter.de-schrijver@nokia.com>
> + *
> + * This file is subject to the terms and conditions of the GNU General
> + * Public License. See the file "COPYING" in the main directory of this
> + * archive for more details.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
> + */
> +
> +#include <linux/module.h>
> +#include <linux/pm.h>
> +#include <linux/i2c/twl4030.h>
> +
> +#define PWR_P1_SW_EVENTS	0x10
> +#define PWR_DEVOFF	(1<<0)
> +
> +#define PHY_TO_OFF_PM_MASTER(p)		(p - 0x36)
> +#define PHY_TO_OFF_PM_RECIEVER(p)	(p - 0x5b)
> +
> +/* resource - hfclk */
> +#define R_HFCLKOUT_DEV_GRP 	PHY_TO_OFF_PM_RECIEVER(0xe6)
> +
> +/* PM events */
> +#define R_P1_SW_EVENTS		PHY_TO_OFF_PM_MASTER(0x46)
> +#define R_P2_SW_EVENTS		PHY_TO_OFF_PM_MASTER(0x47)
> +#define R_P3_SW_EVENTS		PHY_TO_OFF_PM_MASTER(0x48)
> +#define R_CFG_P1_TRANSITION	PHY_TO_OFF_PM_MASTER(0x36)
> +#define R_CFG_P2_TRANSITION	PHY_TO_OFF_PM_MASTER(0x37)
> +#define R_CFG_P3_TRANSITION	PHY_TO_OFF_PM_MASTER(0x38)
> +
> +#define LVL_WAKEUP	0x08
> +
> +#define ENABLE_WARMRESET (1<<4)
> +
> +/* sequence script */
> +
> +#define END_OF_SCRIPT		0x3f
> +
> +#define R_SEQ_ADD_A2S		PHY_TO_OFF_PM_MASTER(0x55)
> +#define R_SEQ_ADD_SA12		PHY_TO_OFF_PM_MASTER(0x56)
> +#define	R_SEQ_ADD_S2A3		PHY_TO_OFF_PM_MASTER(0x57)
> +#define	R_SEQ_ADD_WARM		PHY_TO_OFF_PM_MASTER(0x58)
> +#define R_MEMORY_ADDRESS	PHY_TO_OFF_PM_MASTER(0x59)
> +#define R_MEMORY_DATA		PHY_TO_OFF_PM_MASTER(0x5a)
> +
> +/* Power bus message definitions */
> +
> +#define DEV_GRP_NULL		0x0
> +#define DEV_GRP_P1		0x1
> +#define DEV_GRP_P2		0x2
> +#define DEV_GRP_P3		0x4
> +
> +#define RES_GRP_RES		0x0
> +#define RES_GRP_PP		0x1
> +#define RES_GRP_RC		0x2
> +#define RES_GRP_PP_RC		0x3
> +#define RES_GRP_PR		0x4
> +#define RES_GRP_PP_PR		0x5
> +#define RES_GRP_RC_PR		0x6
> +#define RES_GRP_ALL		0x7
> +
> +#define RES_TYPE2_R0		0x0
> +
> +#define RES_TYPE_ALL		0x7
> +
> +#define RES_STATE_WRST		0xF
> +#define RES_STATE_ACTIVE	0xE
> +#define RES_STATE_SLEEP		0x8
> +#define RES_STATE_OFF		0x0
> +
> +/*
> +*	Power Bus Message Format
> +*
> +*	Broadcast Message (16 Bits)
> +*	DEV_GRP[15:13] MT[12]  RES_GRP[11:9]  RES_TYPE2[8:7] RES_TYPE[6:4]
> +*	RES_STATE[3:0]
> +*
> +*	Singular Message (16 Bits)
> +*	DEV_GRP[15:13] MT[12]  RES_ID[11:4]  RES_STATE[3:0]
> +*
> +*/
> +
> +#define MSG_BROADCAST(devgrp, grp, type, type2, state) \
> +	(devgrp << 13 | 1 << 12 | grp << 9 | type2 << 7 | type << 4 | state)
> +
> +#define MSG_SINGULAR(devgrp, id, state) \
> +	(devgrp << 13 | 0 << 12 | id << 4 | state)
> +
> +#define R_PROTECT_KEY		0x0E
> +#define KEY_1			0xC0
> +#define KEY_2			0x0C
> +
> +struct triton_ins {
> +	u16 pmb_message;
> +	u8 delay;
> +};
> +
> +
> +#define CONFIG_DISABLE_HFCLK	1
> +
> +#if defined(CONFIG_MACH_OMAP_3430SDP) || defined(CONFIG_MACH_OMAP_3430LABRADOR)
> +
> +struct triton_ins sleep_on_seq[] __initdata = {
> +	{MSG_SINGULAR(DEV_GRP_P1, 0xf, RES_STATE_OFF), 4},
> +	{MSG_SINGULAR(DEV_GRP_P1, 0x10, RES_STATE_OFF), 2},
> +#ifdef CONFIG_DISABLE_HFCLK
> +	{MSG_SINGULAR(DEV_GRP_P1, 0x7, RES_STATE_OFF), 3},
> +	{MSG_SINGULAR(DEV_GRP_P1, 0x19, RES_STATE_OFF), 3},
> +#endif /* #ifdef CONFIG_DISABLE_HFCLK */
> +};
> +
> +struct triton_ins sleep_off_seq[] __initdata = {
> +#ifndef CONFIG_DISABLE_HFCLK
> +	{MSG_SINGULAR(DEV_GRP_P1, 0xf, RES_STATE_ACTIVE), 4},
> +	{MSG_SINGULAR(DEV_GRP_P1, 0x10, RES_STATE_ACTIVE), 2},
> +#else
> +	{MSG_SINGULAR(DEV_GRP_P1, 0x7, RES_STATE_ACTIVE), 0x30},
> +	{MSG_SINGULAR(DEV_GRP_P1, 0xf, RES_STATE_ACTIVE), 0x30},
> +	{MSG_SINGULAR(DEV_GRP_P1, 0x10, RES_STATE_ACTIVE), 0x37},
> +	{MSG_SINGULAR(DEV_GRP_P1, 0x19, RES_STATE_ACTIVE), 3},
> +#endif /* #ifndef CONFIG_DISABLE_HFCLK */
> +};
> +
> +struct triton_ins t2_wrst_seq[] __initdata = {
> +	{MSG_SINGULAR(DEV_GRP_NULL, 0x1b, RES_STATE_OFF), 2},
> +	{MSG_SINGULAR(DEV_GRP_P1, 0xf, RES_STATE_WRST), 15},
> +	{MSG_SINGULAR(DEV_GRP_P1, 0x10, RES_STATE_WRST), 15},
> +	{MSG_SINGULAR(DEV_GRP_P1, 0x7, RES_STATE_WRST), 0x60},
> +	{MSG_SINGULAR(DEV_GRP_P1, 0x19, RES_STATE_ACTIVE), 2},
> +	{MSG_SINGULAR(DEV_GRP_NULL, 0x1b, RES_STATE_ACTIVE), 2},
> +};
> +#else
> +struct triton_ins sleep_on_seq[] __initdata = {
> +	{MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_RC, RES_TYPE_ALL, RES_TYPE2_R0,
> +			RES_STATE_SLEEP), 4},
> +	{MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, RES_TYPE_ALL, RES_TYPE_R7,
> +			RES_STATE_SLEEP), 4},
> +};
> +
> +struct triton_ins sleep_off_seq[] __initdata = {
> +	{MSG_SINGULAR(DEV_GRP_NULL, 0x17, RES_STATE_ACTIVE), 0x30},
> +	{MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_PP_PR, RES_TYPE_ALL, RES_TYPE2_R0,
> +			RES_STATE_ACTIVE), 0x37},
> +	{MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, RES_TYPE_ALL, RES_TYPE2_R0,
> +			RES_STATE_ACTIVE), 0x2},
> +};
> +#endif
> +
> +static int __init twl4030_write_script_byte(u8 address, u8 byte)
> +{
> +	int err;
> +
> +	err = twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, address,
> +					R_MEMORY_ADDRESS);
> +	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, byte,
> +					R_MEMORY_DATA);
> +
> +	return err;
> +}
> +
> +static int __init twl4030_write_script_ins(u8 address, u16 pmb_message,
> +						u8 delay, u8 next)
> +{
> +	int err = 0;
> +
> +	address *= 4;
> +	err |= twl4030_write_script_byte(address++, pmb_message >> 8);
> +	err |= twl4030_write_script_byte(address++, pmb_message & 0xff);
> +	err |= twl4030_write_script_byte(address++, delay);
> +	err |= twl4030_write_script_byte(address++, next);
> +
> +	return err;
> +}
> +
> +static int __init twl4030_write_script(u8 address, struct triton_ins *script,
> +					int len)
> +{
> +	int err = 0;
> +
> +	for (; len; len--, address++, script++) {
> +		if (len == 1)
> +			err |= twl4030_write_script_ins(address,
> +							script->pmb_message,
> +							script->delay,
> +							END_OF_SCRIPT);
> +		else
> +			err |= twl4030_write_script_ins(address,
> +							script->pmb_message,
> +							script->delay,
> +							address + 1);
> +	}
> +
> +	return err;
> +}
> +
> +static int __init config_sleep_wake_sequence(void)
> +{
> +	int err = 0;
> +	u8 data;
> +
> +	/*
> +	 * CLKREQ is pulled high on the 2430SDP, therefore, we need to take
> +	 * it out of the HFCLKOUT DEV_GRP for P1 else HFCLKOUT can't be stopped.
> +	 */
> +
> +	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
> +				  0x20, R_HFCLKOUT_DEV_GRP);
> +
> +	/* Set ACTIVE to SLEEP SEQ address in T2 memory*/
> +	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0x2B,
> +				  R_SEQ_ADD_A2S);
> +
> +	/* Set SLEEP to ACTIVE SEQ address for P1 and P2 */
> +	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0x2F,
> +				  R_SEQ_ADD_SA12);
> +
> +	/* Set SLEEP to ACTIVE SEQ address for P3 */
> +	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0x2F,
> +				  R_SEQ_ADD_S2A3);
> +
> +	/* Install Active->Sleep (A2S) sequence */
> +	err |= twl4030_write_script(0x2B, sleep_on_seq,
> +					ARRAY_SIZE(sleep_on_seq));
> +
> +	/* Install Sleep->Active (S2A) sequence */
> +	err |= twl4030_write_script(0x2F, sleep_off_seq,
> +					ARRAY_SIZE(sleep_off_seq));
> +
> +#if defined(CONFIG_MACH_OMAP_3430SDP) || defined(CONFIG_MACH_OMAP_3430LABRADOR)
> +	/* Disabling AC charger effect on sleep-active transitions */
> +	err |= twl4030_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &data,
> +					R_CFG_P1_TRANSITION);
> +	data &= 0x0;
> +	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, data ,
> +					R_CFG_P1_TRANSITION);
> +#endif
> +	/* P1/P2/P3 LVL_WAKEUP should be on LEVEL */
> +	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, LVL_WAKEUP,
> +					R_P1_SW_EVENTS);
> +	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, LVL_WAKEUP,
> +					R_P2_SW_EVENTS);
> +	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, LVL_WAKEUP,
> +				R_P3_SW_EVENTS);
> +
> +	if (err)
> +		printk(KERN_ERR "TWL4030 sleep-wake sequence config error\n");
> +
> +	return err;
> +}
> +
> +
> +/* Programming the WARMRESET Sequence on TRITON */
> +static int __init config_warmreset_sequence(void)
> +{
> +
> +	int e = 0;
> +	u8 rd_data;
> +
> +	if (!ARRAY_SIZE(t2_wrst_seq))
> +		return 0;
> +
> +	/* Set WARM RESET SEQ address for P1 */
> +	e |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0x38,
> +				R_SEQ_ADD_WARM);
> +
> +	/* Install Warm Reset sequence */
> +	e |= twl4030_write_script(0x38, t2_wrst_seq,
> +					ARRAY_SIZE(t2_wrst_seq));
> +
> +	/* P1/P2/P3 enable WARMRESET */
> +	e |= twl4030_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &rd_data,
> +				R_P1_SW_EVENTS);
> +	rd_data |= ENABLE_WARMRESET;
> +	e |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, rd_data,
> +				R_P1_SW_EVENTS);
> +
> +	e |= twl4030_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &rd_data,
> +				R_P2_SW_EVENTS);
> +	rd_data |= ENABLE_WARMRESET;
> +	e |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, rd_data,
> +				R_P2_SW_EVENTS);
> +
> +	e |= twl4030_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &rd_data,
> +				R_P3_SW_EVENTS);
> +	rd_data |= ENABLE_WARMRESET;
> +	e |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, rd_data,
> +				R_P3_SW_EVENTS);
> +
> +	if (e)
> +		printk(KERN_ERR
> +			"TWL4030 Power Companion Warmreset seq config error\n");
> +	return e;
> +}
> +
> +static int __init twl4030_power_init(void)
> +{
> +	int err = 0;
> +
> +	err = twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, KEY_1,
> +				R_PROTECT_KEY);
> +	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, KEY_2,
> +				R_PROTECT_KEY);
> +
> +	if (err)
> +		return err;
> +
> +	err = config_sleep_wake_sequence();
> +	if (err)
> +		return err;
> +
> +	err = config_warmreset_sequence();
> +	if (err)
> +		return err;
> +
> +	err = twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0, R_PROTECT_KEY);
> +
> +	return err;
> +
> +}
> +
> +module_init(twl4030_power_init);

Re: [PATCH] Load triton2 scripts.

[Tony Lindgren]

* Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com> [080807 13:10]:
> Hi Tony,
> 
> This patch should be safe to apply now as the sys off mode pin polarity
> was fixed in the patch "Add early init for voltage controller
> configuration and off mode polarity" (index a6cfc46..fc72c11 100644).
> 
> I compile & boot tested it on SDP board, on both plain master branch and
> with Jouni's workarounds. Works for me.

Hmm, just to confirm... Isn't this one already applied modified with
commits 07667f11a9864671bcec35dd0ee36e47cb3f675c and
3238fb156cf77b537b2df8d897fe62a7feab4939? Can you please check and
let me know if something still needs to be patched.

Thanks,

Tony

> 
> regards,
> Kalle
> 
> On ma, 2008-07-21 at 19:17 +0300, ext Peter 'p2' De Schrijver wrote: 
> > Signed-off-by: Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com>
> > ---
> >  drivers/i2c/chips/Makefile        |    2 +-
> >  drivers/i2c/chips/twl4030-power.c |  337 +++++++++++++++++++++++++++++++++++++
> >  2 files changed, 338 insertions(+), 1 deletions(-)
> >  create mode 100644 drivers/i2c/chips/twl4030-power.c
> > 
> > diff --git a/drivers/i2c/chips/Makefile b/drivers/i2c/chips/Makefile
> > index 1f81ebd..a44e617 100644
> > --- a/drivers/i2c/chips/Makefile
> > +++ b/drivers/i2c/chips/Makefile
> > @@ -23,7 +23,7 @@ obj-$(CONFIG_GPIOEXPANDER_OMAP)	+= gpio_expander_omap.o
> >  obj-$(CONFIG_MENELAUS)		+= menelaus.o
> >  obj-$(CONFIG_SENSORS_TSL2550)	+= tsl2550.o
> >  obj-$(CONFIG_SENSORS_TSL2563)	+= tsl2563.o
> > -obj-$(CONFIG_TWL4030_CORE)	+= twl4030-core.o twl4030-pwrirq.o
> > +obj-$(CONFIG_TWL4030_CORE)	+= twl4030-core.o twl4030-pwrirq.o twl4030-power.o
> >  obj-$(CONFIG_TWL4030_GPIO)	+= twl4030-gpio.o
> >  obj-$(CONFIG_TWL4030_USB)	+= twl4030-usb.o
> >  obj-$(CONFIG_TWL4030_POWEROFF)	+= twl4030-poweroff.o
> > diff --git a/drivers/i2c/chips/twl4030-power.c b/drivers/i2c/chips/twl4030-power.c
> > new file mode 100644
> > index 0000000..195c3c4
> > --- /dev/null
> > +++ b/drivers/i2c/chips/twl4030-power.c
> > @@ -0,0 +1,337 @@
> > +/*
> > + * linux/drivers/i2c/chips/twl4030-power.c
> > + *
> > + * Handle TWL4030 Power initialization
> > + *
> > + * Copyright (C) 2008 Nokia Corporation
> > + * Copyright (C) 2006 Texas Instruments, Inc
> > + *
> > + * Written by 	Kalle Jokiniemi
> > + *		Peter De Schrijver <peter.de-schrijver@nokia.com>
> > + *
> > + * This file is subject to the terms and conditions of the GNU General
> > + * Public License. See the file "COPYING" in the main directory of this
> > + * archive for more details.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> > + * along with this program; if not, write to the Free Software
> > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
> > + */
> > +
> > +#include <linux/module.h>
> > +#include <linux/pm.h>
> > +#include <linux/i2c/twl4030.h>
> > +
> > +#define PWR_P1_SW_EVENTS	0x10
> > +#define PWR_DEVOFF	(1<<0)
> > +
> > +#define PHY_TO_OFF_PM_MASTER(p)		(p - 0x36)
> > +#define PHY_TO_OFF_PM_RECIEVER(p)	(p - 0x5b)
> > +
> > +/* resource - hfclk */
> > +#define R_HFCLKOUT_DEV_GRP 	PHY_TO_OFF_PM_RECIEVER(0xe6)
> > +
> > +/* PM events */
> > +#define R_P1_SW_EVENTS		PHY_TO_OFF_PM_MASTER(0x46)
> > +#define R_P2_SW_EVENTS		PHY_TO_OFF_PM_MASTER(0x47)
> > +#define R_P3_SW_EVENTS		PHY_TO_OFF_PM_MASTER(0x48)
> > +#define R_CFG_P1_TRANSITION	PHY_TO_OFF_PM_MASTER(0x36)
> > +#define R_CFG_P2_TRANSITION	PHY_TO_OFF_PM_MASTER(0x37)
> > +#define R_CFG_P3_TRANSITION	PHY_TO_OFF_PM_MASTER(0x38)
> > +
> > +#define LVL_WAKEUP	0x08
> > +
> > +#define ENABLE_WARMRESET (1<<4)
> > +
> > +/* sequence script */
> > +
> > +#define END_OF_SCRIPT		0x3f
> > +
> > +#define R_SEQ_ADD_A2S		PHY_TO_OFF_PM_MASTER(0x55)
> > +#define R_SEQ_ADD_SA12		PHY_TO_OFF_PM_MASTER(0x56)
> > +#define	R_SEQ_ADD_S2A3		PHY_TO_OFF_PM_MASTER(0x57)
> > +#define	R_SEQ_ADD_WARM		PHY_TO_OFF_PM_MASTER(0x58)
> > +#define R_MEMORY_ADDRESS	PHY_TO_OFF_PM_MASTER(0x59)
> > +#define R_MEMORY_DATA		PHY_TO_OFF_PM_MASTER(0x5a)
> > +
> > +/* Power bus message definitions */
> > +
> > +#define DEV_GRP_NULL		0x0
> > +#define DEV_GRP_P1		0x1
> > +#define DEV_GRP_P2		0x2
> > +#define DEV_GRP_P3		0x4
> > +
> > +#define RES_GRP_RES		0x0
> > +#define RES_GRP_PP		0x1
> > +#define RES_GRP_RC		0x2
> > +#define RES_GRP_PP_RC		0x3
> > +#define RES_GRP_PR		0x4
> > +#define RES_GRP_PP_PR		0x5
> > +#define RES_GRP_RC_PR		0x6
> > +#define RES_GRP_ALL		0x7
> > +
> > +#define RES_TYPE2_R0		0x0
> > +
> > +#define RES_TYPE_ALL		0x7
> > +
> > +#define RES_STATE_WRST		0xF
> > +#define RES_STATE_ACTIVE	0xE
> > +#define RES_STATE_SLEEP		0x8
> > +#define RES_STATE_OFF		0x0
> > +
> > +/*
> > +*	Power Bus Message Format
> > +*
> > +*	Broadcast Message (16 Bits)
> > +*	DEV_GRP[15:13] MT[12]  RES_GRP[11:9]  RES_TYPE2[8:7] RES_TYPE[6:4]
> > +*	RES_STATE[3:0]
> > +*
> > +*	Singular Message (16 Bits)
> > +*	DEV_GRP[15:13] MT[12]  RES_ID[11:4]  RES_STATE[3:0]
> > +*
> > +*/
> > +
> > +#define MSG_BROADCAST(devgrp, grp, type, type2, state) \
> > +	(devgrp << 13 | 1 << 12 | grp << 9 | type2 << 7 | type << 4 | state)
> > +
> > +#define MSG_SINGULAR(devgrp, id, state) \
> > +	(devgrp << 13 | 0 << 12 | id << 4 | state)
> > +
> > +#define R_PROTECT_KEY		0x0E
> > +#define KEY_1			0xC0
> > +#define KEY_2			0x0C
> > +
> > +struct triton_ins {
> > +	u16 pmb_message;
> > +	u8 delay;
> > +};
> > +
> > +
> > +#define CONFIG_DISABLE_HFCLK	1
> > +
> > +#if defined(CONFIG_MACH_OMAP_3430SDP) || defined(CONFIG_MACH_OMAP_3430LABRADOR)
> > +
> > +struct triton_ins sleep_on_seq[] __initdata = {
> > +	{MSG_SINGULAR(DEV_GRP_P1, 0xf, RES_STATE_OFF), 4},
> > +	{MSG_SINGULAR(DEV_GRP_P1, 0x10, RES_STATE_OFF), 2},
> > +#ifdef CONFIG_DISABLE_HFCLK
> > +	{MSG_SINGULAR(DEV_GRP_P1, 0x7, RES_STATE_OFF), 3},
> > +	{MSG_SINGULAR(DEV_GRP_P1, 0x19, RES_STATE_OFF), 3},
> > +#endif /* #ifdef CONFIG_DISABLE_HFCLK */
> > +};
> > +
> > +struct triton_ins sleep_off_seq[] __initdata = {
> > +#ifndef CONFIG_DISABLE_HFCLK
> > +	{MSG_SINGULAR(DEV_GRP_P1, 0xf, RES_STATE_ACTIVE), 4},
> > +	{MSG_SINGULAR(DEV_GRP_P1, 0x10, RES_STATE_ACTIVE), 2},
> > +#else
> > +	{MSG_SINGULAR(DEV_GRP_P1, 0x7, RES_STATE_ACTIVE), 0x30},
> > +	{MSG_SINGULAR(DEV_GRP_P1, 0xf, RES_STATE_ACTIVE), 0x30},
> > +	{MSG_SINGULAR(DEV_GRP_P1, 0x10, RES_STATE_ACTIVE), 0x37},
> > +	{MSG_SINGULAR(DEV_GRP_P1, 0x19, RES_STATE_ACTIVE), 3},
> > +#endif /* #ifndef CONFIG_DISABLE_HFCLK */
> > +};
> > +
> > +struct triton_ins t2_wrst_seq[] __initdata = {
> > +	{MSG_SINGULAR(DEV_GRP_NULL, 0x1b, RES_STATE_OFF), 2},
> > +	{MSG_SINGULAR(DEV_GRP_P1, 0xf, RES_STATE_WRST), 15},
> > +	{MSG_SINGULAR(DEV_GRP_P1, 0x10, RES_STATE_WRST), 15},
> > +	{MSG_SINGULAR(DEV_GRP_P1, 0x7, RES_STATE_WRST), 0x60},
> > +	{MSG_SINGULAR(DEV_GRP_P1, 0x19, RES_STATE_ACTIVE), 2},
> > +	{MSG_SINGULAR(DEV_GRP_NULL, 0x1b, RES_STATE_ACTIVE), 2},
> > +};
> > +#else
> > +struct triton_ins sleep_on_seq[] __initdata = {
> > +	{MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_RC, RES_TYPE_ALL, RES_TYPE2_R0,
> > +			RES_STATE_SLEEP), 4},
> > +	{MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, RES_TYPE_ALL, RES_TYPE_R7,
> > +			RES_STATE_SLEEP), 4},
> > +};
> > +
> > +struct triton_ins sleep_off_seq[] __initdata = {
> > +	{MSG_SINGULAR(DEV_GRP_NULL, 0x17, RES_STATE_ACTIVE), 0x30},
> > +	{MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_PP_PR, RES_TYPE_ALL, RES_TYPE2_R0,
> > +			RES_STATE_ACTIVE), 0x37},
> > +	{MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, RES_TYPE_ALL, RES_TYPE2_R0,
> > +			RES_STATE_ACTIVE), 0x2},
> > +};
> > +#endif
> > +
> > +static int __init twl4030_write_script_byte(u8 address, u8 byte)
> > +{
> > +	int err;
> > +
> > +	err = twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, address,
> > +					R_MEMORY_ADDRESS);
> > +	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, byte,
> > +					R_MEMORY_DATA);
> > +
> > +	return err;
> > +}
> > +
> > +static int __init twl4030_write_script_ins(u8 address, u16 pmb_message,
> > +						u8 delay, u8 next)
> > +{
> > +	int err = 0;
> > +
> > +	address *= 4;
> > +	err |= twl4030_write_script_byte(address++, pmb_message >> 8);
> > +	err |= twl4030_write_script_byte(address++, pmb_message & 0xff);
> > +	err |= twl4030_write_script_byte(address++, delay);
> > +	err |= twl4030_write_script_byte(address++, next);
> > +
> > +	return err;
> > +}
> > +
> > +static int __init twl4030_write_script(u8 address, struct triton_ins *script,
> > +					int len)
> > +{
> > +	int err = 0;
> > +
> > +	for (; len; len--, address++, script++) {
> > +		if (len == 1)
> > +			err |= twl4030_write_script_ins(address,
> > +							script->pmb_message,
> > +							script->delay,
> > +							END_OF_SCRIPT);
> > +		else
> > +			err |= twl4030_write_script_ins(address,
> > +							script->pmb_message,
> > +							script->delay,
> > +							address + 1);
> > +	}
> > +
> > +	return err;
> > +}
> > +
> > +static int __init config_sleep_wake_sequence(void)
> > +{
> > +	int err = 0;
> > +	u8 data;
> > +
> > +	/*
> > +	 * CLKREQ is pulled high on the 2430SDP, therefore, we need to take
> > +	 * it out of the HFCLKOUT DEV_GRP for P1 else HFCLKOUT can't be stopped.
> > +	 */
> > +
> > +	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
> > +				  0x20, R_HFCLKOUT_DEV_GRP);
> > +
> > +	/* Set ACTIVE to SLEEP SEQ address in T2 memory*/
> > +	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0x2B,
> > +				  R_SEQ_ADD_A2S);
> > +
> > +	/* Set SLEEP to ACTIVE SEQ address for P1 and P2 */
> > +	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0x2F,
> > +				  R_SEQ_ADD_SA12);
> > +
> > +	/* Set SLEEP to ACTIVE SEQ address for P3 */
> > +	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0x2F,
> > +				  R_SEQ_ADD_S2A3);
> > +
> > +	/* Install Active->Sleep (A2S) sequence */
> > +	err |= twl4030_write_script(0x2B, sleep_on_seq,
> > +					ARRAY_SIZE(sleep_on_seq));
> > +
> > +	/* Install Sleep->Active (S2A) sequence */
> > +	err |= twl4030_write_script(0x2F, sleep_off_seq,
> > +					ARRAY_SIZE(sleep_off_seq));
> > +
> > +#if defined(CONFIG_MACH_OMAP_3430SDP) || defined(CONFIG_MACH_OMAP_3430LABRADOR)
> > +	/* Disabling AC charger effect on sleep-active transitions */
> > +	err |= twl4030_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &data,
> > +					R_CFG_P1_TRANSITION);
> > +	data &= 0x0;
> > +	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, data ,
> > +					R_CFG_P1_TRANSITION);
> > +#endif
> > +	/* P1/P2/P3 LVL_WAKEUP should be on LEVEL */
> > +	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, LVL_WAKEUP,
> > +					R_P1_SW_EVENTS);
> > +	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, LVL_WAKEUP,
> > +					R_P2_SW_EVENTS);
> > +	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, LVL_WAKEUP,
> > +				R_P3_SW_EVENTS);
> > +
> > +	if (err)
> > +		printk(KERN_ERR "TWL4030 sleep-wake sequence config error\n");
> > +
> > +	return err;
> > +}
> > +
> > +
> > +/* Programming the WARMRESET Sequence on TRITON */
> > +static int __init config_warmreset_sequence(void)
> > +{
> > +
> > +	int e = 0;
> > +	u8 rd_data;
> > +
> > +	if (!ARRAY_SIZE(t2_wrst_seq))
> > +		return 0;
> > +
> > +	/* Set WARM RESET SEQ address for P1 */
> > +	e |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0x38,
> > +				R_SEQ_ADD_WARM);
> > +
> > +	/* Install Warm Reset sequence */
> > +	e |= twl4030_write_script(0x38, t2_wrst_seq,
> > +					ARRAY_SIZE(t2_wrst_seq));
> > +
> > +	/* P1/P2/P3 enable WARMRESET */
> > +	e |= twl4030_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &rd_data,
> > +				R_P1_SW_EVENTS);
> > +	rd_data |= ENABLE_WARMRESET;
> > +	e |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, rd_data,
> > +				R_P1_SW_EVENTS);
> > +
> > +	e |= twl4030_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &rd_data,
> > +				R_P2_SW_EVENTS);
> > +	rd_data |= ENABLE_WARMRESET;
> > +	e |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, rd_data,
> > +				R_P2_SW_EVENTS);
> > +
> > +	e |= twl4030_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &rd_data,
> > +				R_P3_SW_EVENTS);
> > +	rd_data |= ENABLE_WARMRESET;
> > +	e |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, rd_data,
> > +				R_P3_SW_EVENTS);
> > +
> > +	if (e)
> > +		printk(KERN_ERR
> > +			"TWL4030 Power Companion Warmreset seq config error\n");
> > +	return e;
> > +}
> > +
> > +static int __init twl4030_power_init(void)
> > +{
> > +	int err = 0;
> > +
> > +	err = twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, KEY_1,
> > +				R_PROTECT_KEY);
> > +	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, KEY_2,
> > +				R_PROTECT_KEY);
> > +
> > +	if (err)
> > +		return err;
> > +
> > +	err = config_sleep_wake_sequence();
> > +	if (err)
> > +		return err;
> > +
> > +	err = config_warmreset_sequence();
> > +	if (err)
> > +		return err;
> > +
> > +	err = twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0, R_PROTECT_KEY);
> > +
> > +	return err;
> > +
> > +}
> > +
> > +module_init(twl4030_power_init);

Re: [PATCH] Load triton2 scripts.

[Kalle Jokiniemi]

On ma, 2008-08-18 at 16:31 +0300, ext Tony Lindgren wrote:
> * Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com> [080807 13:10]:
> > Hi Tony,
> > 
> > This patch should be safe to apply now as the sys off mode pin polarity
> > was fixed in the patch "Add early init for voltage controller
> > configuration and off mode polarity" (index a6cfc46..fc72c11 100644).
> > 
> > I compile & boot tested it on SDP board, on both plain master branch and
> > with Jouni's workarounds. Works for me.
> 
> Hmm, just to confirm... Isn't this one already applied modified with
> commits 07667f11a9864671bcec35dd0ee36e47cb3f675c and
> 3238fb156cf77b537b2df8d897fe62a7feab4939? Can you please check and
> let me know if something still needs to be patched.

I checked. No, those patches do not apply the triton2 script loading.
They configure the voltage controller and set the off-mode polarity,
which are needed before applying the triton script loading patch.

So you still need to apply the "Load triton2 scripts" patch sent by
Peter De Schrijver. If you wish, I can resend it.

regards,
Kalle


> 
> Thanks,
> 
> Tony
> 
> > 
> > regards,
> > Kalle
> > 
> > On ma, 2008-07-21 at 19:17 +0300, ext Peter 'p2' De Schrijver wrote: 
> > > Signed-off-by: Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com>
> > > ---
> > >  drivers/i2c/chips/Makefile        |    2 +-
> > >  drivers/i2c/chips/twl4030-power.c |  337 +++++++++++++++++++++++++++++++++++++
> > >  2 files changed, 338 insertions(+), 1 deletions(-)
> > >  create mode 100644 drivers/i2c/chips/twl4030-power.c
> > > 
> > > diff --git a/drivers/i2c/chips/Makefile b/drivers/i2c/chips/Makefile
> > > index 1f81ebd..a44e617 100644
> > > --- a/drivers/i2c/chips/Makefile
> > > +++ b/drivers/i2c/chips/Makefile
> > > @@ -23,7 +23,7 @@ obj-$(CONFIG_GPIOEXPANDER_OMAP)	+= gpio_expander_omap.o
> > >  obj-$(CONFIG_MENELAUS)		+= menelaus.o
> > >  obj-$(CONFIG_SENSORS_TSL2550)	+= tsl2550.o
> > >  obj-$(CONFIG_SENSORS_TSL2563)	+= tsl2563.o
> > > -obj-$(CONFIG_TWL4030_CORE)	+= twl4030-core.o twl4030-pwrirq.o
> > > +obj-$(CONFIG_TWL4030_CORE)	+= twl4030-core.o twl4030-pwrirq.o twl4030-power.o
> > >  obj-$(CONFIG_TWL4030_GPIO)	+= twl4030-gpio.o
> > >  obj-$(CONFIG_TWL4030_USB)	+= twl4030-usb.o
> > >  obj-$(CONFIG_TWL4030_POWEROFF)	+= twl4030-poweroff.o
> > > diff --git a/drivers/i2c/chips/twl4030-power.c b/drivers/i2c/chips/twl4030-power.c
> > > new file mode 100644
> > > index 0000000..195c3c4
> > > --- /dev/null
> > > +++ b/drivers/i2c/chips/twl4030-power.c
> > > @@ -0,0 +1,337 @@
> > > +/*
> > > + * linux/drivers/i2c/chips/twl4030-power.c
> > > + *
> > > + * Handle TWL4030 Power initialization
> > > + *
> > > + * Copyright (C) 2008 Nokia Corporation
> > > + * Copyright (C) 2006 Texas Instruments, Inc
> > > + *
> > > + * Written by 	Kalle Jokiniemi
> > > + *		Peter De Schrijver <peter.de-schrijver@nokia.com>
> > > + *
> > > + * This file is subject to the terms and conditions of the GNU General
> > > + * Public License. See the file "COPYING" in the main directory of this
> > > + * archive for more details.
> > > + *
> > > + * This program is distributed in the hope that it will be useful,
> > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > > + * GNU General Public License for more details.
> > > + *
> > > + * You should have received a copy of the GNU General Public License
> > > + * along with this program; if not, write to the Free Software
> > > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
> > > + */
> > > +
> > > +#include <linux/module.h>
> > > +#include <linux/pm.h>
> > > +#include <linux/i2c/twl4030.h>
> > > +
> > > +#define PWR_P1_SW_EVENTS	0x10
> > > +#define PWR_DEVOFF	(1<<0)
> > > +
> > > +#define PHY_TO_OFF_PM_MASTER(p)		(p - 0x36)
> > > +#define PHY_TO_OFF_PM_RECIEVER(p)	(p - 0x5b)
> > > +
> > > +/* resource - hfclk */
> > > +#define R_HFCLKOUT_DEV_GRP 	PHY_TO_OFF_PM_RECIEVER(0xe6)
> > > +
> > > +/* PM events */
> > > +#define R_P1_SW_EVENTS		PHY_TO_OFF_PM_MASTER(0x46)
> > > +#define R_P2_SW_EVENTS		PHY_TO_OFF_PM_MASTER(0x47)
> > > +#define R_P3_SW_EVENTS		PHY_TO_OFF_PM_MASTER(0x48)
> > > +#define R_CFG_P1_TRANSITION	PHY_TO_OFF_PM_MASTER(0x36)
> > > +#define R_CFG_P2_TRANSITION	PHY_TO_OFF_PM_MASTER(0x37)
> > > +#define R_CFG_P3_TRANSITION	PHY_TO_OFF_PM_MASTER(0x38)
> > > +
> > > +#define LVL_WAKEUP	0x08
> > > +
> > > +#define ENABLE_WARMRESET (1<<4)
> > > +
> > > +/* sequence script */
> > > +
> > > +#define END_OF_SCRIPT		0x3f
> > > +
> > > +#define R_SEQ_ADD_A2S		PHY_TO_OFF_PM_MASTER(0x55)
> > > +#define R_SEQ_ADD_SA12		PHY_TO_OFF_PM_MASTER(0x56)
> > > +#define	R_SEQ_ADD_S2A3		PHY_TO_OFF_PM_MASTER(0x57)
> > > +#define	R_SEQ_ADD_WARM		PHY_TO_OFF_PM_MASTER(0x58)
> > > +#define R_MEMORY_ADDRESS	PHY_TO_OFF_PM_MASTER(0x59)
> > > +#define R_MEMORY_DATA		PHY_TO_OFF_PM_MASTER(0x5a)
> > > +
> > > +/* Power bus message definitions */
> > > +
> > > +#define DEV_GRP_NULL		0x0
> > > +#define DEV_GRP_P1		0x1
> > > +#define DEV_GRP_P2		0x2
> > > +#define DEV_GRP_P3		0x4
> > > +
> > > +#define RES_GRP_RES		0x0
> > > +#define RES_GRP_PP		0x1
> > > +#define RES_GRP_RC		0x2
> > > +#define RES_GRP_PP_RC		0x3
> > > +#define RES_GRP_PR		0x4
> > > +#define RES_GRP_PP_PR		0x5
> > > +#define RES_GRP_RC_PR		0x6
> > > +#define RES_GRP_ALL		0x7
> > > +
> > > +#define RES_TYPE2_R0		0x0
> > > +
> > > +#define RES_TYPE_ALL		0x7
> > > +
> > > +#define RES_STATE_WRST		0xF
> > > +#define RES_STATE_ACTIVE	0xE
> > > +#define RES_STATE_SLEEP		0x8
> > > +#define RES_STATE_OFF		0x0
> > > +
> > > +/*
> > > +*	Power Bus Message Format
> > > +*
> > > +*	Broadcast Message (16 Bits)
> > > +*	DEV_GRP[15:13] MT[12]  RES_GRP[11:9]  RES_TYPE2[8:7] RES_TYPE[6:4]
> > > +*	RES_STATE[3:0]
> > > +*
> > > +*	Singular Message (16 Bits)
> > > +*	DEV_GRP[15:13] MT[12]  RES_ID[11:4]  RES_STATE[3:0]
> > > +*
> > > +*/
> > > +
> > > +#define MSG_BROADCAST(devgrp, grp, type, type2, state) \
> > > +	(devgrp << 13 | 1 << 12 | grp << 9 | type2 << 7 | type << 4 | state)
> > > +
> > > +#define MSG_SINGULAR(devgrp, id, state) \
> > > +	(devgrp << 13 | 0 << 12 | id << 4 | state)
> > > +
> > > +#define R_PROTECT_KEY		0x0E
> > > +#define KEY_1			0xC0
> > > +#define KEY_2			0x0C
> > > +
> > > +struct triton_ins {
> > > +	u16 pmb_message;
> > > +	u8 delay;
> > > +};
> > > +
> > > +
> > > +#define CONFIG_DISABLE_HFCLK	1
> > > +
> > > +#if defined(CONFIG_MACH_OMAP_3430SDP) || defined(CONFIG_MACH_OMAP_3430LABRADOR)
> > > +
> > > +struct triton_ins sleep_on_seq[] __initdata = {
> > > +	{MSG_SINGULAR(DEV_GRP_P1, 0xf, RES_STATE_OFF), 4},
> > > +	{MSG_SINGULAR(DEV_GRP_P1, 0x10, RES_STATE_OFF), 2},
> > > +#ifdef CONFIG_DISABLE_HFCLK
> > > +	{MSG_SINGULAR(DEV_GRP_P1, 0x7, RES_STATE_OFF), 3},
> > > +	{MSG_SINGULAR(DEV_GRP_P1, 0x19, RES_STATE_OFF), 3},
> > > +#endif /* #ifdef CONFIG_DISABLE_HFCLK */
> > > +};
> > > +
> > > +struct triton_ins sleep_off_seq[] __initdata = {
> > > +#ifndef CONFIG_DISABLE_HFCLK
> > > +	{MSG_SINGULAR(DEV_GRP_P1, 0xf, RES_STATE_ACTIVE), 4},
> > > +	{MSG_SINGULAR(DEV_GRP_P1, 0x10, RES_STATE_ACTIVE), 2},
> > > +#else
> > > +	{MSG_SINGULAR(DEV_GRP_P1, 0x7, RES_STATE_ACTIVE), 0x30},
> > > +	{MSG_SINGULAR(DEV_GRP_P1, 0xf, RES_STATE_ACTIVE), 0x30},
> > > +	{MSG_SINGULAR(DEV_GRP_P1, 0x10, RES_STATE_ACTIVE), 0x37},
> > > +	{MSG_SINGULAR(DEV_GRP_P1, 0x19, RES_STATE_ACTIVE), 3},
> > > +#endif /* #ifndef CONFIG_DISABLE_HFCLK */
> > > +};
> > > +
> > > +struct triton_ins t2_wrst_seq[] __initdata = {
> > > +	{MSG_SINGULAR(DEV_GRP_NULL, 0x1b, RES_STATE_OFF), 2},
> > > +	{MSG_SINGULAR(DEV_GRP_P1, 0xf, RES_STATE_WRST), 15},
> > > +	{MSG_SINGULAR(DEV_GRP_P1, 0x10, RES_STATE_WRST), 15},
> > > +	{MSG_SINGULAR(DEV_GRP_P1, 0x7, RES_STATE_WRST), 0x60},
> > > +	{MSG_SINGULAR(DEV_GRP_P1, 0x19, RES_STATE_ACTIVE), 2},
> > > +	{MSG_SINGULAR(DEV_GRP_NULL, 0x1b, RES_STATE_ACTIVE), 2},
> > > +};
> > > +#else
> > > +struct triton_ins sleep_on_seq[] __initdata = {
> > > +	{MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_RC, RES_TYPE_ALL, RES_TYPE2_R0,
> > > +			RES_STATE_SLEEP), 4},
> > > +	{MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, RES_TYPE_ALL, RES_TYPE_R7,
> > > +			RES_STATE_SLEEP), 4},
> > > +};
> > > +
> > > +struct triton_ins sleep_off_seq[] __initdata = {
> > > +	{MSG_SINGULAR(DEV_GRP_NULL, 0x17, RES_STATE_ACTIVE), 0x30},
> > > +	{MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_PP_PR, RES_TYPE_ALL, RES_TYPE2_R0,
> > > +			RES_STATE_ACTIVE), 0x37},
> > > +	{MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, RES_TYPE_ALL, RES_TYPE2_R0,
> > > +			RES_STATE_ACTIVE), 0x2},
> > > +};
> > > +#endif
> > > +
> > > +static int __init twl4030_write_script_byte(u8 address, u8 byte)
> > > +{
> > > +	int err;
> > > +
> > > +	err = twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, address,
> > > +					R_MEMORY_ADDRESS);
> > > +	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, byte,
> > > +					R_MEMORY_DATA);
> > > +
> > > +	return err;
> > > +}
> > > +
> > > +static int __init twl4030_write_script_ins(u8 address, u16 pmb_message,
> > > +						u8 delay, u8 next)
> > > +{
> > > +	int err = 0;
> > > +
> > > +	address *= 4;
> > > +	err |= twl4030_write_script_byte(address++, pmb_message >> 8);
> > > +	err |= twl4030_write_script_byte(address++, pmb_message & 0xff);
> > > +	err |= twl4030_write_script_byte(address++, delay);
> > > +	err |= twl4030_write_script_byte(address++, next);
> > > +
> > > +	return err;
> > > +}
> > > +
> > > +static int __init twl4030_write_script(u8 address, struct triton_ins *script,
> > > +					int len)
> > > +{
> > > +	int err = 0;
> > > +
> > > +	for (; len; len--, address++, script++) {
> > > +		if (len == 1)
> > > +			err |= twl4030_write_script_ins(address,
> > > +							script->pmb_message,
> > > +							script->delay,
> > > +							END_OF_SCRIPT);
> > > +		else
> > > +			err |= twl4030_write_script_ins(address,
> > > +							script->pmb_message,
> > > +							script->delay,
> > > +							address + 1);
> > > +	}
> > > +
> > > +	return err;
> > > +}
> > > +
> > > +static int __init config_sleep_wake_sequence(void)
> > > +{
> > > +	int err = 0;
> > > +	u8 data;
> > > +
> > > +	/*
> > > +	 * CLKREQ is pulled high on the 2430SDP, therefore, we need to take
> > > +	 * it out of the HFCLKOUT DEV_GRP for P1 else HFCLKOUT can't be stopped.
> > > +	 */
> > > +
> > > +	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
> > > +				  0x20, R_HFCLKOUT_DEV_GRP);
> > > +
> > > +	/* Set ACTIVE to SLEEP SEQ address in T2 memory*/
> > > +	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0x2B,
> > > +				  R_SEQ_ADD_A2S);
> > > +
> > > +	/* Set SLEEP to ACTIVE SEQ address for P1 and P2 */
> > > +	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0x2F,
> > > +				  R_SEQ_ADD_SA12);
> > > +
> > > +	/* Set SLEEP to ACTIVE SEQ address for P3 */
> > > +	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0x2F,
> > > +				  R_SEQ_ADD_S2A3);
> > > +
> > > +	/* Install Active->Sleep (A2S) sequence */
> > > +	err |= twl4030_write_script(0x2B, sleep_on_seq,
> > > +					ARRAY_SIZE(sleep_on_seq));
> > > +
> > > +	/* Install Sleep->Active (S2A) sequence */
> > > +	err |= twl4030_write_script(0x2F, sleep_off_seq,
> > > +					ARRAY_SIZE(sleep_off_seq));
> > > +
> > > +#if defined(CONFIG_MACH_OMAP_3430SDP) || defined(CONFIG_MACH_OMAP_3430LABRADOR)
> > > +	/* Disabling AC charger effect on sleep-active transitions */
> > > +	err |= twl4030_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &data,
> > > +					R_CFG_P1_TRANSITION);
> > > +	data &= 0x0;
> > > +	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, data ,
> > > +					R_CFG_P1_TRANSITION);
> > > +#endif
> > > +	/* P1/P2/P3 LVL_WAKEUP should be on LEVEL */
> > > +	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, LVL_WAKEUP,
> > > +					R_P1_SW_EVENTS);
> > > +	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, LVL_WAKEUP,
> > > +					R_P2_SW_EVENTS);
> > > +	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, LVL_WAKEUP,
> > > +				R_P3_SW_EVENTS);
> > > +
> > > +	if (err)
> > > +		printk(KERN_ERR "TWL4030 sleep-wake sequence config error\n");
> > > +
> > > +	return err;
> > > +}
> > > +
> > > +
> > > +/* Programming the WARMRESET Sequence on TRITON */
> > > +static int __init config_warmreset_sequence(void)
> > > +{
> > > +
> > > +	int e = 0;
> > > +	u8 rd_data;
> > > +
> > > +	if (!ARRAY_SIZE(t2_wrst_seq))
> > > +		return 0;
> > > +
> > > +	/* Set WARM RESET SEQ address for P1 */
> > > +	e |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0x38,
> > > +				R_SEQ_ADD_WARM);
> > > +
> > > +	/* Install Warm Reset sequence */
> > > +	e |= twl4030_write_script(0x38, t2_wrst_seq,
> > > +					ARRAY_SIZE(t2_wrst_seq));
> > > +
> > > +	/* P1/P2/P3 enable WARMRESET */
> > > +	e |= twl4030_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &rd_data,
> > > +				R_P1_SW_EVENTS);
> > > +	rd_data |= ENABLE_WARMRESET;
> > > +	e |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, rd_data,
> > > +				R_P1_SW_EVENTS);
> > > +
> > > +	e |= twl4030_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &rd_data,
> > > +				R_P2_SW_EVENTS);
> > > +	rd_data |= ENABLE_WARMRESET;
> > > +	e |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, rd_data,
> > > +				R_P2_SW_EVENTS);
> > > +
> > > +	e |= twl4030_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &rd_data,
> > > +				R_P3_SW_EVENTS);
> > > +	rd_data |= ENABLE_WARMRESET;
> > > +	e |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, rd_data,
> > > +				R_P3_SW_EVENTS);
> > > +
> > > +	if (e)
> > > +		printk(KERN_ERR
> > > +			"TWL4030 Power Companion Warmreset seq config error\n");
> > > +	return e;
> > > +}
> > > +
> > > +static int __init twl4030_power_init(void)
> > > +{
> > > +	int err = 0;
> > > +
> > > +	err = twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, KEY_1,
> > > +				R_PROTECT_KEY);
> > > +	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, KEY_2,
> > > +				R_PROTECT_KEY);
> > > +
> > > +	if (err)
> > > +		return err;
> > > +
> > > +	err = config_sleep_wake_sequence();
> > > +	if (err)
> > > +		return err;
> > > +
> > > +	err = config_warmreset_sequence();
> > > +	if (err)
> > > +		return err;
> > > +
> > > +	err = twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0, R_PROTECT_KEY);
> > > +
> > > +	return err;
> > > +
> > > +}
> > > +
> > > +module_init(twl4030_power_init);

Re: [PATCH] Load triton2 scripts.

[Tony Lindgren]

* Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com> [080819 09:59]:
> On ma, 2008-08-18 at 16:31 +0300, ext Tony Lindgren wrote:
> > * Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com> [080807 13:10]:
> > > Hi Tony,
> > > 
> > > This patch should be safe to apply now as the sys off mode pin polarity
> > > was fixed in the patch "Add early init for voltage controller
> > > configuration and off mode polarity" (index a6cfc46..fc72c11 100644).
> > > 
> > > I compile & boot tested it on SDP board, on both plain master branch and
> > > with Jouni's workarounds. Works for me.
> > 
> > Hmm, just to confirm... Isn't this one already applied modified with
> > commits 07667f11a9864671bcec35dd0ee36e47cb3f675c and
> > 3238fb156cf77b537b2df8d897fe62a7feab4939? Can you please check and
> > let me know if something still needs to be patched.
> 
> I checked. No, those patches do not apply the triton2 script loading.
> They configure the voltage controller and set the off-mode polarity,
> which are needed before applying the triton script loading patch.
> 
> So you still need to apply the "Load triton2 scripts" patch sent by
> Peter De Schrijver. If you wish, I can resend it.

OK, thanks. Yeah a resend would be nice!

Tony

> 
> regards,
> Kalle
> 
> 
> > 
> > Thanks,
> > 
> > Tony
> > 
> > > 
> > > regards,
> > > Kalle
> > > 
> > > On ma, 2008-07-21 at 19:17 +0300, ext Peter 'p2' De Schrijver wrote: 
> > > > Signed-off-by: Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com>
> > > > ---
> > > >  drivers/i2c/chips/Makefile        |    2 +-
> > > >  drivers/i2c/chips/twl4030-power.c |  337 +++++++++++++++++++++++++++++++++++++
> > > >  2 files changed, 338 insertions(+), 1 deletions(-)
> > > >  create mode 100644 drivers/i2c/chips/twl4030-power.c
> > > > 
> > > > diff --git a/drivers/i2c/chips/Makefile b/drivers/i2c/chips/Makefile
> > > > index 1f81ebd..a44e617 100644
> > > > --- a/drivers/i2c/chips/Makefile
> > > > +++ b/drivers/i2c/chips/Makefile
> > > > @@ -23,7 +23,7 @@ obj-$(CONFIG_GPIOEXPANDER_OMAP)	+= gpio_expander_omap.o
> > > >  obj-$(CONFIG_MENELAUS)		+= menelaus.o
> > > >  obj-$(CONFIG_SENSORS_TSL2550)	+= tsl2550.o
> > > >  obj-$(CONFIG_SENSORS_TSL2563)	+= tsl2563.o
> > > > -obj-$(CONFIG_TWL4030_CORE)	+= twl4030-core.o twl4030-pwrirq.o
> > > > +obj-$(CONFIG_TWL4030_CORE)	+= twl4030-core.o twl4030-pwrirq.o twl4030-power.o
> > > >  obj-$(CONFIG_TWL4030_GPIO)	+= twl4030-gpio.o
> > > >  obj-$(CONFIG_TWL4030_USB)	+= twl4030-usb.o
> > > >  obj-$(CONFIG_TWL4030_POWEROFF)	+= twl4030-poweroff.o
> > > > diff --git a/drivers/i2c/chips/twl4030-power.c b/drivers/i2c/chips/twl4030-power.c
> > > > new file mode 100644
> > > > index 0000000..195c3c4
> > > > --- /dev/null
> > > > +++ b/drivers/i2c/chips/twl4030-power.c
> > > > @@ -0,0 +1,337 @@
> > > > +/*
> > > > + * linux/drivers/i2c/chips/twl4030-power.c
> > > > + *
> > > > + * Handle TWL4030 Power initialization
> > > > + *
> > > > + * Copyright (C) 2008 Nokia Corporation
> > > > + * Copyright (C) 2006 Texas Instruments, Inc
> > > > + *
> > > > + * Written by 	Kalle Jokiniemi
> > > > + *		Peter De Schrijver <peter.de-schrijver@nokia.com>
> > > > + *
> > > > + * This file is subject to the terms and conditions of the GNU General
> > > > + * Public License. See the file "COPYING" in the main directory of this
> > > > + * archive for more details.
> > > > + *
> > > > + * This program is distributed in the hope that it will be useful,
> > > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > > > + * GNU General Public License for more details.
> > > > + *
> > > > + * You should have received a copy of the GNU General Public License
> > > > + * along with this program; if not, write to the Free Software
> > > > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
> > > > + */
> > > > +
> > > > +#include <linux/module.h>
> > > > +#include <linux/pm.h>
> > > > +#include <linux/i2c/twl4030.h>
> > > > +
> > > > +#define PWR_P1_SW_EVENTS	0x10
> > > > +#define PWR_DEVOFF	(1<<0)
> > > > +
> > > > +#define PHY_TO_OFF_PM_MASTER(p)		(p - 0x36)
> > > > +#define PHY_TO_OFF_PM_RECIEVER(p)	(p - 0x5b)
> > > > +
> > > > +/* resource - hfclk */
> > > > +#define R_HFCLKOUT_DEV_GRP 	PHY_TO_OFF_PM_RECIEVER(0xe6)
> > > > +
> > > > +/* PM events */
> > > > +#define R_P1_SW_EVENTS		PHY_TO_OFF_PM_MASTER(0x46)
> > > > +#define R_P2_SW_EVENTS		PHY_TO_OFF_PM_MASTER(0x47)
> > > > +#define R_P3_SW_EVENTS		PHY_TO_OFF_PM_MASTER(0x48)
> > > > +#define R_CFG_P1_TRANSITION	PHY_TO_OFF_PM_MASTER(0x36)
> > > > +#define R_CFG_P2_TRANSITION	PHY_TO_OFF_PM_MASTER(0x37)
> > > > +#define R_CFG_P3_TRANSITION	PHY_TO_OFF_PM_MASTER(0x38)
> > > > +
> > > > +#define LVL_WAKEUP	0x08
> > > > +
> > > > +#define ENABLE_WARMRESET (1<<4)
> > > > +
> > > > +/* sequence script */
> > > > +
> > > > +#define END_OF_SCRIPT		0x3f
> > > > +
> > > > +#define R_SEQ_ADD_A2S		PHY_TO_OFF_PM_MASTER(0x55)
> > > > +#define R_SEQ_ADD_SA12		PHY_TO_OFF_PM_MASTER(0x56)
> > > > +#define	R_SEQ_ADD_S2A3		PHY_TO_OFF_PM_MASTER(0x57)
> > > > +#define	R_SEQ_ADD_WARM		PHY_TO_OFF_PM_MASTER(0x58)
> > > > +#define R_MEMORY_ADDRESS	PHY_TO_OFF_PM_MASTER(0x59)
> > > > +#define R_MEMORY_DATA		PHY_TO_OFF_PM_MASTER(0x5a)
> > > > +
> > > > +/* Power bus message definitions */
> > > > +
> > > > +#define DEV_GRP_NULL		0x0
> > > > +#define DEV_GRP_P1		0x1
> > > > +#define DEV_GRP_P2		0x2
> > > > +#define DEV_GRP_P3		0x4
> > > > +
> > > > +#define RES_GRP_RES		0x0
> > > > +#define RES_GRP_PP		0x1
> > > > +#define RES_GRP_RC		0x2
> > > > +#define RES_GRP_PP_RC		0x3
> > > > +#define RES_GRP_PR		0x4
> > > > +#define RES_GRP_PP_PR		0x5
> > > > +#define RES_GRP_RC_PR		0x6
> > > > +#define RES_GRP_ALL		0x7
> > > > +
> > > > +#define RES_TYPE2_R0		0x0
> > > > +
> > > > +#define RES_TYPE_ALL		0x7
> > > > +
> > > > +#define RES_STATE_WRST		0xF
> > > > +#define RES_STATE_ACTIVE	0xE
> > > > +#define RES_STATE_SLEEP		0x8
> > > > +#define RES_STATE_OFF		0x0
> > > > +
> > > > +/*
> > > > +*	Power Bus Message Format
> > > > +*
> > > > +*	Broadcast Message (16 Bits)
> > > > +*	DEV_GRP[15:13] MT[12]  RES_GRP[11:9]  RES_TYPE2[8:7] RES_TYPE[6:4]
> > > > +*	RES_STATE[3:0]
> > > > +*
> > > > +*	Singular Message (16 Bits)
> > > > +*	DEV_GRP[15:13] MT[12]  RES_ID[11:4]  RES_STATE[3:0]
> > > > +*
> > > > +*/
> > > > +
> > > > +#define MSG_BROADCAST(devgrp, grp, type, type2, state) \
> > > > +	(devgrp << 13 | 1 << 12 | grp << 9 | type2 << 7 | type << 4 | state)
> > > > +
> > > > +#define MSG_SINGULAR(devgrp, id, state) \
> > > > +	(devgrp << 13 | 0 << 12 | id << 4 | state)
> > > > +
> > > > +#define R_PROTECT_KEY		0x0E
> > > > +#define KEY_1			0xC0
> > > > +#define KEY_2			0x0C
> > > > +
> > > > +struct triton_ins {
> > > > +	u16 pmb_message;
> > > > +	u8 delay;
> > > > +};
> > > > +
> > > > +
> > > > +#define CONFIG_DISABLE_HFCLK	1
> > > > +
> > > > +#if defined(CONFIG_MACH_OMAP_3430SDP) || defined(CONFIG_MACH_OMAP_3430LABRADOR)
> > > > +
> > > > +struct triton_ins sleep_on_seq[] __initdata = {
> > > > +	{MSG_SINGULAR(DEV_GRP_P1, 0xf, RES_STATE_OFF), 4},
> > > > +	{MSG_SINGULAR(DEV_GRP_P1, 0x10, RES_STATE_OFF), 2},
> > > > +#ifdef CONFIG_DISABLE_HFCLK
> > > > +	{MSG_SINGULAR(DEV_GRP_P1, 0x7, RES_STATE_OFF), 3},
> > > > +	{MSG_SINGULAR(DEV_GRP_P1, 0x19, RES_STATE_OFF), 3},
> > > > +#endif /* #ifdef CONFIG_DISABLE_HFCLK */
> > > > +};
> > > > +
> > > > +struct triton_ins sleep_off_seq[] __initdata = {
> > > > +#ifndef CONFIG_DISABLE_HFCLK
> > > > +	{MSG_SINGULAR(DEV_GRP_P1, 0xf, RES_STATE_ACTIVE), 4},
> > > > +	{MSG_SINGULAR(DEV_GRP_P1, 0x10, RES_STATE_ACTIVE), 2},
> > > > +#else
> > > > +	{MSG_SINGULAR(DEV_GRP_P1, 0x7, RES_STATE_ACTIVE), 0x30},
> > > > +	{MSG_SINGULAR(DEV_GRP_P1, 0xf, RES_STATE_ACTIVE), 0x30},
> > > > +	{MSG_SINGULAR(DEV_GRP_P1, 0x10, RES_STATE_ACTIVE), 0x37},
> > > > +	{MSG_SINGULAR(DEV_GRP_P1, 0x19, RES_STATE_ACTIVE), 3},
> > > > +#endif /* #ifndef CONFIG_DISABLE_HFCLK */
> > > > +};
> > > > +
> > > > +struct triton_ins t2_wrst_seq[] __initdata = {
> > > > +	{MSG_SINGULAR(DEV_GRP_NULL, 0x1b, RES_STATE_OFF), 2},
> > > > +	{MSG_SINGULAR(DEV_GRP_P1, 0xf, RES_STATE_WRST), 15},
> > > > +	{MSG_SINGULAR(DEV_GRP_P1, 0x10, RES_STATE_WRST), 15},
> > > > +	{MSG_SINGULAR(DEV_GRP_P1, 0x7, RES_STATE_WRST), 0x60},
> > > > +	{MSG_SINGULAR(DEV_GRP_P1, 0x19, RES_STATE_ACTIVE), 2},
> > > > +	{MSG_SINGULAR(DEV_GRP_NULL, 0x1b, RES_STATE_ACTIVE), 2},
> > > > +};
> > > > +#else
> > > > +struct triton_ins sleep_on_seq[] __initdata = {
> > > > +	{MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_RC, RES_TYPE_ALL, RES_TYPE2_R0,
> > > > +			RES_STATE_SLEEP), 4},
> > > > +	{MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, RES_TYPE_ALL, RES_TYPE_R7,
> > > > +			RES_STATE_SLEEP), 4},
> > > > +};
> > > > +
> > > > +struct triton_ins sleep_off_seq[] __initdata = {
> > > > +	{MSG_SINGULAR(DEV_GRP_NULL, 0x17, RES_STATE_ACTIVE), 0x30},
> > > > +	{MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_PP_PR, RES_TYPE_ALL, RES_TYPE2_R0,
> > > > +			RES_STATE_ACTIVE), 0x37},
> > > > +	{MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, RES_TYPE_ALL, RES_TYPE2_R0,
> > > > +			RES_STATE_ACTIVE), 0x2},
> > > > +};
> > > > +#endif
> > > > +
> > > > +static int __init twl4030_write_script_byte(u8 address, u8 byte)
> > > > +{
> > > > +	int err;
> > > > +
> > > > +	err = twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, address,
> > > > +					R_MEMORY_ADDRESS);
> > > > +	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, byte,
> > > > +					R_MEMORY_DATA);
> > > > +
> > > > +	return err;
> > > > +}
> > > > +
> > > > +static int __init twl4030_write_script_ins(u8 address, u16 pmb_message,
> > > > +						u8 delay, u8 next)
> > > > +{
> > > > +	int err = 0;
> > > > +
> > > > +	address *= 4;
> > > > +	err |= twl4030_write_script_byte(address++, pmb_message >> 8);
> > > > +	err |= twl4030_write_script_byte(address++, pmb_message & 0xff);
> > > > +	err |= twl4030_write_script_byte(address++, delay);
> > > > +	err |= twl4030_write_script_byte(address++, next);
> > > > +
> > > > +	return err;
> > > > +}
> > > > +
> > > > +static int __init twl4030_write_script(u8 address, struct triton_ins *script,
> > > > +					int len)
> > > > +{
> > > > +	int err = 0;
> > > > +
> > > > +	for (; len; len--, address++, script++) {
> > > > +		if (len == 1)
> > > > +			err |= twl4030_write_script_ins(address,
> > > > +							script->pmb_message,
> > > > +							script->delay,
> > > > +							END_OF_SCRIPT);
> > > > +		else
> > > > +			err |= twl4030_write_script_ins(address,
> > > > +							script->pmb_message,
> > > > +							script->delay,
> > > > +							address + 1);
> > > > +	}
> > > > +
> > > > +	return err;
> > > > +}
> > > > +
> > > > +static int __init config_sleep_wake_sequence(void)
> > > > +{
> > > > +	int err = 0;
> > > > +	u8 data;
> > > > +
> > > > +	/*
> > > > +	 * CLKREQ is pulled high on the 2430SDP, therefore, we need to take
> > > > +	 * it out of the HFCLKOUT DEV_GRP for P1 else HFCLKOUT can't be stopped.
> > > > +	 */
> > > > +
> > > > +	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
> > > > +				  0x20, R_HFCLKOUT_DEV_GRP);
> > > > +
> > > > +	/* Set ACTIVE to SLEEP SEQ address in T2 memory*/
> > > > +	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0x2B,
> > > > +				  R_SEQ_ADD_A2S);
> > > > +
> > > > +	/* Set SLEEP to ACTIVE SEQ address for P1 and P2 */
> > > > +	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0x2F,
> > > > +				  R_SEQ_ADD_SA12);
> > > > +
> > > > +	/* Set SLEEP to ACTIVE SEQ address for P3 */
> > > > +	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0x2F,
> > > > +				  R_SEQ_ADD_S2A3);
> > > > +
> > > > +	/* Install Active->Sleep (A2S) sequence */
> > > > +	err |= twl4030_write_script(0x2B, sleep_on_seq,
> > > > +					ARRAY_SIZE(sleep_on_seq));
> > > > +
> > > > +	/* Install Sleep->Active (S2A) sequence */
> > > > +	err |= twl4030_write_script(0x2F, sleep_off_seq,
> > > > +					ARRAY_SIZE(sleep_off_seq));
> > > > +
> > > > +#if defined(CONFIG_MACH_OMAP_3430SDP) || defined(CONFIG_MACH_OMAP_3430LABRADOR)
> > > > +	/* Disabling AC charger effect on sleep-active transitions */
> > > > +	err |= twl4030_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &data,
> > > > +					R_CFG_P1_TRANSITION);
> > > > +	data &= 0x0;
> > > > +	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, data ,
> > > > +					R_CFG_P1_TRANSITION);
> > > > +#endif
> > > > +	/* P1/P2/P3 LVL_WAKEUP should be on LEVEL */
> > > > +	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, LVL_WAKEUP,
> > > > +					R_P1_SW_EVENTS);
> > > > +	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, LVL_WAKEUP,
> > > > +					R_P2_SW_EVENTS);
> > > > +	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, LVL_WAKEUP,
> > > > +				R_P3_SW_EVENTS);
> > > > +
> > > > +	if (err)
> > > > +		printk(KERN_ERR "TWL4030 sleep-wake sequence config error\n");
> > > > +
> > > > +	return err;
> > > > +}
> > > > +
> > > > +
> > > > +/* Programming the WARMRESET Sequence on TRITON */
> > > > +static int __init config_warmreset_sequence(void)
> > > > +{
> > > > +
> > > > +	int e = 0;
> > > > +	u8 rd_data;
> > > > +
> > > > +	if (!ARRAY_SIZE(t2_wrst_seq))
> > > > +		return 0;
> > > > +
> > > > +	/* Set WARM RESET SEQ address for P1 */
> > > > +	e |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0x38,
> > > > +				R_SEQ_ADD_WARM);
> > > > +
> > > > +	/* Install Warm Reset sequence */
> > > > +	e |= twl4030_write_script(0x38, t2_wrst_seq,
> > > > +					ARRAY_SIZE(t2_wrst_seq));
> > > > +
> > > > +	/* P1/P2/P3 enable WARMRESET */
> > > > +	e |= twl4030_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &rd_data,
> > > > +				R_P1_SW_EVENTS);
> > > > +	rd_data |= ENABLE_WARMRESET;
> > > > +	e |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, rd_data,
> > > > +				R_P1_SW_EVENTS);
> > > > +
> > > > +	e |= twl4030_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &rd_data,
> > > > +				R_P2_SW_EVENTS);
> > > > +	rd_data |= ENABLE_WARMRESET;
> > > > +	e |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, rd_data,
> > > > +				R_P2_SW_EVENTS);
> > > > +
> > > > +	e |= twl4030_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &rd_data,
> > > > +				R_P3_SW_EVENTS);
> > > > +	rd_data |= ENABLE_WARMRESET;
> > > > +	e |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, rd_data,
> > > > +				R_P3_SW_EVENTS);
> > > > +
> > > > +	if (e)
> > > > +		printk(KERN_ERR
> > > > +			"TWL4030 Power Companion Warmreset seq config error\n");
> > > > +	return e;
> > > > +}
> > > > +
> > > > +static int __init twl4030_power_init(void)
> > > > +{
> > > > +	int err = 0;
> > > > +
> > > > +	err = twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, KEY_1,
> > > > +				R_PROTECT_KEY);
> > > > +	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, KEY_2,
> > > > +				R_PROTECT_KEY);
> > > > +
> > > > +	if (err)
> > > > +		return err;
> > > > +
> > > > +	err = config_sleep_wake_sequence();
> > > > +	if (err)
> > > > +		return err;
> > > > +
> > > > +	err = config_warmreset_sequence();
> > > > +	if (err)
> > > > +		return err;
> > > > +
> > > > +	err = twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0, R_PROTECT_KEY);
> > > > +
> > > > +	return err;
> > > > +
> > > > +}
> > > > +
> > > > +module_init(twl4030_power_init);

[PATCH] Set correct off mode polarity

[Peter 'p2' De Schrijver]

Signed-off-by: Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com>
---
 arch/arm/mach-omap2/clock34xx.c |    6 +++++-
 1 files changed, 5 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 6bb25cf..b0bc1b9 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -46,6 +46,8 @@
 
 #define MAX_DPLL_WAIT_TRIES		1000000
 
+#define OFFMODE_POL 			(1<<3)
+
 struct vdd_prcm_config *curr_vdd1_prcm_set;
 struct vdd_prcm_config *curr_vdd2_prcm_set;
 static struct clk *dpll1_clk, *dpll2_clk, *dpll3_clk;
@@ -684,6 +686,9 @@ int __init omap2_clk_init(void)
 	}
 #endif
 
+	prm_clear_mod_reg_bits(OFFMODE_POL, OMAP3430_GR_MOD,
+				OMAP3_PRM_POLCTRL_OFFSET);
+
 	printk(KERN_INFO "Clocking rate (Crystal/DPLL/ARM core): "
 	       "%ld.%01ld/%ld/%ld MHz\n",
 	       (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
@@ -797,7 +802,6 @@ static int omap3_select_table_rate(struct clk *clk, unsigned long rate)
 		return -EINVAL;
 	}
 
-
 	if (clk == &virt_vdd1_prcm_set) {
 		curr_mpu_speed = curr_vdd1_prcm_set->speed;
 		clk_set_rate(dpll1_clk, prcm_vdd->speed);
-- 
1.5.3.4

[PATCH] Enable SYSOFFMODE use

[Peter 'p2' De Schrijver]

Signed-off-by: Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com>
---
 arch/arm/mach-omap2/smartreflex.c |   10 +++++-----
 1 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
index 0f3a659..b41fe96 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -396,17 +396,17 @@ static void sr_configure_vc(void)
 
 	/* Setup voltctrl and other setup times */
 	/* XXX CONFIG_SYSOFFMODE has not been implemented yet */
-#ifdef CONFIG_SYSOFFMODE
-	prm_write_mod_reg(OMAP3430_AUTO_OFF | OMAP3430_AUTO_RET,
-			OMAP3430_GR_MOD,
+#ifdef CONFIG_OMAP_SYSOFFMODE
+	prm_write_mod_reg(OMAP3430_AUTO_OFF | OMAP3430_AUTO_RET |
+			OMAP3430_SEL_OFF, OMAP3430_GR_MOD,
 			OMAP3_PRM_VOLTCTRL_OFFSET);
 
 	prm_write_mod_reg(OMAP3430_CLKSETUP_DURATION, OMAP3430_GR_MOD,
 			OMAP3_PRM_CLKSETUP_OFFSET);
 	prm_write_mod_reg((OMAP3430_VOLTSETUP_TIME2 <<
-			OMAP3430_VOLTSETUP_TIME2_OFFSET) |
+			OMAP3430_SETUP_TIME2_SHIFT) |
 			(OMAP3430_VOLTSETUP_TIME1 <<
-			OMAP3430_VOLTSETUP_TIME1_OFFSET),
+			OMAP3430_SETUP_TIME1_SHIFT),
 			OMAP3430_GR_MOD, OMAP3_PRM_VOLTSETUP1_OFFSET);
 
 	prm_write_mod_reg(OMAP3430_VOLTOFFSET_DURATION, OMAP3430_GR_MOD,
-- 
1.5.3.4

[PATCH] Add SYSOFFMODE option.

[Peter 'p2' De Schrijver]

Signed-off-by: Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com>
---
 arch/arm/plat-omap/Kconfig |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index d7b34ff..6f891b7 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -73,6 +73,12 @@ config OMAP_SMARTREFLEX
 	  compensation for VDD1 and VDD2, user must write 1 to
 	  /sys/power/sr_vddX_autocomp, where X is 1 or 2.
 
+config OMAP_SYSOFFMODE
+        bool "OFF mode support"
+	depends on ARCH_OMAP34XX
+	help
+	  Say Y if you want to allow OMAP to enter OFF mode.
+
 config OMAP_SMARTREFLEX_TESTING
 	bool "Smartreflex testing support"
 	depends on OMAP_SMARTREFLEX
-- 
1.5.3.4

[PATCH] Load triton2 scripts.

[Peter 'p2' De Schrijver]

Signed-off-by: Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com>
---
 drivers/i2c/chips/Makefile        |    2 +-
 drivers/i2c/chips/twl4030-power.c |  337 +++++++++++++++++++++++++++++++++++++
 2 files changed, 338 insertions(+), 1 deletions(-)
 create mode 100644 drivers/i2c/chips/twl4030-power.c

diff --git a/drivers/i2c/chips/Makefile b/drivers/i2c/chips/Makefile
index 1f81ebd..a44e617 100644
--- a/drivers/i2c/chips/Makefile
+++ b/drivers/i2c/chips/Makefile
@@ -23,7 +23,7 @@ obj-$(CONFIG_GPIOEXPANDER_OMAP)	+= gpio_expander_omap.o
 obj-$(CONFIG_MENELAUS)		+= menelaus.o
 obj-$(CONFIG_SENSORS_TSL2550)	+= tsl2550.o
 obj-$(CONFIG_SENSORS_TSL2563)	+= tsl2563.o
-obj-$(CONFIG_TWL4030_CORE)	+= twl4030-core.o twl4030-pwrirq.o
+obj-$(CONFIG_TWL4030_CORE)	+= twl4030-core.o twl4030-pwrirq.o twl4030-power.o
 obj-$(CONFIG_TWL4030_GPIO)	+= twl4030-gpio.o
 obj-$(CONFIG_TWL4030_USB)	+= twl4030-usb.o
 obj-$(CONFIG_TWL4030_POWEROFF)	+= twl4030-poweroff.o
diff --git a/drivers/i2c/chips/twl4030-power.c b/drivers/i2c/chips/twl4030-power.c
new file mode 100644
index 0000000..195c3c4
--- /dev/null
+++ b/drivers/i2c/chips/twl4030-power.c
@@ -0,0 +1,337 @@
+/*
+ * linux/drivers/i2c/chips/twl4030-power.c
+ *
+ * Handle TWL4030 Power initialization
+ *
+ * Copyright (C) 2008 Nokia Corporation
+ * Copyright (C) 2006 Texas Instruments, Inc
+ *
+ * Written by 	Kalle Jokiniemi
+ *		Peter De Schrijver <peter.de-schrijver@nokia.com>
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License. See the file "COPYING" in the main directory of this
+ * archive for more details.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/module.h>
+#include <linux/pm.h>
+#include <linux/i2c/twl4030.h>
+
+#define PWR_P1_SW_EVENTS	0x10
+#define PWR_DEVOFF	(1<<0)
+
+#define PHY_TO_OFF_PM_MASTER(p)		(p - 0x36)
+#define PHY_TO_OFF_PM_RECIEVER(p)	(p - 0x5b)
+
+/* resource - hfclk */
+#define R_HFCLKOUT_DEV_GRP 	PHY_TO_OFF_PM_RECIEVER(0xe6)
+
+/* PM events */
+#define R_P1_SW_EVENTS		PHY_TO_OFF_PM_MASTER(0x46)
+#define R_P2_SW_EVENTS		PHY_TO_OFF_PM_MASTER(0x47)
+#define R_P3_SW_EVENTS		PHY_TO_OFF_PM_MASTER(0x48)
+#define R_CFG_P1_TRANSITION	PHY_TO_OFF_PM_MASTER(0x36)
+#define R_CFG_P2_TRANSITION	PHY_TO_OFF_PM_MASTER(0x37)
+#define R_CFG_P3_TRANSITION	PHY_TO_OFF_PM_MASTER(0x38)
+
+#define LVL_WAKEUP	0x08
+
+#define ENABLE_WARMRESET (1<<4)
+
+/* sequence script */
+
+#define END_OF_SCRIPT		0x3f
+
+#define R_SEQ_ADD_A2S		PHY_TO_OFF_PM_MASTER(0x55)
+#define R_SEQ_ADD_SA12		PHY_TO_OFF_PM_MASTER(0x56)
+#define	R_SEQ_ADD_S2A3		PHY_TO_OFF_PM_MASTER(0x57)
+#define	R_SEQ_ADD_WARM		PHY_TO_OFF_PM_MASTER(0x58)
+#define R_MEMORY_ADDRESS	PHY_TO_OFF_PM_MASTER(0x59)
+#define R_MEMORY_DATA		PHY_TO_OFF_PM_MASTER(0x5a)
+
+/* Power bus message definitions */
+
+#define DEV_GRP_NULL		0x0
+#define DEV_GRP_P1		0x1
+#define DEV_GRP_P2		0x2
+#define DEV_GRP_P3		0x4
+
+#define RES_GRP_RES		0x0
+#define RES_GRP_PP		0x1
+#define RES_GRP_RC		0x2
+#define RES_GRP_PP_RC		0x3
+#define RES_GRP_PR		0x4
+#define RES_GRP_PP_PR		0x5
+#define RES_GRP_RC_PR		0x6
+#define RES_GRP_ALL		0x7
+
+#define RES_TYPE2_R0		0x0
+
+#define RES_TYPE_ALL		0x7
+
+#define RES_STATE_WRST		0xF
+#define RES_STATE_ACTIVE	0xE
+#define RES_STATE_SLEEP		0x8
+#define RES_STATE_OFF		0x0
+
+/*
+*	Power Bus Message Format
+*
+*	Broadcast Message (16 Bits)
+*	DEV_GRP[15:13] MT[12]  RES_GRP[11:9]  RES_TYPE2[8:7] RES_TYPE[6:4]
+*	RES_STATE[3:0]
+*
+*	Singular Message (16 Bits)
+*	DEV_GRP[15:13] MT[12]  RES_ID[11:4]  RES_STATE[3:0]
+*
+*/
+
+#define MSG_BROADCAST(devgrp, grp, type, type2, state) \
+	(devgrp << 13 | 1 << 12 | grp << 9 | type2 << 7 | type << 4 | state)
+
+#define MSG_SINGULAR(devgrp, id, state) \
+	(devgrp << 13 | 0 << 12 | id << 4 | state)
+
+#define R_PROTECT_KEY		0x0E
+#define KEY_1			0xC0
+#define KEY_2			0x0C
+
+struct triton_ins {
+	u16 pmb_message;
+	u8 delay;
+};
+
+
+#define CONFIG_DISABLE_HFCLK	1
+
+#if defined(CONFIG_MACH_OMAP_3430SDP) || defined(CONFIG_MACH_OMAP_3430LABRADOR)
+
+struct triton_ins sleep_on_seq[] __initdata = {
+	{MSG_SINGULAR(DEV_GRP_P1, 0xf, RES_STATE_OFF), 4},
+	{MSG_SINGULAR(DEV_GRP_P1, 0x10, RES_STATE_OFF), 2},
+#ifdef CONFIG_DISABLE_HFCLK
+	{MSG_SINGULAR(DEV_GRP_P1, 0x7, RES_STATE_OFF), 3},
+	{MSG_SINGULAR(DEV_GRP_P1, 0x19, RES_STATE_OFF), 3},
+#endif /* #ifdef CONFIG_DISABLE_HFCLK */
+};
+
+struct triton_ins sleep_off_seq[] __initdata = {
+#ifndef CONFIG_DISABLE_HFCLK
+	{MSG_SINGULAR(DEV_GRP_P1, 0xf, RES_STATE_ACTIVE), 4},
+	{MSG_SINGULAR(DEV_GRP_P1, 0x10, RES_STATE_ACTIVE), 2},
+#else
+	{MSG_SINGULAR(DEV_GRP_P1, 0x7, RES_STATE_ACTIVE), 0x30},
+	{MSG_SINGULAR(DEV_GRP_P1, 0xf, RES_STATE_ACTIVE), 0x30},
+	{MSG_SINGULAR(DEV_GRP_P1, 0x10, RES_STATE_ACTIVE), 0x37},
+	{MSG_SINGULAR(DEV_GRP_P1, 0x19, RES_STATE_ACTIVE), 3},
+#endif /* #ifndef CONFIG_DISABLE_HFCLK */
+};
+
+struct triton_ins t2_wrst_seq[] __initdata = {
+	{MSG_SINGULAR(DEV_GRP_NULL, 0x1b, RES_STATE_OFF), 2},
+	{MSG_SINGULAR(DEV_GRP_P1, 0xf, RES_STATE_WRST), 15},
+	{MSG_SINGULAR(DEV_GRP_P1, 0x10, RES_STATE_WRST), 15},
+	{MSG_SINGULAR(DEV_GRP_P1, 0x7, RES_STATE_WRST), 0x60},
+	{MSG_SINGULAR(DEV_GRP_P1, 0x19, RES_STATE_ACTIVE), 2},
+	{MSG_SINGULAR(DEV_GRP_NULL, 0x1b, RES_STATE_ACTIVE), 2},
+};
+#else
+struct triton_ins sleep_on_seq[] __initdata = {
+	{MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_RC, RES_TYPE_ALL, RES_TYPE2_R0,
+			RES_STATE_SLEEP), 4},
+	{MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, RES_TYPE_ALL, RES_TYPE_R7,
+			RES_STATE_SLEEP), 4},
+};
+
+struct triton_ins sleep_off_seq[] __initdata = {
+	{MSG_SINGULAR(DEV_GRP_NULL, 0x17, RES_STATE_ACTIVE), 0x30},
+	{MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_PP_PR, RES_TYPE_ALL, RES_TYPE2_R0,
+			RES_STATE_ACTIVE), 0x37},
+	{MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, RES_TYPE_ALL, RES_TYPE2_R0,
+			RES_STATE_ACTIVE), 0x2},
+};
+#endif
+
+static int __init twl4030_write_script_byte(u8 address, u8 byte)
+{
+	int err;
+
+	err = twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, address,
+					R_MEMORY_ADDRESS);
+	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, byte,
+					R_MEMORY_DATA);
+
+	return err;
+}
+
+static int __init twl4030_write_script_ins(u8 address, u16 pmb_message,
+						u8 delay, u8 next)
+{
+	int err = 0;
+
+	address *= 4;
+	err |= twl4030_write_script_byte(address++, pmb_message >> 8);
+	err |= twl4030_write_script_byte(address++, pmb_message & 0xff);
+	err |= twl4030_write_script_byte(address++, delay);
+	err |= twl4030_write_script_byte(address++, next);
+
+	return err;
+}
+
+static int __init twl4030_write_script(u8 address, struct triton_ins *script,
+					int len)
+{
+	int err = 0;
+
+	for (; len; len--, address++, script++) {
+		if (len == 1)
+			err |= twl4030_write_script_ins(address,
+							script->pmb_message,
+							script->delay,
+							END_OF_SCRIPT);
+		else
+			err |= twl4030_write_script_ins(address,
+							script->pmb_message,
+							script->delay,
+							address + 1);
+	}
+
+	return err;
+}
+
+static int __init config_sleep_wake_sequence(void)
+{
+	int err = 0;
+	u8 data;
+
+	/*
+	 * CLKREQ is pulled high on the 2430SDP, therefore, we need to take
+	 * it out of the HFCLKOUT DEV_GRP for P1 else HFCLKOUT can't be stopped.
+	 */
+
+	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
+				  0x20, R_HFCLKOUT_DEV_GRP);
+
+	/* Set ACTIVE to SLEEP SEQ address in T2 memory*/
+	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0x2B,
+				  R_SEQ_ADD_A2S);
+
+	/* Set SLEEP to ACTIVE SEQ address for P1 and P2 */
+	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0x2F,
+				  R_SEQ_ADD_SA12);
+
+	/* Set SLEEP to ACTIVE SEQ address for P3 */
+	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0x2F,
+				  R_SEQ_ADD_S2A3);
+
+	/* Install Active->Sleep (A2S) sequence */
+	err |= twl4030_write_script(0x2B, sleep_on_seq,
+					ARRAY_SIZE(sleep_on_seq));
+
+	/* Install Sleep->Active (S2A) sequence */
+	err |= twl4030_write_script(0x2F, sleep_off_seq,
+					ARRAY_SIZE(sleep_off_seq));
+
+#if defined(CONFIG_MACH_OMAP_3430SDP) || defined(CONFIG_MACH_OMAP_3430LABRADOR)
+	/* Disabling AC charger effect on sleep-active transitions */
+	err |= twl4030_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &data,
+					R_CFG_P1_TRANSITION);
+	data &= 0x0;
+	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, data ,
+					R_CFG_P1_TRANSITION);
+#endif
+	/* P1/P2/P3 LVL_WAKEUP should be on LEVEL */
+	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, LVL_WAKEUP,
+					R_P1_SW_EVENTS);
+	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, LVL_WAKEUP,
+					R_P2_SW_EVENTS);
+	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, LVL_WAKEUP,
+				R_P3_SW_EVENTS);
+
+	if (err)
+		printk(KERN_ERR "TWL4030 sleep-wake sequence config error\n");
+
+	return err;
+}
+
+
+/* Programming the WARMRESET Sequence on TRITON */
+static int __init config_warmreset_sequence(void)
+{
+
+	int e = 0;
+	u8 rd_data;
+
+	if (!ARRAY_SIZE(t2_wrst_seq))
+		return 0;
+
+	/* Set WARM RESET SEQ address for P1 */
+	e |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0x38,
+				R_SEQ_ADD_WARM);
+
+	/* Install Warm Reset sequence */
+	e |= twl4030_write_script(0x38, t2_wrst_seq,
+					ARRAY_SIZE(t2_wrst_seq));
+
+	/* P1/P2/P3 enable WARMRESET */
+	e |= twl4030_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &rd_data,
+				R_P1_SW_EVENTS);
+	rd_data |= ENABLE_WARMRESET;
+	e |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, rd_data,
+				R_P1_SW_EVENTS);
+
+	e |= twl4030_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &rd_data,
+				R_P2_SW_EVENTS);
+	rd_data |= ENABLE_WARMRESET;
+	e |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, rd_data,
+				R_P2_SW_EVENTS);
+
+	e |= twl4030_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &rd_data,
+				R_P3_SW_EVENTS);
+	rd_data |= ENABLE_WARMRESET;
+	e |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, rd_data,
+				R_P3_SW_EVENTS);
+
+	if (e)
+		printk(KERN_ERR
+			"TWL4030 Power Companion Warmreset seq config error\n");
+	return e;
+}
+
+static int __init twl4030_power_init(void)
+{
+	int err = 0;
+
+	err = twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, KEY_1,
+				R_PROTECT_KEY);
+	err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, KEY_2,
+				R_PROTECT_KEY);
+
+	if (err)
+		return err;
+
+	err = config_sleep_wake_sequence();
+	if (err)
+		return err;
+
+	err = config_warmreset_sequence();
+	if (err)
+		return err;
+
+	err = twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0, R_PROTECT_KEY);
+
+	return err;
+
+}
+
+module_init(twl4030_power_init);
-- 
1.5.3.4

Re: [PATCH] Load triton2 scripts.

[Felipe Balbi]

On Mon, Jul 21, 2008 at 07:02:05PM +0300, Peter 'p2' De Schrijver wrote:
> +/*
> +*	Power Bus Message Format
> +*
> +*	Broadcast Message (16 Bits)
> +*	DEV_GRP[15:13] MT[12]  RES_GRP[11:9]  RES_TYPE2[8:7] RES_TYPE[6:4]
> +*	RES_STATE[3:0]
> +*
> +*	Singular Message (16 Bits)
> +*	DEV_GRP[15:13] MT[12]  RES_ID[11:4]  RES_STATE[3:0]
> +*
> +*/

This comment should follow the coding style:

/*
 * Power Bus Message Format
 *
 * Broadcast Message (16 Bits)
 * DEV_GRP[15:13] MT[12]  RES_GRP[11:9]  RES_TYPE2[8:7] RES_TYPE[6:4]
 * RES_STATE[3:0]
 *
 * Singular Message (16 Bits)
 * DEV_GRP[15:13] MT[12]  RES_ID[11:4]  RES_STATE[3:0]
 */

> +struct triton_ins {
> +	u16 pmb_message;
> +	u8 delay;
> +};
> +
> +

extra line

> +#define CONFIG_DISABLE_HFCLK	1
> +
> +#if defined(CONFIG_MACH_OMAP_3430SDP) || defined(CONFIG_MACH_OMAP_3430LABRADOR)
> +
> +struct triton_ins sleep_on_seq[] __initdata = {
> +	{MSG_SINGULAR(DEV_GRP_P1, 0xf, RES_STATE_OFF), 4},

could you add spaces here??
	{ MSG_SINGULAR(DEV_GRP_P1, 0xf, RES_STATE_OFF), 4 },

-- 
balbi