[PATCH 0/8] OMAP3: PM: Open Switch Retention support in the cpuidle thread.

[PATCH 0/8] OMAP3: PM: Open Switch Retention support in the cpuidle thread.

[Thara Gopinath]

In OMAP all power domains embed some logic and some memory.
The power domain memory contains 
	memory arrays: powered by a dedicated voltage rail
	memory  logic : powered by the same voltage rail as
			the power domain logic but has a
			dedicated power switch(power on switch)
The power domain logic for some power domains can be split between
retention flip flops (RFF) or nonretention flip flops (DFF).

When a power domain is in Open Switch Retention(OSWR) power on
switch is set to 0, Vdd can be lowered to its retention value
and is provided only to the RFF logic. Only the RFF logic is
retained. The DFF logic is lost and reset on wakeup. The voltage
to the memory arrays can be retained or cut which will in turn lead
to memory arrays retaining or losing their contents

This patch series introduces OSWR support for MPU and core domain
in the cpuidle thread. The voltage to memory arrays in these
power domains are also cut during OSWR.

Thara Gopinath (8):
  PM: Increase the cpu idle max state.
  OMAP3 PM: Conditional UART context save restore.
  OMAP2/3 PM: Adding powerdomain APIs for reading the next logic and
    mem state
  OMAP3 PM: Defining .pwrsts_logic_ret field for core power domain
    structure
  OMAP3 PM: Adding conditional core powerdomain context save and
    restore
  OMAP3 PM: Enable DPLL4 autoidle after system off.
  OMAP3 PM: Support for Open SWitch Retention for Core and MPU power
    domains in cpuidle path
  OMAP3 PM: Support to enable disable OSWR feature from pm debug fs

 arch/arm/mach-omap2/board-3430sdp.c           |    4 +
 arch/arm/mach-omap2/cpuidle34xx.c             |  138 +++++++++++++++++++++++--
 arch/arm/mach-omap2/pm-debug.c                |    5 +
 arch/arm/mach-omap2/pm.h                      |    1 +
 arch/arm/mach-omap2/pm34xx.c                  |  137 ++++++++++++++++++-------
 arch/arm/mach-omap2/powerdomain.c             |   84 +++++++++++++++
 arch/arm/mach-omap2/powerdomains34xx.h        |    2 +
 arch/arm/mach-omap2/serial.c                  |   17 ++--
 arch/arm/mach-omap2/sleep34xx.S               |    4 +
 arch/arm/plat-omap/include/plat/powerdomain.h |    4 +
 arch/arm/plat-omap/include/plat/serial.h      |    2 +-
 include/linux/cpuidle.h                       |    2 +-
 12 files changed, 342 insertions(+), 58 deletions(-)

[PATCH 1/8] PM: Increase the cpu idle max state.

[Thara Gopinath]

This patch increases the maximum number of C states possible
in a system in the cpuidle framework. This is necessary for
OMAP3/OMAP4 when support for open switch retention of
powerdomains are added in the cpuidle path.

Signed-off-by: Thara Gopinath <thara@ti.com>
---
 include/linux/cpuidle.h |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/include/linux/cpuidle.h b/include/linux/cpuidle.h
index dcf77fa..8ec8300 100644
--- a/include/linux/cpuidle.h
+++ b/include/linux/cpuidle.h
@@ -17,7 +17,7 @@
 #include <linux/kobject.h>
 #include <linux/completion.h>
 
-#define CPUIDLE_STATE_MAX	8
+#define CPUIDLE_STATE_MAX	16
 #define CPUIDLE_NAME_LEN	16
 #define CPUIDLE_DESC_LEN	32
 
-- 
1.5.6.3

[PATCH 2/8] OMAP3 PM: Conditional UART context save restore.

[Thara Gopinath]

Currently UART context save is done in idle
thread thru a call to omap_uart_prepare_idle irrespective of
what power state is attained by the power domain to which
the UART belongs to. This patch allows omap_uart_prepare_idle
to take power state as a parameter and this function in
turn does a uart context save only if the passed power state
is PWRDM_POWER_OFF. In the restore path a restore will
happen only if a valid save has happened.

Signed-off-by: Thara Gopinath <thara@ti.com>
---
 arch/arm/mach-omap2/pm34xx.c             |    6 +++---
 arch/arm/mach-omap2/serial.c             |   17 +++++++----------
 arch/arm/plat-omap/include/plat/serial.h |    2 +-
 3 files changed, 11 insertions(+), 14 deletions(-)

diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 8f5e819..895e9ef 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -418,7 +418,7 @@ void omap_sram_idle(void)
 			} else
 				omap3_per_save_context();
 		}
-		omap_uart_prepare_idle(2);
+		omap_uart_prepare_idle(2, per_next_state);
 	}
 
 	if (pwrdm_read_pwrst(cam_pwrdm) == PWRDM_POWER_ON)
@@ -435,8 +435,8 @@ void omap_sram_idle(void)
 
 	/* CORE */
 	if (core_next_state < PWRDM_POWER_ON) {
-		omap_uart_prepare_idle(0);
-		omap_uart_prepare_idle(1);
+		omap_uart_prepare_idle(0, core_next_state);
+		omap_uart_prepare_idle(1, core_next_state);
 		if (core_next_state == PWRDM_POWER_OFF) {
 			u32 voltctrl = OMAP3430_AUTO_OFF;
 
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 837b347..fb59d5f 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -168,9 +168,6 @@ static void omap_uart_save_context(struct omap_uart_state *uart)
 	u16 lcr = 0;
 	struct plat_serial8250_port *p = uart->p;
 
-	if (!enable_off_mode)
-		return;
-
 	lcr = serial_read_reg(p, UART_LCR);
 	serial_write_reg(p, UART_LCR, 0xBF);
 	uart->dll = serial_read_reg(p, UART_DLL);
@@ -189,9 +186,6 @@ static void omap_uart_restore_context(struct omap_uart_state *uart)
 	u16 efr = 0;
 	struct plat_serial8250_port *p = uart->p;
 
-	if (!enable_off_mode)
-		return;
-
 	if (!uart->context_valid)
 		return;
 
@@ -235,12 +229,15 @@ static inline void omap_uart_enable_clocks(struct omap_uart_state *uart)
 
 #ifdef CONFIG_PM
 
-static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
+static inline void omap_uart_disable_clocks(struct omap_uart_state *uart,
+							int power_state)
 {
 	if (!uart->clocked)
 		return;
 
-	omap_uart_save_context(uart);
+	if (power_state == PWRDM_POWER_OFF)
+		omap_uart_save_context(uart);
+
 	uart->clocked = 0;
 	clk_disable(uart->ick);
 	clk_disable(uart->fck);
@@ -329,13 +326,13 @@ static void omap_uart_idle_timer(unsigned long data)
 	omap_uart_allow_sleep(uart);
 }
 
-void omap_uart_prepare_idle(int num)
+void omap_uart_prepare_idle(int num, int power_state)
 {
 	struct omap_uart_state *uart;
 
 	list_for_each_entry(uart, &uart_list, node) {
 		if (num == uart->num && uart->can_sleep) {
-			omap_uart_disable_clocks(uart);
+			omap_uart_disable_clocks(uart, power_state);
 			return;
 		}
 	}
diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h
index f5a4a92..ca76742 100644
--- a/arch/arm/plat-omap/include/plat/serial.h
+++ b/arch/arm/plat-omap/include/plat/serial.h
@@ -57,7 +57,7 @@ extern void omap_serial_init_port(int port);
 extern int omap_uart_can_sleep(void);
 extern void omap_uart_check_wakeup(void);
 extern void omap_uart_prepare_suspend(void);
-extern void omap_uart_prepare_idle(int num);
+extern void omap_uart_prepare_idle(int num, int power_state);
 extern void omap_uart_resume_idle(int num);
 extern void omap_uart_enable_irqs(int enable);
 #endif
-- 
1.5.6.3

[PATCH 3/8] OMAP2/3 PM: Adding powerdomain APIs for reading the next logic and mem state

[Thara Gopinath]

This patch adds APIs pwrdm_read_next_logic_pwrst and
pwrdm_read_next_mem_pwrst for reading the next programmed
logic and memory state a powerdomain is to hit in event
of the next power domain state being retention.

Signed-off-by: Thara Gopinath <thara@ti.com>
---
 arch/arm/mach-omap2/powerdomain.c             |   71 +++++++++++++++++++++++++
 arch/arm/plat-omap/include/plat/powerdomain.h |    2 +
 2 files changed, 73 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 26b3f3e..06bf290 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -964,6 +964,29 @@ int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm)
 }
 
 /**
+ * pwrdm_read_next_logic_pwrst - get next powerdomain logic power state
+ * @pwrdm: struct powerdomain * to get next logic power state
+ *
+ * Return the powerdomain pwrdm's logic power state.  Returns -EINVAL
+ * if the powerdomain pointer is null or returns the next logic
+ * power state upon success.
+ */
+int pwrdm_read_next_logic_pwrst(struct powerdomain *pwrdm)
+{
+	if (!pwrdm)
+		return -EINVAL;
+
+	/*
+	 * The register bit names below may not correspond to the
+	 * actual names of the bits in each powerdomain's register,
+	 * but the type of value returned is the same for each
+	 * powerdomain.
+	 */
+	return prm_read_mod_bits_shift(pwrdm->prcm_offs, PM_PWSTCTRL,
+					OMAP3430_LOGICSTATEST);
+}
+
+/**
  * pwrdm_read_mem_pwrst - get current memory bank power state
  * @pwrdm: struct powerdomain * to get current memory bank power state
  * @bank: memory bank number (0-3)
@@ -1065,6 +1088,54 @@ int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
 }
 
 /**
+ * pwrdm_read_next_mem_pwrst - get next memory bank power state
+ * @pwrdm: struct powerdomain * to get mext memory bank power state
+ * @bank: memory bank number (0-3)
+ *
+ * Return the powerdomain pwrdm's next memory power state for bank
+ * x.  Returns -EINVAL if the powerdomain pointer is null, -EEXIST if
+ * the target memory bank does not exist or is not controllable, or
+ * returns the next memory power state upon success.
+ */
+int pwrdm_read_next_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
+{
+	u32 m;
+
+	if (!pwrdm)
+		return -EINVAL;
+
+	if (pwrdm->banks < (bank + 1))
+		return -EEXIST;
+
+	/*
+	 * The register bit names below may not correspond to the
+	 * actual names of the bits in each powerdomain's register,
+	 * but the type of value returned is the same for each
+	 * powerdomain.
+	 */
+	switch (bank) {
+	case 0:
+		m = OMAP3430_SHAREDL1CACHEFLATRETSTATE;
+		break;
+	case 1:
+		m = OMAP3430_L1FLATMEMRETSTATE;
+		break;
+	case 2:
+		m = OMAP3430_SHAREDL2CACHEFLATRETSTATE;
+		break;
+	case 3:
+		m = OMAP3430_SHAREDL2CACHEFLATRETSTATE;
+		break;
+	default:
+		WARN_ON(1); /* should never happen */
+		return -EEXIST;
+	}
+
+	return prm_read_mod_bits_shift(pwrdm->prcm_offs,
+					PM_PWSTCTRL, m);
+}
+
+/**
  * pwrdm_clear_all_prev_pwrst - clear previous powerstate register for a pwrdm
  * @pwrdm: struct powerdomain * to clear
  *
diff --git a/arch/arm/plat-omap/include/plat/powerdomain.h b/arch/arm/plat-omap/include/plat/powerdomain.h
index 0b96005..7576559 100644
--- a/arch/arm/plat-omap/include/plat/powerdomain.h
+++ b/arch/arm/plat-omap/include/plat/powerdomain.h
@@ -170,8 +170,10 @@ int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
 
 int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm);
 int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm);
+int pwrdm_read_next_logic_pwrst(struct powerdomain *pwrdm);
 int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
 int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
+int pwrdm_read_next_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
 
 int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm);
 int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm);
-- 
1.5.6.3

[PATCH 4/8] OMAP3 PM: Defining .pwrsts_logic_ret field for core power domain structure

[Thara Gopinath]

This patch adds the flag .pwrsts_logic_ret info for the core power domain
in the associated powerdomain structure. This flag specifies the states
core domain logic can hit in event of the domain entering retention.

Signed-off-by: Thara Gopinath <thara@ti.com>
---
 arch/arm/mach-omap2/powerdomains34xx.h |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/powerdomains34xx.h b/arch/arm/mach-omap2/powerdomains34xx.h
index 588f7e0..6a058c7 100644
--- a/arch/arm/mach-omap2/powerdomains34xx.h
+++ b/arch/arm/mach-omap2/powerdomains34xx.h
@@ -208,6 +208,7 @@ static struct powerdomain core_34xx_pre_es3_1_pwrdm = {
 					   CHIP_IS_OMAP3430ES2 |
 					   CHIP_IS_OMAP3430ES3_0),
 	.pwrsts		  = PWRSTS_OFF_RET_ON,
+	.pwrsts_logic_ret = PWRSTS_OFF_RET,
 	.dep_bit	  = OMAP3430_EN_CORE_SHIFT,
 	.banks		  = 2,
 	.pwrsts_mem_ret	  = {
@@ -226,6 +227,7 @@ static struct powerdomain core_34xx_es3_1_pwrdm = {
 	.prcm_offs	  = CORE_MOD,
 	.omap_chip	  = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES3_1),
 	.pwrsts		  = PWRSTS_OFF_RET_ON,
+	.pwrsts_logic_ret = PWRSTS_OFF_RET,
 	.dep_bit	  = OMAP3430_EN_CORE_SHIFT,
 	.flags		  = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */
 	.banks		  = 2,
-- 
1.5.6.3

[PATCH 5/8] OMAP3 PM: Adding conditional core powerdomain context save and restore

[Thara Gopinath]

This patch adds a parameter core_state , depicting the power state
which the core domain will attempt to enter, to omap3_core_save_context
and omap3_core_restore_context. This is so as to distinguish between
the context save and restore required when core domain is attempting
OSWR and OFF. Core OSWR does not require interrupt controller,
system control module and dma controller context save and retore
where as Core OFF reuires these.

Signed-off-by: Thara Gopinath <thara@ti.com>
---
 arch/arm/mach-omap2/pm34xx.c |   71 +++++++++++++++++++++++++-----------------
 1 files changed, 42 insertions(+), 29 deletions(-)

diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 895e9ef..e4db1ea 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -150,44 +150,57 @@ static void omap3_disable_io_chain(void)
 		prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN, WKUP_MOD, PM_WKEN);
 }
 
-static void omap3_core_save_context(void)
+static void omap3_core_save_context(int core_state)
 {
-	u32 control_padconf_off;
+	if (core_state == PWRDM_POWER_OFF) {
+		u32 control_padconf_off;
+
+		/* Save the padconf registers */
+		control_padconf_off = omap_ctrl_readl(
+				OMAP343X_CONTROL_PADCONF_OFF);
+		control_padconf_off |= START_PADCONF_SAVE;
+		omap_ctrl_writel(control_padconf_off,
+				OMAP343X_CONTROL_PADCONF_OFF);
+		/* wait for the save to complete */
+		while (!(omap_ctrl_readl(
+				OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS) &
+				PADCONF_SAVE_DONE))
+			udelay(1);
 
-	/* Save the padconf registers */
-	control_padconf_off = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF);
-	control_padconf_off |= START_PADCONF_SAVE;
-	omap_ctrl_writel(control_padconf_off, OMAP343X_CONTROL_PADCONF_OFF);
-	/* wait for the save to complete */
-	while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS)
-			& PADCONF_SAVE_DONE))
-		udelay(1);
+		/*
+		 * Force write last pad into memory, as this can fail in some
+		 * cases according to erratas 1.157, 1.185
+		 */
+		omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
+				OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
 
-	/*
-	 * Force write last pad into memory, as this can fail in some
-	 * cases according to erratas 1.157, 1.185
-	 */
-	omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
-		OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
+		/* Save the Interrupt controller context */
+		omap_intc_save_context();
+
+		/* Save the system control module context,
+		 * padconf already save above
+		 */
+		omap3_control_save_context();
+		omap_dma_global_context_save();
+	}
 
-	/* Save the Interrupt controller context */
-	omap_intc_save_context();
 	/* Save the GPMC context */
 	omap3_gpmc_save_context();
-	/* Save the system control module context, padconf already save above*/
-	omap3_control_save_context();
-	omap_dma_global_context_save();
 }
 
-static void omap3_core_restore_context(void)
+static void omap3_core_restore_context(int core_state)
 {
-	/* Restore the control module context, padconf restored by h/w */
-	omap3_control_restore_context();
+	if (core_state == PWRDM_POWER_OFF) {
+		/* Restore the control module context,
+		 * padconf restored by h/w
+		 */
+		omap3_control_restore_context();
+		/* Restore the interrupt controller context */
+		omap_intc_restore_context();
+		omap_dma_global_context_restore();
+	}
 	/* Restore the GPMC context */
 	omap3_gpmc_restore_context();
-	/* Restore the interrupt controller context */
-	omap_intc_restore_context();
-	omap_dma_global_context_restore();
 }
 
 /*
@@ -445,7 +458,7 @@ void omap_sram_idle(void)
 			prm_set_mod_reg_bits(voltctrl,
 					     OMAP3430_GR_MOD,
 					     OMAP3_PRM_VOLTCTRL_OFFSET);
-			omap3_core_save_context();
+			omap3_core_save_context(PWRDM_POWER_OFF);
 			omap3_prcm_save_context();
 		} else if (core_next_state == PWRDM_POWER_RET) {
 			prm_set_mod_reg_bits(OMAP3430_AUTO_RET,
@@ -497,7 +510,7 @@ void omap_sram_idle(void)
 	if (core_next_state < PWRDM_POWER_ON) {
 		core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
 		if (core_prev_state == PWRDM_POWER_OFF) {
-			omap3_core_restore_context();
+			omap3_core_restore_context(core_prev_state);
 			omap3_prcm_restore_context();
 			omap3_sram_restore_context();
 			omap2_sms_restore_context();
-- 
1.5.6.3

[PATCH 6/8] OMAP3 PM: Enable DPLL4 autoidle after system off.

[Thara Gopinath]

DPLL4 autoidle is controlled through the register CM_PLL_AUTOIDLE
which is to be restored by rom code from the scratchpad in case
of a core domain context loss. But enabling this bit in scratchpad
causes rom code to take an extra 20 ms delay in the restore path.
To avoid this delay this bit is not enabled in the scratchpad today.
This means after a core off happens DPLL4 autoidle is never again
enabled back.
This patch enables DPLL4 autoidle in case of core domain losing
context.

Signed-off-by: Thara Gopinath <thara@ti.com>
---
 arch/arm/mach-omap2/pm34xx.c |    8 ++++++++
 1 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index e4db1ea..6e6d954 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -520,6 +520,14 @@ void omap_sram_idle(void)
 			 */
 			if (cpu_is_omap3430())
 				usb_musb_disable_autoidle();
+			/* We do not program the scratchpad to restore back
+			 * PER DPLL in autoidle due to 20 ms delay in
+			 * rom code restore path. So enable it explicitly
+			 * after core off
+			 */
+			cm_rmw_mod_reg_bits(
+				0x0, (1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT),
+				PLL_MOD, CM_AUTOIDLE);
 		}
 		omap_uart_resume_idle(0);
 		omap_uart_resume_idle(1);
-- 
1.5.6.3

[PATCH 7/8] OMAP3 PM: Support for Open Switch Retention for Core and MPU power domains in cpuidle path

[Thara Gopinath]

This patch adds Open SWitch Retention (OSWR) support for
MPU/CORE domains in Cpuidle. In addition to the normal
power domain retention(Closed SWitch retention) in OSWR,
the powerdomain logic is turned OFF. Power domain memory
banks can be chosen to be retained or turned off. In this
implementation both MPU and Core domain memory banks are
turned off during OSWR.
This patch also adds counters ret_logic_off_counter and
ret_mem_off_counter for each power domain. This keeps track
of power domain logic and memory off during powerdomain
retention. These counters together with the retention counter
can be used to find out whether a power domain has entered
OSWR or not. In case of OSWR both the retention counter and
ret_logic_off_counter will get incremented. ret_mem_off_counter
will get incremented if memory bank off during retention
is implemented. In this implementation in case of core or mpu
domain entering OSWR all three flags will be incremented. In
case of normal retention or CSWR only the retention counter
will be incremented

To support this feature two new C states are being added to
the existing C states which makes the new states look like below.

        C1 - MPU WFI + Core active
        C2 - MPU WFI + Core inactive
        C3 - MPU CSWR + Core inactive
        C4 - MPU OFF + Core inactive
        C5 - MPU CSWR + Core CSWR
        C6 - MPU OFF + Core CSWR
        C7 - MPU OSWR + CORE OSWR (New State)
        C8 - MPU OFF + CORE OSWR  (New State)
        C9 - MPU OFF + CORE OFF

Signed-off-by: Thara Gopinath <thara@ti.com>
---
 arch/arm/mach-omap2/board-3430sdp.c           |    4 +
 arch/arm/mach-omap2/cpuidle34xx.c             |  129 +++++++++++++++++++++++--
 arch/arm/mach-omap2/pm-debug.c                |    3 +
 arch/arm/mach-omap2/pm34xx.c                  |   55 +++++++++--
 arch/arm/mach-omap2/powerdomain.c             |   13 +++
 arch/arm/mach-omap2/sleep34xx.S               |    4 +
 arch/arm/plat-omap/include/plat/powerdomain.h |    2 +
 7 files changed, 194 insertions(+), 16 deletions(-)

diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index 7d68445..071cf22 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -72,6 +72,10 @@ static struct cpuidle_params omap3_cpuidle_params_table[] = {
 	/* C6 */
 	{1, 3000, 8500, 15000},
 	/* C7 */
+	{1, 4000, 10000, 150000},
+	/* C8 */
+	{1, 8000, 25000, 250000},
+	/* C9 */
 	{1, 10000, 30000, 300000},
 };
 
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
index 1cfa5a6..419f683 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -36,14 +36,16 @@
 
 #ifdef CONFIG_CPU_IDLE
 
-#define OMAP3_MAX_STATES 7
+#define OMAP3_MAX_STATES 9
 #define OMAP3_STATE_C1 0 /* C1 - MPU WFI + Core active */
 #define OMAP3_STATE_C2 1 /* C2 - MPU WFI + Core inactive */
 #define OMAP3_STATE_C3 2 /* C3 - MPU CSWR + Core inactive */
 #define OMAP3_STATE_C4 3 /* C4 - MPU OFF + Core iactive */
-#define OMAP3_STATE_C5 4 /* C5 - MPU RET + Core RET */
-#define OMAP3_STATE_C6 5 /* C6 - MPU OFF + Core RET */
-#define OMAP3_STATE_C7 6 /* C7 - MPU OFF + Core OFF */
+#define OMAP3_STATE_C5 4 /* C5 - MPU CSWR + Core CSWR */
+#define OMAP3_STATE_C6 5 /* C6 - MPU OFF + Core CSWR */
+#define OMAP3_STATE_C7 6 /* C7 - MPU OSWR + Core OSWR */
+#define OMAP3_STATE_C8 7 /* C8 - MPU OFF + Core OSWR */
+#define OMAP3_STATE_C9 8 /* C9 - MPU OFF + CORE OFF */
 
 struct omap3_processor_cx {
 	u8 valid;
@@ -52,6 +54,11 @@ struct omap3_processor_cx {
 	u32 wakeup_latency;
 	u32 mpu_state;
 	u32 core_state;
+	u32 mpu_logicl1_ret_state;
+	u32 mpu_l2cache_ret_state;
+	u32 core_logic_state;
+	u32 core_mem1_ret_state;
+	u32 core_mem2_ret_state;
 	u32 threshold;
 	u32 flags;
 };
@@ -81,6 +88,10 @@ static struct cpuidle_params cpuidle_params_table[] = {
 	/* C6 */
 	{1, 3000, 8500, 15000},
 	/* C7 */
+	{1, 4000, 10000, 150000},
+	/* C8 */
+	{1, 8000, 25000, 250000},
+	/* C9 */
 	{1, 10000, 30000, 300000},
 };
 
@@ -119,6 +130,11 @@ static int omap3_enter_idle(struct cpuidle_device *dev,
 	struct omap3_processor_cx *cx = cpuidle_get_statedata(state);
 	struct timespec ts_preidle, ts_postidle, ts_idle;
 	u32 mpu_state = cx->mpu_state, core_state = cx->core_state;
+	u32 mpu_logicl1_ret_state = cx->mpu_logicl1_ret_state;
+	u32 mpu_l2cache_ret_state = cx->mpu_l2cache_ret_state;
+	u32 core_logic_state = cx->core_logic_state;
+	u32 core_mem1_ret_state = cx->core_mem1_ret_state;
+	u32 core_mem2_ret_state = cx->core_mem2_ret_state;
 
 	current_cx_state = *cx;
 
@@ -135,6 +151,20 @@ static int omap3_enter_idle(struct cpuidle_device *dev,
 			core_state = PWRDM_POWER_RET;
 	}
 
+	/* For any state above inactive set the logic and memory retention
+	 * bits in case the powerdomain enters retention
+	 */
+	if (mpu_state <= PWRDM_POWER_RET) {
+		pwrdm_set_logic_retst(mpu_pd, mpu_logicl1_ret_state);
+		pwrdm_set_mem_retst(mpu_pd, 0, mpu_l2cache_ret_state);
+	}
+
+	if (core_state <= PWRDM_POWER_RET) {
+		pwrdm_set_logic_retst(core_pd, core_logic_state);
+		pwrdm_set_mem_retst(core_pd, 0, core_mem1_ret_state);
+		pwrdm_set_mem_retst(core_pd, 1, core_mem2_ret_state);
+	}
+
 	pwrdm_set_next_pwrst(mpu_pd, mpu_state);
 	pwrdm_set_next_pwrst(core_pd, core_state);
 
@@ -217,7 +247,7 @@ void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params)
  *	C3 . MPU CSWR + Core inactive
  *	C4 . MPU OFF + Core inactive
  *	C5 . MPU CSWR + Core CSWR
- *	C6 . MPU OFF + Core CSWR
+ *	C6 . MPU OFF + Core OSWR
  *	C7 . MPU OFF + Core OFF
  */
 void omap_init_power_states(void)
@@ -262,6 +292,10 @@ void omap_init_power_states(void)
 			cpuidle_params_table[OMAP3_STATE_C3].threshold;
 	omap3_power_states[OMAP3_STATE_C3].mpu_state = PWRDM_POWER_RET;
 	omap3_power_states[OMAP3_STATE_C3].core_state = PWRDM_POWER_ON;
+	omap3_power_states[OMAP3_STATE_C3].mpu_logicl1_ret_state =
+				PWRDM_POWER_RET;
+	omap3_power_states[OMAP3_STATE_C3].mpu_l2cache_ret_state =
+				PWRDM_POWER_RET;
 	omap3_power_states[OMAP3_STATE_C3].flags = CPUIDLE_FLAG_TIME_VALID |
 				CPUIDLE_FLAG_CHECK_BM;
 
@@ -277,6 +311,10 @@ void omap_init_power_states(void)
 			cpuidle_params_table[OMAP3_STATE_C4].threshold;
 	omap3_power_states[OMAP3_STATE_C4].mpu_state = PWRDM_POWER_OFF;
 	omap3_power_states[OMAP3_STATE_C4].core_state = PWRDM_POWER_ON;
+	omap3_power_states[OMAP3_STATE_C4].mpu_logicl1_ret_state =
+				PWRDM_POWER_RET;
+	omap3_power_states[OMAP3_STATE_C4].mpu_l2cache_ret_state =
+				PWRDM_POWER_RET;
 	omap3_power_states[OMAP3_STATE_C4].flags = CPUIDLE_FLAG_TIME_VALID |
 				CPUIDLE_FLAG_CHECK_BM;
 
@@ -292,6 +330,15 @@ void omap_init_power_states(void)
 			cpuidle_params_table[OMAP3_STATE_C5].threshold;
 	omap3_power_states[OMAP3_STATE_C5].mpu_state = PWRDM_POWER_RET;
 	omap3_power_states[OMAP3_STATE_C5].core_state = PWRDM_POWER_RET;
+	omap3_power_states[OMAP3_STATE_C5].mpu_logicl1_ret_state =
+				PWRDM_POWER_RET;
+	omap3_power_states[OMAP3_STATE_C5].mpu_l2cache_ret_state =
+				PWRDM_POWER_RET;
+	omap3_power_states[OMAP3_STATE_C5].core_logic_state = PWRDM_POWER_RET;
+	omap3_power_states[OMAP3_STATE_C5].core_mem1_ret_state =
+				PWRDM_POWER_RET;
+	omap3_power_states[OMAP3_STATE_C5].core_mem2_ret_state =
+				PWRDM_POWER_RET;
 	omap3_power_states[OMAP3_STATE_C5].flags = CPUIDLE_FLAG_TIME_VALID |
 				CPUIDLE_FLAG_CHECK_BM;
 
@@ -307,10 +354,19 @@ void omap_init_power_states(void)
 			cpuidle_params_table[OMAP3_STATE_C6].threshold;
 	omap3_power_states[OMAP3_STATE_C6].mpu_state = PWRDM_POWER_OFF;
 	omap3_power_states[OMAP3_STATE_C6].core_state = PWRDM_POWER_RET;
+	omap3_power_states[OMAP3_STATE_C6].mpu_logicl1_ret_state =
+				PWRDM_POWER_RET;
+	omap3_power_states[OMAP3_STATE_C6].mpu_l2cache_ret_state =
+				PWRDM_POWER_RET;
+	omap3_power_states[OMAP3_STATE_C6].core_logic_state = PWRDM_POWER_RET;
+	omap3_power_states[OMAP3_STATE_C6].core_mem1_ret_state =
+				PWRDM_POWER_RET;
+	omap3_power_states[OMAP3_STATE_C6].core_mem2_ret_state =
+				PWRDM_POWER_RET;
 	omap3_power_states[OMAP3_STATE_C6].flags = CPUIDLE_FLAG_TIME_VALID |
 				CPUIDLE_FLAG_CHECK_BM;
 
-	/* C7 . MPU OFF + Core OFF */
+	/* C7 . MPU OSWR + Core OSWR */
 	omap3_power_states[OMAP3_STATE_C7].valid =
 			cpuidle_params_table[OMAP3_STATE_C7].valid;
 	omap3_power_states[OMAP3_STATE_C7].type = OMAP3_STATE_C7;
@@ -320,10 +376,67 @@ void omap_init_power_states(void)
 			cpuidle_params_table[OMAP3_STATE_C7].wake_latency;
 	omap3_power_states[OMAP3_STATE_C7].threshold =
 			cpuidle_params_table[OMAP3_STATE_C7].threshold;
-	omap3_power_states[OMAP3_STATE_C7].mpu_state = PWRDM_POWER_OFF;
-	omap3_power_states[OMAP3_STATE_C7].core_state = PWRDM_POWER_OFF;
+	omap3_power_states[OMAP3_STATE_C7].mpu_state = PWRDM_POWER_RET;
+	omap3_power_states[OMAP3_STATE_C7].core_state = PWRDM_POWER_RET;
+	omap3_power_states[OMAP3_STATE_C7].mpu_logicl1_ret_state =
+				PWRDM_POWER_OFF;
+	omap3_power_states[OMAP3_STATE_C7].mpu_l2cache_ret_state =
+				PWRDM_POWER_OFF;
+	omap3_power_states[OMAP3_STATE_C7].core_logic_state = PWRDM_POWER_OFF;
+	omap3_power_states[OMAP3_STATE_C7].core_mem1_ret_state =
+				PWRDM_POWER_OFF;
+	omap3_power_states[OMAP3_STATE_C7].core_mem2_ret_state =
+				PWRDM_POWER_OFF;
 	omap3_power_states[OMAP3_STATE_C7].flags = CPUIDLE_FLAG_TIME_VALID |
 				CPUIDLE_FLAG_CHECK_BM;
+
+	/* C8 . MPU OFF + Core OSWR */
+	omap3_power_states[OMAP3_STATE_C8].valid =
+			cpuidle_params_table[OMAP3_STATE_C8].valid;
+	omap3_power_states[OMAP3_STATE_C8].type = OMAP3_STATE_C8;
+	omap3_power_states[OMAP3_STATE_C8].sleep_latency =
+			cpuidle_params_table[OMAP3_STATE_C8].sleep_latency;
+	omap3_power_states[OMAP3_STATE_C8].wakeup_latency =
+			cpuidle_params_table[OMAP3_STATE_C8].wake_latency;
+	omap3_power_states[OMAP3_STATE_C8].threshold =
+			cpuidle_params_table[OMAP3_STATE_C8].threshold;
+	omap3_power_states[OMAP3_STATE_C8].mpu_state = PWRDM_POWER_OFF;
+	omap3_power_states[OMAP3_STATE_C8].core_state = PWRDM_POWER_RET;
+	omap3_power_states[OMAP3_STATE_C8].mpu_logicl1_ret_state =
+				PWRDM_POWER_OFF;
+	omap3_power_states[OMAP3_STATE_C8].mpu_l2cache_ret_state =
+				PWRDM_POWER_OFF;
+	omap3_power_states[OMAP3_STATE_C8].core_logic_state = PWRDM_POWER_OFF;
+	omap3_power_states[OMAP3_STATE_C8].core_mem1_ret_state =
+				PWRDM_POWER_OFF;
+	omap3_power_states[OMAP3_STATE_C8].core_mem2_ret_state =
+				PWRDM_POWER_OFF;
+	omap3_power_states[OMAP3_STATE_C8].flags = CPUIDLE_FLAG_TIME_VALID |
+				CPUIDLE_FLAG_CHECK_BM;
+
+	/* C9 . MPU OFF + Core OFF */
+	omap3_power_states[OMAP3_STATE_C9].valid =
+			cpuidle_params_table[OMAP3_STATE_C9].valid;
+	omap3_power_states[OMAP3_STATE_C9].type = OMAP3_STATE_C9;
+	omap3_power_states[OMAP3_STATE_C9].sleep_latency =
+			cpuidle_params_table[OMAP3_STATE_C9].sleep_latency;
+	omap3_power_states[OMAP3_STATE_C9].wakeup_latency =
+			cpuidle_params_table[OMAP3_STATE_C9].wake_latency;
+	omap3_power_states[OMAP3_STATE_C9].threshold =
+			cpuidle_params_table[OMAP3_STATE_C9].threshold;
+	omap3_power_states[OMAP3_STATE_C9].mpu_state = PWRDM_POWER_OFF;
+	omap3_power_states[OMAP3_STATE_C9].core_state = PWRDM_POWER_OFF;
+	omap3_power_states[OMAP3_STATE_C9].mpu_logicl1_ret_state =
+				PWRDM_POWER_OFF;
+	omap3_power_states[OMAP3_STATE_C9].mpu_l2cache_ret_state =
+				PWRDM_POWER_OFF;
+	omap3_power_states[OMAP3_STATE_C9].core_logic_state = PWRDM_POWER_OFF;
+	omap3_power_states[OMAP3_STATE_C9].core_mem1_ret_state =
+				PWRDM_POWER_OFF;
+	omap3_power_states[OMAP3_STATE_C9].core_mem2_ret_state =
+				PWRDM_POWER_OFF;
+	omap3_power_states[OMAP3_STATE_C9].flags = CPUIDLE_FLAG_TIME_VALID |
+				CPUIDLE_FLAG_CHECK_BM;
 }
 
 struct cpuidle_driver omap3_idle_driver = {
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index 85a8c6e..035cfa7 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -385,6 +385,9 @@ static int pwrdm_dbg_show_counter(struct powerdomain *pwrdm, void *user)
 	for (i = 0; i < PWRDM_MAX_PWRSTS; i++)
 		seq_printf(s, ",%s:%d", pwrdm_state_names[i],
 			pwrdm->state_counter[i]);
+	seq_printf(s, ",RET-LOGIC-OFF:%d,RET-MEM-OFF:%d",
+			pwrdm->ret_logic_off_counter,
+			pwrdm->ret_mem_off_counter);
 
 	seq_printf(s, "\n");
 
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 6e6d954..bfdcac2 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -384,7 +384,8 @@ void omap_sram_idle(void)
 	int mpu_next_state = PWRDM_POWER_ON;
 	int per_next_state = PWRDM_POWER_ON;
 	int core_next_state = PWRDM_POWER_ON;
-	int core_prev_state, per_prev_state;
+	int mpu_prev_state, core_prev_state, per_prev_state;
+	int mpu_logic_state, mpu_mem_state, core_logic_state;
 	u32 sdrc_pwr = 0;
 	int per_state_modified = 0;
 
@@ -397,12 +398,25 @@ void omap_sram_idle(void)
 	pwrdm_clear_all_prev_pwrst(per_pwrdm);
 
 	mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
+	mpu_logic_state = pwrdm_read_next_logic_pwrst(mpu_pwrdm);
+	mpu_mem_state = pwrdm_read_next_mem_pwrst(mpu_pwrdm, 0);
+
 	switch (mpu_next_state) {
 	case PWRDM_POWER_ON:
-	case PWRDM_POWER_RET:
 		/* No need to save context */
 		save_state = 0;
 		break;
+	case PWRDM_POWER_RET:
+		if (!mpu_logic_state && !mpu_mem_state)
+			save_state = 3;
+		else if (!mpu_mem_state)
+			save_state = 2;
+		else if (!mpu_logic_state)
+			save_state = 1;
+		else
+			/* No need to save context */
+			save_state = 0;
+		break;
 	case PWRDM_POWER_OFF:
 		save_state = 3;
 		break;
@@ -421,6 +435,8 @@ void omap_sram_idle(void)
 	/* PER */
 	per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
 	core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
+	core_logic_state = pwrdm_read_next_logic_pwrst(core_pwrdm);
+
 	if (per_next_state < PWRDM_POWER_ON) {
 		omap2_gpio_prepare_for_idle(per_next_state);
 		if (per_next_state == PWRDM_POWER_OFF) {
@@ -448,8 +464,8 @@ void omap_sram_idle(void)
 
 	/* CORE */
 	if (core_next_state < PWRDM_POWER_ON) {
-		omap_uart_prepare_idle(0, core_next_state);
-		omap_uart_prepare_idle(1, core_next_state);
+		omap_uart_prepare_idle(0, core_next_state & core_logic_state);
+		omap_uart_prepare_idle(1, core_next_state & core_logic_state);
 		if (core_next_state == PWRDM_POWER_OFF) {
 			u32 voltctrl = OMAP3430_AUTO_OFF;
 
@@ -460,6 +476,20 @@ void omap_sram_idle(void)
 					     OMAP3_PRM_VOLTCTRL_OFFSET);
 			omap3_core_save_context(PWRDM_POWER_OFF);
 			omap3_prcm_save_context();
+		} else if ((core_next_state == PWRDM_POWER_RET) &&
+				(core_logic_state == PWRDM_POWER_OFF)) {
+			/* Disable DPLL4 autoidle bit so that register
+			 * contents match with that stored in the
+			 * scratchpad. If this is not done rom code
+			 * enters into some wrong path while coming
+			 * out of coreOSWR and causes a crash.
+			 */
+			cm_rmw_mod_reg_bits(OMAP3430_AUTO_PERIPH_DPLL_MASK,
+						0x0, PLL_MOD, CM_AUTOIDLE);
+			omap3_core_save_context(PWRDM_POWER_RET);
+			prm_set_mod_reg_bits(OMAP3430_AUTO_RET,
+						OMAP3430_GR_MOD,
+						OMAP3_PRM_VOLTCTRL_OFFSET);
 		} else if (core_next_state == PWRDM_POWER_RET) {
 			prm_set_mod_reg_bits(OMAP3430_AUTO_RET,
 						OMAP3430_GR_MOD,
@@ -502,18 +532,27 @@ void omap_sram_idle(void)
 	    core_next_state == PWRDM_POWER_OFF)
 		sdrc_write_reg(sdrc_pwr, SDRC_POWER);
 
+	mpu_prev_state = pwrdm_read_prev_pwrst(mpu_pwrdm);
 	/* Restore table entry modified during MMU restoration */
-	if (pwrdm_read_prev_pwrst(mpu_pwrdm) == PWRDM_POWER_OFF)
+	if (((mpu_prev_state == PWRDM_POWER_RET) &&
+			(pwrdm_read_prev_logic_pwrst(mpu_pwrdm) ==
+			 PWRDM_POWER_OFF)) || (mpu_prev_state ==
+			 PWRDM_POWER_OFF))
 		restore_table_entry();
 
 	/* CORE */
 	if (core_next_state < PWRDM_POWER_ON) {
 		core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
-		if (core_prev_state == PWRDM_POWER_OFF) {
+		if ((core_prev_state == PWRDM_POWER_OFF) ||
+				(core_prev_state == PWRDM_POWER_RET &&
+				pwrdm_read_prev_logic_pwrst(core_pwrdm) ==
+				PWRDM_POWER_OFF)) {
 			omap3_core_restore_context(core_prev_state);
-			omap3_prcm_restore_context();
+			if (core_prev_state == PWRDM_POWER_OFF) {
+				omap3_prcm_restore_context();
+				omap2_sms_restore_context();
+			}
 			omap3_sram_restore_context();
-			omap2_sms_restore_context();
 			/*
 			 * Errata 1.164 fix : OTG autoidle can prevent
 			 * sleep
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 06bf290..ef9f1bb 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -126,6 +126,16 @@ static int _pwrdm_state_switch(struct powerdomain *pwrdm, int flag)
 		prev = pwrdm_read_prev_pwrst(pwrdm);
 		if (pwrdm->state != prev)
 			pwrdm->state_counter[prev]++;
+		if (prev == PWRDM_POWER_RET) {
+			if ((pwrdm->pwrsts_logic_ret == PWRSTS_OFF_RET) &&
+					(pwrdm_read_prev_logic_pwrst(pwrdm) ==
+					 PWRDM_POWER_OFF))
+				pwrdm->ret_logic_off_counter++;
+			if ((pwrdm->pwrsts_mem_ret[0] == PWRSTS_OFF_RET) &&
+					(pwrdm_read_prev_mem_pwrst(pwrdm, 0) ==
+					PWRDM_POWER_OFF))
+				pwrdm->ret_mem_off_counter++;
+		}
 		break;
 	default:
 		return -EINVAL;
@@ -161,6 +171,9 @@ static __init void _pwrdm_setup(struct powerdomain *pwrdm)
 	for (i = 0; i < PWRDM_MAX_PWRSTS; i++)
 		pwrdm->state_counter[i] = 0;
 
+	pwrdm->ret_logic_off_counter = 0;
+	pwrdm->ret_mem_off_counter = 0;
+
 	pwrdm_wait_transition(pwrdm);
 	pwrdm->state = pwrdm_read_pwrst(pwrdm);
 	pwrdm->state_counter[pwrdm->state] = 1;
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index 69521be..1d88ef3 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -256,8 +256,12 @@ restore:
 	and     r2, r2, #0x3
 	cmp     r2, #0x0	@ Check if target power state was OFF or RET
         moveq   r9, #0x3        @ MPU OFF => L1 and L2 lost
+	beq	restore_from_off
+	cmp	r2, #0x1
+	moveq	r9, #0x3
 	movne	r9, #0x1	@ Only L1 and L2 lost => avoid L2 invalidation
 	bne	logic_l1_restore
+restore_from_off:
 	ldr	r0, control_stat
 	ldr	r1, [r0]
 	and	r1, #0x700
diff --git a/arch/arm/plat-omap/include/plat/powerdomain.h b/arch/arm/plat-omap/include/plat/powerdomain.h
index 7576559..405ccd6 100644
--- a/arch/arm/plat-omap/include/plat/powerdomain.h
+++ b/arch/arm/plat-omap/include/plat/powerdomain.h
@@ -124,6 +124,8 @@ struct powerdomain {
 
 	int state;
 	unsigned state_counter[PWRDM_MAX_PWRSTS];
+	unsigned ret_logic_off_counter;
+	unsigned ret_mem_off_counter;
 
 #ifdef CONFIG_PM_DEBUG
 	s64 timer;
-- 
1.5.6.3

[PATCH 8/8] OMAP3 PM: Support to enable disable OSWR feature from pm debug fs

[Thara Gopinath]

This patch adds enable_oswr flag in pm debug fs to enable
disable OSWR feature.
To enable this feature:
	echo 1 > <path>/debug/pm_debug/enable_oswr
To disable this feature
	echo 0 > <path>/debug/pm_debug/enable_oswr

Signed-off-by: Thara Gopinath <thara@ti.com>
---
 arch/arm/mach-omap2/cpuidle34xx.c |    9 +++++++++
 arch/arm/mach-omap2/pm-debug.c    |    2 ++
 arch/arm/mach-omap2/pm.h          |    1 +
 arch/arm/mach-omap2/pm34xx.c      |    1 +
 4 files changed, 13 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
index 419f683..91ef0df 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -155,11 +155,20 @@ static int omap3_enter_idle(struct cpuidle_device *dev,
 	 * bits in case the powerdomain enters retention
 	 */
 	if (mpu_state <= PWRDM_POWER_RET) {
+		if (!enable_oswr) {
+			mpu_logicl1_ret_state = PWRDM_POWER_RET;
+			mpu_l2cache_ret_state = PWRDM_POWER_RET;
+		}
 		pwrdm_set_logic_retst(mpu_pd, mpu_logicl1_ret_state);
 		pwrdm_set_mem_retst(mpu_pd, 0, mpu_l2cache_ret_state);
 	}
 
 	if (core_state <= PWRDM_POWER_RET) {
+		if (!enable_oswr) {
+			core_logic_state = PWRDM_POWER_RET;
+			core_mem1_ret_state = PWRDM_POWER_RET;
+			core_mem2_ret_state = PWRDM_POWER_RET;
+		}
 		pwrdm_set_logic_retst(core_pd, core_logic_state);
 		pwrdm_set_mem_retst(core_pd, 0, core_mem1_ret_state);
 		pwrdm_set_mem_retst(core_pd, 1, core_mem2_ret_state);
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index 035cfa7..cdb081b 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -601,6 +601,8 @@ static int __init pm_dbg_init(void)
 				   &enable_off_mode, &pm_dbg_option_fops);
 	(void) debugfs_create_file("sleep_while_idle", S_IRUGO | S_IWUGO, d,
 				   &sleep_while_idle, &pm_dbg_option_fops);
+	(void) debugfs_create_file("enable_oswr", S_IRUGO | S_IWUGO, d,
+				   &enable_oswr, &pm_dbg_option_fops);
 	(void) debugfs_create_file("wakeup_timer_seconds", S_IRUGO | S_IWUGO, d,
 				   &wakeup_timer_seconds, &pm_dbg_option_fops);
 
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 75aa685..03c49a8 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -15,6 +15,7 @@
 
 extern u32 enable_off_mode;
 extern u32 sleep_while_idle;
+extern u32 enable_oswr;
 extern u32 voltage_off_while_idle;
 
 extern void *omap3_secure_ram_storage;
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index bfdcac2..53c08a5 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -73,6 +73,7 @@ static inline bool is_suspending(void)
 
 u32 enable_off_mode;
 u32 sleep_while_idle;
+u32 enable_oswr;
 u32 wakeup_timer_seconds;
 u32 voltage_off_while_idle;
 
-- 
1.5.6.3

Re: [PATCH 8/8] OMAP3 PM: Support to enable disable OSWR feature from pm debug fs

[Kevin Hilman]

Thara Gopinath <thara@ti.com> writes:

> This patch adds enable_oswr flag in pm debug fs to enable
> disable OSWR feature.
> To enable this feature:
> 	echo 1 > <path>/debug/pm_debug/enable_oswr
> To disable this feature
> 	echo 0 > <path>/debug/pm_debug/enable_oswr
>
> Signed-off-by: Thara Gopinath <thara@ti.com>

I don't like this approach since it leads to incorrect CPUidle statistics.

Sanjeev has proposed a different approach[1] (which I still need to
review/merge) which just invalidates particular CPUidle states and
then lets the CPUidle enter hook only pick a valid state.

This then will work for the enable_off_mode support and the enable_oswr support
as well as anything else we can dream up down the road.

Kevin

[1] http://marc.info/?l=linux-omap&m=125908504530674&w=2

> ---
>  arch/arm/mach-omap2/cpuidle34xx.c |    9 +++++++++
>  arch/arm/mach-omap2/pm-debug.c    |    2 ++
>  arch/arm/mach-omap2/pm.h          |    1 +
>  arch/arm/mach-omap2/pm34xx.c      |    1 +
>  4 files changed, 13 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
> index 419f683..91ef0df 100644
> --- a/arch/arm/mach-omap2/cpuidle34xx.c
> +++ b/arch/arm/mach-omap2/cpuidle34xx.c
> @@ -155,11 +155,20 @@ static int omap3_enter_idle(struct cpuidle_device *dev,
>  	 * bits in case the powerdomain enters retention
>  	 */
>  	if (mpu_state <= PWRDM_POWER_RET) {
> +		if (!enable_oswr) {
> +			mpu_logicl1_ret_state = PWRDM_POWER_RET;
> +			mpu_l2cache_ret_state = PWRDM_POWER_RET;
> +		}
>  		pwrdm_set_logic_retst(mpu_pd, mpu_logicl1_ret_state);
>  		pwrdm_set_mem_retst(mpu_pd, 0, mpu_l2cache_ret_state);
>  	}
>  
>  	if (core_state <= PWRDM_POWER_RET) {
> +		if (!enable_oswr) {
> +			core_logic_state = PWRDM_POWER_RET;
> +			core_mem1_ret_state = PWRDM_POWER_RET;
> +			core_mem2_ret_state = PWRDM_POWER_RET;
> +		}
>  		pwrdm_set_logic_retst(core_pd, core_logic_state);
>  		pwrdm_set_mem_retst(core_pd, 0, core_mem1_ret_state);
>  		pwrdm_set_mem_retst(core_pd, 1, core_mem2_ret_state);
> diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
> index 035cfa7..cdb081b 100644
> --- a/arch/arm/mach-omap2/pm-debug.c
> +++ b/arch/arm/mach-omap2/pm-debug.c
> @@ -601,6 +601,8 @@ static int __init pm_dbg_init(void)
>  				   &enable_off_mode, &pm_dbg_option_fops);
>  	(void) debugfs_create_file("sleep_while_idle", S_IRUGO | S_IWUGO, d,
>  				   &sleep_while_idle, &pm_dbg_option_fops);
> +	(void) debugfs_create_file("enable_oswr", S_IRUGO | S_IWUGO, d,
> +				   &enable_oswr, &pm_dbg_option_fops);
>  	(void) debugfs_create_file("wakeup_timer_seconds", S_IRUGO | S_IWUGO, d,
>  				   &wakeup_timer_seconds, &pm_dbg_option_fops);
>  
> diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
> index 75aa685..03c49a8 100644
> --- a/arch/arm/mach-omap2/pm.h
> +++ b/arch/arm/mach-omap2/pm.h
> @@ -15,6 +15,7 @@
>  
>  extern u32 enable_off_mode;
>  extern u32 sleep_while_idle;
> +extern u32 enable_oswr;
>  extern u32 voltage_off_while_idle;
>  
>  extern void *omap3_secure_ram_storage;
> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
> index bfdcac2..53c08a5 100644
> --- a/arch/arm/mach-omap2/pm34xx.c
> +++ b/arch/arm/mach-omap2/pm34xx.c
> @@ -73,6 +73,7 @@ static inline bool is_suspending(void)
>  
>  u32 enable_off_mode;
>  u32 sleep_while_idle;
> +u32 enable_oswr;
>  u32 wakeup_timer_seconds;
>  u32 voltage_off_while_idle;
>  
> -- 
> 1.5.6.3
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

RE: [PATCH 8/8] OMAP3 PM: Support to enable disable OSWR feature from pm debug fs

[Gopinath, Thara]

>>-----Original Message-----
>>From: Kevin Hilman [mailto:khilman@deeprootsystems.com]
>>Sent: Saturday, January 23, 2010 6:12 AM
>>To: Gopinath, Thara
>>Cc: linux-omap@vger.kernel.org
>>Subject: Re: [PATCH 8/8] OMAP3 PM: Support to enable disable OSWR feature from pm debug fs
>>
>>Thara Gopinath <thara@ti.com> writes:
>>
>>> This patch adds enable_oswr flag in pm debug fs to enable
>>> disable OSWR feature.
>>> To enable this feature:
>>> 	echo 1 > <path>/debug/pm_debug/enable_oswr
>>> To disable this feature
>>> 	echo 0 > <path>/debug/pm_debug/enable_oswr
>>>
>>> Signed-off-by: Thara Gopinath <thara@ti.com>
>>
>>I don't like this approach since it leads to incorrect CPUidle statistics.
>>
>>Sanjeev has proposed a different approach[1] (which I still need to
>>review/merge) which just invalidates particular CPUidle states and
>>then lets the CPUidle enter hook only pick a valid state.
>>
>>This then will work for the enable_off_mode support and the enable_oswr support
>>as well as anything else we can dream up down the road.

Hi Kevin,

Yes I agree with you.. I did not implement this for OSWR as I did not see it in you pm branch. I thought let the first set of patches for OSWR be merged in and then when we change enable_off_mode we can change enable_oswr also. Is there an issue with this?

Regards
Thara 

>>
>>Kevin
>>
>>[1] http://marc.info/?l=linux-omap&m=125908504530674&w=2
>>
>>> ---
>>>  arch/arm/mach-omap2/cpuidle34xx.c |    9 +++++++++
>>>  arch/arm/mach-omap2/pm-debug.c    |    2 ++
>>>  arch/arm/mach-omap2/pm.h          |    1 +
>>>  arch/arm/mach-omap2/pm34xx.c      |    1 +
>>>  4 files changed, 13 insertions(+), 0 deletions(-)
>>>
>>> diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
>>> index 419f683..91ef0df 100644
>>> --- a/arch/arm/mach-omap2/cpuidle34xx.c
>>> +++ b/arch/arm/mach-omap2/cpuidle34xx.c
>>> @@ -155,11 +155,20 @@ static int omap3_enter_idle(struct cpuidle_device *dev,
>>>  	 * bits in case the powerdomain enters retention
>>>  	 */
>>>  	if (mpu_state <= PWRDM_POWER_RET) {
>>> +		if (!enable_oswr) {
>>> +			mpu_logicl1_ret_state = PWRDM_POWER_RET;
>>> +			mpu_l2cache_ret_state = PWRDM_POWER_RET;
>>> +		}
>>>  		pwrdm_set_logic_retst(mpu_pd, mpu_logicl1_ret_state);
>>>  		pwrdm_set_mem_retst(mpu_pd, 0, mpu_l2cache_ret_state);
>>>  	}
>>>
>>>  	if (core_state <= PWRDM_POWER_RET) {
>>> +		if (!enable_oswr) {
>>> +			core_logic_state = PWRDM_POWER_RET;
>>> +			core_mem1_ret_state = PWRDM_POWER_RET;
>>> +			core_mem2_ret_state = PWRDM_POWER_RET;
>>> +		}
>>>  		pwrdm_set_logic_retst(core_pd, core_logic_state);
>>>  		pwrdm_set_mem_retst(core_pd, 0, core_mem1_ret_state);
>>>  		pwrdm_set_mem_retst(core_pd, 1, core_mem2_ret_state);
>>> diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
>>> index 035cfa7..cdb081b 100644
>>> --- a/arch/arm/mach-omap2/pm-debug.c
>>> +++ b/arch/arm/mach-omap2/pm-debug.c
>>> @@ -601,6 +601,8 @@ static int __init pm_dbg_init(void)
>>>  				   &enable_off_mode, &pm_dbg_option_fops);
>>>  	(void) debugfs_create_file("sleep_while_idle", S_IRUGO | S_IWUGO, d,
>>>  				   &sleep_while_idle, &pm_dbg_option_fops);
>>> +	(void) debugfs_create_file("enable_oswr", S_IRUGO | S_IWUGO, d,
>>> +				   &enable_oswr, &pm_dbg_option_fops);
>>>  	(void) debugfs_create_file("wakeup_timer_seconds", S_IRUGO | S_IWUGO, d,
>>>  				   &wakeup_timer_seconds, &pm_dbg_option_fops);
>>>
>>> diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
>>> index 75aa685..03c49a8 100644
>>> --- a/arch/arm/mach-omap2/pm.h
>>> +++ b/arch/arm/mach-omap2/pm.h
>>> @@ -15,6 +15,7 @@
>>>
>>>  extern u32 enable_off_mode;
>>>  extern u32 sleep_while_idle;
>>> +extern u32 enable_oswr;
>>>  extern u32 voltage_off_while_idle;
>>>
>>>  extern void *omap3_secure_ram_storage;
>>> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
>>> index bfdcac2..53c08a5 100644
>>> --- a/arch/arm/mach-omap2/pm34xx.c
>>> +++ b/arch/arm/mach-omap2/pm34xx.c
>>> @@ -73,6 +73,7 @@ static inline bool is_suspending(void)
>>>
>>>  u32 enable_off_mode;
>>>  u32 sleep_while_idle;
>>> +u32 enable_oswr;
>>>  u32 wakeup_timer_seconds;
>>>  u32 voltage_off_while_idle;
>>>
>>> --
>>> 1.5.6.3
>>>
>>> --
>>> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
>>> the body of a message to majordomo@vger.kernel.org
>>> More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH 8/8] OMAP3 PM: Support to enable disable OSWR feature from pm debug fs

[Kevin Hilman]

"Gopinath, Thara" <thara@ti.com> writes:

>>>-----Original Message-----
>>>From: Kevin Hilman [mailto:khilman@deeprootsystems.com]
>>>Sent: Saturday, January 23, 2010 6:12 AM
>>>To: Gopinath, Thara
>>>Cc: linux-omap@vger.kernel.org
>>>Subject: Re: [PATCH 8/8] OMAP3 PM: Support to enable disable OSWR feature from pm debug fs
>>>
>>>Thara Gopinath <thara@ti.com> writes:
>>>
>>>> This patch adds enable_oswr flag in pm debug fs to enable
>>>> disable OSWR feature.
>>>> To enable this feature:
>>>> 	echo 1 > <path>/debug/pm_debug/enable_oswr
>>>> To disable this feature
>>>> 	echo 0 > <path>/debug/pm_debug/enable_oswr
>>>>
>>>> Signed-off-by: Thara Gopinath <thara@ti.com>
>>>
>>>I don't like this approach since it leads to incorrect CPUidle statistics.
>>>
>>>Sanjeev has proposed a different approach[1] (which I still need to
>>>review/merge) which just invalidates particular CPUidle states and
>>>then lets the CPUidle enter hook only pick a valid state.
>>>
>>>This then will work for the enable_off_mode support and the enable_oswr support
>>>as well as anything else we can dream up down the road.
>
> Hi Kevin,
>
> Yes I agree with you.. I did not implement this for OSWR as I did
> not see it in you pm branch. I thought let the first set of patches
> for OSWR be merged in and then when we change enable_off_mode we can
> change enable_oswr also. Is there an issue with this?

I would rather merge Sanjeev's patch first.  I just reviewed it and
asked him for a few minor fixes and then I'd like to merge it.

Kevin

Re: [PATCH 7/8] OMAP3 PM: Support for Open Switch Retention for Core and MPU power domains in cpuidle path

[Paul Walmsley]

Just FYI some of the multiline comments in this patch have the same 
problem as mentioned before.



- Paul

Re: [PATCH 7/8] OMAP3 PM: Support for Open Switch Retention for Core and MPU power domains in cpuidle path

[Kevin Hilman]

Thara Gopinath <thara@ti.com> writes:

> This patch adds Open SWitch Retention (OSWR) support for
> MPU/CORE domains in Cpuidle. In addition to the normal
> power domain retention(Closed SWitch retention) in OSWR,
> the powerdomain logic is turned OFF. Power domain memory
> banks can be chosen to be retained or turned off. In this
> implementation both MPU and Core domain memory banks are
> turned off during OSWR.
> This patch also adds counters ret_logic_off_counter and
> ret_mem_off_counter for each power domain. This keeps track
> of power domain logic and memory off during powerdomain
> retention. These counters together with the retention counter
> can be used to find out whether a power domain has entered
> OSWR or not. In case of OSWR both the retention counter and
> ret_logic_off_counter will get incremented. ret_mem_off_counter
> will get incremented if memory bank off during retention
> is implemented. In this implementation in case of core or mpu
> domain entering OSWR all three flags will be incremented. In
> case of normal retention or CSWR only the retention counter
> will be incremented
>
> To support this feature two new C states are being added to
> the existing C states which makes the new states look like below.
>
>         C1 - MPU WFI + Core active
>         C2 - MPU WFI + Core inactive
>         C3 - MPU CSWR + Core inactive
>         C4 - MPU OFF + Core inactive
>         C5 - MPU CSWR + Core CSWR
>         C6 - MPU OFF + Core CSWR
>         C7 - MPU OSWR + CORE OSWR (New State)
>         C8 - MPU OFF + CORE OSWR  (New State)
>         C9 - MPU OFF + CORE OFF
>
> Signed-off-by: Thara Gopinath <thara@ti.com>
> ---
>  arch/arm/mach-omap2/board-3430sdp.c           |    4 +
>  arch/arm/mach-omap2/cpuidle34xx.c             |  129 +++++++++++++++++++++++--
>  arch/arm/mach-omap2/pm-debug.c                |    3 +
>  arch/arm/mach-omap2/pm34xx.c                  |   55 +++++++++--
>  arch/arm/mach-omap2/powerdomain.c             |   13 +++
>  arch/arm/mach-omap2/sleep34xx.S               |    4 +
>  arch/arm/plat-omap/include/plat/powerdomain.h |    2 +
>  7 files changed, 194 insertions(+), 16 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
> index 7d68445..071cf22 100644
> --- a/arch/arm/mach-omap2/board-3430sdp.c
> +++ b/arch/arm/mach-omap2/board-3430sdp.c
> @@ -72,6 +72,10 @@ static struct cpuidle_params omap3_cpuidle_params_table[] = {
>  	/* C6 */
>  	{1, 3000, 8500, 15000},
>  	/* C7 */
> +	{1, 4000, 10000, 150000},
> +	/* C8 */
> +	{1, 8000, 25000, 250000},
> +	/* C9 */
>  	{1, 10000, 30000, 300000},
>  };
>  
> diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
> index 1cfa5a6..419f683 100644
> --- a/arch/arm/mach-omap2/cpuidle34xx.c
> +++ b/arch/arm/mach-omap2/cpuidle34xx.c
> @@ -36,14 +36,16 @@
>  
>  #ifdef CONFIG_CPU_IDLE
>  
> -#define OMAP3_MAX_STATES 7
> +#define OMAP3_MAX_STATES 9
>  #define OMAP3_STATE_C1 0 /* C1 - MPU WFI + Core active */
>  #define OMAP3_STATE_C2 1 /* C2 - MPU WFI + Core inactive */
>  #define OMAP3_STATE_C3 2 /* C3 - MPU CSWR + Core inactive */
>  #define OMAP3_STATE_C4 3 /* C4 - MPU OFF + Core iactive */
> -#define OMAP3_STATE_C5 4 /* C5 - MPU RET + Core RET */
> -#define OMAP3_STATE_C6 5 /* C6 - MPU OFF + Core RET */
> -#define OMAP3_STATE_C7 6 /* C7 - MPU OFF + Core OFF */
> +#define OMAP3_STATE_C5 4 /* C5 - MPU CSWR + Core CSWR */
> +#define OMAP3_STATE_C6 5 /* C6 - MPU OFF + Core CSWR */
> +#define OMAP3_STATE_C7 6 /* C7 - MPU OSWR + Core OSWR */
> +#define OMAP3_STATE_C8 7 /* C8 - MPU OFF + Core OSWR */
> +#define OMAP3_STATE_C9 8 /* C9 - MPU OFF + CORE OFF */
>  
>  struct omap3_processor_cx {
>  	u8 valid;
> @@ -52,6 +54,11 @@ struct omap3_processor_cx {
>  	u32 wakeup_latency;
>  	u32 mpu_state;
>  	u32 core_state;
> +	u32 mpu_logicl1_ret_state;
> +	u32 mpu_l2cache_ret_state;
> +	u32 core_logic_state;
> +	u32 core_mem1_ret_state;
> +	u32 core_mem2_ret_state;
>  	u32 threshold;
>  	u32 flags;
>  };
> @@ -81,6 +88,10 @@ static struct cpuidle_params cpuidle_params_table[] = {
>  	/* C6 */
>  	{1, 3000, 8500, 15000},
>  	/* C7 */
> +	{1, 4000, 10000, 150000},
> +	/* C8 */
> +	{1, 8000, 25000, 250000},
> +	/* C9 */
>  	{1, 10000, 30000, 300000},
>  };
>  
> @@ -119,6 +130,11 @@ static int omap3_enter_idle(struct cpuidle_device *dev,
>  	struct omap3_processor_cx *cx = cpuidle_get_statedata(state);
>  	struct timespec ts_preidle, ts_postidle, ts_idle;
>  	u32 mpu_state = cx->mpu_state, core_state = cx->core_state;
> +	u32 mpu_logicl1_ret_state = cx->mpu_logicl1_ret_state;
> +	u32 mpu_l2cache_ret_state = cx->mpu_l2cache_ret_state;
> +	u32 core_logic_state = cx->core_logic_state;
> +	u32 core_mem1_ret_state = cx->core_mem1_ret_state;
> +	u32 core_mem2_ret_state = cx->core_mem2_ret_state;
>  
>  	current_cx_state = *cx;
>  
> @@ -135,6 +151,20 @@ static int omap3_enter_idle(struct cpuidle_device *dev,
>  			core_state = PWRDM_POWER_RET;
>  	}
>  
> +	/* For any state above inactive set the logic and memory retention
> +	 * bits in case the powerdomain enters retention
> +	 */
> +	if (mpu_state <= PWRDM_POWER_RET) {
> +		pwrdm_set_logic_retst(mpu_pd, mpu_logicl1_ret_state);
> +		pwrdm_set_mem_retst(mpu_pd, 0, mpu_l2cache_ret_state);
> +	}
> +
> +	if (core_state <= PWRDM_POWER_RET) {
> +		pwrdm_set_logic_retst(core_pd, core_logic_state);
> +		pwrdm_set_mem_retst(core_pd, 0, core_mem1_ret_state);
> +		pwrdm_set_mem_retst(core_pd, 1, core_mem2_ret_state);
> +	}
> +
>  	pwrdm_set_next_pwrst(mpu_pd, mpu_state);
>  	pwrdm_set_next_pwrst(core_pd, core_state);
>  
> @@ -217,7 +247,7 @@ void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params)
>   *	C3 . MPU CSWR + Core inactive
>   *	C4 . MPU OFF + Core inactive
>   *	C5 . MPU CSWR + Core CSWR
> - *	C6 . MPU OFF + Core CSWR
> + *	C6 . MPU OFF + Core OSWR
>   *	C7 . MPU OFF + Core OFF
>   */
>  void omap_init_power_states(void)
> @@ -262,6 +292,10 @@ void omap_init_power_states(void)
>  			cpuidle_params_table[OMAP3_STATE_C3].threshold;
>  	omap3_power_states[OMAP3_STATE_C3].mpu_state = PWRDM_POWER_RET;
>  	omap3_power_states[OMAP3_STATE_C3].core_state = PWRDM_POWER_ON;
> +	omap3_power_states[OMAP3_STATE_C3].mpu_logicl1_ret_state =
> +				PWRDM_POWER_RET;
> +	omap3_power_states[OMAP3_STATE_C3].mpu_l2cache_ret_state =
> +				PWRDM_POWER_RET;
>  	omap3_power_states[OMAP3_STATE_C3].flags = CPUIDLE_FLAG_TIME_VALID |
>  				CPUIDLE_FLAG_CHECK_BM;
>  
> @@ -277,6 +311,10 @@ void omap_init_power_states(void)
>  			cpuidle_params_table[OMAP3_STATE_C4].threshold;
>  	omap3_power_states[OMAP3_STATE_C4].mpu_state = PWRDM_POWER_OFF;
>  	omap3_power_states[OMAP3_STATE_C4].core_state = PWRDM_POWER_ON;
> +	omap3_power_states[OMAP3_STATE_C4].mpu_logicl1_ret_state =
> +				PWRDM_POWER_RET;
> +	omap3_power_states[OMAP3_STATE_C4].mpu_l2cache_ret_state =
> +				PWRDM_POWER_RET;
>  	omap3_power_states[OMAP3_STATE_C4].flags = CPUIDLE_FLAG_TIME_VALID |
>  				CPUIDLE_FLAG_CHECK_BM;
>  
> @@ -292,6 +330,15 @@ void omap_init_power_states(void)
>  			cpuidle_params_table[OMAP3_STATE_C5].threshold;
>  	omap3_power_states[OMAP3_STATE_C5].mpu_state = PWRDM_POWER_RET;
>  	omap3_power_states[OMAP3_STATE_C5].core_state = PWRDM_POWER_RET;
> +	omap3_power_states[OMAP3_STATE_C5].mpu_logicl1_ret_state =
> +				PWRDM_POWER_RET;
> +	omap3_power_states[OMAP3_STATE_C5].mpu_l2cache_ret_state =
> +				PWRDM_POWER_RET;
> +	omap3_power_states[OMAP3_STATE_C5].core_logic_state = PWRDM_POWER_RET;
> +	omap3_power_states[OMAP3_STATE_C5].core_mem1_ret_state =
> +				PWRDM_POWER_RET;
> +	omap3_power_states[OMAP3_STATE_C5].core_mem2_ret_state =
> +				PWRDM_POWER_RET;
>  	omap3_power_states[OMAP3_STATE_C5].flags = CPUIDLE_FLAG_TIME_VALID |
>  				CPUIDLE_FLAG_CHECK_BM;
>  
> @@ -307,10 +354,19 @@ void omap_init_power_states(void)
>  			cpuidle_params_table[OMAP3_STATE_C6].threshold;
>  	omap3_power_states[OMAP3_STATE_C6].mpu_state = PWRDM_POWER_OFF;
>  	omap3_power_states[OMAP3_STATE_C6].core_state = PWRDM_POWER_RET;
> +	omap3_power_states[OMAP3_STATE_C6].mpu_logicl1_ret_state =
> +				PWRDM_POWER_RET;
> +	omap3_power_states[OMAP3_STATE_C6].mpu_l2cache_ret_state =
> +				PWRDM_POWER_RET;
> +	omap3_power_states[OMAP3_STATE_C6].core_logic_state = PWRDM_POWER_RET;
> +	omap3_power_states[OMAP3_STATE_C6].core_mem1_ret_state =
> +				PWRDM_POWER_RET;
> +	omap3_power_states[OMAP3_STATE_C6].core_mem2_ret_state =
> +				PWRDM_POWER_RET;
>  	omap3_power_states[OMAP3_STATE_C6].flags = CPUIDLE_FLAG_TIME_VALID |
>  				CPUIDLE_FLAG_CHECK_BM;
>  
> -	/* C7 . MPU OFF + Core OFF */
> +	/* C7 . MPU OSWR + Core OSWR */
>  	omap3_power_states[OMAP3_STATE_C7].valid =
>  			cpuidle_params_table[OMAP3_STATE_C7].valid;
>  	omap3_power_states[OMAP3_STATE_C7].type = OMAP3_STATE_C7;
> @@ -320,10 +376,67 @@ void omap_init_power_states(void)
>  			cpuidle_params_table[OMAP3_STATE_C7].wake_latency;
>  	omap3_power_states[OMAP3_STATE_C7].threshold =
>  			cpuidle_params_table[OMAP3_STATE_C7].threshold;
> -	omap3_power_states[OMAP3_STATE_C7].mpu_state = PWRDM_POWER_OFF;
> -	omap3_power_states[OMAP3_STATE_C7].core_state = PWRDM_POWER_OFF;
> +	omap3_power_states[OMAP3_STATE_C7].mpu_state = PWRDM_POWER_RET;
> +	omap3_power_states[OMAP3_STATE_C7].core_state = PWRDM_POWER_RET;
> +	omap3_power_states[OMAP3_STATE_C7].mpu_logicl1_ret_state =
> +				PWRDM_POWER_OFF;
> +	omap3_power_states[OMAP3_STATE_C7].mpu_l2cache_ret_state =
> +				PWRDM_POWER_OFF;
> +	omap3_power_states[OMAP3_STATE_C7].core_logic_state = PWRDM_POWER_OFF;
> +	omap3_power_states[OMAP3_STATE_C7].core_mem1_ret_state =
> +				PWRDM_POWER_OFF;
> +	omap3_power_states[OMAP3_STATE_C7].core_mem2_ret_state =
> +				PWRDM_POWER_OFF;
>  	omap3_power_states[OMAP3_STATE_C7].flags = CPUIDLE_FLAG_TIME_VALID |
>  				CPUIDLE_FLAG_CHECK_BM;
> +
> +	/* C8 . MPU OFF + Core OSWR */
> +	omap3_power_states[OMAP3_STATE_C8].valid =
> +			cpuidle_params_table[OMAP3_STATE_C8].valid;
> +	omap3_power_states[OMAP3_STATE_C8].type = OMAP3_STATE_C8;
> +	omap3_power_states[OMAP3_STATE_C8].sleep_latency =
> +			cpuidle_params_table[OMAP3_STATE_C8].sleep_latency;
> +	omap3_power_states[OMAP3_STATE_C8].wakeup_latency =
> +			cpuidle_params_table[OMAP3_STATE_C8].wake_latency;
> +	omap3_power_states[OMAP3_STATE_C8].threshold =
> +			cpuidle_params_table[OMAP3_STATE_C8].threshold;
> +	omap3_power_states[OMAP3_STATE_C8].mpu_state = PWRDM_POWER_OFF;
> +	omap3_power_states[OMAP3_STATE_C8].core_state = PWRDM_POWER_RET;
> +	omap3_power_states[OMAP3_STATE_C8].mpu_logicl1_ret_state =
> +				PWRDM_POWER_OFF;
> +	omap3_power_states[OMAP3_STATE_C8].mpu_l2cache_ret_state =
> +				PWRDM_POWER_OFF;
> +	omap3_power_states[OMAP3_STATE_C8].core_logic_state = PWRDM_POWER_OFF;
> +	omap3_power_states[OMAP3_STATE_C8].core_mem1_ret_state =
> +				PWRDM_POWER_OFF;
> +	omap3_power_states[OMAP3_STATE_C8].core_mem2_ret_state =
> +				PWRDM_POWER_OFF;
> +	omap3_power_states[OMAP3_STATE_C8].flags = CPUIDLE_FLAG_TIME_VALID |
> +				CPUIDLE_FLAG_CHECK_BM;
> +
> +	/* C9 . MPU OFF + Core OFF */
> +	omap3_power_states[OMAP3_STATE_C9].valid =
> +			cpuidle_params_table[OMAP3_STATE_C9].valid;
> +	omap3_power_states[OMAP3_STATE_C9].type = OMAP3_STATE_C9;
> +	omap3_power_states[OMAP3_STATE_C9].sleep_latency =
> +			cpuidle_params_table[OMAP3_STATE_C9].sleep_latency;
> +	omap3_power_states[OMAP3_STATE_C9].wakeup_latency =
> +			cpuidle_params_table[OMAP3_STATE_C9].wake_latency;
> +	omap3_power_states[OMAP3_STATE_C9].threshold =
> +			cpuidle_params_table[OMAP3_STATE_C9].threshold;
> +	omap3_power_states[OMAP3_STATE_C9].mpu_state = PWRDM_POWER_OFF;
> +	omap3_power_states[OMAP3_STATE_C9].core_state = PWRDM_POWER_OFF;
> +	omap3_power_states[OMAP3_STATE_C9].mpu_logicl1_ret_state =
> +				PWRDM_POWER_OFF;
> +	omap3_power_states[OMAP3_STATE_C9].mpu_l2cache_ret_state =
> +				PWRDM_POWER_OFF;
> +	omap3_power_states[OMAP3_STATE_C9].core_logic_state = PWRDM_POWER_OFF;
> +	omap3_power_states[OMAP3_STATE_C9].core_mem1_ret_state =
> +				PWRDM_POWER_OFF;
> +	omap3_power_states[OMAP3_STATE_C9].core_mem2_ret_state =
> +				PWRDM_POWER_OFF;
> +	omap3_power_states[OMAP3_STATE_C9].flags = CPUIDLE_FLAG_TIME_VALID |
> +				CPUIDLE_FLAG_CHECK_BM;
>  }
>  
>  struct cpuidle_driver omap3_idle_driver = {
> diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
> index 85a8c6e..035cfa7 100644
> --- a/arch/arm/mach-omap2/pm-debug.c
> +++ b/arch/arm/mach-omap2/pm-debug.c
> @@ -385,6 +385,9 @@ static int pwrdm_dbg_show_counter(struct powerdomain *pwrdm, void *user)
>  	for (i = 0; i < PWRDM_MAX_PWRSTS; i++)
>  		seq_printf(s, ",%s:%d", pwrdm_state_names[i],
>  			pwrdm->state_counter[i]);
> +	seq_printf(s, ",RET-LOGIC-OFF:%d,RET-MEM-OFF:%d",
> +			pwrdm->ret_logic_off_counter,
> +			pwrdm->ret_mem_off_counter);
>  
>  	seq_printf(s, "\n");
>  
> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
> index 6e6d954..bfdcac2 100644
> --- a/arch/arm/mach-omap2/pm34xx.c
> +++ b/arch/arm/mach-omap2/pm34xx.c
> @@ -384,7 +384,8 @@ void omap_sram_idle(void)
>  	int mpu_next_state = PWRDM_POWER_ON;
>  	int per_next_state = PWRDM_POWER_ON;
>  	int core_next_state = PWRDM_POWER_ON;
> -	int core_prev_state, per_prev_state;
> +	int mpu_prev_state, core_prev_state, per_prev_state;
> +	int mpu_logic_state, mpu_mem_state, core_logic_state;
>  	u32 sdrc_pwr = 0;
>  	int per_state_modified = 0;
>  
> @@ -397,12 +398,25 @@ void omap_sram_idle(void)
>  	pwrdm_clear_all_prev_pwrst(per_pwrdm);
>  
>  	mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
> +	mpu_logic_state = pwrdm_read_next_logic_pwrst(mpu_pwrdm);
> +	mpu_mem_state = pwrdm_read_next_mem_pwrst(mpu_pwrdm, 0);
> +
>  	switch (mpu_next_state) {
>  	case PWRDM_POWER_ON:
> -	case PWRDM_POWER_RET:
>  		/* No need to save context */
>  		save_state = 0;
>  		break;
> +	case PWRDM_POWER_RET:
> +		if (!mpu_logic_state && !mpu_mem_state)
> +			save_state = 3;
> +		else if (!mpu_mem_state)
> +			save_state = 2;
> +		else if (!mpu_logic_state)
> +			save_state = 1;
> +		else
> +			/* No need to save context */
> +			save_state = 0;
> +		break;
>  	case PWRDM_POWER_OFF:
>  		save_state = 3;
>  		break;
> @@ -421,6 +435,8 @@ void omap_sram_idle(void)
>  	/* PER */
>  	per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
>  	core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
> +	core_logic_state = pwrdm_read_next_logic_pwrst(core_pwrdm);
> +
>  	if (per_next_state < PWRDM_POWER_ON) {
>  		omap2_gpio_prepare_for_idle(per_next_state);
>  		if (per_next_state == PWRDM_POWER_OFF) {
> @@ -448,8 +464,8 @@ void omap_sram_idle(void)
>  
>  	/* CORE */
>  	if (core_next_state < PWRDM_POWER_ON) {
> -		omap_uart_prepare_idle(0, core_next_state);
> -		omap_uart_prepare_idle(1, core_next_state);
> +		omap_uart_prepare_idle(0, core_next_state & core_logic_state);
> +		omap_uart_prepare_idle(1, core_next_state & core_logic_state);

Hmm this (core_next_state & core_logic_state) bitwise AND logic isn't
terribly clear at first glance (at least to me) as it assumes that the
off value is zero.

For readability, I think we need something like:

    uart_power_state = ((core_next_state == PWRDM_POWER_OFF) ||
                        (core_logic_state == PWRDM_POWER_OFF))
    [...]
    omap_uart_prepare_idle(x, uart_power_state);
    
>  		if (core_next_state == PWRDM_POWER_OFF) {
>  			u32 voltctrl = OMAP3430_AUTO_OFF;
>  
> @@ -460,6 +476,20 @@ void omap_sram_idle(void)
>  					     OMAP3_PRM_VOLTCTRL_OFFSET);
>  			omap3_core_save_context(PWRDM_POWER_OFF);
>  			omap3_prcm_save_context();
> +		} else if ((core_next_state == PWRDM_POWER_RET) &&
> +            			(core_logic_state == PWRDM_POWER_OFF)) {
> +			/* Disable DPLL4 autoidle bit so that register
> +			 * contents match with that stored in the
> +			 * scratchpad. If this is not done rom code
> +			 * enters into some wrong path while coming
> +			 * out of coreOSWR and causes a crash.
> +			 */
> +			cm_rmw_mod_reg_bits(OMAP3430_AUTO_PERIPH_DPLL_MASK,
> +						0x0, PLL_MOD, CM_AUTOIDLE);
> +			omap3_core_save_context(PWRDM_POWER_RET);
> +			prm_set_mod_reg_bits(OMAP3430_AUTO_RET,
> +						OMAP3430_GR_MOD,
> +						OMAP3_PRM_VOLTCTRL_OFFSET);
>  		} else if (core_next_state == PWRDM_POWER_RET) {
>  			prm_set_mod_reg_bits(OMAP3430_AUTO_RET,
>  						OMAP3430_GR_MOD,
> @@ -502,18 +532,27 @@ void omap_sram_idle(void)
>  	    core_next_state == PWRDM_POWER_OFF)
>  		sdrc_write_reg(sdrc_pwr, SDRC_POWER);
>  
> +	mpu_prev_state = pwrdm_read_prev_pwrst(mpu_pwrdm);
>  	/* Restore table entry modified during MMU restoration */
> -	if (pwrdm_read_prev_pwrst(mpu_pwrdm) == PWRDM_POWER_OFF)
> +	if (((mpu_prev_state == PWRDM_POWER_RET) &&
> +			(pwrdm_read_prev_logic_pwrst(mpu_pwrdm) ==
> +			 PWRDM_POWER_OFF)) || (mpu_prev_state ==
> +			 PWRDM_POWER_OFF))

minor: for consistency with below checks for CORE, check for OFF
first, then for RET/OSWR.

>  		restore_table_entry();
>  
>  	/* CORE */
>  	if (core_next_state < PWRDM_POWER_ON) {
>  		core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
> -		if (core_prev_state == PWRDM_POWER_OFF) {
> +		if ((core_prev_state == PWRDM_POWER_OFF) ||
> +				(core_prev_state == PWRDM_POWER_RET &&
> +				pwrdm_read_prev_logic_pwrst(core_pwrdm) ==
> +				PWRDM_POWER_OFF)) {
>  			omap3_core_restore_context(core_prev_state);
> -			omap3_prcm_restore_context();
> +			if (core_prev_state == PWRDM_POWER_OFF) {
> +				omap3_prcm_restore_context();
> +				omap2_sms_restore_context();
> +			}
>  			omap3_sram_restore_context();
> -			omap2_sms_restore_context();
>  			/*
>  			 * Errata 1.164 fix : OTG autoidle can prevent
>  			 * sleep
> diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
> index 06bf290..ef9f1bb 100644
> --- a/arch/arm/mach-omap2/powerdomain.c
> +++ b/arch/arm/mach-omap2/powerdomain.c
> @@ -126,6 +126,16 @@ static int _pwrdm_state_switch(struct powerdomain *pwrdm, int flag)
>  		prev = pwrdm_read_prev_pwrst(pwrdm);
>  		if (pwrdm->state != prev)
>  			pwrdm->state_counter[prev]++;
> +		if (prev == PWRDM_POWER_RET) {
> +			if ((pwrdm->pwrsts_logic_ret == PWRSTS_OFF_RET) &&
> +					(pwrdm_read_prev_logic_pwrst(pwrdm) ==
> +					 PWRDM_POWER_OFF))
> +				pwrdm->ret_logic_off_counter++;
> +			if ((pwrdm->pwrsts_mem_ret[0] == PWRSTS_OFF_RET) &&
> +					(pwrdm_read_prev_mem_pwrst(pwrdm, 0) ==
> +					PWRDM_POWER_OFF))
> +				pwrdm->ret_mem_off_counter++;
> +		}
>  		break;
>  	default:
>  		return -EINVAL;
> @@ -161,6 +171,9 @@ static __init void _pwrdm_setup(struct powerdomain *pwrdm)
>  	for (i = 0; i < PWRDM_MAX_PWRSTS; i++)
>  		pwrdm->state_counter[i] = 0;
>  
> +	pwrdm->ret_logic_off_counter = 0;
> +	pwrdm->ret_mem_off_counter = 0;
> +
>  	pwrdm_wait_transition(pwrdm);
>  	pwrdm->state = pwrdm_read_pwrst(pwrdm);
>  	pwrdm->state_counter[pwrdm->state] = 1;
> diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
> index 69521be..1d88ef3 100644
> --- a/arch/arm/mach-omap2/sleep34xx.S
> +++ b/arch/arm/mach-omap2/sleep34xx.S
> @@ -256,8 +256,12 @@ restore:
>  	and     r2, r2, #0x3
>  	cmp     r2, #0x0	@ Check if target power state was OFF or RET
>          moveq   r9, #0x3        @ MPU OFF => L1 and L2 lost
> +	beq	restore_from_off
> +	cmp	r2, #0x1
> +	moveq	r9, #0x3
>  	movne	r9, #0x1	@ Only L1 and L2 lost => avoid L2 invalidation
>  	bne	logic_l1_restore
> +restore_from_off:
>  	ldr	r0, control_stat
>  	ldr	r1, [r0]
>  	and	r1, #0x700
> diff --git a/arch/arm/plat-omap/include/plat/powerdomain.h b/arch/arm/plat-omap/include/plat/powerdomain.h
> index 7576559..405ccd6 100644
> --- a/arch/arm/plat-omap/include/plat/powerdomain.h
> +++ b/arch/arm/plat-omap/include/plat/powerdomain.h
> @@ -124,6 +124,8 @@ struct powerdomain {
>  
>  	int state;
>  	unsigned state_counter[PWRDM_MAX_PWRSTS];
> +	unsigned ret_logic_off_counter;
> +	unsigned ret_mem_off_counter;
>  
>  #ifdef CONFIG_PM_DEBUG
>  	s64 timer;
> -- 
> 1.5.6.3
>
> --
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> the body of a message to majordomo@vger.kernel.org
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Re: [PATCH 6/8] OMAP3 PM: Enable DPLL4 autoidle after system off.

[Paul Walmsley]

Hi Thara,

two comments:

On Wed, 20 Jan 2010, Thara Gopinath wrote:

> DPLL4 autoidle is controlled through the register CM_PLL_AUTOIDLE
> which is to be restored by rom code from the scratchpad in case
> of a core domain context loss. But enabling this bit in scratchpad
> causes rom code to take an extra 20 ms delay in the restore path.
> To avoid this delay this bit is not enabled in the scratchpad today.
> This means after a core off happens DPLL4 autoidle is never again
> enabled back.
> This patch enables DPLL4 autoidle in case of core domain losing
> context.

Shouldn't this be contingent on whether DPLL4 autoidle was enabled before 
the CORE off transition?

> Signed-off-by: Thara Gopinath <thara@ti.com>
> ---
>  arch/arm/mach-omap2/pm34xx.c |    8 ++++++++
>  1 files changed, 8 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
> index e4db1ea..6e6d954 100644
> --- a/arch/arm/mach-omap2/pm34xx.c
> +++ b/arch/arm/mach-omap2/pm34xx.c
> @@ -520,6 +520,14 @@ void omap_sram_idle(void)
>  			 */
>  			if (cpu_is_omap3430())
>  				usb_musb_disable_autoidle();
> +			/* We do not program the scratchpad to restore back
> +			 * PER DPLL in autoidle due to 20 ms delay in
> +			 * rom code restore path. So enable it explicitly
> +			 * after core off
> +			 */

This multi-line comment needs to be fixed to conform to 
Documentation/CodingStyle.

> +			cm_rmw_mod_reg_bits(
> +				0x0, (1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT),
> +				PLL_MOD, CM_AUTOIDLE);
>  		}
>  		omap_uart_resume_idle(0);
>  		omap_uart_resume_idle(1);
> -- 
> 1.5.6.3
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
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> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 


- Paul

RE: [PATCH 6/8] OMAP3 PM: Enable DPLL4 autoidle after system off.

[Gopinath, Thara]

>>-----Original Message-----
>>From: Paul Walmsley [mailto:paul@pwsan.com]
>>Sent: Wednesday, January 20, 2010 11:05 PM
>>To: Gopinath, Thara
>>Cc: linux-omap@vger.kernel.org
>>Subject: Re: [PATCH 6/8] OMAP3 PM: Enable DPLL4 autoidle after system off.
>>
>>Hi Thara,
>>
>>two comments:
>>
>>On Wed, 20 Jan 2010, Thara Gopinath wrote:
>>
>>> DPLL4 autoidle is controlled through the register CM_PLL_AUTOIDLE
>>> which is to be restored by rom code from the scratchpad in case
>>> of a core domain context loss. But enabling this bit in scratchpad
>>> causes rom code to take an extra 20 ms delay in the restore path.
>>> To avoid this delay this bit is not enabled in the scratchpad today.
>>> This means after a core off happens DPLL4 autoidle is never again
>>> enabled back.
>>> This patch enables DPLL4 autoidle in case of core domain losing
>>> context.
>>
>>Shouldn't this be contingent on whether DPLL4 autoidle was enabled before
>>the CORE off transition?

Hi Paul,
Hmmm may be yes.. But you see today we enable all autoidle bits in the init. Why I had to make this unconditional is because later before core entering OSWR I explicitly disable this bit in the register. This is so as to match this register content with those of scratchpad during OSWR. Failing to do this rom code while exiting OSWR will take the path it takes while coming out of core off . This causes a crash in the system today. Also another reason is omap3_prcm_save_context needs to be called only during core off today. If I move saving of this bit and restoring it back into omap3_prcm_save_context and omap3_prcm_restore_context I will have to call it during core OSWR also. Wanted to avoid the extra complications.
But if this approach is not ok, I can modify the save restore APIs to take power state as a parameter and do only dpll4 autoidle save and restore in case of OSWR. Is this ok?

>>
>>> Signed-off-by: Thara Gopinath <thara@ti.com>
>>> ---
>>>  arch/arm/mach-omap2/pm34xx.c |    8 ++++++++
>>>  1 files changed, 8 insertions(+), 0 deletions(-)
>>>
>>> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
>>> index e4db1ea..6e6d954 100644
>>> --- a/arch/arm/mach-omap2/pm34xx.c
>>> +++ b/arch/arm/mach-omap2/pm34xx.c
>>> @@ -520,6 +520,14 @@ void omap_sram_idle(void)
>>>  			 */
>>>  			if (cpu_is_omap3430())
>>>  				usb_musb_disable_autoidle();
>>> +			/* We do not program the scratchpad to restore back
>>> +			 * PER DPLL in autoidle due to 20 ms delay in
>>> +			 * rom code restore path. So enable it explicitly
>>> +			 * after core off
>>> +			 */
>>
>>This multi-line comment needs to be fixed to conform to
>>Documentation/CodingStyle.

Oops.. My bad. Will fix and resend the patch. Don't know why checkpatch is not catching this. I will wait a couple of days for comments on other patches also and resend all of them after fixing the relevant comments.
>>
>>> +			cm_rmw_mod_reg_bits(
>>> +				0x0, (1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT),
>>> +				PLL_MOD, CM_AUTOIDLE);
>>>  		}
>>>  		omap_uart_resume_idle(0);
>>>  		omap_uart_resume_idle(1);
>>> --
>>> 1.5.6.3
>>>
>>> --
>>> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
>>> the body of a message to majordomo@vger.kernel.org
>>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>>>
>>
>>
>>- Paul

RE: [PATCH 6/8] OMAP3 PM: Enable DPLL4 autoidle after system off.

[Paul Walmsley]

Hello Thara,

On Thu, 21 Jan 2010, Gopinath, Thara wrote:

> >>-----Original Message-----
> >>From: Paul Walmsley [mailto:paul@pwsan.com]
> >>Sent: Wednesday, January 20, 2010 11:05 PM
> >>To: Gopinath, Thara
> >>Cc: linux-omap@vger.kernel.org
> >>Subject: Re: [PATCH 6/8] OMAP3 PM: Enable DPLL4 autoidle after system off.
> >>
> >>On Wed, 20 Jan 2010, Thara Gopinath wrote:
> >>
> >>> DPLL4 autoidle is controlled through the register CM_PLL_AUTOIDLE
> >>> which is to be restored by rom code from the scratchpad in case
> >>> of a core domain context loss. But enabling this bit in scratchpad
> >>> causes rom code to take an extra 20 ms delay in the restore path.
> >>> To avoid this delay this bit is not enabled in the scratchpad today.
> >>> This means after a core off happens DPLL4 autoidle is never again
> >>> enabled back.
> >>> This patch enables DPLL4 autoidle in case of core domain losing
> >>> context.
> >>
> >>Shouldn't this be contingent on whether DPLL4 autoidle was enabled before
> >>the CORE off transition?
> 
> Hi Paul, Hmmm may be yes.. But you see today we enable all autoidle bits 
> in the init.

That may change depending on device wakeup latency constraints.  If a 
device has a low wakeup latency, we may choose to keep a DPLL running.  
Sometimes this is also changed to work around silicon bugs.  So we should 
avoid adding code that makes assumptions about any of those autoidle bits.

> Why I had to make this unconditional is because later before core 
> entering OSWR I explicitly disable this bit in the register. This is so 
> as to match this register content with those of scratchpad during OSWR. 
> Failing to do this rom code while exiting OSWR will take the path it 
> takes while coming out of core off . This causes a crash in the system 
> today. 

Fine, but can't you save the previous state of the DPLL autoidle with 
omap3_dpll_autoidle_read() before you disable it prior to OSWR, and just 
restore it afterwards?

> Also another reason is omap3_prcm_save_context needs to be called 
> only during core off today.

Is this because the CM registers are part of the logic section of the CORE 
powerdomain?

> If I move saving of this bit and restoring it back into 
> omap3_prcm_save_context and omap3_prcm_restore_context I will have to 
> call it during core OSWR also.

If you're not calling those now for OSWR, you shouldn't have to call them 
just to save and restore the DPLL4 autoidle state, right?  Wouldn't it 
work to simply read the current autoidle state with 
omap3_dpll_autoidle_read() before entering OSWR, then restore it 
afterwards with omap3_dpll_{allow,deny}_idle() ?

> Wanted to avoid the extra complications. 

And the extra delay.  Reads and writes from L4_WAKEUP-connected devices 
are sllloooooowwwww.

> But if this approach is not ok, I can modify the save restore APIs to 
> take power state as a parameter and do only dpll4 autoidle save and 
> restore in case of OSWR. Is this ok?

Well, let me know what you think of the above...

> >>> Signed-off-by: Thara Gopinath <thara@ti.com>
> >>> ---
> >>>  arch/arm/mach-omap2/pm34xx.c |    8 ++++++++
> >>>  1 files changed, 8 insertions(+), 0 deletions(-)
> >>>
> >>> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
> >>> index e4db1ea..6e6d954 100644
> >>> --- a/arch/arm/mach-omap2/pm34xx.c
> >>> +++ b/arch/arm/mach-omap2/pm34xx.c
> >>> @@ -520,6 +520,14 @@ void omap_sram_idle(void)
> >>>  			 */
> >>>  			if (cpu_is_omap3430())
> >>>  				usb_musb_disable_autoidle();
> >>> +			/* We do not program the scratchpad to restore back
> >>> +			 * PER DPLL in autoidle due to 20 ms delay in
> >>> +			 * rom code restore path. So enable it explicitly
> >>> +			 * after core off
> >>> +			 */
> >>
> >>This multi-line comment needs to be fixed to conform to
> >>Documentation/CodingStyle.
> 
> Oops.. My bad. Will fix and resend the patch. Don't know why checkpatch 
> is not catching this. I will wait a couple of days for comments on other 
> patches also and resend all of them after fixing the relevant comments.
>
> >>> +			cm_rmw_mod_reg_bits(
> >>> +				0x0, (1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT),
> >>> +				PLL_MOD, CM_AUTOIDLE);

One other comment.  Any reason why this patch can't use the 
omap3_dpll_allow_idle() and omap3_dpll_deny_idle() functions, rather than 
writing to the register directly?

> >>>  		}
> >>>  		omap_uart_resume_idle(0);
> >>>  		omap_uart_resume_idle(1);
> >>> --
> >>> 1.5.6.3


- Paul

RE: [PATCH 6/8] OMAP3 PM: Enable DPLL4 autoidle after system off.

[Gopinath, Thara]

Hi Paul,
>>
>>That may change depending on device wakeup latency constraints.  If a
>>device has a low wakeup latency, we may choose to keep a DPLL running.
>>Sometimes this is also changed to work around silicon bugs.  So we should
>>avoid adding code that makes assumptions about any of those autoidle bits.
>>
>>> Why I had to make this unconditional is because later before core
>>> entering OSWR I explicitly disable this bit in the register. This is so
>>> as to match this register content with those of scratchpad during OSWR.
>>> Failing to do this rom code while exiting OSWR will take the path it
>>> takes while coming out of core off . This causes a crash in the system
>>> today.
>>
>>Fine, but can't you save the previous state of the DPLL autoidle with
>>omap3_dpll_autoidle_read() before you disable it prior to OSWR, and just
>>restore it afterwards?
>>
>>> Also another reason is omap3_prcm_save_context needs to be called
>>> only during core off today.
>>
>>Is this because the CM registers are part of the logic section of the CORE
>>powerdomain?

This is because CM module is built with Retention flip flops(RFF) and during OSWR the voltage is still supplied to the logic built with RFF. Thus no content loss.

>>
>>> If I move saving of this bit and restoring it back into
>>> omap3_prcm_save_context and omap3_prcm_restore_context I will have to
>>> call it during core OSWR also.
>>
>>If you're not calling those now for OSWR, you shouldn't have to call them
>>just to save and restore the DPLL4 autoidle state, right?  Wouldn't it
>>work to simply read the current autoidle state with
>>omap3_dpll_autoidle_read() before entering OSWR, then restore it
>>afterwards with omap3_dpll_{allow,deny}_idle() ?
>>
>>> Wanted to avoid the extra complications.
>>
>>And the extra delay.  Reads and writes from L4_WAKEUP-connected devices
>>are sllloooooowwwww.

Agreed.
>>
>>> But if this approach is not ok, I can modify the save restore APIs to
>>> take power state as a parameter and do only dpll4 autoidle save and
>>> restore in case of OSWR. Is this ok?
>>
>>Well, let me know what you think of the above...

I am ok with this. Only thing is it will involve a clk_get("dpll4_clk") and then rest of the API calls as you have suggested. Considering this is in cpuidle path, will the latencies be high?
If we have a latency issue, we can still keep the logic same as you have suggested and instead of dpll api's directly use CM API's to implement the same. So use cm_read_mod_reg and cm_rmw_mod_reg_bits.

Regards
Thara

RE: [PATCH 6/8] OMAP3 PM: Enable DPLL4 autoidle after system off.

[Paul Walmsley]

Hi,

On Thu, 21 Jan 2010, Gopinath, Thara wrote:

> >>> But if this approach is not ok, I can modify the save restore APIs to
> >>> take power state as a parameter and do only dpll4 autoidle save and
> >>> restore in case of OSWR. Is this ok?
> >>
> >>Well, let me know what you think of the above...
> 
> I am ok with this. Only thing is it will involve a clk_get("dpll4_clk") 
> and then rest of the API calls as you have suggested. Considering this 
> is in cpuidle path, will the latencies be high?

How about doing the clk_get() in advance in omap3_pm_init(), and store the 
struct clk pointer in a static variable that can be referenced from the 
cpuidle path?

> If we have a latency issue, we can still keep the logic same as you have 
> suggested and instead of dpll api's directly use CM API's to implement 
> the same. So use cm_read_mod_reg and cm_rmw_mod_reg_bits.

We could but let's try the DPLL API first.  I doubt the difference between 
using the DPLL API and using the cm_* functions will be measurable.  If 
you look at the code for those functions, there's not much to them.


- Paul

Re: [PATCH 5/8] OMAP3 PM: Adding conditional core powerdomain context save and restore

[Kevin Hilman]

Thara Gopinath <thara@ti.com> writes:

> This patch adds a parameter core_state , depicting the power state
> which the core domain will attempt to enter, to omap3_core_save_context
> and omap3_core_restore_context. This is so as to distinguish between
> the context save and restore required when core domain is attempting
> OSWR and OFF. Core OSWR does not require interrupt controller,
> system control module and dma controller context save and retore
> where as Core OFF reuires these.
>
> Signed-off-by: Thara Gopinath <thara@ti.com>

Looks good, pulling this into PM branch after one minor fixup below...

> ---
>  arch/arm/mach-omap2/pm34xx.c |   71 +++++++++++++++++++++++++-----------------
>  1 files changed, 42 insertions(+), 29 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
> index 895e9ef..e4db1ea 100644
> --- a/arch/arm/mach-omap2/pm34xx.c
> +++ b/arch/arm/mach-omap2/pm34xx.c
> @@ -150,44 +150,57 @@ static void omap3_disable_io_chain(void)
>  		prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN, WKUP_MOD, PM_WKEN);
>  }
>  
> -static void omap3_core_save_context(void)
> +static void omap3_core_save_context(int core_state)
>  {
> -	u32 control_padconf_off;
> +	if (core_state == PWRDM_POWER_OFF) {
> +		u32 control_padconf_off;
> +
> +		/* Save the padconf registers */
> +		control_padconf_off = omap_ctrl_readl(
> +				OMAP343X_CONTROL_PADCONF_OFF);
> +		control_padconf_off |= START_PADCONF_SAVE;
> +		omap_ctrl_writel(control_padconf_off,
> +				OMAP343X_CONTROL_PADCONF_OFF);
> +		/* wait for the save to complete */
> +		while (!(omap_ctrl_readl(
> +				OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS) &
> +				PADCONF_SAVE_DONE))
> +			udelay(1);
>  
> -	/* Save the padconf registers */
> -	control_padconf_off = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF);
> -	control_padconf_off |= START_PADCONF_SAVE;
> -	omap_ctrl_writel(control_padconf_off, OMAP343X_CONTROL_PADCONF_OFF);
> -	/* wait for the save to complete */
> -	while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS)
> -			& PADCONF_SAVE_DONE))
> -		udelay(1);
> +		/*
> +		 * Force write last pad into memory, as this can fail in some
> +		 * cases according to erratas 1.157, 1.185
> +		 */
> +		omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
> +				OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
>  
> -	/*
> -	 * Force write last pad into memory, as this can fail in some
> -	 * cases according to erratas 1.157, 1.185
> -	 */
> -	omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
> -		OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
> +		/* Save the Interrupt controller context */
> +		omap_intc_save_context();
> +
> +		/* Save the system control module context,
> +		 * padconf already save above
> +		 */
> +		omap3_control_save_context();
> +		omap_dma_global_context_save();
> +	}
>  
> -	/* Save the Interrupt controller context */
> -	omap_intc_save_context();
>  	/* Save the GPMC context */
>  	omap3_gpmc_save_context();
> -	/* Save the system control module context, padconf already save above*/
> -	omap3_control_save_context();
> -	omap_dma_global_context_save();
>  }
>  
> -static void omap3_core_restore_context(void)
> +static void omap3_core_restore_context(int core_state)
>  {
> -	/* Restore the control module context, padconf restored by h/w */
> -	omap3_control_restore_context();
> +	if (core_state == PWRDM_POWER_OFF) {
> +		/* Restore the control module context,
> +		 * padconf restored by h/w
> +		 */

changing this to proper multi-line comment.

Kevin

> +		omap3_control_restore_context();
> +		/* Restore the interrupt controller context */
> +		omap_intc_restore_context();
> +		omap_dma_global_context_restore();
> +	}
>  	/* Restore the GPMC context */
>  	omap3_gpmc_restore_context();
> -	/* Restore the interrupt controller context */
> -	omap_intc_restore_context();
> -	omap_dma_global_context_restore();
>  }
>  
>  /*
> @@ -445,7 +458,7 @@ void omap_sram_idle(void)
>  			prm_set_mod_reg_bits(voltctrl,
>  					     OMAP3430_GR_MOD,
>  					     OMAP3_PRM_VOLTCTRL_OFFSET);
> -			omap3_core_save_context();
> +			omap3_core_save_context(PWRDM_POWER_OFF);
>  			omap3_prcm_save_context();
>  		} else if (core_next_state == PWRDM_POWER_RET) {
>  			prm_set_mod_reg_bits(OMAP3430_AUTO_RET,
> @@ -497,7 +510,7 @@ void omap_sram_idle(void)
>  	if (core_next_state < PWRDM_POWER_ON) {
>  		core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
>  		if (core_prev_state == PWRDM_POWER_OFF) {
> -			omap3_core_restore_context();
> +			omap3_core_restore_context(core_prev_state);
>  			omap3_prcm_restore_context();
>  			omap3_sram_restore_context();
>  			omap2_sms_restore_context();
> -- 
> 1.5.6.3
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH 4/8] OMAP3 PM: Defining .pwrsts_logic_ret field for core power domain structure

[Paul Walmsley]

On Wed, 20 Jan 2010, Thara Gopinath wrote:

> This patch adds the flag .pwrsts_logic_ret info for the core power domain
> in the associated powerdomain structure. This flag specifies the states
> core domain logic can hit in event of the domain entering retention.
> 
> Signed-off-by: Thara Gopinath <thara@ti.com>

Looks fine to me,


- Paul

Re: [PATCH 3/8] OMAP2/3 PM: Adding powerdomain APIs for reading the next logic and mem state

[Paul Walmsley]

Hi Thara,

some more comments:

On Wed, 20 Jan 2010, Thara Gopinath wrote:

> This patch adds APIs pwrdm_read_next_logic_pwrst and

Shouldn't this be pwrdm_read_logic_retst(), to match the existing code's 
pwrdm_set_logic_retst() ?

> pwrdm_read_next_mem_pwrst 

and similarly, shouldn't this be pwrdm_read_next_mem_retst() to match the 
existing code's pwrdm_read_mem_retst() ?

> for reading the next programmed logic and memory state a powerdomain is 
> to hit in event of the next power domain state being retention.
> 
> Signed-off-by: Thara Gopinath <thara@ti.com>
> ---
>  arch/arm/mach-omap2/powerdomain.c             |   71 +++++++++++++++++++++++++
>  arch/arm/plat-omap/include/plat/powerdomain.h |    2 +
>  2 files changed, 73 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
> index 26b3f3e..06bf290 100644
> --- a/arch/arm/mach-omap2/powerdomain.c
> +++ b/arch/arm/mach-omap2/powerdomain.c
> @@ -964,6 +964,29 @@ int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm)
>  }
>  
>  /**
> + * pwrdm_read_next_logic_pwrst - get next powerdomain logic power state
> + * @pwrdm: struct powerdomain * to get next logic power state
> + *
> + * Return the powerdomain pwrdm's logic power state.  Returns -EINVAL
> + * if the powerdomain pointer is null or returns the next logic
> + * power state upon success.
> + */
> +int pwrdm_read_next_logic_pwrst(struct powerdomain *pwrdm)

(see above)

> +{
> +	if (!pwrdm)
> +		return -EINVAL;
> +
> +	/*
> +	 * The register bit names below may not correspond to the
> +	 * actual names of the bits in each powerdomain's register,
> +	 * but the type of value returned is the same for each
> +	 * powerdomain.
> +	 */
> +	return prm_read_mod_bits_shift(pwrdm->prcm_offs, PM_PWSTCTRL,
> +					OMAP3430_LOGICSTATEST);
> +}
> +
> +/**
>   * pwrdm_read_mem_pwrst - get current memory bank power state
>   * @pwrdm: struct powerdomain * to get current memory bank power state
>   * @bank: memory bank number (0-3)
> @@ -1065,6 +1088,54 @@ int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
>  }
>  
>  /**
> + * pwrdm_read_next_mem_pwrst - get next memory bank power state
> + * @pwrdm: struct powerdomain * to get mext memory bank power state
> + * @bank: memory bank number (0-3)
> + *
> + * Return the powerdomain pwrdm's next memory power state for bank
> + * x.  Returns -EINVAL if the powerdomain pointer is null, -EEXIST if
> + * the target memory bank does not exist or is not controllable, or
> + * returns the next memory power state upon success.
> + */
> +int pwrdm_read_next_mem_pwrst(struct powerdomain *pwrdm, u8 bank)

(see above)

> +{
> +	u32 m;
> +
> +	if (!pwrdm)
> +		return -EINVAL;
> +
> +	if (pwrdm->banks < (bank + 1))
> +		return -EEXIST;
> +
> +	/*
> +	 * The register bit names below may not correspond to the
> +	 * actual names of the bits in each powerdomain's register,
> +	 * but the type of value returned is the same for each
> +	 * powerdomain.
> +	 */
> +	switch (bank) {
> +	case 0:
> +		m = OMAP3430_SHAREDL1CACHEFLATRETSTATE;
> +		break;
> +	case 1:
> +		m = OMAP3430_L1FLATMEMRETSTATE;
> +		break;
> +	case 2:
> +		m = OMAP3430_SHAREDL2CACHEFLATRETSTATE;
> +		break;
> +	case 3:
> +		m = OMAP3430_SHAREDL2CACHEFLATRETSTATE;
> +		break;
> +	default:
> +		WARN_ON(1); /* should never happen */
> +		return -EEXIST;
> +	}
> +
> +	return prm_read_mod_bits_shift(pwrdm->prcm_offs,
> +					PM_PWSTCTRL, m);
> +}
> +
> +/**
>   * pwrdm_clear_all_prev_pwrst - clear previous powerstate register for a pwrdm
>   * @pwrdm: struct powerdomain * to clear
>   *
> diff --git a/arch/arm/plat-omap/include/plat/powerdomain.h b/arch/arm/plat-omap/include/plat/powerdomain.h
> index 0b96005..7576559 100644
> --- a/arch/arm/plat-omap/include/plat/powerdomain.h
> +++ b/arch/arm/plat-omap/include/plat/powerdomain.h
> @@ -170,8 +170,10 @@ int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
>  
>  int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm);
>  int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm);
> +int pwrdm_read_next_logic_pwrst(struct powerdomain *pwrdm);

(as above)

>  int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
>  int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
> +int pwrdm_read_next_mem_pwrst(struct powerdomain *pwrdm, u8 bank);

(as above)

>  
>  int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm);
>  int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm);
> -- 
> 1.5.6.3
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 


- Paul

RE: [PATCH 3/8] OMAP2/3 PM: Adding powerdomain APIs for reading the next logic and mem state

[Gopinath, Thara]

>>-----Original Message-----
>>From: Paul Walmsley [mailto:paul@pwsan.com]
>>Sent: Thursday, January 21, 2010 11:43 AM
>>To: Gopinath, Thara
>>Cc: linux-omap@vger.kernel.org
>>Subject: Re: [PATCH 3/8] OMAP2/3 PM: Adding powerdomain APIs for reading the next logic and mem state
>>
>>Hi Thara,
>>
>>some more comments:
>>
>>On Wed, 20 Jan 2010, Thara Gopinath wrote:
>>
>>> This patch adds APIs pwrdm_read_next_logic_pwrst and
>>
>>Shouldn't this be pwrdm_read_logic_retst(), to match the existing code's
>>pwrdm_set_logic_retst() ?
>>
>>> pwrdm_read_next_mem_pwrst
>>
>>and similarly, shouldn't this be pwrdm_read_next_mem_retst() to match the
>>existing code's pwrdm_read_mem_retst() ?

Hello Paul,

Yes agreed. I just looked at pwrdm_read_next_pwrst and implemented these. Will repost with correct API names.

Regards
Thara

Re: [PATCH 2/8] OMAP3 PM: Conditional UART context save restore.

[Kevin Hilman]

Thara Gopinath <thara@ti.com> writes:

> Currently UART context save is done in idle
> thread thru a call to omap_uart_prepare_idle irrespective of
> what power state is attained by the power domain to which
> the UART belongs to. This patch allows omap_uart_prepare_idle
> to take power state as a parameter and this function in
> turn does a uart context save only if the passed power state
> is PWRDM_POWER_OFF. In the restore path a restore will
> happen only if a valid save has happened.
>
> Signed-off-by: Thara Gopinath <thara@ti.com>

Nice.  Pulling this one into PM branch and queuing for 2.6.34.

Kevin

> ---
>  arch/arm/mach-omap2/pm34xx.c             |    6 +++---
>  arch/arm/mach-omap2/serial.c             |   17 +++++++----------
>  arch/arm/plat-omap/include/plat/serial.h |    2 +-
>  3 files changed, 11 insertions(+), 14 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
> index 8f5e819..895e9ef 100644
> --- a/arch/arm/mach-omap2/pm34xx.c
> +++ b/arch/arm/mach-omap2/pm34xx.c
> @@ -418,7 +418,7 @@ void omap_sram_idle(void)
>  			} else
>  				omap3_per_save_context();
>  		}
> -		omap_uart_prepare_idle(2);
> +		omap_uart_prepare_idle(2, per_next_state);
>  	}
>  
>  	if (pwrdm_read_pwrst(cam_pwrdm) == PWRDM_POWER_ON)
> @@ -435,8 +435,8 @@ void omap_sram_idle(void)
>  
>  	/* CORE */
>  	if (core_next_state < PWRDM_POWER_ON) {
> -		omap_uart_prepare_idle(0);
> -		omap_uart_prepare_idle(1);
> +		omap_uart_prepare_idle(0, core_next_state);
> +		omap_uart_prepare_idle(1, core_next_state);
>  		if (core_next_state == PWRDM_POWER_OFF) {
>  			u32 voltctrl = OMAP3430_AUTO_OFF;
>  
> diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
> index 837b347..fb59d5f 100644
> --- a/arch/arm/mach-omap2/serial.c
> +++ b/arch/arm/mach-omap2/serial.c
> @@ -168,9 +168,6 @@ static void omap_uart_save_context(struct omap_uart_state *uart)
>  	u16 lcr = 0;
>  	struct plat_serial8250_port *p = uart->p;
>  
> -	if (!enable_off_mode)
> -		return;
> -
>  	lcr = serial_read_reg(p, UART_LCR);
>  	serial_write_reg(p, UART_LCR, 0xBF);
>  	uart->dll = serial_read_reg(p, UART_DLL);
> @@ -189,9 +186,6 @@ static void omap_uart_restore_context(struct omap_uart_state *uart)
>  	u16 efr = 0;
>  	struct plat_serial8250_port *p = uart->p;
>  
> -	if (!enable_off_mode)
> -		return;
> -
>  	if (!uart->context_valid)
>  		return;
>  
> @@ -235,12 +229,15 @@ static inline void omap_uart_enable_clocks(struct omap_uart_state *uart)
>  
>  #ifdef CONFIG_PM
>  
> -static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
> +static inline void omap_uart_disable_clocks(struct omap_uart_state *uart,
> +							int power_state)
>  {
>  	if (!uart->clocked)
>  		return;
>  
> -	omap_uart_save_context(uart);
> +	if (power_state == PWRDM_POWER_OFF)
> +		omap_uart_save_context(uart);
> +
>  	uart->clocked = 0;
>  	clk_disable(uart->ick);
>  	clk_disable(uart->fck);
> @@ -329,13 +326,13 @@ static void omap_uart_idle_timer(unsigned long data)
>  	omap_uart_allow_sleep(uart);
>  }
>  
> -void omap_uart_prepare_idle(int num)
> +void omap_uart_prepare_idle(int num, int power_state)
>  {
>  	struct omap_uart_state *uart;
>  
>  	list_for_each_entry(uart, &uart_list, node) {
>  		if (num == uart->num && uart->can_sleep) {
> -			omap_uart_disable_clocks(uart);
> +			omap_uart_disable_clocks(uart, power_state);
>  			return;
>  		}
>  	}
> diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h
> index f5a4a92..ca76742 100644
> --- a/arch/arm/plat-omap/include/plat/serial.h
> +++ b/arch/arm/plat-omap/include/plat/serial.h
> @@ -57,7 +57,7 @@ extern void omap_serial_init_port(int port);
>  extern int omap_uart_can_sleep(void);
>  extern void omap_uart_check_wakeup(void);
>  extern void omap_uart_prepare_suspend(void);
> -extern void omap_uart_prepare_idle(int num);
> +extern void omap_uart_prepare_idle(int num, int power_state);
>  extern void omap_uart_resume_idle(int num);
>  extern void omap_uart_enable_irqs(int enable);
>  #endif
> -- 
> 1.5.6.3
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH 0/8] OMAP3: PM: Open Switch Retention support in the cpuidle thread.

[Paul Walmsley]

Hi Thara,

I'd like to merge the powerdomain changes separately from the other 
changes, most of which should probably go through Kevin's PM branch.

After you revise your patches based on the comments, can you take your 
patches 3, 4, and the powerdomain portions of patch 7 and post those in a 
separate series as an OSWR preparatory powerdomain patch set?  That will 
make it easier for both Kevin and I to handle.

Note: the powerdomain code will need to be edited somewhat to bring it 
up-to-date with the latest OMAP4 changes in the for_2.6.34 branch, which 
is where your patches will go.  I'm happy to do this, but after I do it, 
will you be able to test the updated series to ensure that this process 
didn't break anything?

regards,

- Paul

RE: [PATCH 0/8] OMAP3: PM: Open Switch Retention support in the cpuidle thread.

[Gopinath, Thara]

>>-----Original Message-----
>>From: Paul Walmsley [mailto:paul@pwsan.com]
>>Sent: Thursday, January 21, 2010 11:54 AM
>>To: Gopinath, Thara
>>Cc: linux-omap@vger.kernel.org; khilman@deeprootsystems.com
>>Subject: Re: [PATCH 0/8] OMAP3: PM: Open Switch Retention support in the cpuidle thread.
>>
>>
>>Hi Thara,
>>
>>I'd like to merge the powerdomain changes separately from the other
>>changes, most of which should probably go through Kevin's PM branch.
>>
>>After you revise your patches based on the comments, can you take your
>>patches 3, 4, and the powerdomain portions of patch 7 and post those in a
>>separate series as an OSWR preparatory powerdomain patch set?  That will
>>make it easier for both Kevin and I to handle.

When you say patch 7, I believe you are mentioning the book keeping part for OSWR where logic_ret_off and mem_ret_off counters are added. I can separate this out and post these three patches separately. Do let me know should I base these on linux-omap master branch or Kevin's pm tree.

>>
>>Note: the powerdomain code will need to be edited somewhat to bring it
>>up-to-date with the latest OMAP4 changes in the for_2.6.34 branch, which
>>is where your patches will go.  I'm happy to do this, but after I do it,
>>will you be able to test the updated series to ensure that this process
>>didn't break anything?

Thanks for this and sure I can test the updated series! But I do not understand what OMAP4 specific support has to be added for these three patches. These three patches will be considerably free of OMAP2/OMAP3/OMAP4 specific stuff. Or are you talking of rebasing on 2.6.34 kernel?

Regards
Thara

RE: [PATCH 0/8] OMAP3: PM: Open Switch Retention support in the cpuidle thread.

[Paul Walmsley]

On Thu, 21 Jan 2010, Gopinath, Thara wrote:

> >>-----Original Message-----
> >>From: Paul Walmsley [mailto:paul@pwsan.com]
> >>Sent: Thursday, January 21, 2010 11:54 AM
> >>To: Gopinath, Thara
> >>Cc: linux-omap@vger.kernel.org; khilman@deeprootsystems.com
> >>Subject: Re: [PATCH 0/8] OMAP3: PM: Open Switch Retention support in the cpuidle thread.
> >>
> >>I'd like to merge the powerdomain changes separately from the other
> >>changes, most of which should probably go through Kevin's PM branch.
> >>
> >>After you revise your patches based on the comments, can you take your
> >>patches 3, 4, and the powerdomain portions of patch 7 and post those in a
> >>separate series as an OSWR preparatory powerdomain patch set?  That will
> >>make it easier for both Kevin and I to handle.
> 
> When you say patch 7, I believe you are mentioning the book keeping part 
> for OSWR where logic_ret_off and mem_ret_off counters are added.

Yes, to be specific, I'm talking about:

diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 06bf290..ef9f1bb 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -126,6 +126,16 @@ static int _pwrdm_state_switch(struct powerdomain 
*pwrdm, int flag)
                prev = pwrdm_read_prev_pwrst(pwrdm);
                if (pwrdm->state != prev)
                        pwrdm->state_counter[prev]++;
+               if (prev == PWRDM_POWER_RET) {
+                       if ((pwrdm->pwrsts_logic_ret == PWRSTS_OFF_RET) &&
+                                       (pwrdm_read_prev_logic_pwrst(pwrdm) ==
+                                        PWRDM_POWER_OFF))
+                               pwrdm->ret_logic_off_counter++;
+                       if ((pwrdm->pwrsts_mem_ret[0] == PWRSTS_OFF_RET) &&
+                                       (pwrdm_read_prev_mem_pwrst(pwrdm, 0) ==
+                                       PWRDM_POWER_OFF))
+                               pwrdm->ret_mem_off_counter++;
+               }
                break;
        default:
                return -EINVAL;
@@ -161,6 +171,9 @@ static __init void _pwrdm_setup(struct powerdomain *pwrdm)
        for (i = 0; i < PWRDM_MAX_PWRSTS; i++)
                pwrdm->state_counter[i] = 0;
 
+       pwrdm->ret_logic_off_counter = 0;
+       pwrdm->ret_mem_off_counter = 0;
+
        pwrdm_wait_transition(pwrdm);
        pwrdm->state = pwrdm_read_pwrst(pwrdm);
        pwrdm->state_counter[pwrdm->state] = 1;


and

diff --git a/arch/arm/plat-omap/include/plat/powerdomain.h b/arch/arm/plat-omap/include/plat/powerdomain.h
index 7576559..405ccd6 100644
--- a/arch/arm/plat-omap/include/plat/powerdomain.h
+++ b/arch/arm/plat-omap/include/plat/powerdomain.h
@@ -124,6 +124,8 @@ struct powerdomain {
 
        int state;
        unsigned state_counter[PWRDM_MAX_PWRSTS];
+       unsigned ret_logic_off_counter;
+       unsigned ret_mem_off_counter;
 
 #ifdef CONFIG_PM_DEBUG
        s64 timer;

> I can separate this out and post these three patches separately. Do let 
> me know should I base these on linux-omap master branch or Kevin's pm 
> tree.

l-o master, please.

> >>Note: the powerdomain code will need to be edited somewhat to bring it
> >>up-to-date with the latest OMAP4 changes in the for_2.6.34 branch, which
> >>is where your patches will go.  I'm happy to do this, but after I do it,
> >>will you be able to test the updated series to ensure that this process
> >>didn't break anything?
> 
> Thanks for this and sure I can test the updated series!

Great.

> But I do not understand what OMAP4 specific support has to be added for 
> these three patches. These three patches will be considerably free of 
> OMAP2/OMAP3/OMAP4 specific stuff. Or are you talking of rebasing on 
> 2.6.34 kernel?

OMAP4 has an additional memory bank.  Also the names of the bitfields have 
been abstracted out, e.g., OMAP_MEM0_RETSTATE_MASK instead of 
OMAP3430_SHAREDL1CACHEFLATRETSTATE.   You can check 'for_2.6.34' branch at 
git://git.pwsan.com/linux-2.6 to see what it looks like.


- Paul