[PATCH 01/06] OMAP3: PM: Update omap_3430sdp_pm_defconfig

[PATCH 01/06] OMAP3: PM: Update omap_3430sdp_pm_defconfig

[Rajendra Nayak]

This patch disables OMAP FB driver from the pm defconfig
for SDP as it seems to gate sleep and throw some irq errors
omapfb omapfb: irq error status 0062
omapfb omapfb: irq error status 00c2
omapfb omapfb: irq error status 0060

Also ondemand CPUFreq governor support is enabled.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
---
 arch/arm/configs/omap_3430sdp_pm_defconfig |   38 +--------------------------
 1 files changed, 2 insertions(+), 36 deletions(-)

diff --git a/arch/arm/configs/omap_3430sdp_pm_defconfig b/arch/arm/configs/omap_3430sdp_pm_defconfig
index e06fea5..aefdb5b 100644
--- a/arch/arm/configs/omap_3430sdp_pm_defconfig
+++ b/arch/arm/configs/omap_3430sdp_pm_defconfig
@@ -315,7 +315,7 @@ CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
 CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
 # CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
 # CONFIG_CPU_FREQ_GOV_USERSPACE is not set
-# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
 # CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
 CONFIG_CPU_IDLE=y
 CONFIG_CPU_IDLE_GOV_LADDER=y
@@ -808,37 +808,8 @@ CONFIG_TWL4030_CORE=y
 #
 # CONFIG_VGASTATE is not set
 # CONFIG_VIDEO_OUTPUT_CONTROL is not set
-CONFIG_FB=y
-# CONFIG_FIRMWARE_EDID is not set
-# CONFIG_FB_DDC is not set
-# CONFIG_FB_BOOT_VESA_SUPPORT is not set
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
-# CONFIG_FB_SYS_FILLRECT is not set
-# CONFIG_FB_SYS_COPYAREA is not set
-# CONFIG_FB_SYS_IMAGEBLIT is not set
-# CONFIG_FB_FOREIGN_ENDIAN is not set
-# CONFIG_FB_SYS_FOPS is not set
-# CONFIG_FB_SVGALIB is not set
-# CONFIG_FB_MACMODES is not set
-# CONFIG_FB_BACKLIGHT is not set
-# CONFIG_FB_MODE_HELPERS is not set
-# CONFIG_FB_TILEBLITTING is not set
-
-#
-# Frame buffer hardware drivers
-#
-# CONFIG_FB_S1D13XXX is not set
-# CONFIG_FB_VIRTUAL is not set
-# CONFIG_FB_METRONOME is not set
-# CONFIG_FB_MB862XX is not set
-CONFIG_FB_OMAP=y
+# CONFIG_FB is not set
 # CONFIG_FB_OMAP_LCD_VGA is not set
-# CONFIG_FB_OMAP_LCDC_EXTERNAL is not set
-# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set
-CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE=2
 # CONFIG_BACKLIGHT_LCD_SUPPORT is not set
 
 #
@@ -851,11 +822,6 @@ CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE=2
 #
 # CONFIG_VGA_CONSOLE is not set
 CONFIG_DUMMY_CONSOLE=y
-# CONFIG_FRAMEBUFFER_CONSOLE is not set
-CONFIG_LOGO=y
-CONFIG_LOGO_LINUX_MONO=y
-CONFIG_LOGO_LINUX_VGA16=y
-CONFIG_LOGO_LINUX_CLUT224=y
 # CONFIG_SOUND is not set
 # CONFIG_HID_SUPPORT is not set
 CONFIG_USB_SUPPORT=y
-- 
1.5.4.7

[PATCH 02/06] OMAP3: PM: Add PER wakeup dependency on WKUP domain

[Rajendra Nayak]

This patch adds a Wakeup dependency of PER domain on WKUP
domain as a Workaround for a OMAP3430 limitation which causes
PER domain GPIO's to drive random values while coming back
from OFF mode. This limitation applies to all silicon rev's
of OMAP3430.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
---
 arch/arm/mach-omap2/pm34xx.c |    9 +++++++++
 1 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 80992c5..231b33e 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -86,6 +86,7 @@ static int (*_omap_save_secure_sram)(u32 *addr);
 static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
 static struct powerdomain *core_pwrdm, *per_pwrdm;
 static struct powerdomain *cam_pwrdm;
+static struct powerdomain *wkup_pwrdm;
 
 static struct prm_setup_times prm_setup = {
 	.clksetup = 0xff,
@@ -1042,6 +1043,7 @@ int __init omap3_pm_init(void)
 	per_pwrdm = pwrdm_lookup("per_pwrdm");
 	core_pwrdm = pwrdm_lookup("core_pwrdm");
 	cam_pwrdm = pwrdm_lookup("cam_pwrdm");
+	wkup_pwrdm = pwrdm_lookup("wkup_pwrdm");
 
 	omap_push_sram_idle();
 
@@ -1063,6 +1065,13 @@ int __init omap3_pm_init(void)
 	*/
 	pwrdm_add_wkdep(per_pwrdm, core_pwrdm);
 
+	/*
+	 * This is a WA for an OMAP limitation (Listed in the omap errata doc
+	 * Section 2.23) which causes GPIO modules in PER domain to drive random
+	 * values while coming back from OFF mode.
+	 */
+	pwrdm_add_wkdep(per_pwrdm, wkup_pwrdm);
+
 	if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
 		omap3_secure_ram_storage =
 			kmalloc(0x803F, GFP_KERNEL);
-- 
1.5.4.7

[PATCH 03/06] OMAP3: PM: VDD2 dvfs at higher VDD1 opp

[Rajendra Nayak]

This patch makes sure that VDD2 dvfs always happens at
a higher VDD1 OPP, hence bringing down the VDD2 DVFS latency
to a large extent.
Having a smaller VDD2 dvfs latency helps drivers which are sensitive
to the time during which SDRAM is inaccessible due to SDRC iclk being
disabled.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
---
 arch/arm/mach-omap2/resource34xx.c |    5 +++--
 1 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-omap2/resource34xx.c b/arch/arm/mach-omap2/resource34xx.c
index 9908e52..4c87436 100644
--- a/arch/arm/mach-omap2/resource34xx.c
+++ b/arch/arm/mach-omap2/resource34xx.c
@@ -353,6 +353,9 @@ int set_opp(struct shared_resource *resp, u32 target_level)
 	int ind;
 
 	if (resp == vdd1_resp) {
+		if (target_level < 3)
+			resource_release("vdd2_opp", &vdd2_dev);
+
 		resource_set_opp_level(VDD1_OPP, target_level, 0);
 		/*
 		 * For VDD1 OPP3 and above, make sure the interconnect
@@ -361,8 +364,6 @@ int set_opp(struct shared_resource *resp, u32 target_level)
 		 */
 		if (target_level >= 3)
 			resource_request("vdd2_opp", &vdd2_dev, 400000);
-		else
-			resource_release("vdd2_opp", &vdd2_dev);
 
 	} else if (resp == vdd2_resp) {
 		tput = target_level;
-- 
1.5.4.7

[PATCH 04/06] OMAP3: PM: Put optimal SMPS stabilization delay

[Rajendra Nayak]

This patch removes the worst case T2 SMPS stabilization delay
of 360 us (needed for a 0v to 1.35 switch) and adds calculated
delay based on the actual volatge switch.
The delay is based on the T2 SMPS slew rate of 4mV/uS.
Each step based on VSEL difference corresponds to 12.5 mv

Hence the formula used:
delay = (steps * 12.5)/4 + (2 us of buffer).

This also adds a SMPS stabilization delay in the sr_reset_voltage()
function which seems to be needed.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
---
 arch/arm/mach-omap2/resource34xx.c |    9 ++++--
 arch/arm/mach-omap2/resource34xx.h |    2 +-
 arch/arm/mach-omap2/smartreflex.c  |   48 ++++++++++++++++++++++++++++-------
 arch/arm/mach-omap2/smartreflex.h  |    2 +-
 4 files changed, 46 insertions(+), 15 deletions(-)

diff --git a/arch/arm/mach-omap2/resource34xx.c b/arch/arm/mach-omap2/resource34xx.c
index 4c87436..82405b6 100644
--- a/arch/arm/mach-omap2/resource34xx.c
+++ b/arch/arm/mach-omap2/resource34xx.c
@@ -258,6 +258,7 @@ static int program_opp_freq(int res, int target_level, int current_level)
 #ifdef CONFIG_PM
 	omap3_save_scratchpad_contents();
 #endif
+
 	*curr_opp = target_level;
 	return target_level;
 }
@@ -267,9 +268,10 @@ static int program_opp(int res, struct omap_opp *opp, int target_level,
 {
 	int i, ret = 0, raise;
 #ifdef CONFIG_OMAP_SMARTREFLEX
-	unsigned long t_opp;
+	unsigned long t_opp, c_opp;
 
 	t_opp = ID_VDD(res) | ID_OPP_NO(opp[target_level].opp_id);
+	c_opp = ID_VDD(res) | ID_OPP_NO(opp[current_level].opp_id);
 #endif
 	if (target_level > current_level)
 		raise = 1;
@@ -282,8 +284,9 @@ static int program_opp(int res, struct omap_opp *opp, int target_level,
 					current_level);
 #ifdef CONFIG_OMAP_SMARTREFLEX
 		else
-			sr_voltagescale_vcbypass(t_opp,
-					opp[target_level].vsel);
+			sr_voltagescale_vcbypass(t_opp, c_opp,
+				opp[target_level].vsel,
+				opp[current_level].vsel);
 #endif
 	}
 
diff --git a/arch/arm/mach-omap2/resource34xx.h b/arch/arm/mach-omap2/resource34xx.h
index 8d95a00..a160665 100644
--- a/arch/arm/mach-omap2/resource34xx.h
+++ b/arch/arm/mach-omap2/resource34xx.h
@@ -28,7 +28,7 @@
 #include <mach/omap-pm.h>
 #include <mach/omap34xx.h>
 
-extern int sr_voltagescale_vcbypass(u32 target_opp, u8 vsel);
+extern int sr_voltagescale_vcbypass(u32 t_opp, u32 c_opp, u8 t_vsel, u8 c_vsel);
 
 /*
  * mpu_latency/core_latency are used to control the cpuidle C state.
diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
index 422c917..a2fe00e 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -449,6 +449,9 @@ static int sr_reset_voltage(int srid)
 	u32 reg_addr = 0;
 	u32 loop_cnt = 0, retries_cnt = 0;
 	u32 vc_bypass_value;
+	u32 t2_smps_steps = 0;
+	u32 t2_smps_delay = 0;
+	u32 prm_vp1_voltage, prm_vp2_voltage;
 
 	if (srid == SR1) {
 		target_opp_no = get_vdd1_opp();
@@ -458,6 +461,9 @@ static int sr_reset_voltage(int srid)
 		}
 		vsel = mpu_opps[target_opp_no].vsel;
 		reg_addr = R_VDD1_SR_CONTROL;
+		prm_vp1_voltage = prm_read_mod_reg(OMAP3430_GR_MOD,
+						OMAP3_PRM_VP1_VOLTAGE_OFFSET);
+		t2_smps_steps = abs(vsel - prm_vp1_voltage);
 	} else if (srid == SR2) {
 		target_opp_no = get_vdd2_opp();
 		if (!target_opp_no) {
@@ -466,6 +472,9 @@ static int sr_reset_voltage(int srid)
 		}
 		vsel = l3_opps[target_opp_no].vsel;
 		reg_addr = R_VDD2_SR_CONTROL;
+		prm_vp2_voltage = prm_read_mod_reg(OMAP3430_GR_MOD,
+						OMAP3_PRM_VP2_VOLTAGE_OFFSET);
+		t2_smps_steps = abs(vsel - prm_vp2_voltage);
 	}
 
 	vc_bypass_value = (vsel << OMAP3430_DATA_SHIFT) |
@@ -493,6 +502,14 @@ static int sr_reset_voltage(int srid)
 		vc_bypass_value = prm_read_mod_reg(OMAP3430_GR_MOD,
 					OMAP3_PRM_VC_BYPASS_VAL_OFFSET);
 	}
+
+	/*
+	 *  T2 SMPS slew rate (min) 4mV/uS, step size 12.5mV,
+	 *  2us added as buffer.
+	 */
+	t2_smps_delay = ((t2_smps_steps * 125) / 40) + 2;
+	udelay(t2_smps_delay);
+
 	return 0;
 }
 
@@ -751,37 +768,43 @@ void disable_smartreflex(int srid)
 }
 
 /* Voltage Scaling using SR VCBYPASS */
-int sr_voltagescale_vcbypass(u32 target_opp, u8 vsel)
+int sr_voltagescale_vcbypass(u32 target_opp, u32 current_opp,
+					u8 target_vsel, u8 current_vsel)
 {
 	int sr_status = 0;
-	u32 vdd, target_opp_no;
+	u32 vdd, target_opp_no, current_opp_no;
 	u32 vc_bypass_value;
 	u32 reg_addr = 0;
 	u32 loop_cnt = 0, retries_cnt = 0;
+	u32 t2_smps_steps = 0;
+	u32 t2_smps_delay = 0;
 
 	vdd = get_vdd(target_opp);
 	target_opp_no = get_opp_no(target_opp);
+	current_opp_no = get_opp_no(current_opp);
 
 	if (vdd == VDD1_OPP) {
 		sr_status = sr_stop_vddautocomap(SR1);
+		t2_smps_steps = abs(target_vsel - current_vsel);
 
 		prm_rmw_mod_reg_bits(OMAP3430_VC_CMD_ON_MASK,
-					(vsel << OMAP3430_VC_CMD_ON_SHIFT),
-					OMAP3430_GR_MOD,
-					OMAP3_PRM_VC_CMD_VAL_0_OFFSET);
+				(target_vsel << OMAP3430_VC_CMD_ON_SHIFT),
+				OMAP3430_GR_MOD,
+				OMAP3_PRM_VC_CMD_VAL_0_OFFSET);
 		reg_addr = R_VDD1_SR_CONTROL;
 
 	} else if (vdd == VDD2_OPP) {
 		sr_status = sr_stop_vddautocomap(SR2);
+		t2_smps_steps =  abs(target_vsel - current_vsel);
 
 		prm_rmw_mod_reg_bits(OMAP3430_VC_CMD_ON_MASK,
-					(vsel << OMAP3430_VC_CMD_ON_SHIFT),
-					OMAP3430_GR_MOD,
-					OMAP3_PRM_VC_CMD_VAL_1_OFFSET);
+				(target_vsel << OMAP3430_VC_CMD_ON_SHIFT),
+				OMAP3430_GR_MOD,
+				OMAP3_PRM_VC_CMD_VAL_1_OFFSET);
 		reg_addr = R_VDD2_SR_CONTROL;
 	}
 
-	vc_bypass_value = (vsel << OMAP3430_DATA_SHIFT) |
+	vc_bypass_value = (target_vsel << OMAP3430_DATA_SHIFT) |
 			(reg_addr << OMAP3430_REGADDR_SHIFT) |
 			(R_SRI2C_SLAVE_ADDR << OMAP3430_SLAVEADDR_SHIFT);
 
@@ -807,7 +830,12 @@ int sr_voltagescale_vcbypass(u32 target_opp, u8 vsel)
 					OMAP3_PRM_VC_BYPASS_VAL_OFFSET);
 	}
 
-	udelay(T2_SMPS_UPDATE_DELAY);
+	/*
+	 *  T2 SMPS slew rate (min) 4mV/uS, step size 12.5mV,
+	 *  2us added as buffer.
+	 */
+	t2_smps_delay = ((t2_smps_steps * 125) / 40) + 2;
+	udelay(t2_smps_delay);
 
 	if (sr_status) {
 		if (vdd == VDD1_OPP)
diff --git a/arch/arm/mach-omap2/smartreflex.h b/arch/arm/mach-omap2/smartreflex.h
index 94e522b..2a0e823 100644
--- a/arch/arm/mach-omap2/smartreflex.h
+++ b/arch/arm/mach-omap2/smartreflex.h
@@ -245,7 +245,7 @@ extern u32 current_vdd2_opp;
 #ifdef CONFIG_OMAP_SMARTREFLEX
 void enable_smartreflex(int srid);
 void disable_smartreflex(int srid);
-int sr_voltagescale_vcbypass(u32 target_opp, u8 vsel);
+int sr_voltagescale_vcbypass(u32 t_opp, u32 c_opp, u8 t_vsel, u8 c_vsel);
 void sr_start_vddautocomap(int srid, u32 target_opp_no);
 int sr_stop_vddautocomap(int srid);
 #else
-- 
1.5.4.7

[PATCH 05/06] OMAP3: PM: Implement locking for any scratchpad access

[Rajendra Nayak]

This patch implements locking using the semaphore in scratchpad
memory preventing any concurrent access to scratchpad from OMAP
and Baseband/Modem processor.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
---
 arch/arm/mach-omap2/resource34xx.c |    6 +++++-
 arch/arm/mach-omap2/resource34xx.h |    2 ++
 arch/arm/mach-omap2/sleep34xx.S    |   32 ++++++++++++++++++++++++++++++++
 3 files changed, 39 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/resource34xx.c b/arch/arm/mach-omap2/resource34xx.c
index 82405b6..408d3ab 100644
--- a/arch/arm/mach-omap2/resource34xx.c
+++ b/arch/arm/mach-omap2/resource34xx.c
@@ -236,6 +236,7 @@ static int program_opp_freq(int res, int target_level, int current_level)
 	int ret = 0, l3_div;
 	int *curr_opp;
 
+	lock_scratchpad_sem();
 	if (res == VDD1_OPP) {
 		curr_opp = &curr_vdd1_opp;
 		clk_set_rate(dpll1_clk, mpu_opps[target_level].rate);
@@ -253,11 +254,14 @@ static int program_opp_freq(int res, int target_level, int current_level)
 		ret = clk_set_rate(dpll3_clk,
 				l3_opps[target_level].rate * l3_div);
 	}
-	if (ret)
+	if (ret) {
+		unlock_scratchpad_sem();
 		return current_level;
+	}
 #ifdef CONFIG_PM
 	omap3_save_scratchpad_contents();
 #endif
+	unlock_scratchpad_sem();
 
 	*curr_opp = target_level;
 	return target_level;
diff --git a/arch/arm/mach-omap2/resource34xx.h b/arch/arm/mach-omap2/resource34xx.h
index a160665..5b5618a 100644
--- a/arch/arm/mach-omap2/resource34xx.h
+++ b/arch/arm/mach-omap2/resource34xx.h
@@ -29,6 +29,8 @@
 #include <mach/omap34xx.h>
 
 extern int sr_voltagescale_vcbypass(u32 t_opp, u32 c_opp, u8 t_vsel, u8 c_vsel);
+extern void lock_scratchpad_sem();
+extern void unlock_scratchpad_sem();
 
 /*
  * mpu_latency/core_latency are used to control the cpuidle C state.
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index 38aa3fd..aedcf94 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -39,6 +39,7 @@
 #define PM_PREPWSTST_MPU_V	OMAP34XX_PRM_REGADDR(MPU_MOD, \
 				OMAP3430_PM_PREPWSTST)
 #define CM_IDLEST1_CORE_V	OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1)
+#define SDRC_SCRATCHPAD_SEM_V	0xd800291C
 
 /*
  * This is the physical address of the register as specified
@@ -62,6 +63,37 @@
 #define SDRC_DLLA_STATUS_V	OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
 #define SDRC_DLLA_CTRL_V	OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
 
+        .text
+/* Function to aquire the semaphore in scratchpad */
+ENTRY(lock_scratchpad_sem)
+	stmfd	sp!, {lr}	@ save registers on stack
+wait_sem:
+	mov	r0,#1
+	ldr	r1, sdrc_scratchpad_sem
+wait_loop:
+	ldr	r2, [r1]	@ load the lock value
+	cmp	r2, r0		@ is the lock free ?
+	beq	wait_loop	@ not free...
+	swp	r2, r0, [r1]	@ semaphore free so lock it and proceed
+	cmp	r2, r0		@ did we succeed ?
+	beq	wait_sem	@ no - try again
+	ldmfd	sp!, {pc}	@ restore regs and return
+sdrc_scratchpad_sem:
+        .word SDRC_SCRATCHPAD_SEM_V
+ENTRY(lock_scratchpad_sem_sz)
+        .word   . - lock_scratchpad_sem
+
+        .text
+/* Function to release the scratchpad semaphore */
+ENTRY(unlock_scratchpad_sem)
+	stmfd	sp!, {lr}	@ save registers on stack
+	ldr	r3, sdrc_scratchpad_sem
+	mov	r2,#0
+	str	r2,[r3]
+	ldmfd	sp!, {pc}	@ restore regs and return
+ENTRY(unlock_scratchpad_sem_sz)
+        .word   . - unlock_scratchpad_sem
+
 	.text
 /* Function call to get the restore pointer for resume from OFF */
 ENTRY(get_restore_pointer)
-- 
1.5.4.7

[PATCH 06/06] OMAP3: PM: Update VDD1 OPP2 voltage level from 1.05 to 1.075

[Rajendra Nayak]

This patch updates the VDD1 OPP2 volatge according to the latest
Operating Condition Addendum from 1.05v to 1.075v

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
---
 arch/arm/mach-omap2/omap3-opp.h |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-omap2/omap3-opp.h b/arch/arm/mach-omap2/omap3-opp.h
index 4bb165e..3c9a582 100644
--- a/arch/arm/mach-omap2/omap3-opp.h
+++ b/arch/arm/mach-omap2/omap3-opp.h
@@ -26,7 +26,7 @@ static struct omap_opp omap3_mpu_rate_table[] = {
 	/*OPP1*/
 	{S125M, VDD1_OPP1, 0x1E},
 	/*OPP2*/
-	{S250M, VDD1_OPP2, 0x24},
+	{S250M, VDD1_OPP2, 0x26},
 	/*OPP3*/
 	{S500M, VDD1_OPP3, 0x30},
 	/*OPP4*/
@@ -50,7 +50,7 @@ static struct omap_opp omap3_dsp_rate_table[] = {
 	/*OPP1*/
 	{S90M, VDD1_OPP1, 0x1E},
 	/*OPP2*/
-	{S180M, VDD1_OPP2, 0x24},
+	{S180M, VDD1_OPP2, 0x26},
 	/*OPP3*/
 	{S360M, VDD1_OPP3, 0x30},
 	/*OPP4*/
-- 
1.5.4.7

Re: [PATCH 02/06] OMAP3: PM: Add PER wakeup dependency on WKUP domain

[Högander Jouni]

ext Rajendra Nayak <rnayak@ti.com> writes:

> This patch adds a Wakeup dependency of PER domain on WKUP
> domain as a Workaround for a OMAP3430 limitation which causes
> PER domain GPIO's to drive random values while coming back
> from OFF mode. This limitation applies to all silicon rev's
> of OMAP3430.

I think this errata is already taken care in gpio code. We are
configuring gpio output pads into safe mode and using pull up/down according
to gpio state.

>
> Signed-off-by: Rajendra Nayak <rnayak@ti.com>
> ---
>  arch/arm/mach-omap2/pm34xx.c |    9 +++++++++
>  1 files changed, 9 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
> index 80992c5..231b33e 100644
> --- a/arch/arm/mach-omap2/pm34xx.c
> +++ b/arch/arm/mach-omap2/pm34xx.c
> @@ -86,6 +86,7 @@ static int (*_omap_save_secure_sram)(u32 *addr);
>  static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
>  static struct powerdomain *core_pwrdm, *per_pwrdm;
>  static struct powerdomain *cam_pwrdm;
> +static struct powerdomain *wkup_pwrdm;
>  
>  static struct prm_setup_times prm_setup = {
>  	.clksetup = 0xff,
> @@ -1042,6 +1043,7 @@ int __init omap3_pm_init(void)
>  	per_pwrdm = pwrdm_lookup("per_pwrdm");
>  	core_pwrdm = pwrdm_lookup("core_pwrdm");
>  	cam_pwrdm = pwrdm_lookup("cam_pwrdm");
> +	wkup_pwrdm = pwrdm_lookup("wkup_pwrdm");
>  
>  	omap_push_sram_idle();
>  
> @@ -1063,6 +1065,13 @@ int __init omap3_pm_init(void)
>  	*/
>  	pwrdm_add_wkdep(per_pwrdm, core_pwrdm);
>  
> +	/*
> +	 * This is a WA for an OMAP limitation (Listed in the omap errata doc
> +	 * Section 2.23) which causes GPIO modules in PER domain to drive random
> +	 * values while coming back from OFF mode.
> +	 */
> +	pwrdm_add_wkdep(per_pwrdm, wkup_pwrdm);
> +
>  	if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
>  		omap3_secure_ram_storage =
>  			kmalloc(0x803F, GFP_KERNEL);
> -- 
> 1.5.4.7
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

-- 
Jouni Högander
--
To unsubscribe from this list: send the line "unsubscribe linux-omap" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

RE: [PATCH 02/06] OMAP3: PM: Add PER wakeup dependency on WKUP domain

[Nayak, Rajendra]

>-----Original Message-----
>From: Högander Jouni [mailto:jouni.hogander@nokia.com] 
>Sent: Friday, May 29, 2009 11:21 AM
>To: Nayak, Rajendra
>Cc: linux-omap@vger.kernel.org
>Subject: Re: [PATCH 02/06] OMAP3: PM: Add PER wakeup 
>dependency on WKUP domain
>
>ext Rajendra Nayak <rnayak@ti.com> writes:
>
>> This patch adds a Wakeup dependency of PER domain on WKUP
>> domain as a Workaround for a OMAP3430 limitation which causes
>> PER domain GPIO's to drive random values while coming back
>> from OFF mode. This limitation applies to all silicon rev's
>> of OMAP3430.
>
>I think this errata is already taken care in gpio code. We are
>configuring gpio output pads into safe mode and using pull 
>up/down according
>to gpio state.

Ok.. this might not be needed in that case.
Thanks

>
>>
>> Signed-off-by: Rajendra Nayak <rnayak@ti.com>
>> ---
>>  arch/arm/mach-omap2/pm34xx.c |    9 +++++++++
>>  1 files changed, 9 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/mach-omap2/pm34xx.c 
>b/arch/arm/mach-omap2/pm34xx.c
>> index 80992c5..231b33e 100644
>> --- a/arch/arm/mach-omap2/pm34xx.c
>> +++ b/arch/arm/mach-omap2/pm34xx.c
>> @@ -86,6 +86,7 @@ static int (*_omap_save_secure_sram)(u32 *addr);
>>  static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
>>  static struct powerdomain *core_pwrdm, *per_pwrdm;
>>  static struct powerdomain *cam_pwrdm;
>> +static struct powerdomain *wkup_pwrdm;
>>  
>>  static struct prm_setup_times prm_setup = {
>>  	.clksetup = 0xff,
>> @@ -1042,6 +1043,7 @@ int __init omap3_pm_init(void)
>>  	per_pwrdm = pwrdm_lookup("per_pwrdm");
>>  	core_pwrdm = pwrdm_lookup("core_pwrdm");
>>  	cam_pwrdm = pwrdm_lookup("cam_pwrdm");
>> +	wkup_pwrdm = pwrdm_lookup("wkup_pwrdm");
>>  
>>  	omap_push_sram_idle();
>>  
>> @@ -1063,6 +1065,13 @@ int __init omap3_pm_init(void)
>>  	*/
>>  	pwrdm_add_wkdep(per_pwrdm, core_pwrdm);
>>  
>> +	/*
>> +	 * This is a WA for an OMAP limitation (Listed in the 
>omap errata doc
>> +	 * Section 2.23) which causes GPIO modules in PER 
>domain to drive random
>> +	 * values while coming back from OFF mode.
>> +	 */
>> +	pwrdm_add_wkdep(per_pwrdm, wkup_pwrdm);
>> +
>>  	if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
>>  		omap3_secure_ram_storage =
>>  			kmalloc(0x803F, GFP_KERNEL);
>> -- 
>> 1.5.4.7
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe 
>linux-omap" in
>> the body of a message to majordomo@vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>
>-- 
>Jouni Högander
>
>

Re: [PATCH 05/06] OMAP3: PM: Implement locking for any scratchpad access

[Kevin Hilman]

Rajendra Nayak <rnayak@ti.com> writes:

> This patch implements locking using the semaphore in scratchpad
> memory preventing any concurrent access to scratchpad from OMAP
> and Baseband/Modem processor.
>
> Signed-off-by: Rajendra Nayak <rnayak@ti.com>

Any reason this function has to be written in asm?  It's written along
with a bunch of other asm functions that are copied to and executed
from SRAM, but that doesn't appear to be the case here.

Looks like a simple C function would be clearer here.

Kevin

> ---
>  arch/arm/mach-omap2/resource34xx.c |    6 +++++-
>  arch/arm/mach-omap2/resource34xx.h |    2 ++
>  arch/arm/mach-omap2/sleep34xx.S    |   32 ++++++++++++++++++++++++++++++++
>  3 files changed, 39 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/resource34xx.c b/arch/arm/mach-omap2/resource34xx.c
> index 82405b6..408d3ab 100644
> --- a/arch/arm/mach-omap2/resource34xx.c
> +++ b/arch/arm/mach-omap2/resource34xx.c
> @@ -236,6 +236,7 @@ static int program_opp_freq(int res, int target_level, int current_level)
>  	int ret = 0, l3_div;
>  	int *curr_opp;
>  
> +	lock_scratchpad_sem();
>  	if (res == VDD1_OPP) {
>  		curr_opp = &curr_vdd1_opp;
>  		clk_set_rate(dpll1_clk, mpu_opps[target_level].rate);
> @@ -253,11 +254,14 @@ static int program_opp_freq(int res, int target_level, int current_level)
>  		ret = clk_set_rate(dpll3_clk,
>  				l3_opps[target_level].rate * l3_div);
>  	}
> -	if (ret)
> +	if (ret) {
> +		unlock_scratchpad_sem();
>  		return current_level;
> +	}
>  #ifdef CONFIG_PM
>  	omap3_save_scratchpad_contents();
>  #endif
> +	unlock_scratchpad_sem();
>  
>  	*curr_opp = target_level;
>  	return target_level;
> diff --git a/arch/arm/mach-omap2/resource34xx.h b/arch/arm/mach-omap2/resource34xx.h
> index a160665..5b5618a 100644
> --- a/arch/arm/mach-omap2/resource34xx.h
> +++ b/arch/arm/mach-omap2/resource34xx.h
> @@ -29,6 +29,8 @@
>  #include <mach/omap34xx.h>
>  
>  extern int sr_voltagescale_vcbypass(u32 t_opp, u32 c_opp, u8 t_vsel, u8 c_vsel);
> +extern void lock_scratchpad_sem();
> +extern void unlock_scratchpad_sem();
>  
>  /*
>   * mpu_latency/core_latency are used to control the cpuidle C state.
> diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
> index 38aa3fd..aedcf94 100644
> --- a/arch/arm/mach-omap2/sleep34xx.S
> +++ b/arch/arm/mach-omap2/sleep34xx.S
> @@ -39,6 +39,7 @@
>  #define PM_PREPWSTST_MPU_V	OMAP34XX_PRM_REGADDR(MPU_MOD, \
>  				OMAP3430_PM_PREPWSTST)
>  #define CM_IDLEST1_CORE_V	OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1)
> +#define SDRC_SCRATCHPAD_SEM_V	0xd800291C
>  
>  /*
>   * This is the physical address of the register as specified
> @@ -62,6 +63,37 @@
>  #define SDRC_DLLA_STATUS_V	OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
>  #define SDRC_DLLA_CTRL_V	OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
>  
> +        .text
> +/* Function to aquire the semaphore in scratchpad */
> +ENTRY(lock_scratchpad_sem)
> +	stmfd	sp!, {lr}	@ save registers on stack
> +wait_sem:
> +	mov	r0,#1
> +	ldr	r1, sdrc_scratchpad_sem
> +wait_loop:
> +	ldr	r2, [r1]	@ load the lock value
> +	cmp	r2, r0		@ is the lock free ?
> +	beq	wait_loop	@ not free...
> +	swp	r2, r0, [r1]	@ semaphore free so lock it and proceed
> +	cmp	r2, r0		@ did we succeed ?
> +	beq	wait_sem	@ no - try again
> +	ldmfd	sp!, {pc}	@ restore regs and return
> +sdrc_scratchpad_sem:
> +        .word SDRC_SCRATCHPAD_SEM_V
> +ENTRY(lock_scratchpad_sem_sz)
> +        .word   . - lock_scratchpad_sem
> +
> +        .text
> +/* Function to release the scratchpad semaphore */
> +ENTRY(unlock_scratchpad_sem)
> +	stmfd	sp!, {lr}	@ save registers on stack
> +	ldr	r3, sdrc_scratchpad_sem
> +	mov	r2,#0
> +	str	r2,[r3]
> +	ldmfd	sp!, {pc}	@ restore regs and return
> +ENTRY(unlock_scratchpad_sem_sz)
> +        .word   . - unlock_scratchpad_sem
> +
>  	.text
>  /* Function call to get the restore pointer for resume from OFF */
>  ENTRY(get_restore_pointer)
> -- 
> 1.5.4.7
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

RE: [PATCH 05/06] OMAP3: PM: Implement locking for any scratchpad access

[Nayak, Rajendra]

 

>-----Original Message-----
>From: Kevin Hilman [mailto:khilman@deeprootsystems.com] 
>Sent: Friday, June 05, 2009 4:54 AM
>To: Nayak, Rajendra
>Cc: linux-omap@vger.kernel.org
>Subject: Re: [PATCH 05/06] OMAP3: PM: Implement locking for 
>any scratchpad access
>
>Rajendra Nayak <rnayak@ti.com> writes:
>
>> This patch implements locking using the semaphore in scratchpad
>> memory preventing any concurrent access to scratchpad from OMAP
>> and Baseband/Modem processor.
>>
>> Signed-off-by: Rajendra Nayak <rnayak@ti.com>
>
>Any reason this function has to be written in asm?  It's written along
>with a bunch of other asm functions that are copied to and executed
>from SRAM, but that doesn't appear to be the case here.
>
>Looks like a simple C function would be clearer here.

Kevin,

The idea was to atomically read and write into the semaphore memory
location in scratchpad using a swp instruction.
I am not too sure how to do this in C.

regards,
Rajendra 

>
>Kevin
>
>> ---
>>  arch/arm/mach-omap2/resource34xx.c |    6 +++++-
>>  arch/arm/mach-omap2/resource34xx.h |    2 ++
>>  arch/arm/mach-omap2/sleep34xx.S    |   32 
>++++++++++++++++++++++++++++++++
>>  3 files changed, 39 insertions(+), 1 deletions(-)
>>
>> diff --git a/arch/arm/mach-omap2/resource34xx.c 
>b/arch/arm/mach-omap2/resource34xx.c
>> index 82405b6..408d3ab 100644
>> --- a/arch/arm/mach-omap2/resource34xx.c
>> +++ b/arch/arm/mach-omap2/resource34xx.c
>> @@ -236,6 +236,7 @@ static int program_opp_freq(int res, int 
>target_level, int current_level)
>>  	int ret = 0, l3_div;
>>  	int *curr_opp;
>>  
>> +	lock_scratchpad_sem();
>>  	if (res == VDD1_OPP) {
>>  		curr_opp = &curr_vdd1_opp;
>>  		clk_set_rate(dpll1_clk, mpu_opps[target_level].rate);
>> @@ -253,11 +254,14 @@ static int program_opp_freq(int res, 
>int target_level, int current_level)
>>  		ret = clk_set_rate(dpll3_clk,
>>  				l3_opps[target_level].rate * l3_div);
>>  	}
>> -	if (ret)
>> +	if (ret) {
>> +		unlock_scratchpad_sem();
>>  		return current_level;
>> +	}
>>  #ifdef CONFIG_PM
>>  	omap3_save_scratchpad_contents();
>>  #endif
>> +	unlock_scratchpad_sem();
>>  
>>  	*curr_opp = target_level;
>>  	return target_level;
>> diff --git a/arch/arm/mach-omap2/resource34xx.h 
>b/arch/arm/mach-omap2/resource34xx.h
>> index a160665..5b5618a 100644
>> --- a/arch/arm/mach-omap2/resource34xx.h
>> +++ b/arch/arm/mach-omap2/resource34xx.h
>> @@ -29,6 +29,8 @@
>>  #include <mach/omap34xx.h>
>>  
>>  extern int sr_voltagescale_vcbypass(u32 t_opp, u32 c_opp, 
>u8 t_vsel, u8 c_vsel);
>> +extern void lock_scratchpad_sem();
>> +extern void unlock_scratchpad_sem();
>>  
>>  /*
>>   * mpu_latency/core_latency are used to control the cpuidle C state.
>> diff --git a/arch/arm/mach-omap2/sleep34xx.S 
>b/arch/arm/mach-omap2/sleep34xx.S
>> index 38aa3fd..aedcf94 100644
>> --- a/arch/arm/mach-omap2/sleep34xx.S
>> +++ b/arch/arm/mach-omap2/sleep34xx.S
>> @@ -39,6 +39,7 @@
>>  #define PM_PREPWSTST_MPU_V	OMAP34XX_PRM_REGADDR(MPU_MOD, \
>>  				OMAP3430_PM_PREPWSTST)
>>  #define CM_IDLEST1_CORE_V	OMAP34XX_CM_REGADDR(CORE_MOD, 
>CM_IDLEST1)
>> +#define SDRC_SCRATCHPAD_SEM_V	0xd800291C
>>  
>>  /*
>>   * This is the physical address of the register as specified
>> @@ -62,6 +63,37 @@
>>  #define SDRC_DLLA_STATUS_V	OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
>>  #define SDRC_DLLA_CTRL_V	OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
>>  
>> +        .text
>> +/* Function to aquire the semaphore in scratchpad */
>> +ENTRY(lock_scratchpad_sem)
>> +	stmfd	sp!, {lr}	@ save registers on stack
>> +wait_sem:
>> +	mov	r0,#1
>> +	ldr	r1, sdrc_scratchpad_sem
>> +wait_loop:
>> +	ldr	r2, [r1]	@ load the lock value
>> +	cmp	r2, r0		@ is the lock free ?
>> +	beq	wait_loop	@ not free...
>> +	swp	r2, r0, [r1]	@ semaphore free so lock it and proceed
>> +	cmp	r2, r0		@ did we succeed ?
>> +	beq	wait_sem	@ no - try again
>> +	ldmfd	sp!, {pc}	@ restore regs and return
>> +sdrc_scratchpad_sem:
>> +        .word SDRC_SCRATCHPAD_SEM_V
>> +ENTRY(lock_scratchpad_sem_sz)
>> +        .word   . - lock_scratchpad_sem
>> +
>> +        .text
>> +/* Function to release the scratchpad semaphore */
>> +ENTRY(unlock_scratchpad_sem)
>> +	stmfd	sp!, {lr}	@ save registers on stack
>> +	ldr	r3, sdrc_scratchpad_sem
>> +	mov	r2,#0
>> +	str	r2,[r3]
>> +	ldmfd	sp!, {pc}	@ restore regs and return
>> +ENTRY(unlock_scratchpad_sem_sz)
>> +        .word   . - unlock_scratchpad_sem
>> +
>>  	.text
>>  /* Function call to get the restore pointer for resume from OFF */
>>  ENTRY(get_restore_pointer)
>> -- 
>> 1.5.4.7
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe 
>linux-omap" in
>> the body of a message to majordomo@vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>
>

Re: [PATCH 05/06] OMAP3: PM: Implement locking for any scratchpad access

[Paul Walmsley]

Hi Rajendra,

On Thu, 28 May 2009, Rajendra Nayak wrote:

> This patch implements locking using the semaphore in scratchpad
> memory preventing any concurrent access to scratchpad from OMAP
> and Baseband/Modem processor.

This patch might be okay for the target use case.  But there might still 
be a race window with this patch, where the modem could steal the MPU's 
lock or vice versa.

That swp tries to guarantee atomicity through exclusive memory accesses, 
but the AXI2OCP bridge section of the TRM claims that the bridge 
translates "exclusive accesses to non-exclusive read/write in the bridge" 
(section 3.2.3.2).  That seems to suggest that the memory accesses will be 
non-atomic and that therefore a race window exists.

The easiest way to close it up tight might be to use the ICR, and have the 
modem request permission to write to the scratchpad RAM from the MPU, or 
vice versa.  I realize that "easiest" is definitely relative in this 
case...


- Paul

> 
> Signed-off-by: Rajendra Nayak <rnayak@ti.com>
> ---
>  arch/arm/mach-omap2/resource34xx.c |    6 +++++-
>  arch/arm/mach-omap2/resource34xx.h |    2 ++
>  arch/arm/mach-omap2/sleep34xx.S    |   32 ++++++++++++++++++++++++++++++++
>  3 files changed, 39 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/resource34xx.c b/arch/arm/mach-omap2/resource34xx.c
> index 82405b6..408d3ab 100644
> --- a/arch/arm/mach-omap2/resource34xx.c
> +++ b/arch/arm/mach-omap2/resource34xx.c
> @@ -236,6 +236,7 @@ static int program_opp_freq(int res, int target_level, int current_level)
>  	int ret = 0, l3_div;
>  	int *curr_opp;
>  
> +	lock_scratchpad_sem();
>  	if (res == VDD1_OPP) {
>  		curr_opp = &curr_vdd1_opp;
>  		clk_set_rate(dpll1_clk, mpu_opps[target_level].rate);
> @@ -253,11 +254,14 @@ static int program_opp_freq(int res, int target_level, int current_level)
>  		ret = clk_set_rate(dpll3_clk,
>  				l3_opps[target_level].rate * l3_div);
>  	}
> -	if (ret)
> +	if (ret) {
> +		unlock_scratchpad_sem();
>  		return current_level;
> +	}
>  #ifdef CONFIG_PM
>  	omap3_save_scratchpad_contents();
>  #endif
> +	unlock_scratchpad_sem();
>  
>  	*curr_opp = target_level;
>  	return target_level;
> diff --git a/arch/arm/mach-omap2/resource34xx.h b/arch/arm/mach-omap2/resource34xx.h
> index a160665..5b5618a 100644
> --- a/arch/arm/mach-omap2/resource34xx.h
> +++ b/arch/arm/mach-omap2/resource34xx.h
> @@ -29,6 +29,8 @@
>  #include <mach/omap34xx.h>
>  
>  extern int sr_voltagescale_vcbypass(u32 t_opp, u32 c_opp, u8 t_vsel, u8 c_vsel);
> +extern void lock_scratchpad_sem();
> +extern void unlock_scratchpad_sem();
>  
>  /*
>   * mpu_latency/core_latency are used to control the cpuidle C state.
> diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
> index 38aa3fd..aedcf94 100644
> --- a/arch/arm/mach-omap2/sleep34xx.S
> +++ b/arch/arm/mach-omap2/sleep34xx.S
> @@ -39,6 +39,7 @@
>  #define PM_PREPWSTST_MPU_V	OMAP34XX_PRM_REGADDR(MPU_MOD, \
>  				OMAP3430_PM_PREPWSTST)
>  #define CM_IDLEST1_CORE_V	OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1)
> +#define SDRC_SCRATCHPAD_SEM_V	0xd800291C
>  
>  /*
>   * This is the physical address of the register as specified
> @@ -62,6 +63,37 @@
>  #define SDRC_DLLA_STATUS_V	OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
>  #define SDRC_DLLA_CTRL_V	OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
>  
> +        .text
> +/* Function to aquire the semaphore in scratchpad */
> +ENTRY(lock_scratchpad_sem)
> +	stmfd	sp!, {lr}	@ save registers on stack
> +wait_sem:
> +	mov	r0,#1
> +	ldr	r1, sdrc_scratchpad_sem
> +wait_loop:
> +	ldr	r2, [r1]	@ load the lock value
> +	cmp	r2, r0		@ is the lock free ?
> +	beq	wait_loop	@ not free...
> +	swp	r2, r0, [r1]	@ semaphore free so lock it and proceed
> +	cmp	r2, r0		@ did we succeed ?
> +	beq	wait_sem	@ no - try again
> +	ldmfd	sp!, {pc}	@ restore regs and return
> +sdrc_scratchpad_sem:
> +        .word SDRC_SCRATCHPAD_SEM_V
> +ENTRY(lock_scratchpad_sem_sz)
> +        .word   . - lock_scratchpad_sem
> +
> +        .text
> +/* Function to release the scratchpad semaphore */
> +ENTRY(unlock_scratchpad_sem)
> +	stmfd	sp!, {lr}	@ save registers on stack
> +	ldr	r3, sdrc_scratchpad_sem
> +	mov	r2,#0
> +	str	r2,[r3]
> +	ldmfd	sp!, {pc}	@ restore regs and return
> +ENTRY(unlock_scratchpad_sem_sz)
> +        .word   . - unlock_scratchpad_sem
> +
>  	.text
>  /* Function call to get the restore pointer for resume from OFF */
>  ENTRY(get_restore_pointer)
> -- 
> 1.5.4.7
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 


- Paul

RE: [PATCH 05/06] OMAP3: PM: Implement locking for any scratchpad access

[Woodruff, Richard]

> From: linux-omap-owner@vger.kernel.org [mailto:linux-omap-
> owner@vger.kernel.org] On Behalf Of Paul Walmsley
> Sent: Friday, June 05, 2009 4:26 PM

> On Thu, 28 May 2009, Rajendra Nayak wrote:
>
> > This patch implements locking using the semaphore in scratchpad
> > memory preventing any concurrent access to scratchpad from OMAP
> > and Baseband/Modem processor.
>
> This patch might be okay for the target use case.  But there might still
> be a race window with this patch, where the modem could steal the MPU's
> lock or vice versa.
>
> That swp tries to guarantee atomicity through exclusive memory accesses,
> but the AXI2OCP bridge section of the TRM claims that the bridge
> translates "exclusive accesses to non-exclusive read/write in the bridge"
> (section 3.2.3.2).  That seems to suggest that the memory accesses will be
> non-atomic and that therefore a race window exists.

This is an incorrect interpretation.  A race does not exist because of this point.

The AXI2OCP does translate external excusive operations this way (STREX/LWREX).  This is not the same for SWP.  SWP generates a global bus lock.

Exclusive operations do have a reservation in the L2 block.  So they are good until they go to external memory.  On OMAP these work as you expect with respect to the ARM, but won't work between ARM and DSP or other master.

SWP on the other hand still works.  SWP is a relative pig compared to STREX/LWREX as it locks the whole L3, compared to a small key address, but, it's a lot lighter than a mailbox.


Regards,
Richard W.

Re: [PATCH 05/06] OMAP3: PM: Implement locking for any scratchpad access

[Kevin Hilman]

Rajendra Nayak <rnayak@ti.com> writes:

> This patch implements locking using the semaphore in scratchpad
> memory preventing any concurrent access to scratchpad from OMAP
> and Baseband/Modem processor.
>
> Signed-off-by: Rajendra Nayak <rnayak@ti.com>

Applying to PM brach after the clarifications.

Thanks,

Kevin

> ---
>  arch/arm/mach-omap2/resource34xx.c |    6 +++++-
>  arch/arm/mach-omap2/resource34xx.h |    2 ++
>  arch/arm/mach-omap2/sleep34xx.S    |   32 ++++++++++++++++++++++++++++++++
>  3 files changed, 39 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/resource34xx.c b/arch/arm/mach-omap2/resource34xx.c
> index 82405b6..408d3ab 100644
> --- a/arch/arm/mach-omap2/resource34xx.c
> +++ b/arch/arm/mach-omap2/resource34xx.c
> @@ -236,6 +236,7 @@ static int program_opp_freq(int res, int target_level, int current_level)
>  	int ret = 0, l3_div;
>  	int *curr_opp;
>  
> +	lock_scratchpad_sem();
>  	if (res == VDD1_OPP) {
>  		curr_opp = &curr_vdd1_opp;
>  		clk_set_rate(dpll1_clk, mpu_opps[target_level].rate);
> @@ -253,11 +254,14 @@ static int program_opp_freq(int res, int target_level, int current_level)
>  		ret = clk_set_rate(dpll3_clk,
>  				l3_opps[target_level].rate * l3_div);
>  	}
> -	if (ret)
> +	if (ret) {
> +		unlock_scratchpad_sem();
>  		return current_level;
> +	}
>  #ifdef CONFIG_PM
>  	omap3_save_scratchpad_contents();
>  #endif
> +	unlock_scratchpad_sem();
>  
>  	*curr_opp = target_level;
>  	return target_level;
> diff --git a/arch/arm/mach-omap2/resource34xx.h b/arch/arm/mach-omap2/resource34xx.h
> index a160665..5b5618a 100644
> --- a/arch/arm/mach-omap2/resource34xx.h
> +++ b/arch/arm/mach-omap2/resource34xx.h
> @@ -29,6 +29,8 @@
>  #include <mach/omap34xx.h>
>  
>  extern int sr_voltagescale_vcbypass(u32 t_opp, u32 c_opp, u8 t_vsel, u8 c_vsel);
> +extern void lock_scratchpad_sem();
> +extern void unlock_scratchpad_sem();
>  
>  /*
>   * mpu_latency/core_latency are used to control the cpuidle C state.
> diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
> index 38aa3fd..aedcf94 100644
> --- a/arch/arm/mach-omap2/sleep34xx.S
> +++ b/arch/arm/mach-omap2/sleep34xx.S
> @@ -39,6 +39,7 @@
>  #define PM_PREPWSTST_MPU_V	OMAP34XX_PRM_REGADDR(MPU_MOD, \
>  				OMAP3430_PM_PREPWSTST)
>  #define CM_IDLEST1_CORE_V	OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1)
> +#define SDRC_SCRATCHPAD_SEM_V	0xd800291C
>  
>  /*
>   * This is the physical address of the register as specified
> @@ -62,6 +63,37 @@
>  #define SDRC_DLLA_STATUS_V	OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
>  #define SDRC_DLLA_CTRL_V	OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
>  
> +        .text
> +/* Function to aquire the semaphore in scratchpad */
> +ENTRY(lock_scratchpad_sem)
> +	stmfd	sp!, {lr}	@ save registers on stack
> +wait_sem:
> +	mov	r0,#1
> +	ldr	r1, sdrc_scratchpad_sem
> +wait_loop:
> +	ldr	r2, [r1]	@ load the lock value
> +	cmp	r2, r0		@ is the lock free ?
> +	beq	wait_loop	@ not free...
> +	swp	r2, r0, [r1]	@ semaphore free so lock it and proceed
> +	cmp	r2, r0		@ did we succeed ?
> +	beq	wait_sem	@ no - try again
> +	ldmfd	sp!, {pc}	@ restore regs and return
> +sdrc_scratchpad_sem:
> +        .word SDRC_SCRATCHPAD_SEM_V
> +ENTRY(lock_scratchpad_sem_sz)
> +        .word   . - lock_scratchpad_sem
> +
> +        .text
> +/* Function to release the scratchpad semaphore */
> +ENTRY(unlock_scratchpad_sem)
> +	stmfd	sp!, {lr}	@ save registers on stack
> +	ldr	r3, sdrc_scratchpad_sem
> +	mov	r2,#0
> +	str	r2,[r3]
> +	ldmfd	sp!, {pc}	@ restore regs and return
> +ENTRY(unlock_scratchpad_sem_sz)
> +        .word   . - unlock_scratchpad_sem
> +
>  	.text
>  /* Function call to get the restore pointer for resume from OFF */
>  ENTRY(get_restore_pointer)
> -- 
> 1.5.4.7
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

RE: [PATCH 05/06] OMAP3: PM: Implement locking for any scratchpad access

[Paul Walmsley]

On Fri, 5 Jun 2009, Woodruff, Richard wrote:

> > From: linux-omap-owner@vger.kernel.org [mailto:linux-omap-
> > owner@vger.kernel.org] On Behalf Of Paul Walmsley
> > Sent: Friday, June 05, 2009 4:26 PM
> 
> > On Thu, 28 May 2009, Rajendra Nayak wrote:
> >
> > > This patch implements locking using the semaphore in scratchpad
> > > memory preventing any concurrent access to scratchpad from OMAP
> > > and Baseband/Modem processor.
> >
> > This patch might be okay for the target use case.  But there might still
> > be a race window with this patch, where the modem could steal the MPU's
> > lock or vice versa.
> >
> > That swp tries to guarantee atomicity through exclusive memory accesses,
> > but the AXI2OCP bridge section of the TRM claims that the bridge
> > translates "exclusive accesses to non-exclusive read/write in the bridge"
> > (section 3.2.3.2).  That seems to suggest that the memory accesses will be
> > non-atomic and that therefore a race window exists.
> 
> This is an incorrect interpretation.  A race does not exist because of this point.
> 
> The AXI2OCP does translate external excusive operations this way 
> (STREX/LWREX).  This is not the same for SWP.  SWP generates a global 
> bus lock.
> 
> Exclusive operations do have a reservation in the L2 block.  So they are 
> good until they go to external memory.  On OMAP these work as you expect 
> with respect to the ARM, but won't work between ARM and DSP or other 
> master.
> 
> SWP on the other hand still works.  SWP is a relative pig compared to 
> STREX/LWREX as it locks the whole L3, compared to a small key address, 
> but, it's a lot lighter than a mailbox.

OK, thanks for the explanation, Richard.  Sounds like it's okay then,


- Paul