From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Mahadeva, Avinash" Subject: Re: [PATCH 1/2 v2] OMAP2/3: hwmod: fix the i2c-reset timeout during bootup Date: Thu, 7 Apr 2011 12:12:37 +0530 Message-ID: References: <1302018015-8858-1-git-send-email-avinashhm@ti.com> <1302018015-8858-2-git-send-email-avinashhm@ti.com> <87mxk4zh7u.fsf@ti.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0374941514==" Return-path: In-Reply-To: <87mxk4zh7u.fsf@ti.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Kevin Hilman Cc: Paul Walmsley , linux-omap@vger.kernel.org, Benoit Cousson , linux-arm-kernel@lists.infradead.org, Rajendra Nayak List-Id: linux-omap@vger.kernel.org --===============0374941514== Content-Type: multipart/alternative; boundary=20cf303f69ea428dcc04a04e6a1a --20cf303f69ea428dcc04a04e6a1a Content-Type: text/plain; charset=ISO-8859-1 On Tue, Apr 5, 2011 at 11:57 PM, Kevin Hilman wrote: > "Avinash.H.M" writes: > > > The i2c module has a special reset sequence. The sequence is > > - Disable the I2C. > > - Write to SOFTRESET bit. > > - Enable the I2C. > > - Poll on the RESETDONE bit. > > This sequence must be followed for i2c reset in omap2, omap3. The > sequence is > > implemented as a function and the i2c_class is updated with the correct > > 'reset' pointer. > > > > Cc: Rajendra Nayak > > Cc: Paul Walmsley > > Cc: Benoit Cousson > > Cc: Kevin Hilman > > Signed-off-by: Avinash.H.M > > [...] > > > + > > +/** > > + * omap_i2c_reset- reset the omap i2c module. > > + * @oh: struct omap_hwmod * > > + * > > + * The i2c moudle in omap2, omap3 had a special sequence to reset. The > > + * sequence is: > > + * - Disable the I2C. > > + * - Write to SOFTRESET bit. > > + * - Enable the I2C. > > + * - Poll on the RESETDONE bit. > > + * The sequence is implemented in below function. This is called for > 2420, > > + * 2430 and omap3. > > + */ > > +int omap_i2c_reset(struct omap_hwmod *oh) > > +{ > > + u32 v; > > + int c = 0; > > + > > + /* Disable I2C */ > > + v = omap_hwmod_read(oh, I2C_CON_OFFSET); > > + v = v & ~I2C_EN; > > + omap_hwmod_write(v, oh, I2C_CON_OFFSET); > > + > > + /* Write to the SOFTRESET bit */ > > + v = oh->_sysc_cache; > > + v |= (0x1 << oh->class->sysc->sysc_fields->srst_shift); > > + > > + oh->_sysc_cache = v; > > + omap_hwmod_write(v, oh, oh->class->sysc->sysc_offs); > > Direct SYSCONFIG access isn't right here. This should go through > omap_hwmod. > > What is probably needed is exposing _ocp_softreset to device code > via something like omap_hwmod_ocp_softreset() and calling that here. > > Hi Kevin , thanks for the review. OK. I ll create a wrapper function ' omap_hwmod_ocp_softreset' around '_ocp_softreset' and call it here . b r , - avinash. > Kevin > --20cf303f69ea428dcc04a04e6a1a Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable

On Tue, Apr 5, 2011 at 11:57 PM, Kevin H= ilman <khilman@ti.co= m> wrote:
"Avinash.H.M" <avinashhm@ti.com> writes:

> The i2c module has a special reset sequence. The sequence is
> - Disable the I2C.
> - Write to SOFTRESET bit.
> - Enable the I2C.
> - Poll on the RESETDONE bit.
> This sequence must be followed for i2c reset in omap2, omap3. The sequ= ence is
> implemented as a function and the i2c_class is updated with the correc= t
> 'reset' pointer.
>
> Cc: Rajendra Nayak <rnayak@ti.com<= /a>>
> Cc: Paul Walmsley <paul@pwsan.com= >
> Cc: Benoit Cousson <b-cousson@t= i.com>
> Cc: Kevin Hilman <khilman@ti.com<= /a>>
> Signed-off-by: Avinash.H.M <avi= nashhm@ti.com>

[...]

> +
> +/**
> + * omap_i2c_reset- reset the omap i2c module.
> + * @oh: struct omap_hwmod *
> + *
> + * The i2c moudle in omap2, omap3 had a special sequence to reset. Th= e
> + * sequence is:
> + * - Disable the I2C.
> + * - Write to SOFTRESET bit.
> + * - Enable the I2C.
> + * - Poll on the RESETDONE bit.
> + * The sequence is implemented in below function. This is called for = 2420,
> + * 2430 and omap3.
> + */
> +int omap_i2c_reset(struct omap_hwmod *oh)
> +{
> + =A0 =A0 u32 v;
> + =A0 =A0 int c =3D 0;
> +
> + =A0 =A0 /* Disable I2C */
> + =A0 =A0 v =3D omap_hwmod_read(oh, I2C_CON_OFFSET);
> + =A0 =A0 v =3D v & ~I2C_EN;
> + =A0 =A0 omap_hwmod_write(v, oh, I2C_CON_OFFSET);
> +
> + =A0 =A0 /* Write to the SOFTRESET bit */
> + =A0 =A0 v =3D oh->_sysc_cache;
> + =A0 =A0 v |=3D (0x1 << oh->class->sysc->sysc_fields-&= gt;srst_shift);
> +
> + =A0 =A0 oh->_sysc_cache =3D v;
> + =A0 =A0 omap_hwmod_write(v, oh, oh->class->sysc->sysc_offs)= ;

Direct SYSCONFIG access isn't right here. =A0 This should go thro= ugh
omap_hwmod.

What is probably needed is exposing _ocp_softreset to device code
via something like omap_hwmod_ocp_softreset() and calling that here.


Hi Kevin ,
thanks for the review.

OK. I ll create a wrapper function ' om= ap_hwmod_ocp_softreset'
around '_ocp_softreset' and call it = here .

b r ,
- avinash.

=A0
Kevin

--20cf303f69ea428dcc04a04e6a1a-- --===============0374941514== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel --===============0374941514==--