From: Russell King <rmk+kernel@arm.linux.org.uk>
To: linux-arm-kernel@lists.ifradead.org
Cc: Tony Lindgren <tony@atomide.com>,
linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: [PATCH 84/97] ARM: l2c: omap2: avoid reading directly from the L2 registers in platform code
Date: Mon, 28 Apr 2014 20:33:21 +0100 [thread overview]
Message-ID: <E1WerIn-0001ZP-6I@rmk-PC.arm.linux.org.uk> (raw)
In-Reply-To: <20140428192419.GV26756@n2100.arm.linux.org.uk>
Avoid reading directly from the L2 registers in platform code. The L2
code will have already saved the register values itself into the
l2x0_saved_regs structure, so platform code should just move these
values to where they're required.
This is safe because the L2x0 will have been initialised by an early
initcall, whereas the OMAP4 PM code is initialised late.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
arch/arm/mach-omap2/omap-mpuss-lowpower.c | 16 ++++++----------
1 file changed, 6 insertions(+), 10 deletions(-)
diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
index ba43f49fbb59..61cb77f8cf12 100644
--- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
+++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
@@ -187,19 +187,15 @@ static void l2x0_pwrst_prepare(unsigned int cpu_id, unsigned int save_state)
* in every restore MPUSS OFF path.
*/
#ifdef CONFIG_CACHE_L2X0
-static void save_l2x0_context(void)
+static void __init save_l2x0_context(void)
{
- u32 val;
- void __iomem *l2x0_base = omap4_get_l2cache_base();
- if (l2x0_base) {
- val = __raw_readl(l2x0_base + L2X0_AUX_CTRL);
- __raw_writel(val, sar_base + L2X0_AUXCTRL_OFFSET);
- val = __raw_readl(l2x0_base + L310_PREFETCH_CTRL);
- __raw_writel(val, sar_base + L2X0_PREFETCH_CTRL_OFFSET);
- }
+ __raw_writel(l2x0_saved_regs.aux_ctrl,
+ sar_base + L2X0_AUXCTRL_OFFSET);
+ __raw_writel(l2x0_saved_regs.prefetch_ctrl,
+ sar_base + L2X0_PREFETCH_CTRL_OFFSET);
}
#else
-static void save_l2x0_context(void)
+static void __init save_l2x0_context(void)
{}
#endif
--
1.8.3.1
next prev parent reply other threads:[~2014-04-28 19:33 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20140428192419.GV26756@n2100.arm.linux.org.uk>
2014-04-28 19:26 ` [PATCH 04/97] ARM: l2c: omap2: remove ES1.0 support Russell King
2014-04-28 19:29 ` [PATCH 42/97] ARM: l2c: omap2: implement new write_sec method Russell King
2014-04-28 19:29 ` [PATCH 43/97] ARM: l2c: omap2: remove explicit SMI calls to enable L2 cache Russell King
2014-04-28 19:30 ` [PATCH 49/97] ARM: l2c: fix register naming Russell King
[not found] ` <E1WerFu-0001Wq-BX-eh5Bv4kxaXIANfyc6IWni62ZND6+EDdj@public.gmane.org>
2014-04-28 20:05 ` Stephen Warren
2014-04-28 19:30 ` [PATCH 51/97] ARM: l2c: remove platforms/SoCs setting early BRESP Russell King
[not found] ` <E1WerG4-0001X4-Ic-eh5Bv4kxaXIANfyc6IWni62ZND6+EDdj@public.gmane.org>
2014-04-28 20:04 ` Stephen Warren
2014-04-29 0:02 ` Simon Horman
2014-04-29 0:21 ` Russell King - ARM Linux
2014-05-01 15:12 ` Grant Likely
[not found] ` <20140501151236.078E3C409DA-WNowdnHR2B42iJbIjFUEsiwD8/FfD2ys@public.gmane.org>
2014-05-01 16:18 ` Jon Loeliger
2014-05-03 21:37 ` Olof Johansson
2014-04-29 16:17 ` Stephen Warren
2014-04-30 6:13 ` Simon Horman
2014-04-28 19:31 ` [PATCH 63/97] ARM: l2c: omap2: remove cache size override Russell King
2014-04-28 19:33 ` Russell King [this message]
2014-04-28 19:33 ` [PATCH 86/97] ARM: l2c: always enable non-secure access to lockdown registers Russell King
2014-04-28 19:33 ` [PATCH 87/97] ARM: l2c: omap2+: get rid of redundant cache replacement policy setting Russell King
2014-04-28 19:33 ` [PATCH 88/97] ARM: l2c: omap2+: get rid of init call Russell King
2014-04-28 19:33 ` [PATCH 89/97] ARM: l2c: AM43x: add L2 cache support Russell King
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